2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
40 #include "radeon_asic.h"
44 #include "rs600_reg_safe.h"
46 static void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
49 static const u32 crtc_offsets[2] =
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
55 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
63 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
77 * avivo_wait_for_vblank - vblank wait asic callback.
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
84 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
88 if (crtc >= rdev->num_crtc)
91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
97 while (avivo_is_in_vblank(rdev, crtc)) {
99 if (!avivo_is_counter_moving(rdev, crtc))
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
112 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
114 /* enable the pflip int */
115 radeon_irq_kms_pflip_irq_get(rdev, crtc);
118 void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
120 /* disable the pflip int */
121 radeon_irq_kms_pflip_irq_put(rdev, crtc);
124 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
126 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
127 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
130 /* Lock the graphics update lock */
131 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
132 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
134 /* update the scanout addresses */
135 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
137 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
140 /* Wait for update_pending to go high. */
141 for (i = 0; i < rdev->usec_timeout; i++) {
142 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
146 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
148 /* Unlock the lock, so double-buffering can take place inside vblank */
149 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
150 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
152 /* Return current update_pending status: */
153 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
156 void rs600_pm_misc(struct radeon_device *rdev)
158 int requested_index = rdev->pm.requested_power_state_index;
159 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
160 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
161 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
162 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
164 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
165 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
166 tmp = RREG32(voltage->gpio.reg);
167 if (voltage->active_high)
168 tmp |= voltage->gpio.mask;
170 tmp &= ~(voltage->gpio.mask);
171 WREG32(voltage->gpio.reg, tmp);
173 udelay(voltage->delay);
175 tmp = RREG32(voltage->gpio.reg);
176 if (voltage->active_high)
177 tmp &= ~voltage->gpio.mask;
179 tmp |= voltage->gpio.mask;
180 WREG32(voltage->gpio.reg, tmp);
182 udelay(voltage->delay);
184 } else if (voltage->type == VOLTAGE_VDDC)
185 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
187 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
188 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
189 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
190 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
191 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
192 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
193 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
194 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
195 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
196 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
199 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
200 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
202 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
204 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
205 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
206 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
207 if (voltage->delay) {
208 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
209 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
211 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
213 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
214 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
216 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
217 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
218 hdp_dyn_cntl &= ~HDP_FORCEON;
220 hdp_dyn_cntl |= HDP_FORCEON;
221 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
223 /* mc_host_dyn seems to cause hangs from time to time */
224 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
225 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
226 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
228 mc_host_dyn_cntl |= MC_HOST_FORCEON;
229 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
231 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
232 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
233 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
235 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
236 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
239 if ((rdev->flags & RADEON_IS_PCIE) &&
240 !(rdev->flags & RADEON_IS_IGP) &&
241 rdev->asic->pm.set_pcie_lanes &&
243 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
244 radeon_set_pcie_lanes(rdev,
246 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
250 void rs600_pm_prepare(struct radeon_device *rdev)
252 struct drm_device *ddev = rdev->ddev;
253 struct drm_crtc *crtc;
254 struct radeon_crtc *radeon_crtc;
257 /* disable any active CRTCs */
258 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
259 radeon_crtc = to_radeon_crtc(crtc);
260 if (radeon_crtc->enabled) {
261 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
262 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
263 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
268 void rs600_pm_finish(struct radeon_device *rdev)
270 struct drm_device *ddev = rdev->ddev;
271 struct drm_crtc *crtc;
272 struct radeon_crtc *radeon_crtc;
275 /* enable any active CRTCs */
276 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
277 radeon_crtc = to_radeon_crtc(crtc);
278 if (radeon_crtc->enabled) {
279 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
280 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
281 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
286 /* hpd for digital panel detect/disconnect */
287 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
290 bool connected = false;
294 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
295 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
299 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
300 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
309 void rs600_hpd_set_polarity(struct radeon_device *rdev,
310 enum radeon_hpd_id hpd)
313 bool connected = rs600_hpd_sense(rdev, hpd);
317 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
319 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
321 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
322 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
325 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
327 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
329 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
330 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
337 void rs600_hpd_init(struct radeon_device *rdev)
339 struct drm_device *dev = rdev->ddev;
340 struct drm_connector *connector;
343 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
344 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
345 switch (radeon_connector->hpd.hpd) {
347 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
348 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
351 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
352 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
357 enable |= 1 << radeon_connector->hpd.hpd;
358 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
360 radeon_irq_kms_enable_hpd(rdev, enable);
363 void rs600_hpd_fini(struct radeon_device *rdev)
365 struct drm_device *dev = rdev->ddev;
366 struct drm_connector *connector;
367 unsigned disable = 0;
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
371 switch (radeon_connector->hpd.hpd) {
373 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
374 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
377 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
378 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
383 disable |= 1 << radeon_connector->hpd.hpd;
385 radeon_irq_kms_disable_hpd(rdev, disable);
388 int rs600_asic_reset(struct radeon_device *rdev)
390 struct rv515_mc_save save;
394 status = RREG32(R_000E40_RBBM_STATUS);
395 if (!G_000E40_GUI_ACTIVE(status)) {
398 /* Stops all mc clients */
399 rv515_mc_stop(rdev, &save);
400 status = RREG32(R_000E40_RBBM_STATUS);
401 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
403 WREG32(RADEON_CP_CSQ_CNTL, 0);
404 tmp = RREG32(RADEON_CP_RB_CNTL);
405 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
406 WREG32(RADEON_CP_RB_RPTR_WR, 0);
407 WREG32(RADEON_CP_RB_WPTR, 0);
408 WREG32(RADEON_CP_RB_CNTL, tmp);
409 pci_save_state(rdev->pdev);
410 /* disable bus mastering */
411 pci_clear_master(rdev->pdev);
414 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
415 S_0000F0_SOFT_RESET_GA(1));
416 RREG32(R_0000F0_RBBM_SOFT_RESET);
418 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
420 status = RREG32(R_000E40_RBBM_STATUS);
421 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
423 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
424 RREG32(R_0000F0_RBBM_SOFT_RESET);
426 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
428 status = RREG32(R_000E40_RBBM_STATUS);
429 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
431 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
432 RREG32(R_0000F0_RBBM_SOFT_RESET);
434 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
436 status = RREG32(R_000E40_RBBM_STATUS);
437 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
438 /* restore PCI & busmastering */
439 pci_restore_state(rdev->pdev);
440 /* Check if GPU is idle */
441 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
442 dev_err(rdev->dev, "failed to reset GPU\n");
445 dev_info(rdev->dev, "GPU reset succeed\n");
446 rv515_mc_resume(rdev, &save);
453 void rs600_gart_tlb_flush(struct radeon_device *rdev)
457 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
458 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
459 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
461 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
462 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
463 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
465 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
466 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
467 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
468 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
471 static int rs600_gart_init(struct radeon_device *rdev)
475 if (rdev->gart.robj) {
476 WARN(1, "RS600 GART already initialized\n");
479 /* Initialize common gart structure */
480 r = radeon_gart_init(rdev);
484 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
485 return radeon_gart_table_vram_alloc(rdev);
488 static int rs600_gart_enable(struct radeon_device *rdev)
493 if (rdev->gart.robj == NULL) {
494 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
497 r = radeon_gart_table_vram_pin(rdev);
500 radeon_gart_restore(rdev);
501 /* Enable bus master */
502 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
503 WREG32(RADEON_BUS_CNTL, tmp);
504 /* FIXME: setup default page */
505 WREG32_MC(R_000100_MC_PT0_CNTL,
506 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
507 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
509 for (i = 0; i < 19; i++) {
510 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
511 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
512 S_00016C_SYSTEM_ACCESS_MODE_MASK(
513 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
514 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
515 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
516 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
517 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
518 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
520 /* enable first context */
521 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
522 S_000102_ENABLE_PAGE_TABLE(1) |
523 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
525 /* disable all other contexts */
526 for (i = 1; i < 8; i++)
527 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
529 /* setup the page table */
530 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
531 rdev->gart.table_addr);
532 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
533 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
534 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
536 /* System context maps to VRAM space */
537 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
538 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
540 /* enable page tables */
541 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
542 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
543 tmp = RREG32_MC(R_000009_MC_CNTL1);
544 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
545 rs600_gart_tlb_flush(rdev);
546 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
547 (unsigned)(rdev->mc.gtt_size >> 20),
548 (unsigned long long)rdev->gart.table_addr);
549 rdev->gart.ready = true;
553 static void rs600_gart_disable(struct radeon_device *rdev)
557 /* FIXME: disable out of gart access */
558 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
559 tmp = RREG32_MC(R_000009_MC_CNTL1);
560 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
561 radeon_gart_table_vram_unpin(rdev);
564 static void rs600_gart_fini(struct radeon_device *rdev)
566 radeon_gart_fini(rdev);
567 rs600_gart_disable(rdev);
568 radeon_gart_table_vram_free(rdev);
571 #define R600_PTE_VALID (1 << 0)
572 #define R600_PTE_SYSTEM (1 << 1)
573 #define R600_PTE_SNOOPED (1 << 2)
574 #define R600_PTE_READABLE (1 << 5)
575 #define R600_PTE_WRITEABLE (1 << 6)
577 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
579 void __iomem *ptr = (void *)rdev->gart.ptr;
581 if (i < 0 || i > rdev->gart.num_gpu_pages) {
584 addr = addr & 0xFFFFFFFFFFFFF000ULL;
585 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
586 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
587 writeq(addr, ptr + (i * 8));
591 int rs600_irq_set(struct radeon_device *rdev)
594 uint32_t mode_int = 0;
595 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
596 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
597 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
598 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
600 if (ASIC_IS_DCE2(rdev))
601 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
602 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
606 if (!rdev->irq.installed) {
607 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
608 WREG32(R_000040_GEN_INT_CNTL, 0);
611 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
612 tmp |= S_000040_SW_INT_EN(1);
614 if (rdev->irq.crtc_vblank_int[0] ||
615 atomic_read(&rdev->irq.pflip[0])) {
616 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
618 if (rdev->irq.crtc_vblank_int[1] ||
619 atomic_read(&rdev->irq.pflip[1])) {
620 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
622 if (rdev->irq.hpd[0]) {
623 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
625 if (rdev->irq.hpd[1]) {
626 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
628 if (rdev->irq.afmt[0]) {
629 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
631 WREG32(R_000040_GEN_INT_CNTL, tmp);
632 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
633 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
634 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
635 if (ASIC_IS_DCE2(rdev))
636 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
640 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
642 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
643 uint32_t irq_mask = S_000044_SW_INT(1);
646 if (G_000044_DISPLAY_INT_STAT(irqs)) {
647 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
648 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
649 WREG32(R_006534_D1MODE_VBLANK_STATUS,
650 S_006534_D1MODE_VBLANK_ACK(1));
652 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
653 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
654 S_006D34_D2MODE_VBLANK_ACK(1));
656 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
657 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
658 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
659 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
661 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
662 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
663 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
664 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
667 rdev->irq.stat_regs.r500.disp_int = 0;
670 if (ASIC_IS_DCE2(rdev)) {
671 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
672 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
673 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
674 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
675 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
676 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
679 rdev->irq.stat_regs.r500.hdmi0_status = 0;
682 WREG32(R_000044_GEN_INT_STATUS, irqs);
684 return irqs & irq_mask;
687 void rs600_irq_disable(struct radeon_device *rdev)
689 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
690 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
691 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
692 WREG32(R_000040_GEN_INT_CNTL, 0);
693 WREG32(R_006540_DxMODE_INT_MASK, 0);
694 /* Wait and acknowledge irq */
699 int rs600_irq_process(struct radeon_device *rdev)
701 u32 status, msi_rearm;
702 bool queue_hotplug = false;
703 bool queue_hdmi = false;
705 status = rs600_irq_ack(rdev);
707 !rdev->irq.stat_regs.r500.disp_int &&
708 !rdev->irq.stat_regs.r500.hdmi0_status) {
712 rdev->irq.stat_regs.r500.disp_int ||
713 rdev->irq.stat_regs.r500.hdmi0_status) {
715 if (G_000044_SW_INT(status)) {
716 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
718 /* Vertical blank interrupts */
719 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
720 if (rdev->irq.crtc_vblank_int[0]) {
721 drm_handle_vblank(rdev->ddev, 0);
722 rdev->pm.vblank_sync = true;
723 wake_up(&rdev->irq.vblank_queue);
725 if (atomic_read(&rdev->irq.pflip[0]))
726 radeon_crtc_handle_flip(rdev, 0);
728 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
729 if (rdev->irq.crtc_vblank_int[1]) {
730 drm_handle_vblank(rdev->ddev, 1);
731 rdev->pm.vblank_sync = true;
732 wake_up(&rdev->irq.vblank_queue);
734 if (atomic_read(&rdev->irq.pflip[1]))
735 radeon_crtc_handle_flip(rdev, 1);
737 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
738 queue_hotplug = true;
741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
742 queue_hotplug = true;
745 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
747 DRM_DEBUG("HDMI0\n");
749 status = rs600_irq_ack(rdev);
752 schedule_work(&rdev->hotplug_work);
754 schedule_work(&rdev->audio_work);
755 if (rdev->msi_enabled) {
756 switch (rdev->family) {
760 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
761 WREG32(RADEON_BUS_CNTL, msi_rearm);
762 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
765 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
772 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
775 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
777 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
780 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
784 for (i = 0; i < rdev->usec_timeout; i++) {
785 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
792 static void rs600_gpu_init(struct radeon_device *rdev)
794 r420_pipes_init(rdev);
795 /* Wait for mc idle */
796 if (rs600_mc_wait_for_idle(rdev))
797 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
800 static void rs600_mc_init(struct radeon_device *rdev)
804 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
805 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
806 rdev->mc.vram_is_ddr = true;
807 rdev->mc.vram_width = 128;
808 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
810 rdev->mc.visible_vram_size = rdev->mc.aper_size;
811 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
812 base = RREG32_MC(R_000004_MC_FB_LOCATION);
813 base = G_000004_MC_FB_START(base) << 16;
814 radeon_vram_location(rdev, &rdev->mc, base);
815 rdev->mc.gtt_base_align = 0;
816 radeon_gtt_location(rdev, &rdev->mc);
817 radeon_update_bandwidth_info(rdev);
820 void rs600_bandwidth_update(struct radeon_device *rdev)
822 struct drm_display_mode *mode0 = NULL;
823 struct drm_display_mode *mode1 = NULL;
824 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
825 /* FIXME: implement full support */
827 radeon_update_display_priority(rdev);
829 if (rdev->mode_info.crtcs[0]->base.enabled)
830 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
831 if (rdev->mode_info.crtcs[1]->base.enabled)
832 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
834 rs690_line_buffer_adjust(rdev, mode0, mode1);
836 if (rdev->disp_priority == 2) {
837 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
838 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
839 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
840 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
841 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
842 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
843 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
844 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
848 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
853 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
854 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
855 S_000070_MC_IND_CITF_ARB0(1));
856 r = RREG32(R_000074_MC_IND_DATA);
857 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
861 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
865 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
866 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
867 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
868 WREG32(R_000074_MC_IND_DATA, v);
869 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
872 static void rs600_debugfs(struct radeon_device *rdev)
874 if (r100_debugfs_rbbm_init(rdev))
875 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
878 void rs600_set_safe_registers(struct radeon_device *rdev)
880 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
881 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
884 static void rs600_mc_program(struct radeon_device *rdev)
886 struct rv515_mc_save save;
888 /* Stops all mc clients */
889 rv515_mc_stop(rdev, &save);
891 /* Wait for mc idle */
892 if (rs600_mc_wait_for_idle(rdev))
893 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
895 /* FIXME: What does AGP means for such chipset ? */
896 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
897 WREG32_MC(R_000006_AGP_BASE, 0);
898 WREG32_MC(R_000007_AGP_BASE_2, 0);
900 WREG32_MC(R_000004_MC_FB_LOCATION,
901 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
902 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
903 WREG32(R_000134_HDP_FB_LOCATION,
904 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
906 rv515_mc_resume(rdev, &save);
909 static int rs600_startup(struct radeon_device *rdev)
913 rs600_mc_program(rdev);
915 rv515_clock_startup(rdev);
916 /* Initialize GPU configuration (# pipes, ...) */
917 rs600_gpu_init(rdev);
918 /* Initialize GART (initialize after TTM so we can allocate
919 * memory through TTM but finalize after TTM) */
920 r = rs600_gart_enable(rdev);
924 /* allocate wb buffer */
925 r = radeon_wb_init(rdev);
929 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
931 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
936 if (!rdev->irq.installed) {
937 r = radeon_irq_kms_init(rdev);
943 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
945 r = r100_cp_init(rdev, 1024 * 1024);
947 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
951 r = radeon_ib_pool_init(rdev);
953 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
957 r = r600_audio_init(rdev);
959 dev_err(rdev->dev, "failed initializing audio\n");
966 int rs600_resume(struct radeon_device *rdev)
970 /* Make sur GART are not working */
971 rs600_gart_disable(rdev);
972 /* Resume clock before doing reset */
973 rv515_clock_startup(rdev);
974 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
975 if (radeon_asic_reset(rdev)) {
976 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
977 RREG32(R_000E40_RBBM_STATUS),
978 RREG32(R_0007C0_CP_STAT));
981 atom_asic_init(rdev->mode_info.atom_context);
982 /* Resume clock after posting */
983 rv515_clock_startup(rdev);
984 /* Initialize surface registers */
985 radeon_surface_init(rdev);
987 rdev->accel_working = true;
988 r = rs600_startup(rdev);
990 rdev->accel_working = false;
995 int rs600_suspend(struct radeon_device *rdev)
997 r600_audio_fini(rdev);
998 r100_cp_disable(rdev);
999 radeon_wb_disable(rdev);
1000 rs600_irq_disable(rdev);
1001 rs600_gart_disable(rdev);
1005 void rs600_fini(struct radeon_device *rdev)
1007 r600_audio_fini(rdev);
1009 radeon_wb_fini(rdev);
1010 radeon_ib_pool_fini(rdev);
1011 radeon_gem_fini(rdev);
1012 rs600_gart_fini(rdev);
1013 radeon_irq_kms_fini(rdev);
1014 radeon_fence_driver_fini(rdev);
1015 radeon_bo_fini(rdev);
1016 radeon_atombios_fini(rdev);
1021 int rs600_init(struct radeon_device *rdev)
1026 rv515_vga_render_disable(rdev);
1027 /* Initialize scratch registers */
1028 radeon_scratch_init(rdev);
1029 /* Initialize surface registers */
1030 radeon_surface_init(rdev);
1031 /* restore some register to sane defaults */
1032 r100_restore_sanity(rdev);
1034 if (!radeon_get_bios(rdev)) {
1035 if (ASIC_IS_AVIVO(rdev))
1038 if (rdev->is_atom_bios) {
1039 r = radeon_atombios_init(rdev);
1043 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1046 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1047 if (radeon_asic_reset(rdev)) {
1049 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1050 RREG32(R_000E40_RBBM_STATUS),
1051 RREG32(R_0007C0_CP_STAT));
1053 /* check if cards are posted or not */
1054 if (radeon_boot_test_post_card(rdev) == false)
1057 /* Initialize clocks */
1058 radeon_get_clock_info(rdev->ddev);
1059 /* initialize memory controller */
1060 rs600_mc_init(rdev);
1061 rs600_debugfs(rdev);
1063 r = radeon_fence_driver_init(rdev);
1066 /* Memory manager */
1067 r = radeon_bo_init(rdev);
1070 r = rs600_gart_init(rdev);
1073 rs600_set_safe_registers(rdev);
1075 rdev->accel_working = true;
1076 r = rs600_startup(rdev);
1078 /* Somethings want wront with the accel init stop accel */
1079 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1081 radeon_wb_fini(rdev);
1082 radeon_ib_pool_fini(rdev);
1083 rs600_gart_fini(rdev);
1084 radeon_irq_kms_fini(rdev);
1085 rdev->accel_working = false;