drivers/gpu/drm/radeon/si.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "radeon_drm.h"
  32 #include "sid.h"
  33 #include "atom.h"
  34 #include "si_blit_shaders.h"
  35
  36 #define SI_PFP_UCODE_SIZE 2144
  37 #define SI_PM4_UCODE_SIZE 2144
  38 #define SI_CE_UCODE_SIZE 2144
  39 #define SI_RLC_UCODE_SIZE 2048
  40 #define SI_MC_UCODE_SIZE 7769
  41
  42 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
  43 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
  44 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
  45 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
  46 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
  47 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
  48 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
  49 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
  50 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
  51 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
  52 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
  53 MODULE_FIRMWARE("radeon/VERDE_me.bin");
  54 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
  55 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
  56 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
  57
  58 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  59 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  60 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  61
  62 /* get temperature in millidegrees */
  63 int si_get_temp(struct radeon_device *rdev)
  64 {
  65         u32 temp;
  66         int actual_temp = 0;
  67
  68         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
  69                 CTF_TEMP_SHIFT;
  70
  71         if (temp & 0x200)
  72                 actual_temp = 255;
  73         else
  74                 actual_temp = temp & 0x1ff;
  75
  76         actual_temp = (actual_temp * 1000);
  77
  78         return actual_temp;
  79 }
  80
  81 #define TAHITI_IO_MC_REGS_SIZE 36
  82
  83 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  84         {0x0000006f, 0x03044000},
  85         {0x00000070, 0x0480c018},
  86         {0x00000071, 0x00000040},
  87         {0x00000072, 0x01000000},
  88         {0x00000074, 0x000000ff},
  89         {0x00000075, 0x00143400},
  90         {0x00000076, 0x08ec0800},
  91         {0x00000077, 0x040000cc},
  92         {0x00000079, 0x00000000},
  93         {0x0000007a, 0x21000409},
  94         {0x0000007c, 0x00000000},
  95         {0x0000007d, 0xe8000000},
  96         {0x0000007e, 0x044408a8},
  97         {0x0000007f, 0x00000003},
  98         {0x00000080, 0x00000000},
  99         {0x00000081, 0x01000000},
 100         {0x00000082, 0x02000000},
 101         {0x00000083, 0x00000000},
 102         {0x00000084, 0xe3f3e4f4},
 103         {0x00000085, 0x00052024},
 104         {0x00000087, 0x00000000},
 105         {0x00000088, 0x66036603},
 106         {0x00000089, 0x01000000},
 107         {0x0000008b, 0x1c0a0000},
 108         {0x0000008c, 0xff010000},
 109         {0x0000008e, 0xffffefff},
 110         {0x0000008f, 0xfff3efff},
 111         {0x00000090, 0xfff3efbf},
 112         {0x00000094, 0x00101101},
 113         {0x00000095, 0x00000fff},
 114         {0x00000096, 0x00116fff},
 115         {0x00000097, 0x60010000},
 116         {0x00000098, 0x10010000},
 117         {0x00000099, 0x00006000},
 118         {0x0000009a, 0x00001000},
 119         {0x0000009f, 0x00a77400}
 120 };
 121
 122 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 123         {0x0000006f, 0x03044000},
 124         {0x00000070, 0x0480c018},
 125         {0x00000071, 0x00000040},
 126         {0x00000072, 0x01000000},
 127         {0x00000074, 0x000000ff},
 128         {0x00000075, 0x00143400},
 129         {0x00000076, 0x08ec0800},
 130         {0x00000077, 0x040000cc},
 131         {0x00000079, 0x00000000},
 132         {0x0000007a, 0x21000409},
 133         {0x0000007c, 0x00000000},
 134         {0x0000007d, 0xe8000000},
 135         {0x0000007e, 0x044408a8},
 136         {0x0000007f, 0x00000003},
 137         {0x00000080, 0x00000000},
 138         {0x00000081, 0x01000000},
 139         {0x00000082, 0x02000000},
 140         {0x00000083, 0x00000000},
 141         {0x00000084, 0xe3f3e4f4},
 142         {0x00000085, 0x00052024},
 143         {0x00000087, 0x00000000},
 144         {0x00000088, 0x66036603},
 145         {0x00000089, 0x01000000},
 146         {0x0000008b, 0x1c0a0000},
 147         {0x0000008c, 0xff010000},
 148         {0x0000008e, 0xffffefff},
 149         {0x0000008f, 0xfff3efff},
 150         {0x00000090, 0xfff3efbf},
 151         {0x00000094, 0x00101101},
 152         {0x00000095, 0x00000fff},
 153         {0x00000096, 0x00116fff},
 154         {0x00000097, 0x60010000},
 155         {0x00000098, 0x10010000},
 156         {0x00000099, 0x00006000},
 157         {0x0000009a, 0x00001000},
 158         {0x0000009f, 0x00a47400}
 159 };
 160
 161 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 162         {0x0000006f, 0x03044000},
 163         {0x00000070, 0x0480c018},
 164         {0x00000071, 0x00000040},
 165         {0x00000072, 0x01000000},
 166         {0x00000074, 0x000000ff},
 167         {0x00000075, 0x00143400},
 168         {0x00000076, 0x08ec0800},
 169         {0x00000077, 0x040000cc},
 170         {0x00000079, 0x00000000},
 171         {0x0000007a, 0x21000409},
 172         {0x0000007c, 0x00000000},
 173         {0x0000007d, 0xe8000000},
 174         {0x0000007e, 0x044408a8},
 175         {0x0000007f, 0x00000003},
 176         {0x00000080, 0x00000000},
 177         {0x00000081, 0x01000000},
 178         {0x00000082, 0x02000000},
 179         {0x00000083, 0x00000000},
 180         {0x00000084, 0xe3f3e4f4},
 181         {0x00000085, 0x00052024},
 182         {0x00000087, 0x00000000},
 183         {0x00000088, 0x66036603},
 184         {0x00000089, 0x01000000},
 185         {0x0000008b, 0x1c0a0000},
 186         {0x0000008c, 0xff010000},
 187         {0x0000008e, 0xffffefff},
 188         {0x0000008f, 0xfff3efff},
 189         {0x00000090, 0xfff3efbf},
 190         {0x00000094, 0x00101101},
 191         {0x00000095, 0x00000fff},
 192         {0x00000096, 0x00116fff},
 193         {0x00000097, 0x60010000},
 194         {0x00000098, 0x10010000},
 195         {0x00000099, 0x00006000},
 196         {0x0000009a, 0x00001000},
 197         {0x0000009f, 0x00a37400}
 198 };
 199
 200 /* ucode loading */
 201 static int si_mc_load_microcode(struct radeon_device *rdev)
 202 {
 203         const __be32 *fw_data;
 204         u32 running, blackout = 0;
 205         u32 *io_mc_regs;
 206         int i, ucode_size, regs_size;
 207
 208         if (!rdev->mc_fw)
 209                 return -EINVAL;
 210
 211         switch (rdev->family) {
 212         case CHIP_TAHITI:
 213                 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
 214                 ucode_size = SI_MC_UCODE_SIZE;
 215                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 216                 break;
 217         case CHIP_PITCAIRN:
 218                 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
 219                 ucode_size = SI_MC_UCODE_SIZE;
 220                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 221                 break;
 222         case CHIP_VERDE:
 223         default:
 224                 io_mc_regs = (u32 *)&verde_io_mc_regs;
 225                 ucode_size = SI_MC_UCODE_SIZE;
 226                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 227                 break;
 228         }
 229
 230         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 231
 232         if (running == 0) {
 233                 if (running) {
 234                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 235                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
 236                 }
 237
 238                 /* reset the engine and set to writable */
 239                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 240                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 241
 242                 /* load mc io regs */
 243                 for (i = 0; i < regs_size; i++) {
 244                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 245                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 246                 }
 247                 /* load the MC ucode */
 248                 fw_data = (const __be32 *)rdev->mc_fw->data;
 249                 for (i = 0; i < ucode_size; i++)
 250                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 251
 252                 /* put the engine back into the active state */
 253                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 254                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 255                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 256
 257                 /* wait for training to complete */
 258                 for (i = 0; i < rdev->usec_timeout; i++) {
 259                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
 260                                 break;
 261                         udelay(1);
 262                 }
 263                 for (i = 0; i < rdev->usec_timeout; i++) {
 264                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
 265                                 break;
 266                         udelay(1);
 267                 }
 268
 269                 if (running)
 270                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 271         }
 272
 273         return 0;
 274 }
 275
 276 static int si_init_microcode(struct radeon_device *rdev)
 277 {
 278         struct platform_device *pdev;
 279         const char *chip_name;
 280         const char *rlc_chip_name;
 281         size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
 282         char fw_name[30];
 283         int err;
 284
 285         DRM_DEBUG("\n");
 286
 287         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 288         err = IS_ERR(pdev);
 289         if (err) {
 290                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 291                 return -EINVAL;
 292         }
 293
 294         switch (rdev->family) {
 295         case CHIP_TAHITI:
 296                 chip_name = "TAHITI";
 297                 rlc_chip_name = "TAHITI";
 298                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 299                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 300                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 301                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 302                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 303                 break;
 304         case CHIP_PITCAIRN:
 305                 chip_name = "PITCAIRN";
 306                 rlc_chip_name = "PITCAIRN";
 307                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 308                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 309                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 310                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 311                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 312                 break;
 313         case CHIP_VERDE:
 314                 chip_name = "VERDE";
 315                 rlc_chip_name = "VERDE";
 316                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 317                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 318                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 319                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 320                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 321                 break;
 322         default: BUG();
 323         }
 324
 325         DRM_INFO("Loading %s Microcode\n", chip_name);
 326
 327         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 328         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 329         if (err)
 330                 goto out;
 331         if (rdev->pfp_fw->size != pfp_req_size) {
 332                 printk(KERN_ERR
 333                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 334                        rdev->pfp_fw->size, fw_name);
 335                 err = -EINVAL;
 336                 goto out;
 337         }
 338
 339         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 340         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 341         if (err)
 342                 goto out;
 343         if (rdev->me_fw->size != me_req_size) {
 344                 printk(KERN_ERR
 345                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 346                        rdev->me_fw->size, fw_name);
 347                 err = -EINVAL;
 348         }
 349
 350         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 351         err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
 352         if (err)
 353                 goto out;
 354         if (rdev->ce_fw->size != ce_req_size) {
 355                 printk(KERN_ERR
 356                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 357                        rdev->ce_fw->size, fw_name);
 358                 err = -EINVAL;
 359         }
 360
 361         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 362         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 363         if (err)
 364                 goto out;
 365         if (rdev->rlc_fw->size != rlc_req_size) {
 366                 printk(KERN_ERR
 367                        "si_rlc: Bogus length %zu in firmware \"%s\"\n",
 368                        rdev->rlc_fw->size, fw_name);
 369                 err = -EINVAL;
 370         }
 371
 372         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 373         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 374         if (err)
 375                 goto out;
 376         if (rdev->mc_fw->size != mc_req_size) {
 377                 printk(KERN_ERR
 378                        "si_mc: Bogus length %zu in firmware \"%s\"\n",
 379                        rdev->mc_fw->size, fw_name);
 380                 err = -EINVAL;
 381         }
 382
 383 out:
 384         platform_device_unregister(pdev);
 385
 386         if (err) {
 387                 if (err != -EINVAL)
 388                         printk(KERN_ERR
 389                                "si_cp: Failed to load firmware \"%s\"\n",
 390                                fw_name);
 391                 release_firmware(rdev->pfp_fw);
 392                 rdev->pfp_fw = NULL;
 393                 release_firmware(rdev->me_fw);
 394                 rdev->me_fw = NULL;
 395                 release_firmware(rdev->ce_fw);
 396                 rdev->ce_fw = NULL;
 397                 release_firmware(rdev->rlc_fw);
 398                 rdev->rlc_fw = NULL;
 399                 release_firmware(rdev->mc_fw);
 400                 rdev->mc_fw = NULL;
 401         }
 402         return err;
 403 }
 404
 405 /* watermark setup */
 406 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
 407                                    struct radeon_crtc *radeon_crtc,
 408                                    struct drm_display_mode *mode,
 409                                    struct drm_display_mode *other_mode)
 410 {
 411         u32 tmp;
 412         /*
 413          * Line Buffer Setup
 414          * There are 3 line buffers, each one shared by 2 display controllers.
 415          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 416          * the display controllers.  The paritioning is done via one of four
 417          * preset allocations specified in bits 21:20:
 418          *  0 - half lb
 419          *  2 - whole lb, other crtc must be disabled
 420          */
 421         /* this can get tricky if we have two large displays on a paired group
 422          * of crtcs.  Ideally for multiple large displays we'd assign them to
 423          * non-linked crtcs for maximum line buffer allocation.
 424          */
 425         if (radeon_crtc->base.enabled && mode) {
 426                 if (other_mode)
 427                         tmp = 0; /* 1/2 */
 428                 else
 429                         tmp = 2; /* whole */
 430         } else
 431                 tmp = 0;
 432
 433         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
 434                DC_LB_MEMORY_CONFIG(tmp));
 435
 436         if (radeon_crtc->base.enabled && mode) {
 437                 switch (tmp) {
 438                 case 0:
 439                 default:
 440                         return 4096 * 2;
 441                 case 2:
 442                         return 8192 * 2;
 443                 }
 444         }
 445
 446         /* controller not enabled, so no lb used */
 447         return 0;
 448 }
 449
 450 static u32 dce6_get_number_of_dram_channels(struct radeon_device *rdev)
 451 {
 452         u32 tmp = RREG32(MC_SHARED_CHMAP);
 453
 454         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 455         case 0:
 456         default:
 457                 return 1;
 458         case 1:
 459                 return 2;
 460         case 2:
 461                 return 4;
 462         case 3:
 463                 return 8;
 464         case 4:
 465                 return 3;
 466         case 5:
 467                 return 6;
 468         case 6:
 469                 return 10;
 470         case 7:
 471                 return 12;
 472         case 8:
 473                 return 16;
 474         }
 475 }
 476
 477 struct dce6_wm_params {
 478         u32 dram_channels; /* number of dram channels */
 479         u32 yclk;          /* bandwidth per dram data pin in kHz */
 480         u32 sclk;          /* engine clock in kHz */
 481         u32 disp_clk;      /* display clock in kHz */
 482         u32 src_width;     /* viewport width */
 483         u32 active_time;   /* active display time in ns */
 484         u32 blank_time;    /* blank time in ns */
 485         bool interlaced;    /* mode is interlaced */
 486         fixed20_12 vsc;    /* vertical scale ratio */
 487         u32 num_heads;     /* number of active crtcs */
 488         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 489         u32 lb_size;       /* line buffer allocated to pipe */
 490         u32 vtaps;         /* vertical scaler taps */
 491 };
 492
 493 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
 494 {
 495         /* Calculate raw DRAM Bandwidth */
 496         fixed20_12 dram_efficiency; /* 0.7 */
 497         fixed20_12 yclk, dram_channels, bandwidth;
 498         fixed20_12 a;
 499
 500         a.full = dfixed_const(1000);
 501         yclk.full = dfixed_const(wm->yclk);
 502         yclk.full = dfixed_div(yclk, a);
 503         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 504         a.full = dfixed_const(10);
 505         dram_efficiency.full = dfixed_const(7);
 506         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 507         bandwidth.full = dfixed_mul(dram_channels, yclk);
 508         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 509
 510         return dfixed_trunc(bandwidth);
 511 }
 512
 513 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 514 {
 515         /* Calculate DRAM Bandwidth and the part allocated to display. */
 516         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 517         fixed20_12 yclk, dram_channels, bandwidth;
 518         fixed20_12 a;
 519
 520         a.full = dfixed_const(1000);
 521         yclk.full = dfixed_const(wm->yclk);
 522         yclk.full = dfixed_div(yclk, a);
 523         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 524         a.full = dfixed_const(10);
 525         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 526         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 527         bandwidth.full = dfixed_mul(dram_channels, yclk);
 528         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 529
 530         return dfixed_trunc(bandwidth);
 531 }
 532
 533 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
 534 {
 535         /* Calculate the display Data return Bandwidth */
 536         fixed20_12 return_efficiency; /* 0.8 */
 537         fixed20_12 sclk, bandwidth;
 538         fixed20_12 a;
 539
 540         a.full = dfixed_const(1000);
 541         sclk.full = dfixed_const(wm->sclk);
 542         sclk.full = dfixed_div(sclk, a);
 543         a.full = dfixed_const(10);
 544         return_efficiency.full = dfixed_const(8);
 545         return_efficiency.full = dfixed_div(return_efficiency, a);
 546         a.full = dfixed_const(32);
 547         bandwidth.full = dfixed_mul(a, sclk);
 548         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 549
 550         return dfixed_trunc(bandwidth);
 551 }
 552
 553 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
 554 {
 555         return 32;
 556 }
 557
 558 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
 559 {
 560         /* Calculate the DMIF Request Bandwidth */
 561         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 562         fixed20_12 disp_clk, sclk, bandwidth;
 563         fixed20_12 a, b1, b2;
 564         u32 min_bandwidth;
 565
 566         a.full = dfixed_const(1000);
 567         disp_clk.full = dfixed_const(wm->disp_clk);
 568         disp_clk.full = dfixed_div(disp_clk, a);
 569         a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
 570         b1.full = dfixed_mul(a, disp_clk);
 571
 572         a.full = dfixed_const(1000);
 573         sclk.full = dfixed_const(wm->sclk);
 574         sclk.full = dfixed_div(sclk, a);
 575         a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
 576         b2.full = dfixed_mul(a, sclk);
 577
 578         a.full = dfixed_const(10);
 579         disp_clk_request_efficiency.full = dfixed_const(8);
 580         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 581
 582         min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
 583
 584         a.full = dfixed_const(min_bandwidth);
 585         bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
 586
 587         return dfixed_trunc(bandwidth);
 588 }
 589
 590 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
 591 {
 592         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 593         u32 dram_bandwidth = dce6_dram_bandwidth(wm);
 594         u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
 595         u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
 596
 597         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 598 }
 599
 600 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
 601 {
 602         /* Calculate the display mode Average Bandwidth
 603          * DisplayMode should contain the source and destination dimensions,
 604          * timing, etc.
 605          */
 606         fixed20_12 bpp;
 607         fixed20_12 line_time;
 608         fixed20_12 src_width;
 609         fixed20_12 bandwidth;
 610         fixed20_12 a;
 611
 612         a.full = dfixed_const(1000);
 613         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 614         line_time.full = dfixed_div(line_time, a);
 615         bpp.full = dfixed_const(wm->bytes_per_pixel);
 616         src_width.full = dfixed_const(wm->src_width);
 617         bandwidth.full = dfixed_mul(src_width, bpp);
 618         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 619         bandwidth.full = dfixed_div(bandwidth, line_time);
 620
 621         return dfixed_trunc(bandwidth);
 622 }
 623
 624 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
 625 {
 626         /* First calcualte the latency in ns */
 627         u32 mc_latency = 2000; /* 2000 ns. */
 628         u32 available_bandwidth = dce6_available_bandwidth(wm);
 629         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 630         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 631         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 632         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 633                 (wm->num_heads * cursor_line_pair_return_time);
 634         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 635         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 636         u32 tmp, dmif_size = 12288;
 637         fixed20_12 a, b, c;
 638
 639         if (wm->num_heads == 0)
 640                 return 0;
 641
 642         a.full = dfixed_const(2);
 643         b.full = dfixed_const(1);
 644         if ((wm->vsc.full > a.full) ||
 645             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 646             (wm->vtaps >= 5) ||
 647             ((wm->vsc.full >= a.full) && wm->interlaced))
 648                 max_src_lines_per_dst_line = 4;
 649         else
 650                 max_src_lines_per_dst_line = 2;
 651
 652         a.full = dfixed_const(available_bandwidth);
 653         b.full = dfixed_const(wm->num_heads);
 654         a.full = dfixed_div(a, b);
 655
 656         b.full = dfixed_const(mc_latency + 512);
 657         c.full = dfixed_const(wm->disp_clk);
 658         b.full = dfixed_div(b, c);
 659
 660         c.full = dfixed_const(dmif_size);
 661         b.full = dfixed_div(c, b);
 662
 663         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
 664
 665         b.full = dfixed_const(1000);
 666         c.full = dfixed_const(wm->disp_clk);
 667         b.full = dfixed_div(c, b);
 668         c.full = dfixed_const(wm->bytes_per_pixel);
 669         b.full = dfixed_mul(b, c);
 670
 671         lb_fill_bw = min(tmp, dfixed_trunc(b));
 672
 673         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 674         b.full = dfixed_const(1000);
 675         c.full = dfixed_const(lb_fill_bw);
 676         b.full = dfixed_div(c, b);
 677         a.full = dfixed_div(a, b);
 678         line_fill_time = dfixed_trunc(a);
 679
 680         if (line_fill_time < wm->active_time)
 681                 return latency;
 682         else
 683                 return latency + (line_fill_time - wm->active_time);
 684
 685 }
 686
 687 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 688 {
 689         if (dce6_average_bandwidth(wm) <=
 690             (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
 691                 return true;
 692         else
 693                 return false;
 694 };
 695
 696 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
 697 {
 698         if (dce6_average_bandwidth(wm) <=
 699             (dce6_available_bandwidth(wm) / wm->num_heads))
 700                 return true;
 701         else
 702                 return false;
 703 };
 704
 705 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
 706 {
 707         u32 lb_partitions = wm->lb_size / wm->src_width;
 708         u32 line_time = wm->active_time + wm->blank_time;
 709         u32 latency_tolerant_lines;
 710         u32 latency_hiding;
 711         fixed20_12 a;
 712
 713         a.full = dfixed_const(1);
 714         if (wm->vsc.full > a.full)
 715                 latency_tolerant_lines = 1;
 716         else {
 717                 if (lb_partitions <= (wm->vtaps + 1))
 718                         latency_tolerant_lines = 1;
 719                 else
 720                         latency_tolerant_lines = 2;
 721         }
 722
 723         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 724
 725         if (dce6_latency_watermark(wm) <= latency_hiding)
 726                 return true;
 727         else
 728                 return false;
 729 }
 730
 731 static void dce6_program_watermarks(struct radeon_device *rdev,
 732                                          struct radeon_crtc *radeon_crtc,
 733                                          u32 lb_size, u32 num_heads)
 734 {
 735         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 736         struct dce6_wm_params wm;
 737         u32 pixel_period;
 738         u32 line_time = 0;
 739         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 740         u32 priority_a_mark = 0, priority_b_mark = 0;
 741         u32 priority_a_cnt = PRIORITY_OFF;
 742         u32 priority_b_cnt = PRIORITY_OFF;
 743         u32 tmp, arb_control3;
 744         fixed20_12 a, b, c;
 745
 746         if (radeon_crtc->base.enabled && num_heads && mode) {
 747                 pixel_period = 1000000 / (u32)mode->clock;
 748                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 749                 priority_a_cnt = 0;
 750                 priority_b_cnt = 0;
 751
 752                 wm.yclk = rdev->pm.current_mclk * 10;
 753                 wm.sclk = rdev->pm.current_sclk * 10;
 754                 wm.disp_clk = mode->clock;
 755                 wm.src_width = mode->crtc_hdisplay;
 756                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 757                 wm.blank_time = line_time - wm.active_time;
 758                 wm.interlaced = false;
 759                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 760                         wm.interlaced = true;
 761                 wm.vsc = radeon_crtc->vsc;
 762                 wm.vtaps = 1;
 763                 if (radeon_crtc->rmx_type != RMX_OFF)
 764                         wm.vtaps = 2;
 765                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 766                 wm.lb_size = lb_size;
 767                 wm.dram_channels = dce6_get_number_of_dram_channels(rdev);
 768                 wm.num_heads = num_heads;
 769
 770                 /* set for high clocks */
 771                 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
 772                 /* set for low clocks */
 773                 /* wm.yclk = low clk; wm.sclk = low clk */
 774                 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
 775
 776                 /* possibly force display priority to high */
 777                 /* should really do this at mode validation time... */
 778                 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 779                     !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
 780                     !dce6_check_latency_hiding(&wm) ||
 781                     (rdev->disp_priority == 2)) {
 782                         DRM_DEBUG_KMS("force priority to high\n");
 783                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 784                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 785                 }
 786
 787                 a.full = dfixed_const(1000);
 788                 b.full = dfixed_const(mode->clock);
 789                 b.full = dfixed_div(b, a);
 790                 c.full = dfixed_const(latency_watermark_a);
 791                 c.full = dfixed_mul(c, b);
 792                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 793                 c.full = dfixed_div(c, a);
 794                 a.full = dfixed_const(16);
 795                 c.full = dfixed_div(c, a);
 796                 priority_a_mark = dfixed_trunc(c);
 797                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 798
 799                 a.full = dfixed_const(1000);
 800                 b.full = dfixed_const(mode->clock);
 801                 b.full = dfixed_div(b, a);
 802                 c.full = dfixed_const(latency_watermark_b);
 803                 c.full = dfixed_mul(c, b);
 804                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 805                 c.full = dfixed_div(c, a);
 806                 a.full = dfixed_const(16);
 807                 c.full = dfixed_div(c, a);
 808                 priority_b_mark = dfixed_trunc(c);
 809                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 810         }
 811
 812         /* select wm A */
 813         arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
 814         tmp = arb_control3;
 815         tmp &= ~LATENCY_WATERMARK_MASK(3);
 816         tmp |= LATENCY_WATERMARK_MASK(1);
 817         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
 818         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
 819                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 820                 LATENCY_HIGH_WATERMARK(line_time)));
 821         /* select wm B */
 822         tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
 823         tmp &= ~LATENCY_WATERMARK_MASK(3);
 824         tmp |= LATENCY_WATERMARK_MASK(2);
 825         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
 826         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
 827                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 828                 LATENCY_HIGH_WATERMARK(line_time)));
 829         /* restore original selection */
 830         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
 831
 832         /* write the priority marks */
 833         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 834         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 835
 836 }
 837
 838 void dce6_bandwidth_update(struct radeon_device *rdev)
 839 {
 840         struct drm_display_mode *mode0 = NULL;
 841         struct drm_display_mode *mode1 = NULL;
 842         u32 num_heads = 0, lb_size;
 843         int i;
 844
 845         radeon_update_display_priority(rdev);
 846
 847         for (i = 0; i < rdev->num_crtc; i++) {
 848                 if (rdev->mode_info.crtcs[i]->base.enabled)
 849                         num_heads++;
 850         }
 851         for (i = 0; i < rdev->num_crtc; i += 2) {
 852                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 853                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 854                 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 855                 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 856                 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 857                 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 858         }
 859 }
 860
 861 /*
 862  * Core functions
 863  */
 864 static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 865                                            u32 num_tile_pipes,
 866                                            u32 num_backends_per_asic,
 867                                            u32 *backend_disable_mask_per_asic,
 868                                            u32 num_shader_engines)
 869 {
 870         u32 backend_map = 0;
 871         u32 enabled_backends_mask = 0;
 872         u32 enabled_backends_count = 0;
 873         u32 num_backends_per_se;
 874         u32 cur_pipe;
 875         u32 swizzle_pipe[SI_MAX_PIPES];
 876         u32 cur_backend = 0;
 877         u32 i;
 878         bool force_no_swizzle;
 879
 880         /* force legal values */
 881         if (num_tile_pipes < 1)
 882                 num_tile_pipes = 1;
 883         if (num_tile_pipes > rdev->config.si.max_tile_pipes)
 884                 num_tile_pipes = rdev->config.si.max_tile_pipes;
 885         if (num_shader_engines < 1)
 886                 num_shader_engines = 1;
 887         if (num_shader_engines > rdev->config.si.max_shader_engines)
 888                 num_shader_engines = rdev->config.si.max_shader_engines;
 889         if (num_backends_per_asic < num_shader_engines)
 890                 num_backends_per_asic = num_shader_engines;
 891         if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
 892                 num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
 893
 894         /* make sure we have the same number of backends per se */
 895         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 896         /* set up the number of backends per se */
 897         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 898         if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
 899                 num_backends_per_se = rdev->config.si.max_backends_per_se;
 900                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 901         }
 902
 903         /* create enable mask and count for enabled backends */
 904         for (i = 0; i < SI_MAX_BACKENDS; ++i) {
 905                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 906                         enabled_backends_mask |= (1 << i);
 907                         ++enabled_backends_count;
 908                 }
 909                 if (enabled_backends_count == num_backends_per_asic)
 910                         break;
 911         }
 912
 913         /* force the backends mask to match the current number of backends */
 914         if (enabled_backends_count != num_backends_per_asic) {
 915                 u32 this_backend_enabled;
 916                 u32 shader_engine;
 917                 u32 backend_per_se;
 918
 919                 enabled_backends_mask = 0;
 920                 enabled_backends_count = 0;
 921                 *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
 922                 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
 923                         /* calc the current se */
 924                         shader_engine = i / rdev->config.si.max_backends_per_se;
 925                         /* calc the backend per se */
 926                         backend_per_se = i % rdev->config.si.max_backends_per_se;
 927                         /* default to not enabled */
 928                         this_backend_enabled = 0;
 929                         if ((shader_engine < num_shader_engines) &&
 930                             (backend_per_se < num_backends_per_se))
 931                                 this_backend_enabled = 1;
 932                         if (this_backend_enabled) {
 933                                 enabled_backends_mask |= (1 << i);
 934                                 *backend_disable_mask_per_asic &= ~(1 << i);
 935                                 ++enabled_backends_count;
 936                         }
 937                 }
 938         }
 939
 940
 941         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
 942         switch (rdev->family) {
 943         case CHIP_TAHITI:
 944         case CHIP_PITCAIRN:
 945         case CHIP_VERDE:
 946                 force_no_swizzle = true;
 947                 break;
 948         default:
 949                 force_no_swizzle = false;
 950                 break;
 951         }
 952         if (force_no_swizzle) {
 953                 bool last_backend_enabled = false;
 954
 955                 force_no_swizzle = false;
 956                 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
 957                         if (((enabled_backends_mask >> i) & 1) == 1) {
 958                                 if (last_backend_enabled)
 959                                         force_no_swizzle = true;
 960                                 last_backend_enabled = true;
 961                         } else
 962                                 last_backend_enabled = false;
 963                 }
 964         }
 965
 966         switch (num_tile_pipes) {
 967         case 1:
 968         case 3:
 969         case 5:
 970         case 7:
 971                 DRM_ERROR("odd number of pipes!\n");
 972                 break;
 973         case 2:
 974                 swizzle_pipe[0] = 0;
 975                 swizzle_pipe[1] = 1;
 976                 break;
 977         case 4:
 978                 if (force_no_swizzle) {
 979                         swizzle_pipe[0] = 0;
 980                         swizzle_pipe[1] = 1;
 981                         swizzle_pipe[2] = 2;
 982                         swizzle_pipe[3] = 3;
 983                 } else {
 984                         swizzle_pipe[0] = 0;
 985                         swizzle_pipe[1] = 2;
 986                         swizzle_pipe[2] = 1;
 987                         swizzle_pipe[3] = 3;
 988                 }
 989                 break;
 990         case 6:
 991                 if (force_no_swizzle) {
 992                         swizzle_pipe[0] = 0;
 993                         swizzle_pipe[1] = 1;
 994                         swizzle_pipe[2] = 2;
 995                         swizzle_pipe[3] = 3;
 996                         swizzle_pipe[4] = 4;
 997                         swizzle_pipe[5] = 5;
 998                 } else {
 999                         swizzle_pipe[0] = 0;
1000                         swizzle_pipe[1] = 2;
1001                         swizzle_pipe[2] = 4;
1002                         swizzle_pipe[3] = 1;
1003                         swizzle_pipe[4] = 3;
1004                         swizzle_pipe[5] = 5;
1005                 }
1006                 break;
1007         case 8:
1008                 if (force_no_swizzle) {
1009                         swizzle_pipe[0] = 0;
1010                         swizzle_pipe[1] = 1;
1011                         swizzle_pipe[2] = 2;
1012                         swizzle_pipe[3] = 3;
1013                         swizzle_pipe[4] = 4;
1014                         swizzle_pipe[5] = 5;
1015                         swizzle_pipe[6] = 6;
1016                         swizzle_pipe[7] = 7;
1017                 } else {
1018                         swizzle_pipe[0] = 0;
1019                         swizzle_pipe[1] = 2;
1020                         swizzle_pipe[2] = 4;
1021                         swizzle_pipe[3] = 6;
1022                         swizzle_pipe[4] = 1;
1023                         swizzle_pipe[5] = 3;
1024                         swizzle_pipe[6] = 5;
1025                         swizzle_pipe[7] = 7;
1026                 }
1027                 break;
1028         }
1029
1030         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1031                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1032                         cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1033
1034                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1035
1036                 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1037         }
1038
1039         return backend_map;
1040 }
1041
1042 static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
1043                                         u32 disable_mask_per_se,
1044                                         u32 max_disable_mask_per_se,
1045                                         u32 num_shader_engines)
1046 {
1047         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
1048         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
1049
1050         if (num_shader_engines == 1)
1051                 return disable_mask_per_asic;
1052         else if (num_shader_engines == 2)
1053                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
1054         else
1055                 return 0xffffffff;
1056 }
1057
1058 static void si_tiling_mode_table_init(struct radeon_device *rdev)
1059 {
1060         const u32 num_tile_mode_states = 32;
1061         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1062
1063         switch (rdev->config.si.mem_row_size_in_kb) {
1064         case 1:
1065                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1066                 break;
1067         case 2:
1068         default:
1069                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1070                 break;
1071         case 4:
1072                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1073                 break;
1074         }
1075
1076         if ((rdev->family == CHIP_TAHITI) ||
1077             (rdev->family == CHIP_PITCAIRN)) {
1078                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1079                         switch (reg_offset) {
1080                         case 0:  /* non-AA compressed depth or any compressed stencil */
1081                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1082                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1083                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1084                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1085                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1086                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1087                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1088                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1089                                 break;
1090                         case 1:  /* 2xAA/4xAA compressed depth only */
1091                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1092                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1093                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1094                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1095                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1096                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1097                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1098                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1099                                 break;
1100                         case 2:  /* 8xAA compressed depth only */
1101                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1102                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1103                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1104                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1105                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1106                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1108                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1109                                 break;
1110                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1111                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1112                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1113                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1114                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1115                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1116                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1117                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1118                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1119                                 break;
1120                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1121                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1122                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1123                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1125                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1126                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1128                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1129                                 break;
1130                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1131                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1133                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134                                                  TILE_SPLIT(split_equal_to_row_size) |
1135                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1136                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1137                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1138                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1139                                 break;
1140                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1141                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1142                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1143                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144                                                  TILE_SPLIT(split_equal_to_row_size) |
1145                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1146                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1148                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1149                                 break;
1150                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1151                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1153                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1154                                                  TILE_SPLIT(split_equal_to_row_size) |
1155                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1156                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1159                                 break;
1160                         case 8:  /* 1D and 1D Array Surfaces */
1161                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1162                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1163                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1164                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1165                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1166                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1167                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1168                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1169                                 break;
1170                         case 9:  /* Displayable maps. */
1171                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1172                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1173                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1174                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1175                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1176                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1178                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1179                                 break;
1180                         case 10:  /* Display 8bpp. */
1181                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1182                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1183                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1184                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1185                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1186                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1187                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1188                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1189                                 break;
1190                         case 11:  /* Display 16bpp. */
1191                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1192                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1193                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1194                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1195                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1196                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1199                                 break;
1200                         case 12:  /* Display 32bpp. */
1201                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1203                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1205                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1206                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1207                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1208                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1209                                 break;
1210                         case 13:  /* Thin. */
1211                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1212                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1213                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1214                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1215                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1216                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1217                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1218                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1219                                 break;
1220                         case 14:  /* Thin 8 bpp. */
1221                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1222                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1223                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1224                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1225                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1226                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1227                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1228                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1229                                 break;
1230                         case 15:  /* Thin 16 bpp. */
1231                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1233                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1234                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1235                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1236                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1237                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1238                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1239                                 break;
1240                         case 16:  /* Thin 32 bpp. */
1241                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1243                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1244                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1245                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1246                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1247                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1248                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1249                                 break;
1250                         case 17:  /* Thin 64 bpp. */
1251                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1252                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1253                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1254                                                  TILE_SPLIT(split_equal_to_row_size) |
1255                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1256                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1257                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1258                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1259                                 break;
1260                         case 21:  /* 8 bpp PRT. */
1261                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1262                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1263                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1264                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1265                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1266                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1267                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1268                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1269                                 break;
1270                         case 22:  /* 16 bpp PRT */
1271                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1273                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1274                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1275                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1276                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1277                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1278                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1279                                 break;
1280                         case 23:  /* 32 bpp PRT */
1281                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1282                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1283                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1284                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1285                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1286                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1287                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1288                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1289                                 break;
1290                         case 24:  /* 64 bpp PRT */
1291                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1292                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1293                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1294                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1295                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1296                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1297                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1298                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1299                                 break;
1300                         case 25:  /* 128 bpp PRT */
1301                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1302                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1303                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1304                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1305                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
1306                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1307                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1308                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1309                                 break;
1310                         default:
1311                                 gb_tile_moden = 0;
1312                                 break;
1313                         }
1314                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1315                 }
1316         } else if (rdev->family == CHIP_VERDE) {
1317                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1318                         switch (reg_offset) {
1319                         case 0:  /* non-AA compressed depth or any compressed stencil */
1320                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1321                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1322                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1323                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1324                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1325                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1326                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1327                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1328                                 break;
1329                         case 1:  /* 2xAA/4xAA compressed depth only */
1330                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1331                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1332                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1333                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1334                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1335                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1337                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1338                                 break;
1339                         case 2:  /* 8xAA compressed depth only */
1340                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1341                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1342                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1343                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1344                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1345                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1346                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1347                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1348                                 break;
1349                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1350                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1351                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1352                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1353                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1354                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1355                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1357                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1358                                 break;
1359                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1360                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1361                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1362                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1363                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1364                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1365                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1366                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1367                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1368                                 break;
1369                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1370                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1371                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1372                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1373                                                  TILE_SPLIT(split_equal_to_row_size) |
1374                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1375                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1377                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1378                                 break;
1379                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1380                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1381                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1382                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1383                                                  TILE_SPLIT(split_equal_to_row_size) |
1384                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1385                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1386                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1387                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1388                                 break;
1389                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1390                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1392                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1393                                                  TILE_SPLIT(split_equal_to_row_size) |
1394                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1395                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1396                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1397                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1398                                 break;
1399                         case 8:  /* 1D and 1D Array Surfaces */
1400                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1401                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1402                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1403                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1404                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1405                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1406                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1407                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1408                                 break;
1409                         case 9:  /* Displayable maps. */
1410                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1412                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1413                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1414                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1415                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1416                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1417                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1418                                 break;
1419                         case 10:  /* Display 8bpp. */
1420                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1421                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1422                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1423                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1424                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1425                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1426                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1427                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1428                                 break;
1429                         case 11:  /* Display 16bpp. */
1430                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1431                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1432                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1433                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1434                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1435                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1436                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1437                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1438                                 break;
1439                         case 12:  /* Display 32bpp. */
1440                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1441                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1443                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1444                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1445                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1446                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1447                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1448                                 break;
1449                         case 13:  /* Thin. */
1450                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1451                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1452                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1453                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1454                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1455                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1456                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1457                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1458                                 break;
1459                         case 14:  /* Thin 8 bpp. */
1460                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1461                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1462                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1463                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1464                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1465                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1466                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1467                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1468                                 break;
1469                         case 15:  /* Thin 16 bpp. */
1470                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1471                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1472                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1473                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1474                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1475                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1476                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1477                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1478                                 break;
1479                         case 16:  /* Thin 32 bpp. */
1480                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1481                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1482                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1483                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1484                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1485                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1486                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1487                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1488                                 break;
1489                         case 17:  /* Thin 64 bpp. */
1490                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1491                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1492                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1493                                                  TILE_SPLIT(split_equal_to_row_size) |
1494                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1495                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1496                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1497                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1498                                 break;
1499                         case 21:  /* 8 bpp PRT. */
1500                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1501                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1502                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1503                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1504                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1505                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1506                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1507                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1508                                 break;
1509                         case 22:  /* 16 bpp PRT */
1510                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1511                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1512                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1513                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1514                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1515                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1516                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1517                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1518                                 break;
1519                         case 23:  /* 32 bpp PRT */
1520                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1521                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1522                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1523                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1524                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1525                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1527                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1528                                 break;
1529                         case 24:  /* 64 bpp PRT */
1530                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1531                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1532                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1533                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1534                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1535                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1536                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1537                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1538                                 break;
1539                         case 25:  /* 128 bpp PRT */
1540                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1541                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1542                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1543                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1544                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
1545                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1547                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1548                                 break;
1549                         default:
1550                                 gb_tile_moden = 0;
1551                                 break;
1552                         }
1553                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1554                 }
1555         } else
1556                 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1557 }
1558
1559 static void si_gpu_init(struct radeon_device *rdev)
1560 {
1561         u32 cc_rb_backend_disable = 0;
1562         u32 cc_gc_shader_array_config;
1563         u32 gb_addr_config = 0;
1564         u32 mc_shared_chmap, mc_arb_ramcfg;
1565         u32 gb_backend_map;
1566         u32 cgts_tcc_disable;
1567         u32 sx_debug_1;
1568         u32 gc_user_shader_array_config;
1569         u32 gc_user_rb_backend_disable;
1570         u32 cgts_user_tcc_disable;
1571         u32 hdp_host_path_cntl;
1572         u32 tmp;
1573         int i, j;
1574
1575         switch (rdev->family) {
1576         case CHIP_TAHITI:
1577                 rdev->config.si.max_shader_engines = 2;
1578                 rdev->config.si.max_pipes_per_simd = 4;
1579                 rdev->config.si.max_tile_pipes = 12;
1580                 rdev->config.si.max_simds_per_se = 8;
1581                 rdev->config.si.max_backends_per_se = 4;
1582                 rdev->config.si.max_texture_channel_caches = 12;
1583                 rdev->config.si.max_gprs = 256;
1584                 rdev->config.si.max_gs_threads = 32;
1585                 rdev->config.si.max_hw_contexts = 8;
1586
1587                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1588                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1589                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1590                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1591                 break;
1592         case CHIP_PITCAIRN:
1593                 rdev->config.si.max_shader_engines = 2;
1594                 rdev->config.si.max_pipes_per_simd = 4;
1595                 rdev->config.si.max_tile_pipes = 8;
1596                 rdev->config.si.max_simds_per_se = 5;
1597                 rdev->config.si.max_backends_per_se = 4;
1598                 rdev->config.si.max_texture_channel_caches = 8;
1599                 rdev->config.si.max_gprs = 256;
1600                 rdev->config.si.max_gs_threads = 32;
1601                 rdev->config.si.max_hw_contexts = 8;
1602
1603                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1604                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1605                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1606                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1607                 break;
1608         case CHIP_VERDE:
1609         default:
1610                 rdev->config.si.max_shader_engines = 1;
1611                 rdev->config.si.max_pipes_per_simd = 4;
1612                 rdev->config.si.max_tile_pipes = 4;
1613                 rdev->config.si.max_simds_per_se = 2;
1614                 rdev->config.si.max_backends_per_se = 4;
1615                 rdev->config.si.max_texture_channel_caches = 4;
1616                 rdev->config.si.max_gprs = 256;
1617                 rdev->config.si.max_gs_threads = 32;
1618                 rdev->config.si.max_hw_contexts = 8;
1619
1620                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1621                 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1622                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1623                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1624                 break;
1625         }
1626
1627         /* Initialize HDP */
1628         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1629                 WREG32((0x2c14 + j), 0x00000000);
1630                 WREG32((0x2c18 + j), 0x00000000);
1631                 WREG32((0x2c1c + j), 0x00000000);
1632                 WREG32((0x2c20 + j), 0x00000000);
1633                 WREG32((0x2c24 + j), 0x00000000);
1634         }
1635
1636         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1637
1638         evergreen_fix_pci_max_read_req_size(rdev);
1639
1640         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1641
1642         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1643         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1644
1645         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
1646         cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1647         cgts_tcc_disable = 0xffff0000;
1648         for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
1649                 cgts_tcc_disable &= ~(1 << (16 + i));
1650         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
1651         gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1652         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
1653
1654         rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
1655         rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1656         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1657         rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
1658         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1659         rdev->config.si.backend_disable_mask_per_asic =
1660                 si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
1661                                              rdev->config.si.num_shader_engines);
1662         rdev->config.si.backend_map =
1663                 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1664                                                 rdev->config.si.num_backends_per_se *
1665                                                 rdev->config.si.num_shader_engines,
1666                                                 &rdev->config.si.backend_disable_mask_per_asic,
1667                                                 rdev->config.si.num_shader_engines);
1668         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
1669         rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
1670         rdev->config.si.mem_max_burst_length_bytes = 256;
1671         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1672         rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1673         if (rdev->config.si.mem_row_size_in_kb > 4)
1674                 rdev->config.si.mem_row_size_in_kb = 4;
1675         /* XXX use MC settings? */
1676         rdev->config.si.shader_engine_tile_size = 32;
1677         rdev->config.si.num_gpus = 1;
1678         rdev->config.si.multi_gpu_tile_size = 64;
1679
1680         gb_addr_config = 0;
1681         switch (rdev->config.si.num_tile_pipes) {
1682         case 1:
1683                 gb_addr_config |= NUM_PIPES(0);
1684                 break;
1685         case 2:
1686                 gb_addr_config |= NUM_PIPES(1);
1687                 break;
1688         case 4:
1689                 gb_addr_config |= NUM_PIPES(2);
1690                 break;
1691         case 8:
1692         default:
1693                 gb_addr_config |= NUM_PIPES(3);
1694                 break;
1695         }
1696
1697         tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
1698         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
1699         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
1700         tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
1701         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
1702         switch (rdev->config.si.num_gpus) {
1703         case 1:
1704         default:
1705                 gb_addr_config |= NUM_GPUS(0);
1706                 break;
1707         case 2:
1708                 gb_addr_config |= NUM_GPUS(1);
1709                 break;
1710         case 4:
1711                 gb_addr_config |= NUM_GPUS(2);
1712                 break;
1713         }
1714         switch (rdev->config.si.multi_gpu_tile_size) {
1715         case 16:
1716                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
1717                 break;
1718         case 32:
1719         default:
1720                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
1721                 break;
1722         case 64:
1723                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1724                 break;
1725         case 128:
1726                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
1727                 break;
1728         }
1729         switch (rdev->config.si.mem_row_size_in_kb) {
1730         case 1:
1731         default:
1732                 gb_addr_config |= ROW_SIZE(0);
1733                 break;
1734         case 2:
1735                 gb_addr_config |= ROW_SIZE(1);
1736                 break;
1737         case 4:
1738                 gb_addr_config |= ROW_SIZE(2);
1739                 break;
1740         }
1741
1742         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1743         rdev->config.si.num_tile_pipes = (1 << tmp);
1744         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1745         rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
1746         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1747         rdev->config.si.num_shader_engines = tmp + 1;
1748         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1749         rdev->config.si.num_gpus = tmp + 1;
1750         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1751         rdev->config.si.multi_gpu_tile_size = 1 << tmp;
1752         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1753         rdev->config.si.mem_row_size_in_kb = 1 << tmp;
1754
1755         gb_backend_map =
1756                 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1757                                                 rdev->config.si.num_backends_per_se *
1758                                                 rdev->config.si.num_shader_engines,
1759                                                 &rdev->config.si.backend_disable_mask_per_asic,
1760                                                 rdev->config.si.num_shader_engines);
1761
1762         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1763          * not have bank info, so create a custom tiling dword.
1764          * bits 3:0   num_pipes
1765          * bits 7:4   num_banks
1766          * bits 11:8  group_size
1767          * bits 15:12 row_size
1768          */
1769         rdev->config.si.tile_config = 0;
1770         switch (rdev->config.si.num_tile_pipes) {
1771         case 1:
1772                 rdev->config.si.tile_config |= (0 << 0);
1773                 break;
1774         case 2:
1775                 rdev->config.si.tile_config |= (1 << 0);
1776                 break;
1777         case 4:
1778                 rdev->config.si.tile_config |= (2 << 0);
1779                 break;
1780         case 8:
1781         default:
1782                 /* XXX what about 12? */
1783                 rdev->config.si.tile_config |= (3 << 0);
1784                 break;
1785         }
1786         rdev->config.si.tile_config |=
1787                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1788         rdev->config.si.tile_config |=
1789                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1790         rdev->config.si.tile_config |=
1791                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1792
1793         rdev->config.si.backend_map = gb_backend_map;
1794         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1795         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1796         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1797
1798         /* primary versions */
1799         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1800         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1801         WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1802
1803         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1804
1805         /* user versions */
1806         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1807         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1808         WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1809
1810         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1811
1812         si_tiling_mode_table_init(rdev);
1813
1814         /* set HW defaults for 3D engine */
1815         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1816                                      ROQ_IB2_START(0x2b)));
1817         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1818
1819         sx_debug_1 = RREG32(SX_DEBUG_1);
1820         WREG32(SX_DEBUG_1, sx_debug_1);
1821
1822         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1823
1824         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1825                                  SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1826                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1827                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1828
1829         WREG32(VGT_NUM_INSTANCES, 1);
1830
1831         WREG32(CP_PERFMON_CNTL, 0);
1832
1833         WREG32(SQ_CONFIG, 0);
1834
1835         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1836                                           FORCE_EOV_MAX_REZ_CNT(255)));
1837
1838         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1839                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1840
1841         WREG32(VGT_GS_VERTEX_REUSE, 16);
1842         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1843
1844         WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1845         WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1846         WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1847         WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1848         WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1849         WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1850         WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1851         WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1852
1853         tmp = RREG32(HDP_MISC_CNTL);
1854         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1855         WREG32(HDP_MISC_CNTL, tmp);
1856
1857         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1858         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1859
1860         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1861
1862         udelay(50);
1863 }
1864
1865 /*
1866  * GPU scratch registers helpers function.
1867  */
1868 static void si_scratch_init(struct radeon_device *rdev)
1869 {
1870         int i;
1871
1872         rdev->scratch.num_reg = 7;
1873         rdev->scratch.reg_base = SCRATCH_REG0;
1874         for (i = 0; i < rdev->scratch.num_reg; i++) {
1875                 rdev->scratch.free[i] = true;
1876                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1877         }
1878 }
1879
1880 void si_fence_ring_emit(struct radeon_device *rdev,
1881                         struct radeon_fence *fence)
1882 {
1883         struct radeon_ring *ring = &rdev->ring[fence->ring];
1884         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1885
1886         /* flush read cache over gart */
1887         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1888         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1889         radeon_ring_write(ring, 0);
1890         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1891         radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1892                           PACKET3_TC_ACTION_ENA |
1893                           PACKET3_SH_KCACHE_ACTION_ENA |
1894                           PACKET3_SH_ICACHE_ACTION_ENA);
1895         radeon_ring_write(ring, 0xFFFFFFFF);
1896         radeon_ring_write(ring, 0);
1897         radeon_ring_write(ring, 10); /* poll interval */
1898         /* EVENT_WRITE_EOP - flush caches, send int */
1899         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1900         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1901         radeon_ring_write(ring, addr & 0xffffffff);
1902         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1903         radeon_ring_write(ring, fence->seq);
1904         radeon_ring_write(ring, 0);
1905 }
1906
1907 /*
1908  * IB stuff
1909  */
1910 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1911 {
1912         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1913         u32 header;
1914
1915         if (ib->is_const_ib)
1916                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1917         else
1918                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1919
1920         radeon_ring_write(ring, header);
1921         radeon_ring_write(ring,
1922 #ifdef __BIG_ENDIAN
1923                           (2 << 0) |
1924 #endif
1925                           (ib->gpu_addr & 0xFFFFFFFC));
1926         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1927         radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1928
1929         /* flush read cache over gart for this vmid */
1930         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1931         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1932         radeon_ring_write(ring, ib->vm_id);
1933         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1934         radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1935                           PACKET3_TC_ACTION_ENA |
1936                           PACKET3_SH_KCACHE_ACTION_ENA |
1937                           PACKET3_SH_ICACHE_ACTION_ENA);
1938         radeon_ring_write(ring, 0xFFFFFFFF);
1939         radeon_ring_write(ring, 0);
1940         radeon_ring_write(ring, 10); /* poll interval */
1941 }
1942
1943 /*
1944  * CP.
1945  */
1946 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1947 {
1948         if (enable)
1949                 WREG32(CP_ME_CNTL, 0);
1950         else {
1951                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1952                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1953                 WREG32(SCRATCH_UMSK, 0);
1954         }
1955         udelay(50);
1956 }
1957
1958 static int si_cp_load_microcode(struct radeon_device *rdev)
1959 {
1960         const __be32 *fw_data;
1961         int i;
1962
1963         if (!rdev->me_fw || !rdev->pfp_fw)
1964                 return -EINVAL;
1965
1966         si_cp_enable(rdev, false);
1967
1968         /* PFP */
1969         fw_data = (const __be32 *)rdev->pfp_fw->data;
1970         WREG32(CP_PFP_UCODE_ADDR, 0);
1971         for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1972                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1973         WREG32(CP_PFP_UCODE_ADDR, 0);
1974
1975         /* CE */
1976         fw_data = (const __be32 *)rdev->ce_fw->data;
1977         WREG32(CP_CE_UCODE_ADDR, 0);
1978         for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1979                 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1980         WREG32(CP_CE_UCODE_ADDR, 0);
1981
1982         /* ME */
1983         fw_data = (const __be32 *)rdev->me_fw->data;
1984         WREG32(CP_ME_RAM_WADDR, 0);
1985         for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1986                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1987         WREG32(CP_ME_RAM_WADDR, 0);
1988
1989         WREG32(CP_PFP_UCODE_ADDR, 0);
1990         WREG32(CP_CE_UCODE_ADDR, 0);
1991         WREG32(CP_ME_RAM_WADDR, 0);
1992         WREG32(CP_ME_RAM_RADDR, 0);
1993         return 0;
1994 }
1995
1996 static int si_cp_start(struct radeon_device *rdev)
1997 {
1998         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1999         int r, i;
2000
2001         r = radeon_ring_lock(rdev, ring, 7 + 4);
2002         if (r) {
2003                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2004                 return r;
2005         }
2006         /* init the CP */
2007         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2008         radeon_ring_write(ring, 0x1);
2009         radeon_ring_write(ring, 0x0);
2010         radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
2011         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2012         radeon_ring_write(ring, 0);
2013         radeon_ring_write(ring, 0);
2014
2015         /* init the CE partitions */
2016         radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2017         radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2018         radeon_ring_write(ring, 0xc000);
2019         radeon_ring_write(ring, 0xe000);
2020         radeon_ring_unlock_commit(rdev, ring);
2021
2022         si_cp_enable(rdev, true);
2023
2024         r = radeon_ring_lock(rdev, ring, si_default_size + 10);
2025         if (r) {
2026                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2027                 return r;
2028         }
2029
2030         /* setup clear context state */
2031         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2032         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2033
2034         for (i = 0; i < si_default_size; i++)
2035                 radeon_ring_write(ring, si_default_state[i]);
2036
2037         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2038         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2039
2040         /* set clear context state */
2041         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2042         radeon_ring_write(ring, 0);
2043
2044         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2045         radeon_ring_write(ring, 0x00000316);
2046         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2047         radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2048
2049         radeon_ring_unlock_commit(rdev, ring);
2050
2051         for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
2052                 ring = &rdev->ring[i];
2053                 r = radeon_ring_lock(rdev, ring, 2);
2054
2055                 /* clear the compute context state */
2056                 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2057                 radeon_ring_write(ring, 0);
2058
2059                 radeon_ring_unlock_commit(rdev, ring);
2060         }
2061
2062         return 0;
2063 }
2064
2065 static void si_cp_fini(struct radeon_device *rdev)
2066 {
2067         si_cp_enable(rdev, false);
2068         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2069         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2070         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2071 }
2072
2073 static int si_cp_resume(struct radeon_device *rdev)
2074 {
2075         struct radeon_ring *ring;
2076         u32 tmp;
2077         u32 rb_bufsz;
2078         int r;
2079
2080         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2081         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2082                                  SOFT_RESET_PA |
2083                                  SOFT_RESET_VGT |
2084                                  SOFT_RESET_SPI |
2085                                  SOFT_RESET_SX));
2086         RREG32(GRBM_SOFT_RESET);
2087         mdelay(15);
2088         WREG32(GRBM_SOFT_RESET, 0);
2089         RREG32(GRBM_SOFT_RESET);
2090
2091         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2092         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2093
2094         /* Set the write pointer delay */
2095         WREG32(CP_RB_WPTR_DELAY, 0);
2096
2097         WREG32(CP_DEBUG, 0);
2098         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2099
2100         /* ring 0 - compute and gfx */
2101         /* Set ring buffer size */
2102         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2103         rb_bufsz = drm_order(ring->ring_size / 8);
2104         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2105 #ifdef __BIG_ENDIAN
2106         tmp |= BUF_SWAP_32BIT;
2107 #endif
2108         WREG32(CP_RB0_CNTL, tmp);
2109
2110         /* Initialize the ring buffer's read and write pointers */
2111         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2112         ring->wptr = 0;
2113         WREG32(CP_RB0_WPTR, ring->wptr);
2114
2115         /* set the wb address wether it's enabled or not */
2116         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2117         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2118
2119         if (rdev->wb.enabled)
2120                 WREG32(SCRATCH_UMSK, 0xff);
2121         else {
2122                 tmp |= RB_NO_UPDATE;
2123                 WREG32(SCRATCH_UMSK, 0);
2124         }
2125
2126         mdelay(1);
2127         WREG32(CP_RB0_CNTL, tmp);
2128
2129         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2130
2131         ring->rptr = RREG32(CP_RB0_RPTR);
2132
2133         /* ring1  - compute only */
2134         /* Set ring buffer size */
2135         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2136         rb_bufsz = drm_order(ring->ring_size / 8);
2137         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2138 #ifdef __BIG_ENDIAN
2139         tmp |= BUF_SWAP_32BIT;
2140 #endif
2141         WREG32(CP_RB1_CNTL, tmp);
2142
2143         /* Initialize the ring buffer's read and write pointers */
2144         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2145         ring->wptr = 0;
2146         WREG32(CP_RB1_WPTR, ring->wptr);
2147
2148         /* set the wb address wether it's enabled or not */
2149         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2150         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2151
2152         mdelay(1);
2153         WREG32(CP_RB1_CNTL, tmp);
2154
2155         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2156
2157         ring->rptr = RREG32(CP_RB1_RPTR);
2158
2159         /* ring2 - compute only */
2160         /* Set ring buffer size */
2161         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2162         rb_bufsz = drm_order(ring->ring_size / 8);
2163         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2164 #ifdef __BIG_ENDIAN
2165         tmp |= BUF_SWAP_32BIT;
2166 #endif
2167         WREG32(CP_RB2_CNTL, tmp);
2168
2169         /* Initialize the ring buffer's read and write pointers */
2170         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2171         ring->wptr = 0;
2172         WREG32(CP_RB2_WPTR, ring->wptr);
2173
2174         /* set the wb address wether it's enabled or not */
2175         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2176         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2177
2178         mdelay(1);
2179         WREG32(CP_RB2_CNTL, tmp);
2180
2181         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2182
2183         ring->rptr = RREG32(CP_RB2_RPTR);
2184
2185         /* start the rings */
2186         si_cp_start(rdev);
2187         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2188         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2189         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2190         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2191         if (r) {
2192                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2193                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2194                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2195                 return r;
2196         }
2197         r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2198         if (r) {
2199                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2200         }
2201         r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2202         if (r) {
2203                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2204         }
2205
2206         return 0;
2207 }
2208
2209 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2210 {
2211         u32 srbm_status;
2212         u32 grbm_status, grbm_status2;
2213         u32 grbm_status_se0, grbm_status_se1;
2214         struct r100_gpu_lockup *lockup = &rdev->config.si.lockup;
2215         int r;
2216
2217         srbm_status = RREG32(SRBM_STATUS);
2218         grbm_status = RREG32(GRBM_STATUS);
2219         grbm_status2 = RREG32(GRBM_STATUS2);
2220         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2221         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2222         if (!(grbm_status & GUI_ACTIVE)) {
2223                 r100_gpu_lockup_update(lockup, ring);
2224                 return false;
2225         }
2226         /* force CP activities */
2227         r = radeon_ring_lock(rdev, ring, 2);
2228         if (!r) {
2229                 /* PACKET2 NOP */
2230                 radeon_ring_write(ring, 0x80000000);
2231                 radeon_ring_write(ring, 0x80000000);
2232                 radeon_ring_unlock_commit(rdev, ring);
2233         }
2234         /* XXX deal with CP0,1,2 */
2235         ring->rptr = RREG32(ring->rptr_reg);
2236         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
2237 }
2238
2239 static int si_gpu_soft_reset(struct radeon_device *rdev)
2240 {
2241         struct evergreen_mc_save save;
2242         u32 grbm_reset = 0;
2243
2244         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2245                 return 0;
2246
2247         dev_info(rdev->dev, "GPU softreset \n");
2248         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2249                 RREG32(GRBM_STATUS));
2250         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2251                 RREG32(GRBM_STATUS2));
2252         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2253                 RREG32(GRBM_STATUS_SE0));
2254         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2255                 RREG32(GRBM_STATUS_SE1));
2256         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2257                 RREG32(SRBM_STATUS));
2258         evergreen_mc_stop(rdev, &save);
2259         if (radeon_mc_wait_for_idle(rdev)) {
2260                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2261         }
2262         /* Disable CP parsing/prefetching */
2263         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2264
2265         /* reset all the gfx blocks */
2266         grbm_reset = (SOFT_RESET_CP |
2267                       SOFT_RESET_CB |
2268                       SOFT_RESET_DB |
2269                       SOFT_RESET_GDS |
2270                       SOFT_RESET_PA |
2271                       SOFT_RESET_SC |
2272                       SOFT_RESET_SPI |
2273                       SOFT_RESET_SX |
2274                       SOFT_RESET_TC |
2275                       SOFT_RESET_TA |
2276                       SOFT_RESET_VGT |
2277                       SOFT_RESET_IA);
2278
2279         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2280         WREG32(GRBM_SOFT_RESET, grbm_reset);
2281         (void)RREG32(GRBM_SOFT_RESET);
2282         udelay(50);
2283         WREG32(GRBM_SOFT_RESET, 0);
2284         (void)RREG32(GRBM_SOFT_RESET);
2285         /* Wait a little for things to settle down */
2286         udelay(50);
2287         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2288                 RREG32(GRBM_STATUS));
2289         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2290                 RREG32(GRBM_STATUS2));
2291         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2292                 RREG32(GRBM_STATUS_SE0));
2293         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2294                 RREG32(GRBM_STATUS_SE1));
2295         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2296                 RREG32(SRBM_STATUS));
2297         evergreen_mc_resume(rdev, &save);
2298         return 0;
2299 }
2300
2301 int si_asic_reset(struct radeon_device *rdev)
2302 {
2303         return si_gpu_soft_reset(rdev);
2304 }
2305
2306 /* MC */
2307 static void si_mc_program(struct radeon_device *rdev)
2308 {
2309         struct evergreen_mc_save save;
2310         u32 tmp;
2311         int i, j;
2312
2313         /* Initialize HDP */
2314         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2315                 WREG32((0x2c14 + j), 0x00000000);
2316                 WREG32((0x2c18 + j), 0x00000000);
2317                 WREG32((0x2c1c + j), 0x00000000);
2318                 WREG32((0x2c20 + j), 0x00000000);
2319                 WREG32((0x2c24 + j), 0x00000000);
2320         }
2321         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2322
2323         evergreen_mc_stop(rdev, &save);
2324         if (radeon_mc_wait_for_idle(rdev)) {
2325                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2326         }
2327         /* Lockout access through VGA aperture*/
2328         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2329         /* Update configuration */
2330         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2331                rdev->mc.vram_start >> 12);
2332         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2333                rdev->mc.vram_end >> 12);
2334         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2335                rdev->vram_scratch.gpu_addr >> 12);
2336         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2337         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2338         WREG32(MC_VM_FB_LOCATION, tmp);
2339         /* XXX double check these! */
2340         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2341         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2342         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2343         WREG32(MC_VM_AGP_BASE, 0);
2344         WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2345         WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2346         if (radeon_mc_wait_for_idle(rdev)) {
2347                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2348         }
2349         evergreen_mc_resume(rdev, &save);
2350         /* we need to own VRAM, so turn off the VGA renderer here
2351          * to stop it overwriting our objects */
2352         rv515_vga_render_disable(rdev);
2353 }
2354
2355 /* SI MC address space is 40 bits */
2356 static void si_vram_location(struct radeon_device *rdev,
2357                              struct radeon_mc *mc, u64 base)
2358 {
2359         mc->vram_start = base;
2360         if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2361                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2362                 mc->real_vram_size = mc->aper_size;
2363                 mc->mc_vram_size = mc->aper_size;
2364         }
2365         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2366         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2367                         mc->mc_vram_size >> 20, mc->vram_start,
2368                         mc->vram_end, mc->real_vram_size >> 20);
2369 }
2370
2371 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2372 {
2373         u64 size_af, size_bf;
2374
2375         size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2376         size_bf = mc->vram_start & ~mc->gtt_base_align;
2377         if (size_bf > size_af) {
2378                 if (mc->gtt_size > size_bf) {
2379                         dev_warn(rdev->dev, "limiting GTT\n");
2380                         mc->gtt_size = size_bf;
2381                 }
2382                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2383         } else {
2384                 if (mc->gtt_size > size_af) {
2385                         dev_warn(rdev->dev, "limiting GTT\n");
2386                         mc->gtt_size = size_af;
2387                 }
2388                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2389         }
2390         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2391         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2392                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2393 }
2394
2395 static void si_vram_gtt_location(struct radeon_device *rdev,
2396                                  struct radeon_mc *mc)
2397 {
2398         if (mc->mc_vram_size > 0xFFC0000000ULL) {
2399                 /* leave room for at least 1024M GTT */
2400                 dev_warn(rdev->dev, "limiting VRAM\n");
2401                 mc->real_vram_size = 0xFFC0000000ULL;
2402                 mc->mc_vram_size = 0xFFC0000000ULL;
2403         }
2404         si_vram_location(rdev, &rdev->mc, 0);
2405         rdev->mc.gtt_base_align = 0;
2406         si_gtt_location(rdev, mc);
2407 }
2408
2409 static int si_mc_init(struct radeon_device *rdev)
2410 {
2411         u32 tmp;
2412         int chansize, numchan;
2413
2414         /* Get VRAM informations */
2415         rdev->mc.vram_is_ddr = true;
2416         tmp = RREG32(MC_ARB_RAMCFG);
2417         if (tmp & CHANSIZE_OVERRIDE) {
2418                 chansize = 16;
2419         } else if (tmp & CHANSIZE_MASK) {
2420                 chansize = 64;
2421         } else {
2422                 chansize = 32;
2423         }
2424         tmp = RREG32(MC_SHARED_CHMAP);
2425         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2426         case 0:
2427         default:
2428                 numchan = 1;
2429                 break;
2430         case 1:
2431                 numchan = 2;
2432                 break;
2433         case 2:
2434                 numchan = 4;
2435                 break;
2436         case 3:
2437                 numchan = 8;
2438                 break;
2439         case 4:
2440                 numchan = 3;
2441                 break;
2442         case 5:
2443                 numchan = 6;
2444                 break;
2445         case 6:
2446                 numchan = 10;
2447                 break;
2448         case 7:
2449                 numchan = 12;
2450                 break;
2451         case 8:
2452                 numchan = 16;
2453                 break;
2454         }
2455         rdev->mc.vram_width = numchan * chansize;
2456         /* Could aper size report 0 ? */
2457         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2458         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2459         /* size in MB on si */
2460         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2461         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2462         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2463         si_vram_gtt_location(rdev, &rdev->mc);
2464         radeon_update_bandwidth_info(rdev);
2465
2466         return 0;
2467 }
2468
2469 /*
2470  * GART
2471  */
2472 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2473 {
2474         /* flush hdp cache */
2475         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2476
2477         /* bits 0-15 are the VM contexts0-15 */
2478         WREG32(VM_INVALIDATE_REQUEST, 1);
2479 }
2480
2481 int si_pcie_gart_enable(struct radeon_device *rdev)
2482 {
2483         int r, i;
2484
2485         if (rdev->gart.robj == NULL) {
2486                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2487                 return -EINVAL;
2488         }
2489         r = radeon_gart_table_vram_pin(rdev);
2490         if (r)
2491                 return r;
2492         radeon_gart_restore(rdev);
2493         /* Setup TLB control */
2494         WREG32(MC_VM_MX_L1_TLB_CNTL,
2495                (0xA << 7) |
2496                ENABLE_L1_TLB |
2497                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2498                ENABLE_ADVANCED_DRIVER_MODEL |
2499                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2500         /* Setup L2 cache */
2501         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2502                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2503                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2504                EFFECTIVE_L2_QUEUE_SIZE(7) |
2505                CONTEXT1_IDENTITY_ACCESS_MODE(1));
2506         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2507         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2508                L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2509         /* setup context0 */
2510         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2511         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2512         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2513         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2514                         (u32)(rdev->dummy_page.addr >> 12));
2515         WREG32(VM_CONTEXT0_CNTL2, 0);
2516         WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2517                                   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2518
2519         WREG32(0x15D4, 0);
2520         WREG32(0x15D8, 0);
2521         WREG32(0x15DC, 0);
2522
2523         /* empty context1-15 */
2524         /* FIXME start with 1G, once using 2 level pt switch to full
2525          * vm size space
2526          */
2527         /* set vm size, must be a multiple of 4 */
2528         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2529         WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE);
2530         for (i = 1; i < 16; i++) {
2531                 if (i < 8)
2532                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2533                                rdev->gart.table_addr >> 12);
2534                 else
2535                         WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2536                                rdev->gart.table_addr >> 12);
2537         }
2538
2539         /* enable context1-15 */
2540         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2541                (u32)(rdev->dummy_page.addr >> 12));
2542         WREG32(VM_CONTEXT1_CNTL2, 0);
2543         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2544                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2545
2546         si_pcie_gart_tlb_flush(rdev);
2547         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2548                  (unsigned)(rdev->mc.gtt_size >> 20),
2549                  (unsigned long long)rdev->gart.table_addr);
2550         rdev->gart.ready = true;
2551         return 0;
2552 }
2553
2554 void si_pcie_gart_disable(struct radeon_device *rdev)
2555 {
2556         /* Disable all tables */
2557         WREG32(VM_CONTEXT0_CNTL, 0);
2558         WREG32(VM_CONTEXT1_CNTL, 0);
2559         /* Setup TLB control */
2560         WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2561                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2562         /* Setup L2 cache */
2563         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2564                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2565                EFFECTIVE_L2_QUEUE_SIZE(7) |
2566                CONTEXT1_IDENTITY_ACCESS_MODE(1));
2567         WREG32(VM_L2_CNTL2, 0);
2568         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2569                L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2570         radeon_gart_table_vram_unpin(rdev);
2571 }
2572
2573 void si_pcie_gart_fini(struct radeon_device *rdev)
2574 {
2575         si_pcie_gart_disable(rdev);
2576         radeon_gart_table_vram_free(rdev);
2577         radeon_gart_fini(rdev);
2578 }
2579
2580 /* vm parser */
2581 static bool si_vm_reg_valid(u32 reg)
2582 {
2583         /* context regs are fine */
2584         if (reg >= 0x28000)
2585                 return true;
2586
2587         /* check config regs */
2588         switch (reg) {
2589         case GRBM_GFX_INDEX:
2590         case VGT_VTX_VECT_EJECT_REG:
2591         case VGT_CACHE_INVALIDATION:
2592         case VGT_ESGS_RING_SIZE:
2593         case VGT_GSVS_RING_SIZE:
2594         case VGT_GS_VERTEX_REUSE:
2595         case VGT_PRIMITIVE_TYPE:
2596         case VGT_INDEX_TYPE:
2597         case VGT_NUM_INDICES:
2598         case VGT_NUM_INSTANCES:
2599         case VGT_TF_RING_SIZE:
2600         case VGT_HS_OFFCHIP_PARAM:
2601         case VGT_TF_MEMORY_BASE:
2602         case PA_CL_ENHANCE:
2603         case PA_SU_LINE_STIPPLE_VALUE:
2604         case PA_SC_LINE_STIPPLE_STATE:
2605         case PA_SC_ENHANCE:
2606         case SQC_CACHES:
2607         case SPI_STATIC_THREAD_MGMT_1:
2608         case SPI_STATIC_THREAD_MGMT_2:
2609         case SPI_STATIC_THREAD_MGMT_3:
2610         case SPI_PS_MAX_WAVE_ID:
2611         case SPI_CONFIG_CNTL:
2612         case SPI_CONFIG_CNTL_1:
2613         case TA_CNTL_AUX:
2614                 return true;
2615         default:
2616                 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2617                 return false;
2618         }
2619 }
2620
2621 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2622                                   u32 *ib, struct radeon_cs_packet *pkt)
2623 {
2624         switch (pkt->opcode) {
2625         case PACKET3_NOP:
2626         case PACKET3_SET_BASE:
2627         case PACKET3_SET_CE_DE_COUNTERS:
2628         case PACKET3_LOAD_CONST_RAM:
2629         case PACKET3_WRITE_CONST_RAM:
2630         case PACKET3_WRITE_CONST_RAM_OFFSET:
2631         case PACKET3_DUMP_CONST_RAM:
2632         case PACKET3_INCREMENT_CE_COUNTER:
2633         case PACKET3_WAIT_ON_DE_COUNTER:
2634         case PACKET3_CE_WRITE:
2635                 break;
2636         default:
2637                 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2638                 return -EINVAL;
2639         }
2640         return 0;
2641 }
2642
2643 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2644                                    u32 *ib, struct radeon_cs_packet *pkt)
2645 {
2646         u32 idx = pkt->idx + 1;
2647         u32 idx_value = ib[idx];
2648         u32 start_reg, end_reg, reg, i;
2649
2650         switch (pkt->opcode) {
2651         case PACKET3_NOP:
2652         case PACKET3_SET_BASE:
2653         case PACKET3_CLEAR_STATE:
2654         case PACKET3_INDEX_BUFFER_SIZE:
2655         case PACKET3_DISPATCH_DIRECT:
2656         case PACKET3_DISPATCH_INDIRECT:
2657         case PACKET3_ALLOC_GDS:
2658         case PACKET3_WRITE_GDS_RAM:
2659         case PACKET3_ATOMIC_GDS:
2660         case PACKET3_ATOMIC:
2661         case PACKET3_OCCLUSION_QUERY:
2662         case PACKET3_SET_PREDICATION:
2663         case PACKET3_COND_EXEC:
2664         case PACKET3_PRED_EXEC:
2665         case PACKET3_DRAW_INDIRECT:
2666         case PACKET3_DRAW_INDEX_INDIRECT:
2667         case PACKET3_INDEX_BASE:
2668         case PACKET3_DRAW_INDEX_2:
2669         case PACKET3_CONTEXT_CONTROL:
2670         case PACKET3_INDEX_TYPE:
2671         case PACKET3_DRAW_INDIRECT_MULTI:
2672         case PACKET3_DRAW_INDEX_AUTO:
2673         case PACKET3_DRAW_INDEX_IMMD:
2674         case PACKET3_NUM_INSTANCES:
2675         case PACKET3_DRAW_INDEX_MULTI_AUTO:
2676         case PACKET3_STRMOUT_BUFFER_UPDATE:
2677         case PACKET3_DRAW_INDEX_OFFSET_2:
2678         case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2679         case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2680         case PACKET3_MPEG_INDEX:
2681         case PACKET3_WAIT_REG_MEM:
2682         case PACKET3_MEM_WRITE:
2683         case PACKET3_PFP_SYNC_ME:
2684         case PACKET3_SURFACE_SYNC:
2685         case PACKET3_EVENT_WRITE:
2686         case PACKET3_EVENT_WRITE_EOP:
2687         case PACKET3_EVENT_WRITE_EOS:
2688         case PACKET3_SET_CONTEXT_REG:
2689         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2690         case PACKET3_SET_SH_REG:
2691         case PACKET3_SET_SH_REG_OFFSET:
2692         case PACKET3_INCREMENT_DE_COUNTER:
2693         case PACKET3_WAIT_ON_CE_COUNTER:
2694         case PACKET3_WAIT_ON_AVAIL_BUFFER:
2695         case PACKET3_ME_WRITE:
2696                 break;
2697         case PACKET3_COPY_DATA:
2698                 if ((idx_value & 0xf00) == 0) {
2699                         reg = ib[idx + 3] * 4;
2700                         if (!si_vm_reg_valid(reg))
2701                                 return -EINVAL;
2702                 }
2703                 break;
2704         case PACKET3_WRITE_DATA:
2705                 if ((idx_value & 0xf00) == 0) {
2706                         start_reg = ib[idx + 1] * 4;
2707                         if (idx_value & 0x10000) {
2708                                 if (!si_vm_reg_valid(start_reg))
2709                                         return -EINVAL;
2710                         } else {
2711                                 for (i = 0; i < (pkt->count - 2); i++) {
2712                                         reg = start_reg + (4 * i);
2713                                         if (!si_vm_reg_valid(reg))
2714                                                 return -EINVAL;
2715                                 }
2716                         }
2717                 }
2718                 break;
2719         case PACKET3_COND_WRITE:
2720                 if (idx_value & 0x100) {
2721                         reg = ib[idx + 5] * 4;
2722                         if (!si_vm_reg_valid(reg))
2723                                 return -EINVAL;
2724                 }
2725                 break;
2726         case PACKET3_COPY_DW:
2727                 if (idx_value & 0x2) {
2728                         reg = ib[idx + 3] * 4;
2729                         if (!si_vm_reg_valid(reg))
2730                                 return -EINVAL;
2731                 }
2732                 break;
2733         case PACKET3_SET_CONFIG_REG:
2734                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2735                 end_reg = 4 * pkt->count + start_reg - 4;
2736                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2737                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2738                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2739                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2740                         return -EINVAL;
2741                 }
2742                 for (i = 0; i < pkt->count; i++) {
2743                         reg = start_reg + (4 * i);
2744                         if (!si_vm_reg_valid(reg))
2745                                 return -EINVAL;
2746                 }
2747                 break;
2748         default:
2749                 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2750                 return -EINVAL;
2751         }
2752         return 0;
2753 }
2754
2755 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2756                                        u32 *ib, struct radeon_cs_packet *pkt)
2757 {
2758         u32 idx = pkt->idx + 1;
2759         u32 idx_value = ib[idx];
2760         u32 start_reg, reg, i;
2761
2762         switch (pkt->opcode) {
2763         case PACKET3_NOP:
2764         case PACKET3_SET_BASE:
2765         case PACKET3_CLEAR_STATE:
2766         case PACKET3_DISPATCH_DIRECT:
2767         case PACKET3_DISPATCH_INDIRECT:
2768         case PACKET3_ALLOC_GDS:
2769         case PACKET3_WRITE_GDS_RAM:
2770         case PACKET3_ATOMIC_GDS:
2771         case PACKET3_ATOMIC:
2772         case PACKET3_OCCLUSION_QUERY:
2773         case PACKET3_SET_PREDICATION:
2774         case PACKET3_COND_EXEC:
2775         case PACKET3_PRED_EXEC:
2776         case PACKET3_CONTEXT_CONTROL:
2777         case PACKET3_STRMOUT_BUFFER_UPDATE:
2778         case PACKET3_WAIT_REG_MEM:
2779         case PACKET3_MEM_WRITE:
2780         case PACKET3_PFP_SYNC_ME:
2781         case PACKET3_SURFACE_SYNC:
2782         case PACKET3_EVENT_WRITE:
2783         case PACKET3_EVENT_WRITE_EOP:
2784         case PACKET3_EVENT_WRITE_EOS:
2785         case PACKET3_SET_CONTEXT_REG:
2786         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2787         case PACKET3_SET_SH_REG:
2788         case PACKET3_SET_SH_REG_OFFSET:
2789         case PACKET3_INCREMENT_DE_COUNTER:
2790         case PACKET3_WAIT_ON_CE_COUNTER:
2791         case PACKET3_WAIT_ON_AVAIL_BUFFER:
2792         case PACKET3_ME_WRITE:
2793                 break;
2794         case PACKET3_COPY_DATA:
2795                 if ((idx_value & 0xf00) == 0) {
2796                         reg = ib[idx + 3] * 4;
2797                         if (!si_vm_reg_valid(reg))
2798                                 return -EINVAL;
2799                 }
2800                 break;
2801         case PACKET3_WRITE_DATA:
2802                 if ((idx_value & 0xf00) == 0) {
2803                         start_reg = ib[idx + 1] * 4;
2804                         if (idx_value & 0x10000) {
2805                                 if (!si_vm_reg_valid(start_reg))
2806                                         return -EINVAL;
2807                         } else {
2808                                 for (i = 0; i < (pkt->count - 2); i++) {
2809                                         reg = start_reg + (4 * i);
2810                                         if (!si_vm_reg_valid(reg))
2811                                                 return -EINVAL;
2812                                 }
2813                         }
2814                 }
2815                 break;
2816         case PACKET3_COND_WRITE:
2817                 if (idx_value & 0x100) {
2818                         reg = ib[idx + 5] * 4;
2819                         if (!si_vm_reg_valid(reg))
2820                                 return -EINVAL;
2821                 }
2822                 break;
2823         case PACKET3_COPY_DW:
2824                 if (idx_value & 0x2) {
2825                         reg = ib[idx + 3] * 4;
2826                         if (!si_vm_reg_valid(reg))
2827                                 return -EINVAL;
2828                 }
2829                 break;
2830         default:
2831                 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2832                 return -EINVAL;
2833         }
2834         return 0;
2835 }
2836
2837 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2838 {
2839         int ret = 0;
2840         u32 idx = 0;
2841         struct radeon_cs_packet pkt;
2842
2843         do {
2844                 pkt.idx = idx;
2845                 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2846                 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2847                 pkt.one_reg_wr = 0;
2848                 switch (pkt.type) {
2849                 case PACKET_TYPE0:
2850                         dev_err(rdev->dev, "Packet0 not allowed!\n");
2851                         ret = -EINVAL;
2852                         break;
2853                 case PACKET_TYPE2:
2854                         idx += 1;
2855                         break;
2856                 case PACKET_TYPE3:
2857                         pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2858                         if (ib->is_const_ib)
2859                                 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2860                         else {
2861                                 switch (ib->fence->ring) {
2862                                 case RADEON_RING_TYPE_GFX_INDEX:
2863                                         ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2864                                         break;
2865                                 case CAYMAN_RING_TYPE_CP1_INDEX:
2866                                 case CAYMAN_RING_TYPE_CP2_INDEX:
2867                                         ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2868                                         break;
2869                                 default:
2870                                         dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->fence->ring);
2871                                         ret = -EINVAL;
2872                                         break;
2873                                 }
2874                         }
2875                         idx += pkt.count + 2;
2876                         break;
2877                 default:
2878                         dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2879                         ret = -EINVAL;
2880                         break;
2881                 }
2882                 if (ret)
2883                         break;
2884         } while (idx < ib->length_dw);
2885
2886         return ret;
2887 }
2888
2889 /*
2890  * vm
2891  */
2892 int si_vm_init(struct radeon_device *rdev)
2893 {
2894         /* number of VMs */
2895         rdev->vm_manager.nvm = 16;
2896         /* base offset of vram pages */
2897         rdev->vm_manager.vram_base_offset = 0;
2898
2899         return 0;
2900 }
2901
2902 void si_vm_fini(struct radeon_device *rdev)
2903 {
2904 }
2905
2906 int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
2907 {
2908         if (id < 8)
2909                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
2910         else
2911                 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
2912                        vm->pt_gpu_addr >> 12);
2913         /* flush hdp cache */
2914         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2915         /* bits 0-15 are the VM contexts0-15 */
2916         WREG32(VM_INVALIDATE_REQUEST, 1 << id);
2917         return 0;
2918 }
2919
2920 void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
2921 {
2922         if (vm->id < 8)
2923                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
2924         else
2925                 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
2926         /* flush hdp cache */
2927         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2928         /* bits 0-15 are the VM contexts0-15 */
2929         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2930 }
2931
2932 void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
2933 {
2934         if (vm->id == -1)
2935                 return;
2936
2937         /* flush hdp cache */
2938         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2939         /* bits 0-15 are the VM contexts0-15 */
2940         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2941 }
2942