2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
30 #include "radeon_asic.h"
31 #include <drm/radeon_drm.h>
34 #include "si_blit_shaders.h"
36 #define SI_PFP_UCODE_SIZE 2144
37 #define SI_PM4_UCODE_SIZE 2144
38 #define SI_CE_UCODE_SIZE 2144
39 #define SI_RLC_UCODE_SIZE 2048
40 #define SI_MC_UCODE_SIZE 7769
42 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53 MODULE_FIRMWARE("radeon/VERDE_me.bin");
54 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
58 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59 extern void r600_ih_ring_fini(struct radeon_device *rdev);
60 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
61 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
63 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
64 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
65 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
67 /* get temperature in millidegrees */
68 int si_get_temp(struct radeon_device *rdev)
73 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
79 actual_temp = temp & 0x1ff;
81 actual_temp = (actual_temp * 1000);
86 #define TAHITI_IO_MC_REGS_SIZE 36
88 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
89 {0x0000006f, 0x03044000},
90 {0x00000070, 0x0480c018},
91 {0x00000071, 0x00000040},
92 {0x00000072, 0x01000000},
93 {0x00000074, 0x000000ff},
94 {0x00000075, 0x00143400},
95 {0x00000076, 0x08ec0800},
96 {0x00000077, 0x040000cc},
97 {0x00000079, 0x00000000},
98 {0x0000007a, 0x21000409},
99 {0x0000007c, 0x00000000},
100 {0x0000007d, 0xe8000000},
101 {0x0000007e, 0x044408a8},
102 {0x0000007f, 0x00000003},
103 {0x00000080, 0x00000000},
104 {0x00000081, 0x01000000},
105 {0x00000082, 0x02000000},
106 {0x00000083, 0x00000000},
107 {0x00000084, 0xe3f3e4f4},
108 {0x00000085, 0x00052024},
109 {0x00000087, 0x00000000},
110 {0x00000088, 0x66036603},
111 {0x00000089, 0x01000000},
112 {0x0000008b, 0x1c0a0000},
113 {0x0000008c, 0xff010000},
114 {0x0000008e, 0xffffefff},
115 {0x0000008f, 0xfff3efff},
116 {0x00000090, 0xfff3efbf},
117 {0x00000094, 0x00101101},
118 {0x00000095, 0x00000fff},
119 {0x00000096, 0x00116fff},
120 {0x00000097, 0x60010000},
121 {0x00000098, 0x10010000},
122 {0x00000099, 0x00006000},
123 {0x0000009a, 0x00001000},
124 {0x0000009f, 0x00a77400}
127 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
128 {0x0000006f, 0x03044000},
129 {0x00000070, 0x0480c018},
130 {0x00000071, 0x00000040},
131 {0x00000072, 0x01000000},
132 {0x00000074, 0x000000ff},
133 {0x00000075, 0x00143400},
134 {0x00000076, 0x08ec0800},
135 {0x00000077, 0x040000cc},
136 {0x00000079, 0x00000000},
137 {0x0000007a, 0x21000409},
138 {0x0000007c, 0x00000000},
139 {0x0000007d, 0xe8000000},
140 {0x0000007e, 0x044408a8},
141 {0x0000007f, 0x00000003},
142 {0x00000080, 0x00000000},
143 {0x00000081, 0x01000000},
144 {0x00000082, 0x02000000},
145 {0x00000083, 0x00000000},
146 {0x00000084, 0xe3f3e4f4},
147 {0x00000085, 0x00052024},
148 {0x00000087, 0x00000000},
149 {0x00000088, 0x66036603},
150 {0x00000089, 0x01000000},
151 {0x0000008b, 0x1c0a0000},
152 {0x0000008c, 0xff010000},
153 {0x0000008e, 0xffffefff},
154 {0x0000008f, 0xfff3efff},
155 {0x00000090, 0xfff3efbf},
156 {0x00000094, 0x00101101},
157 {0x00000095, 0x00000fff},
158 {0x00000096, 0x00116fff},
159 {0x00000097, 0x60010000},
160 {0x00000098, 0x10010000},
161 {0x00000099, 0x00006000},
162 {0x0000009a, 0x00001000},
163 {0x0000009f, 0x00a47400}
166 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
167 {0x0000006f, 0x03044000},
168 {0x00000070, 0x0480c018},
169 {0x00000071, 0x00000040},
170 {0x00000072, 0x01000000},
171 {0x00000074, 0x000000ff},
172 {0x00000075, 0x00143400},
173 {0x00000076, 0x08ec0800},
174 {0x00000077, 0x040000cc},
175 {0x00000079, 0x00000000},
176 {0x0000007a, 0x21000409},
177 {0x0000007c, 0x00000000},
178 {0x0000007d, 0xe8000000},
179 {0x0000007e, 0x044408a8},
180 {0x0000007f, 0x00000003},
181 {0x00000080, 0x00000000},
182 {0x00000081, 0x01000000},
183 {0x00000082, 0x02000000},
184 {0x00000083, 0x00000000},
185 {0x00000084, 0xe3f3e4f4},
186 {0x00000085, 0x00052024},
187 {0x00000087, 0x00000000},
188 {0x00000088, 0x66036603},
189 {0x00000089, 0x01000000},
190 {0x0000008b, 0x1c0a0000},
191 {0x0000008c, 0xff010000},
192 {0x0000008e, 0xffffefff},
193 {0x0000008f, 0xfff3efff},
194 {0x00000090, 0xfff3efbf},
195 {0x00000094, 0x00101101},
196 {0x00000095, 0x00000fff},
197 {0x00000096, 0x00116fff},
198 {0x00000097, 0x60010000},
199 {0x00000098, 0x10010000},
200 {0x00000099, 0x00006000},
201 {0x0000009a, 0x00001000},
202 {0x0000009f, 0x00a37400}
206 static int si_mc_load_microcode(struct radeon_device *rdev)
208 const __be32 *fw_data;
209 u32 running, blackout = 0;
211 int i, ucode_size, regs_size;
216 switch (rdev->family) {
218 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
219 ucode_size = SI_MC_UCODE_SIZE;
220 regs_size = TAHITI_IO_MC_REGS_SIZE;
223 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
224 ucode_size = SI_MC_UCODE_SIZE;
225 regs_size = TAHITI_IO_MC_REGS_SIZE;
229 io_mc_regs = (u32 *)&verde_io_mc_regs;
230 ucode_size = SI_MC_UCODE_SIZE;
231 regs_size = TAHITI_IO_MC_REGS_SIZE;
235 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
239 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
240 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
243 /* reset the engine and set to writable */
244 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
245 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
247 /* load mc io regs */
248 for (i = 0; i < regs_size; i++) {
249 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
250 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
252 /* load the MC ucode */
253 fw_data = (const __be32 *)rdev->mc_fw->data;
254 for (i = 0; i < ucode_size; i++)
255 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
257 /* put the engine back into the active state */
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
259 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
260 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
262 /* wait for training to complete */
263 for (i = 0; i < rdev->usec_timeout; i++) {
264 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
268 for (i = 0; i < rdev->usec_timeout; i++) {
269 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
275 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
281 static int si_init_microcode(struct radeon_device *rdev)
283 struct platform_device *pdev;
284 const char *chip_name;
285 const char *rlc_chip_name;
286 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
292 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
295 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
299 switch (rdev->family) {
301 chip_name = "TAHITI";
302 rlc_chip_name = "TAHITI";
303 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
304 me_req_size = SI_PM4_UCODE_SIZE * 4;
305 ce_req_size = SI_CE_UCODE_SIZE * 4;
306 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
307 mc_req_size = SI_MC_UCODE_SIZE * 4;
310 chip_name = "PITCAIRN";
311 rlc_chip_name = "PITCAIRN";
312 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
313 me_req_size = SI_PM4_UCODE_SIZE * 4;
314 ce_req_size = SI_CE_UCODE_SIZE * 4;
315 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
316 mc_req_size = SI_MC_UCODE_SIZE * 4;
320 rlc_chip_name = "VERDE";
321 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
322 me_req_size = SI_PM4_UCODE_SIZE * 4;
323 ce_req_size = SI_CE_UCODE_SIZE * 4;
324 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
325 mc_req_size = SI_MC_UCODE_SIZE * 4;
330 DRM_INFO("Loading %s Microcode\n", chip_name);
332 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
333 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
336 if (rdev->pfp_fw->size != pfp_req_size) {
338 "si_cp: Bogus length %zu in firmware \"%s\"\n",
339 rdev->pfp_fw->size, fw_name);
344 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
345 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
348 if (rdev->me_fw->size != me_req_size) {
350 "si_cp: Bogus length %zu in firmware \"%s\"\n",
351 rdev->me_fw->size, fw_name);
355 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
356 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
359 if (rdev->ce_fw->size != ce_req_size) {
361 "si_cp: Bogus length %zu in firmware \"%s\"\n",
362 rdev->ce_fw->size, fw_name);
366 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
367 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
370 if (rdev->rlc_fw->size != rlc_req_size) {
372 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
373 rdev->rlc_fw->size, fw_name);
377 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
378 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
381 if (rdev->mc_fw->size != mc_req_size) {
383 "si_mc: Bogus length %zu in firmware \"%s\"\n",
384 rdev->mc_fw->size, fw_name);
389 platform_device_unregister(pdev);
394 "si_cp: Failed to load firmware \"%s\"\n",
396 release_firmware(rdev->pfp_fw);
398 release_firmware(rdev->me_fw);
400 release_firmware(rdev->ce_fw);
402 release_firmware(rdev->rlc_fw);
404 release_firmware(rdev->mc_fw);
410 /* watermark setup */
411 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
412 struct radeon_crtc *radeon_crtc,
413 struct drm_display_mode *mode,
414 struct drm_display_mode *other_mode)
419 * There are 3 line buffers, each one shared by 2 display controllers.
420 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
421 * the display controllers. The paritioning is done via one of four
422 * preset allocations specified in bits 21:20:
424 * 2 - whole lb, other crtc must be disabled
426 /* this can get tricky if we have two large displays on a paired group
427 * of crtcs. Ideally for multiple large displays we'd assign them to
428 * non-linked crtcs for maximum line buffer allocation.
430 if (radeon_crtc->base.enabled && mode) {
438 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
439 DC_LB_MEMORY_CONFIG(tmp));
441 if (radeon_crtc->base.enabled && mode) {
451 /* controller not enabled, so no lb used */
455 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
457 u32 tmp = RREG32(MC_SHARED_CHMAP);
459 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
482 struct dce6_wm_params {
483 u32 dram_channels; /* number of dram channels */
484 u32 yclk; /* bandwidth per dram data pin in kHz */
485 u32 sclk; /* engine clock in kHz */
486 u32 disp_clk; /* display clock in kHz */
487 u32 src_width; /* viewport width */
488 u32 active_time; /* active display time in ns */
489 u32 blank_time; /* blank time in ns */
490 bool interlaced; /* mode is interlaced */
491 fixed20_12 vsc; /* vertical scale ratio */
492 u32 num_heads; /* number of active crtcs */
493 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
494 u32 lb_size; /* line buffer allocated to pipe */
495 u32 vtaps; /* vertical scaler taps */
498 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
500 /* Calculate raw DRAM Bandwidth */
501 fixed20_12 dram_efficiency; /* 0.7 */
502 fixed20_12 yclk, dram_channels, bandwidth;
505 a.full = dfixed_const(1000);
506 yclk.full = dfixed_const(wm->yclk);
507 yclk.full = dfixed_div(yclk, a);
508 dram_channels.full = dfixed_const(wm->dram_channels * 4);
509 a.full = dfixed_const(10);
510 dram_efficiency.full = dfixed_const(7);
511 dram_efficiency.full = dfixed_div(dram_efficiency, a);
512 bandwidth.full = dfixed_mul(dram_channels, yclk);
513 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
515 return dfixed_trunc(bandwidth);
518 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
520 /* Calculate DRAM Bandwidth and the part allocated to display. */
521 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
522 fixed20_12 yclk, dram_channels, bandwidth;
525 a.full = dfixed_const(1000);
526 yclk.full = dfixed_const(wm->yclk);
527 yclk.full = dfixed_div(yclk, a);
528 dram_channels.full = dfixed_const(wm->dram_channels * 4);
529 a.full = dfixed_const(10);
530 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
531 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
532 bandwidth.full = dfixed_mul(dram_channels, yclk);
533 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
535 return dfixed_trunc(bandwidth);
538 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
540 /* Calculate the display Data return Bandwidth */
541 fixed20_12 return_efficiency; /* 0.8 */
542 fixed20_12 sclk, bandwidth;
545 a.full = dfixed_const(1000);
546 sclk.full = dfixed_const(wm->sclk);
547 sclk.full = dfixed_div(sclk, a);
548 a.full = dfixed_const(10);
549 return_efficiency.full = dfixed_const(8);
550 return_efficiency.full = dfixed_div(return_efficiency, a);
551 a.full = dfixed_const(32);
552 bandwidth.full = dfixed_mul(a, sclk);
553 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
555 return dfixed_trunc(bandwidth);
558 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
563 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
565 /* Calculate the DMIF Request Bandwidth */
566 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
567 fixed20_12 disp_clk, sclk, bandwidth;
568 fixed20_12 a, b1, b2;
571 a.full = dfixed_const(1000);
572 disp_clk.full = dfixed_const(wm->disp_clk);
573 disp_clk.full = dfixed_div(disp_clk, a);
574 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
575 b1.full = dfixed_mul(a, disp_clk);
577 a.full = dfixed_const(1000);
578 sclk.full = dfixed_const(wm->sclk);
579 sclk.full = dfixed_div(sclk, a);
580 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
581 b2.full = dfixed_mul(a, sclk);
583 a.full = dfixed_const(10);
584 disp_clk_request_efficiency.full = dfixed_const(8);
585 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
587 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
589 a.full = dfixed_const(min_bandwidth);
590 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
592 return dfixed_trunc(bandwidth);
595 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
597 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
598 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
599 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
600 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
602 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
605 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
607 /* Calculate the display mode Average Bandwidth
608 * DisplayMode should contain the source and destination dimensions,
612 fixed20_12 line_time;
613 fixed20_12 src_width;
614 fixed20_12 bandwidth;
617 a.full = dfixed_const(1000);
618 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
619 line_time.full = dfixed_div(line_time, a);
620 bpp.full = dfixed_const(wm->bytes_per_pixel);
621 src_width.full = dfixed_const(wm->src_width);
622 bandwidth.full = dfixed_mul(src_width, bpp);
623 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
624 bandwidth.full = dfixed_div(bandwidth, line_time);
626 return dfixed_trunc(bandwidth);
629 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
631 /* First calcualte the latency in ns */
632 u32 mc_latency = 2000; /* 2000 ns. */
633 u32 available_bandwidth = dce6_available_bandwidth(wm);
634 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
635 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
636 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
637 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
638 (wm->num_heads * cursor_line_pair_return_time);
639 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
640 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
641 u32 tmp, dmif_size = 12288;
644 if (wm->num_heads == 0)
647 a.full = dfixed_const(2);
648 b.full = dfixed_const(1);
649 if ((wm->vsc.full > a.full) ||
650 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
652 ((wm->vsc.full >= a.full) && wm->interlaced))
653 max_src_lines_per_dst_line = 4;
655 max_src_lines_per_dst_line = 2;
657 a.full = dfixed_const(available_bandwidth);
658 b.full = dfixed_const(wm->num_heads);
659 a.full = dfixed_div(a, b);
661 b.full = dfixed_const(mc_latency + 512);
662 c.full = dfixed_const(wm->disp_clk);
663 b.full = dfixed_div(b, c);
665 c.full = dfixed_const(dmif_size);
666 b.full = dfixed_div(c, b);
668 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
670 b.full = dfixed_const(1000);
671 c.full = dfixed_const(wm->disp_clk);
672 b.full = dfixed_div(c, b);
673 c.full = dfixed_const(wm->bytes_per_pixel);
674 b.full = dfixed_mul(b, c);
676 lb_fill_bw = min(tmp, dfixed_trunc(b));
678 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
679 b.full = dfixed_const(1000);
680 c.full = dfixed_const(lb_fill_bw);
681 b.full = dfixed_div(c, b);
682 a.full = dfixed_div(a, b);
683 line_fill_time = dfixed_trunc(a);
685 if (line_fill_time < wm->active_time)
688 return latency + (line_fill_time - wm->active_time);
692 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
694 if (dce6_average_bandwidth(wm) <=
695 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
701 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
703 if (dce6_average_bandwidth(wm) <=
704 (dce6_available_bandwidth(wm) / wm->num_heads))
710 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
712 u32 lb_partitions = wm->lb_size / wm->src_width;
713 u32 line_time = wm->active_time + wm->blank_time;
714 u32 latency_tolerant_lines;
718 a.full = dfixed_const(1);
719 if (wm->vsc.full > a.full)
720 latency_tolerant_lines = 1;
722 if (lb_partitions <= (wm->vtaps + 1))
723 latency_tolerant_lines = 1;
725 latency_tolerant_lines = 2;
728 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
730 if (dce6_latency_watermark(wm) <= latency_hiding)
736 static void dce6_program_watermarks(struct radeon_device *rdev,
737 struct radeon_crtc *radeon_crtc,
738 u32 lb_size, u32 num_heads)
740 struct drm_display_mode *mode = &radeon_crtc->base.mode;
741 struct dce6_wm_params wm;
744 u32 latency_watermark_a = 0, latency_watermark_b = 0;
745 u32 priority_a_mark = 0, priority_b_mark = 0;
746 u32 priority_a_cnt = PRIORITY_OFF;
747 u32 priority_b_cnt = PRIORITY_OFF;
748 u32 tmp, arb_control3;
751 if (radeon_crtc->base.enabled && num_heads && mode) {
752 pixel_period = 1000000 / (u32)mode->clock;
753 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
757 wm.yclk = rdev->pm.current_mclk * 10;
758 wm.sclk = rdev->pm.current_sclk * 10;
759 wm.disp_clk = mode->clock;
760 wm.src_width = mode->crtc_hdisplay;
761 wm.active_time = mode->crtc_hdisplay * pixel_period;
762 wm.blank_time = line_time - wm.active_time;
763 wm.interlaced = false;
764 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
765 wm.interlaced = true;
766 wm.vsc = radeon_crtc->vsc;
768 if (radeon_crtc->rmx_type != RMX_OFF)
770 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
771 wm.lb_size = lb_size;
772 if (rdev->family == CHIP_ARUBA)
773 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
775 wm.dram_channels = si_get_number_of_dram_channels(rdev);
776 wm.num_heads = num_heads;
778 /* set for high clocks */
779 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
780 /* set for low clocks */
781 /* wm.yclk = low clk; wm.sclk = low clk */
782 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
784 /* possibly force display priority to high */
785 /* should really do this at mode validation time... */
786 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
787 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
788 !dce6_check_latency_hiding(&wm) ||
789 (rdev->disp_priority == 2)) {
790 DRM_DEBUG_KMS("force priority to high\n");
791 priority_a_cnt |= PRIORITY_ALWAYS_ON;
792 priority_b_cnt |= PRIORITY_ALWAYS_ON;
795 a.full = dfixed_const(1000);
796 b.full = dfixed_const(mode->clock);
797 b.full = dfixed_div(b, a);
798 c.full = dfixed_const(latency_watermark_a);
799 c.full = dfixed_mul(c, b);
800 c.full = dfixed_mul(c, radeon_crtc->hsc);
801 c.full = dfixed_div(c, a);
802 a.full = dfixed_const(16);
803 c.full = dfixed_div(c, a);
804 priority_a_mark = dfixed_trunc(c);
805 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
807 a.full = dfixed_const(1000);
808 b.full = dfixed_const(mode->clock);
809 b.full = dfixed_div(b, a);
810 c.full = dfixed_const(latency_watermark_b);
811 c.full = dfixed_mul(c, b);
812 c.full = dfixed_mul(c, radeon_crtc->hsc);
813 c.full = dfixed_div(c, a);
814 a.full = dfixed_const(16);
815 c.full = dfixed_div(c, a);
816 priority_b_mark = dfixed_trunc(c);
817 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
821 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
823 tmp &= ~LATENCY_WATERMARK_MASK(3);
824 tmp |= LATENCY_WATERMARK_MASK(1);
825 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
826 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
827 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
828 LATENCY_HIGH_WATERMARK(line_time)));
830 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
831 tmp &= ~LATENCY_WATERMARK_MASK(3);
832 tmp |= LATENCY_WATERMARK_MASK(2);
833 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
834 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
835 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
836 LATENCY_HIGH_WATERMARK(line_time)));
837 /* restore original selection */
838 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
840 /* write the priority marks */
841 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
842 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
846 void dce6_bandwidth_update(struct radeon_device *rdev)
848 struct drm_display_mode *mode0 = NULL;
849 struct drm_display_mode *mode1 = NULL;
850 u32 num_heads = 0, lb_size;
853 radeon_update_display_priority(rdev);
855 for (i = 0; i < rdev->num_crtc; i++) {
856 if (rdev->mode_info.crtcs[i]->base.enabled)
859 for (i = 0; i < rdev->num_crtc; i += 2) {
860 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
861 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
862 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
863 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
864 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
865 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
872 static void si_tiling_mode_table_init(struct radeon_device *rdev)
874 const u32 num_tile_mode_states = 32;
875 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
877 switch (rdev->config.si.mem_row_size_in_kb) {
879 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
883 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
886 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
890 if ((rdev->family == CHIP_TAHITI) ||
891 (rdev->family == CHIP_PITCAIRN)) {
892 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
893 switch (reg_offset) {
894 case 0: /* non-AA compressed depth or any compressed stencil */
895 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
896 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
897 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
898 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
899 NUM_BANKS(ADDR_SURF_16_BANK) |
900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
904 case 1: /* 2xAA/4xAA compressed depth only */
905 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
906 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
907 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
909 NUM_BANKS(ADDR_SURF_16_BANK) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
914 case 2: /* 8xAA compressed depth only */
915 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
917 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
918 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
919 NUM_BANKS(ADDR_SURF_16_BANK) |
920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
924 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
925 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
927 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
929 NUM_BANKS(ADDR_SURF_16_BANK) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
934 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
935 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
936 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
937 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
938 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
939 NUM_BANKS(ADDR_SURF_16_BANK) |
940 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
941 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
942 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
944 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
945 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
947 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
948 TILE_SPLIT(split_equal_to_row_size) |
949 NUM_BANKS(ADDR_SURF_16_BANK) |
950 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
954 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
957 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
958 TILE_SPLIT(split_equal_to_row_size) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
961 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
962 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
964 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
965 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
967 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
968 TILE_SPLIT(split_equal_to_row_size) |
969 NUM_BANKS(ADDR_SURF_16_BANK) |
970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
974 case 8: /* 1D and 1D Array Surfaces */
975 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
976 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
977 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
979 NUM_BANKS(ADDR_SURF_16_BANK) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
984 case 9: /* Displayable maps. */
985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
986 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
987 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
989 NUM_BANKS(ADDR_SURF_16_BANK) |
990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
994 case 10: /* Display 8bpp. */
995 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
996 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
997 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
998 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
999 NUM_BANKS(ADDR_SURF_16_BANK) |
1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1004 case 11: /* Display 16bpp. */
1005 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1006 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1008 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1009 NUM_BANKS(ADDR_SURF_16_BANK) |
1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1014 case 12: /* Display 32bpp. */
1015 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1016 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1017 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1019 NUM_BANKS(ADDR_SURF_16_BANK) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1024 case 13: /* Thin. */
1025 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1026 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1027 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1029 NUM_BANKS(ADDR_SURF_16_BANK) |
1030 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1034 case 14: /* Thin 8 bpp. */
1035 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1036 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1037 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1039 NUM_BANKS(ADDR_SURF_16_BANK) |
1040 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1044 case 15: /* Thin 16 bpp. */
1045 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1047 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1049 NUM_BANKS(ADDR_SURF_16_BANK) |
1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1054 case 16: /* Thin 32 bpp. */
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1057 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1059 NUM_BANKS(ADDR_SURF_16_BANK) |
1060 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1064 case 17: /* Thin 64 bpp. */
1065 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1067 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1068 TILE_SPLIT(split_equal_to_row_size) |
1069 NUM_BANKS(ADDR_SURF_16_BANK) |
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1074 case 21: /* 8 bpp PRT. */
1075 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1076 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1079 NUM_BANKS(ADDR_SURF_16_BANK) |
1080 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1081 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1082 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1084 case 22: /* 16 bpp PRT */
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1089 NUM_BANKS(ADDR_SURF_16_BANK) |
1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1094 case 23: /* 32 bpp PRT */
1095 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 NUM_BANKS(ADDR_SURF_16_BANK) |
1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1104 case 24: /* 64 bpp PRT */
1105 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1109 NUM_BANKS(ADDR_SURF_16_BANK) |
1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1114 case 25: /* 128 bpp PRT */
1115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1119 NUM_BANKS(ADDR_SURF_8_BANK) |
1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1128 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1130 } else if (rdev->family == CHIP_VERDE) {
1131 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1132 switch (reg_offset) {
1133 case 0: /* non-AA compressed depth or any compressed stencil */
1134 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1135 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1136 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1138 NUM_BANKS(ADDR_SURF_16_BANK) |
1139 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1141 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1143 case 1: /* 2xAA/4xAA compressed depth only */
1144 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1145 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1146 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1147 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1148 NUM_BANKS(ADDR_SURF_16_BANK) |
1149 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1153 case 2: /* 8xAA compressed depth only */
1154 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1155 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1156 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1158 NUM_BANKS(ADDR_SURF_16_BANK) |
1159 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1163 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1164 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1165 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1166 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1167 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1168 NUM_BANKS(ADDR_SURF_16_BANK) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1173 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1174 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1175 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1176 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1177 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1178 NUM_BANKS(ADDR_SURF_16_BANK) |
1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1183 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1184 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1185 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1186 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1187 TILE_SPLIT(split_equal_to_row_size) |
1188 NUM_BANKS(ADDR_SURF_16_BANK) |
1189 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1193 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1194 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1196 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1197 TILE_SPLIT(split_equal_to_row_size) |
1198 NUM_BANKS(ADDR_SURF_16_BANK) |
1199 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1203 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1204 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1206 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1207 TILE_SPLIT(split_equal_to_row_size) |
1208 NUM_BANKS(ADDR_SURF_16_BANK) |
1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1213 case 8: /* 1D and 1D Array Surfaces */
1214 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1215 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1216 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1218 NUM_BANKS(ADDR_SURF_16_BANK) |
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1223 case 9: /* Displayable maps. */
1224 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1228 NUM_BANKS(ADDR_SURF_16_BANK) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1233 case 10: /* Display 8bpp. */
1234 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1238 NUM_BANKS(ADDR_SURF_16_BANK) |
1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1243 case 11: /* Display 16bpp. */
1244 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1248 NUM_BANKS(ADDR_SURF_16_BANK) |
1249 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1253 case 12: /* Display 32bpp. */
1254 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1255 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1258 NUM_BANKS(ADDR_SURF_16_BANK) |
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1263 case 13: /* Thin. */
1264 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1265 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1268 NUM_BANKS(ADDR_SURF_16_BANK) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1273 case 14: /* Thin 8 bpp. */
1274 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1275 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1278 NUM_BANKS(ADDR_SURF_16_BANK) |
1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1283 case 15: /* Thin 16 bpp. */
1284 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1285 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1286 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1288 NUM_BANKS(ADDR_SURF_16_BANK) |
1289 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1293 case 16: /* Thin 32 bpp. */
1294 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1295 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1296 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1297 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1298 NUM_BANKS(ADDR_SURF_16_BANK) |
1299 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1300 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1301 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1303 case 17: /* Thin 64 bpp. */
1304 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1305 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1306 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1307 TILE_SPLIT(split_equal_to_row_size) |
1308 NUM_BANKS(ADDR_SURF_16_BANK) |
1309 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1310 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1311 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1313 case 21: /* 8 bpp PRT. */
1314 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1315 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1316 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1318 NUM_BANKS(ADDR_SURF_16_BANK) |
1319 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1323 case 22: /* 16 bpp PRT */
1324 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1326 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1327 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1328 NUM_BANKS(ADDR_SURF_16_BANK) |
1329 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1330 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1331 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1333 case 23: /* 32 bpp PRT */
1334 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1335 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1336 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1337 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1338 NUM_BANKS(ADDR_SURF_16_BANK) |
1339 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1343 case 24: /* 64 bpp PRT */
1344 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1347 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1348 NUM_BANKS(ADDR_SURF_16_BANK) |
1349 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1353 case 25: /* 128 bpp PRT */
1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1356 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1357 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1358 NUM_BANKS(ADDR_SURF_8_BANK) |
1359 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1367 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1370 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1373 static void si_select_se_sh(struct radeon_device *rdev,
1374 u32 se_num, u32 sh_num)
1376 u32 data = INSTANCE_BROADCAST_WRITES;
1378 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1379 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1380 else if (se_num == 0xffffffff)
1381 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1382 else if (sh_num == 0xffffffff)
1383 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1385 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1386 WREG32(GRBM_GFX_INDEX, data);
1389 static u32 si_create_bitmask(u32 bit_width)
1393 for (i = 0; i < bit_width; i++) {
1400 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1404 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1406 data &= INACTIVE_CUS_MASK;
1409 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1411 data >>= INACTIVE_CUS_SHIFT;
1413 mask = si_create_bitmask(cu_per_sh);
1415 return ~data & mask;
1418 static void si_setup_spi(struct radeon_device *rdev,
1419 u32 se_num, u32 sh_per_se,
1423 u32 data, mask, active_cu;
1425 for (i = 0; i < se_num; i++) {
1426 for (j = 0; j < sh_per_se; j++) {
1427 si_select_se_sh(rdev, i, j);
1428 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1429 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1432 for (k = 0; k < 16; k++) {
1434 if (active_cu & mask) {
1436 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1442 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1445 static u32 si_get_rb_disabled(struct radeon_device *rdev,
1446 u32 max_rb_num, u32 se_num,
1451 data = RREG32(CC_RB_BACKEND_DISABLE);
1453 data &= BACKEND_DISABLE_MASK;
1456 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1458 data >>= BACKEND_DISABLE_SHIFT;
1460 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1465 static void si_setup_rb(struct radeon_device *rdev,
1466 u32 se_num, u32 sh_per_se,
1471 u32 disabled_rbs = 0;
1472 u32 enabled_rbs = 0;
1474 for (i = 0; i < se_num; i++) {
1475 for (j = 0; j < sh_per_se; j++) {
1476 si_select_se_sh(rdev, i, j);
1477 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1478 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1481 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1484 for (i = 0; i < max_rb_num; i++) {
1485 if (!(disabled_rbs & mask))
1486 enabled_rbs |= mask;
1490 for (i = 0; i < se_num; i++) {
1491 si_select_se_sh(rdev, i, 0xffffffff);
1493 for (j = 0; j < sh_per_se; j++) {
1494 switch (enabled_rbs & 3) {
1496 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1499 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1503 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1508 WREG32(PA_SC_RASTER_CONFIG, data);
1510 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1513 static void si_gpu_init(struct radeon_device *rdev)
1515 u32 gb_addr_config = 0;
1516 u32 mc_shared_chmap, mc_arb_ramcfg;
1518 u32 hdp_host_path_cntl;
1522 switch (rdev->family) {
1524 rdev->config.si.max_shader_engines = 2;
1525 rdev->config.si.max_tile_pipes = 12;
1526 rdev->config.si.max_cu_per_sh = 8;
1527 rdev->config.si.max_sh_per_se = 2;
1528 rdev->config.si.max_backends_per_se = 4;
1529 rdev->config.si.max_texture_channel_caches = 12;
1530 rdev->config.si.max_gprs = 256;
1531 rdev->config.si.max_gs_threads = 32;
1532 rdev->config.si.max_hw_contexts = 8;
1534 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1535 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1536 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1537 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1538 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1541 rdev->config.si.max_shader_engines = 2;
1542 rdev->config.si.max_tile_pipes = 8;
1543 rdev->config.si.max_cu_per_sh = 5;
1544 rdev->config.si.max_sh_per_se = 2;
1545 rdev->config.si.max_backends_per_se = 4;
1546 rdev->config.si.max_texture_channel_caches = 8;
1547 rdev->config.si.max_gprs = 256;
1548 rdev->config.si.max_gs_threads = 32;
1549 rdev->config.si.max_hw_contexts = 8;
1551 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1552 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1553 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1554 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1555 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1559 rdev->config.si.max_shader_engines = 1;
1560 rdev->config.si.max_tile_pipes = 4;
1561 rdev->config.si.max_cu_per_sh = 2;
1562 rdev->config.si.max_sh_per_se = 2;
1563 rdev->config.si.max_backends_per_se = 4;
1564 rdev->config.si.max_texture_channel_caches = 4;
1565 rdev->config.si.max_gprs = 256;
1566 rdev->config.si.max_gs_threads = 32;
1567 rdev->config.si.max_hw_contexts = 8;
1569 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1570 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1571 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1572 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1573 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1577 /* Initialize HDP */
1578 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1579 WREG32((0x2c14 + j), 0x00000000);
1580 WREG32((0x2c18 + j), 0x00000000);
1581 WREG32((0x2c1c + j), 0x00000000);
1582 WREG32((0x2c20 + j), 0x00000000);
1583 WREG32((0x2c24 + j), 0x00000000);
1586 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1588 evergreen_fix_pci_max_read_req_size(rdev);
1590 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1592 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1593 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1595 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1596 rdev->config.si.mem_max_burst_length_bytes = 256;
1597 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1598 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1599 if (rdev->config.si.mem_row_size_in_kb > 4)
1600 rdev->config.si.mem_row_size_in_kb = 4;
1601 /* XXX use MC settings? */
1602 rdev->config.si.shader_engine_tile_size = 32;
1603 rdev->config.si.num_gpus = 1;
1604 rdev->config.si.multi_gpu_tile_size = 64;
1606 /* fix up row size */
1607 gb_addr_config &= ~ROW_SIZE_MASK;
1608 switch (rdev->config.si.mem_row_size_in_kb) {
1611 gb_addr_config |= ROW_SIZE(0);
1614 gb_addr_config |= ROW_SIZE(1);
1617 gb_addr_config |= ROW_SIZE(2);
1621 /* setup tiling info dword. gb_addr_config is not adequate since it does
1622 * not have bank info, so create a custom tiling dword.
1623 * bits 3:0 num_pipes
1624 * bits 7:4 num_banks
1625 * bits 11:8 group_size
1626 * bits 15:12 row_size
1628 rdev->config.si.tile_config = 0;
1629 switch (rdev->config.si.num_tile_pipes) {
1631 rdev->config.si.tile_config |= (0 << 0);
1634 rdev->config.si.tile_config |= (1 << 0);
1637 rdev->config.si.tile_config |= (2 << 0);
1641 /* XXX what about 12? */
1642 rdev->config.si.tile_config |= (3 << 0);
1645 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1646 case 0: /* four banks */
1647 rdev->config.si.tile_config |= 0 << 4;
1649 case 1: /* eight banks */
1650 rdev->config.si.tile_config |= 1 << 4;
1652 case 2: /* sixteen banks */
1654 rdev->config.si.tile_config |= 2 << 4;
1657 rdev->config.si.tile_config |=
1658 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1659 rdev->config.si.tile_config |=
1660 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1662 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1663 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1664 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1665 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1666 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1668 si_tiling_mode_table_init(rdev);
1670 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1671 rdev->config.si.max_sh_per_se,
1672 rdev->config.si.max_backends_per_se);
1674 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1675 rdev->config.si.max_sh_per_se,
1676 rdev->config.si.max_cu_per_sh);
1679 /* set HW defaults for 3D engine */
1680 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1681 ROQ_IB2_START(0x2b)));
1682 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1684 sx_debug_1 = RREG32(SX_DEBUG_1);
1685 WREG32(SX_DEBUG_1, sx_debug_1);
1687 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1689 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1690 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1691 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1692 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1694 WREG32(VGT_NUM_INSTANCES, 1);
1696 WREG32(CP_PERFMON_CNTL, 0);
1698 WREG32(SQ_CONFIG, 0);
1700 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1701 FORCE_EOV_MAX_REZ_CNT(255)));
1703 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1704 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1706 WREG32(VGT_GS_VERTEX_REUSE, 16);
1707 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1709 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1710 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1711 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1712 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1713 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1714 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1715 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1716 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1718 tmp = RREG32(HDP_MISC_CNTL);
1719 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1720 WREG32(HDP_MISC_CNTL, tmp);
1722 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1723 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1725 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1731 * GPU scratch registers helpers function.
1733 static void si_scratch_init(struct radeon_device *rdev)
1737 rdev->scratch.num_reg = 7;
1738 rdev->scratch.reg_base = SCRATCH_REG0;
1739 for (i = 0; i < rdev->scratch.num_reg; i++) {
1740 rdev->scratch.free[i] = true;
1741 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1745 void si_fence_ring_emit(struct radeon_device *rdev,
1746 struct radeon_fence *fence)
1748 struct radeon_ring *ring = &rdev->ring[fence->ring];
1749 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1751 /* flush read cache over gart */
1752 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1753 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1754 radeon_ring_write(ring, 0);
1755 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1756 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1757 PACKET3_TC_ACTION_ENA |
1758 PACKET3_SH_KCACHE_ACTION_ENA |
1759 PACKET3_SH_ICACHE_ACTION_ENA);
1760 radeon_ring_write(ring, 0xFFFFFFFF);
1761 radeon_ring_write(ring, 0);
1762 radeon_ring_write(ring, 10); /* poll interval */
1763 /* EVENT_WRITE_EOP - flush caches, send int */
1764 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1765 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1766 radeon_ring_write(ring, addr & 0xffffffff);
1767 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1768 radeon_ring_write(ring, fence->seq);
1769 radeon_ring_write(ring, 0);
1775 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1777 struct radeon_ring *ring = &rdev->ring[ib->ring];
1780 if (ib->is_const_ib) {
1781 /* set switch buffer packet before const IB */
1782 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1783 radeon_ring_write(ring, 0);
1785 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1788 if (ring->rptr_save_reg) {
1789 next_rptr = ring->wptr + 3 + 4 + 8;
1790 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 radeon_ring_write(ring, ((ring->rptr_save_reg -
1792 PACKET3_SET_CONFIG_REG_START) >> 2));
1793 radeon_ring_write(ring, next_rptr);
1794 } else if (rdev->wb.enabled) {
1795 next_rptr = ring->wptr + 5 + 4 + 8;
1796 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1797 radeon_ring_write(ring, (1 << 8));
1798 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1799 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1800 radeon_ring_write(ring, next_rptr);
1803 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1806 radeon_ring_write(ring, header);
1807 radeon_ring_write(ring,
1811 (ib->gpu_addr & 0xFFFFFFFC));
1812 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1813 radeon_ring_write(ring, ib->length_dw |
1814 (ib->vm ? (ib->vm->id << 24) : 0));
1816 if (!ib->is_const_ib) {
1817 /* flush read cache over gart for this vmid */
1818 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1819 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1820 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1821 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1822 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1823 PACKET3_TC_ACTION_ENA |
1824 PACKET3_SH_KCACHE_ACTION_ENA |
1825 PACKET3_SH_ICACHE_ACTION_ENA);
1826 radeon_ring_write(ring, 0xFFFFFFFF);
1827 radeon_ring_write(ring, 0);
1828 radeon_ring_write(ring, 10); /* poll interval */
1835 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1838 WREG32(CP_ME_CNTL, 0);
1840 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1841 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1842 WREG32(SCRATCH_UMSK, 0);
1843 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1844 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1845 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1850 static int si_cp_load_microcode(struct radeon_device *rdev)
1852 const __be32 *fw_data;
1855 if (!rdev->me_fw || !rdev->pfp_fw)
1858 si_cp_enable(rdev, false);
1861 fw_data = (const __be32 *)rdev->pfp_fw->data;
1862 WREG32(CP_PFP_UCODE_ADDR, 0);
1863 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1864 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1865 WREG32(CP_PFP_UCODE_ADDR, 0);
1868 fw_data = (const __be32 *)rdev->ce_fw->data;
1869 WREG32(CP_CE_UCODE_ADDR, 0);
1870 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1871 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1872 WREG32(CP_CE_UCODE_ADDR, 0);
1875 fw_data = (const __be32 *)rdev->me_fw->data;
1876 WREG32(CP_ME_RAM_WADDR, 0);
1877 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1878 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1879 WREG32(CP_ME_RAM_WADDR, 0);
1881 WREG32(CP_PFP_UCODE_ADDR, 0);
1882 WREG32(CP_CE_UCODE_ADDR, 0);
1883 WREG32(CP_ME_RAM_WADDR, 0);
1884 WREG32(CP_ME_RAM_RADDR, 0);
1888 static int si_cp_start(struct radeon_device *rdev)
1890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1893 r = radeon_ring_lock(rdev, ring, 7 + 4);
1895 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1899 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1900 radeon_ring_write(ring, 0x1);
1901 radeon_ring_write(ring, 0x0);
1902 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1903 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1904 radeon_ring_write(ring, 0);
1905 radeon_ring_write(ring, 0);
1907 /* init the CE partitions */
1908 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1909 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1910 radeon_ring_write(ring, 0xc000);
1911 radeon_ring_write(ring, 0xe000);
1912 radeon_ring_unlock_commit(rdev, ring);
1914 si_cp_enable(rdev, true);
1916 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1918 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1922 /* setup clear context state */
1923 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1924 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1926 for (i = 0; i < si_default_size; i++)
1927 radeon_ring_write(ring, si_default_state[i]);
1929 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1930 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1932 /* set clear context state */
1933 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1934 radeon_ring_write(ring, 0);
1936 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1937 radeon_ring_write(ring, 0x00000316);
1938 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1939 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1941 radeon_ring_unlock_commit(rdev, ring);
1943 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
1944 ring = &rdev->ring[i];
1945 r = radeon_ring_lock(rdev, ring, 2);
1947 /* clear the compute context state */
1948 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
1949 radeon_ring_write(ring, 0);
1951 radeon_ring_unlock_commit(rdev, ring);
1957 static void si_cp_fini(struct radeon_device *rdev)
1959 struct radeon_ring *ring;
1960 si_cp_enable(rdev, false);
1962 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1963 radeon_ring_fini(rdev, ring);
1964 radeon_scratch_free(rdev, ring->rptr_save_reg);
1966 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1967 radeon_ring_fini(rdev, ring);
1968 radeon_scratch_free(rdev, ring->rptr_save_reg);
1970 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1971 radeon_ring_fini(rdev, ring);
1972 radeon_scratch_free(rdev, ring->rptr_save_reg);
1975 static int si_cp_resume(struct radeon_device *rdev)
1977 struct radeon_ring *ring;
1982 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1983 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1988 RREG32(GRBM_SOFT_RESET);
1990 WREG32(GRBM_SOFT_RESET, 0);
1991 RREG32(GRBM_SOFT_RESET);
1993 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1994 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1996 /* Set the write pointer delay */
1997 WREG32(CP_RB_WPTR_DELAY, 0);
1999 WREG32(CP_DEBUG, 0);
2000 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2002 /* ring 0 - compute and gfx */
2003 /* Set ring buffer size */
2004 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2005 rb_bufsz = drm_order(ring->ring_size / 8);
2006 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2008 tmp |= BUF_SWAP_32BIT;
2010 WREG32(CP_RB0_CNTL, tmp);
2012 /* Initialize the ring buffer's read and write pointers */
2013 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2015 WREG32(CP_RB0_WPTR, ring->wptr);
2017 /* set the wb address whether it's enabled or not */
2018 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2019 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2021 if (rdev->wb.enabled)
2022 WREG32(SCRATCH_UMSK, 0xff);
2024 tmp |= RB_NO_UPDATE;
2025 WREG32(SCRATCH_UMSK, 0);
2029 WREG32(CP_RB0_CNTL, tmp);
2031 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2033 ring->rptr = RREG32(CP_RB0_RPTR);
2035 /* ring1 - compute only */
2036 /* Set ring buffer size */
2037 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2038 rb_bufsz = drm_order(ring->ring_size / 8);
2039 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2041 tmp |= BUF_SWAP_32BIT;
2043 WREG32(CP_RB1_CNTL, tmp);
2045 /* Initialize the ring buffer's read and write pointers */
2046 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2048 WREG32(CP_RB1_WPTR, ring->wptr);
2050 /* set the wb address whether it's enabled or not */
2051 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2052 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2055 WREG32(CP_RB1_CNTL, tmp);
2057 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2059 ring->rptr = RREG32(CP_RB1_RPTR);
2061 /* ring2 - compute only */
2062 /* Set ring buffer size */
2063 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2064 rb_bufsz = drm_order(ring->ring_size / 8);
2065 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2067 tmp |= BUF_SWAP_32BIT;
2069 WREG32(CP_RB2_CNTL, tmp);
2071 /* Initialize the ring buffer's read and write pointers */
2072 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2074 WREG32(CP_RB2_WPTR, ring->wptr);
2076 /* set the wb address whether it's enabled or not */
2077 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2078 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2081 WREG32(CP_RB2_CNTL, tmp);
2083 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2085 ring->rptr = RREG32(CP_RB2_RPTR);
2087 /* start the rings */
2089 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2090 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2091 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2092 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2094 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2095 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2096 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2099 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2101 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2103 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2105 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2111 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2114 u32 grbm_status, grbm_status2;
2115 u32 grbm_status_se0, grbm_status_se1;
2117 srbm_status = RREG32(SRBM_STATUS);
2118 grbm_status = RREG32(GRBM_STATUS);
2119 grbm_status2 = RREG32(GRBM_STATUS2);
2120 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2121 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2122 if (!(grbm_status & GUI_ACTIVE)) {
2123 radeon_ring_lockup_update(ring);
2126 /* force CP activities */
2127 radeon_ring_force_activity(rdev, ring);
2128 return radeon_ring_test_lockup(rdev, ring);
2131 static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
2137 tmp = RREG32(GRBM_STATUS);
2138 if (tmp & (PA_BUSY | SC_BUSY |
2139 BCI_BUSY | SX_BUSY |
2140 TA_BUSY | VGT_BUSY |
2142 GDS_BUSY | SPI_BUSY |
2143 IA_BUSY | IA_BUSY_NO_DMA))
2144 reset_mask |= RADEON_RESET_GFX;
2146 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2147 CP_BUSY | CP_COHERENCY_BUSY))
2148 reset_mask |= RADEON_RESET_CP;
2150 if (tmp & GRBM_EE_BUSY)
2151 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2154 tmp = RREG32(GRBM_STATUS2);
2155 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2156 reset_mask |= RADEON_RESET_RLC;
2158 /* DMA_STATUS_REG 0 */
2159 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2160 if (!(tmp & DMA_IDLE))
2161 reset_mask |= RADEON_RESET_DMA;
2163 /* DMA_STATUS_REG 1 */
2164 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2165 if (!(tmp & DMA_IDLE))
2166 reset_mask |= RADEON_RESET_DMA1;
2169 tmp = RREG32(SRBM_STATUS2);
2171 reset_mask |= RADEON_RESET_DMA;
2173 if (tmp & DMA1_BUSY)
2174 reset_mask |= RADEON_RESET_DMA1;
2177 tmp = RREG32(SRBM_STATUS);
2180 reset_mask |= RADEON_RESET_IH;
2183 reset_mask |= RADEON_RESET_SEM;
2185 if (tmp & GRBM_RQ_PENDING)
2186 reset_mask |= RADEON_RESET_GRBM;
2189 reset_mask |= RADEON_RESET_VMC;
2191 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2192 MCC_BUSY | MCD_BUSY))
2193 reset_mask |= RADEON_RESET_MC;
2195 if (evergreen_is_display_hung(rdev))
2196 reset_mask |= RADEON_RESET_DISPLAY;
2199 tmp = RREG32(VM_L2_STATUS);
2201 reset_mask |= RADEON_RESET_VMC;
2206 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2208 struct evergreen_mc_save save;
2209 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2212 if (reset_mask == 0)
2215 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2217 evergreen_print_gpu_status_regs(rdev);
2218 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2219 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2220 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2221 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2223 evergreen_mc_stop(rdev, &save);
2224 if (evergreen_mc_wait_for_idle(rdev)) {
2225 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2228 /* Disable CP parsing/prefetching */
2229 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2231 if (reset_mask & RADEON_RESET_DMA) {
2233 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2234 tmp &= ~DMA_RB_ENABLE;
2235 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2237 if (reset_mask & RADEON_RESET_DMA1) {
2239 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2240 tmp &= ~DMA_RB_ENABLE;
2241 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2244 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2245 grbm_soft_reset = SOFT_RESET_CB |
2259 if (reset_mask & RADEON_RESET_CP) {
2260 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2262 srbm_soft_reset |= SOFT_RESET_GRBM;
2265 if (reset_mask & RADEON_RESET_DMA)
2266 srbm_soft_reset |= SOFT_RESET_DMA;
2268 if (reset_mask & RADEON_RESET_DMA1)
2269 srbm_soft_reset |= SOFT_RESET_DMA1;
2271 if (reset_mask & RADEON_RESET_DISPLAY)
2272 srbm_soft_reset |= SOFT_RESET_DC;
2274 if (reset_mask & RADEON_RESET_RLC)
2275 grbm_soft_reset |= SOFT_RESET_RLC;
2277 if (reset_mask & RADEON_RESET_SEM)
2278 srbm_soft_reset |= SOFT_RESET_SEM;
2280 if (reset_mask & RADEON_RESET_IH)
2281 srbm_soft_reset |= SOFT_RESET_IH;
2283 if (reset_mask & RADEON_RESET_GRBM)
2284 srbm_soft_reset |= SOFT_RESET_GRBM;
2286 if (reset_mask & RADEON_RESET_VMC)
2287 srbm_soft_reset |= SOFT_RESET_VMC;
2289 if (reset_mask & RADEON_RESET_MC)
2290 srbm_soft_reset |= SOFT_RESET_MC;
2292 if (grbm_soft_reset) {
2293 tmp = RREG32(GRBM_SOFT_RESET);
2294 tmp |= grbm_soft_reset;
2295 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2296 WREG32(GRBM_SOFT_RESET, tmp);
2297 tmp = RREG32(GRBM_SOFT_RESET);
2301 tmp &= ~grbm_soft_reset;
2302 WREG32(GRBM_SOFT_RESET, tmp);
2303 tmp = RREG32(GRBM_SOFT_RESET);
2306 if (srbm_soft_reset) {
2307 tmp = RREG32(SRBM_SOFT_RESET);
2308 tmp |= srbm_soft_reset;
2309 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2310 WREG32(SRBM_SOFT_RESET, tmp);
2311 tmp = RREG32(SRBM_SOFT_RESET);
2315 tmp &= ~srbm_soft_reset;
2316 WREG32(SRBM_SOFT_RESET, tmp);
2317 tmp = RREG32(SRBM_SOFT_RESET);
2320 /* Wait a little for things to settle down */
2323 evergreen_mc_resume(rdev, &save);
2326 evergreen_print_gpu_status_regs(rdev);
2329 int si_asic_reset(struct radeon_device *rdev)
2333 reset_mask = si_gpu_check_soft_reset(rdev);
2336 r600_set_bios_scratch_engine_hung(rdev, true);
2338 si_gpu_soft_reset(rdev, reset_mask);
2340 reset_mask = si_gpu_check_soft_reset(rdev);
2343 r600_set_bios_scratch_engine_hung(rdev, false);
2349 static void si_mc_program(struct radeon_device *rdev)
2351 struct evergreen_mc_save save;
2355 /* Initialize HDP */
2356 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2357 WREG32((0x2c14 + j), 0x00000000);
2358 WREG32((0x2c18 + j), 0x00000000);
2359 WREG32((0x2c1c + j), 0x00000000);
2360 WREG32((0x2c20 + j), 0x00000000);
2361 WREG32((0x2c24 + j), 0x00000000);
2363 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2365 evergreen_mc_stop(rdev, &save);
2366 if (radeon_mc_wait_for_idle(rdev)) {
2367 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2369 /* Lockout access through VGA aperture*/
2370 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2371 /* Update configuration */
2372 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2373 rdev->mc.vram_start >> 12);
2374 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2375 rdev->mc.vram_end >> 12);
2376 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2377 rdev->vram_scratch.gpu_addr >> 12);
2378 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2379 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2380 WREG32(MC_VM_FB_LOCATION, tmp);
2381 /* XXX double check these! */
2382 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2383 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2384 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2385 WREG32(MC_VM_AGP_BASE, 0);
2386 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2387 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2388 if (radeon_mc_wait_for_idle(rdev)) {
2389 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2391 evergreen_mc_resume(rdev, &save);
2392 /* we need to own VRAM, so turn off the VGA renderer here
2393 * to stop it overwriting our objects */
2394 rv515_vga_render_disable(rdev);
2397 /* SI MC address space is 40 bits */
2398 static void si_vram_location(struct radeon_device *rdev,
2399 struct radeon_mc *mc, u64 base)
2401 mc->vram_start = base;
2402 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2403 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2404 mc->real_vram_size = mc->aper_size;
2405 mc->mc_vram_size = mc->aper_size;
2407 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2408 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2409 mc->mc_vram_size >> 20, mc->vram_start,
2410 mc->vram_end, mc->real_vram_size >> 20);
2413 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2415 u64 size_af, size_bf;
2417 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2418 size_bf = mc->vram_start & ~mc->gtt_base_align;
2419 if (size_bf > size_af) {
2420 if (mc->gtt_size > size_bf) {
2421 dev_warn(rdev->dev, "limiting GTT\n");
2422 mc->gtt_size = size_bf;
2424 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2426 if (mc->gtt_size > size_af) {
2427 dev_warn(rdev->dev, "limiting GTT\n");
2428 mc->gtt_size = size_af;
2430 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2432 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2433 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2434 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2437 static void si_vram_gtt_location(struct radeon_device *rdev,
2438 struct radeon_mc *mc)
2440 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2441 /* leave room for at least 1024M GTT */
2442 dev_warn(rdev->dev, "limiting VRAM\n");
2443 mc->real_vram_size = 0xFFC0000000ULL;
2444 mc->mc_vram_size = 0xFFC0000000ULL;
2446 si_vram_location(rdev, &rdev->mc, 0);
2447 rdev->mc.gtt_base_align = 0;
2448 si_gtt_location(rdev, mc);
2451 static int si_mc_init(struct radeon_device *rdev)
2454 int chansize, numchan;
2456 /* Get VRAM informations */
2457 rdev->mc.vram_is_ddr = true;
2458 tmp = RREG32(MC_ARB_RAMCFG);
2459 if (tmp & CHANSIZE_OVERRIDE) {
2461 } else if (tmp & CHANSIZE_MASK) {
2466 tmp = RREG32(MC_SHARED_CHMAP);
2467 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2497 rdev->mc.vram_width = numchan * chansize;
2498 /* Could aper size report 0 ? */
2499 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2500 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2501 /* size in MB on si */
2502 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2503 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2504 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2505 si_vram_gtt_location(rdev, &rdev->mc);
2506 radeon_update_bandwidth_info(rdev);
2514 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2516 /* flush hdp cache */
2517 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2519 /* bits 0-15 are the VM contexts0-15 */
2520 WREG32(VM_INVALIDATE_REQUEST, 1);
2523 static int si_pcie_gart_enable(struct radeon_device *rdev)
2527 if (rdev->gart.robj == NULL) {
2528 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2531 r = radeon_gart_table_vram_pin(rdev);
2534 radeon_gart_restore(rdev);
2535 /* Setup TLB control */
2536 WREG32(MC_VM_MX_L1_TLB_CNTL,
2539 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2540 ENABLE_ADVANCED_DRIVER_MODEL |
2541 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2542 /* Setup L2 cache */
2543 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2544 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2545 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2546 EFFECTIVE_L2_QUEUE_SIZE(7) |
2547 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2548 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2549 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2550 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2551 /* setup context0 */
2552 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2553 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2554 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2555 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2556 (u32)(rdev->dummy_page.addr >> 12));
2557 WREG32(VM_CONTEXT0_CNTL2, 0);
2558 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2559 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2565 /* empty context1-15 */
2566 /* set vm size, must be a multiple of 4 */
2567 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2568 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2569 /* Assign the pt base to something valid for now; the pts used for
2570 * the VMs are determined by the application and setup and assigned
2571 * on the fly in the vm part of radeon_gart.c
2573 for (i = 1; i < 16; i++) {
2575 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2576 rdev->gart.table_addr >> 12);
2578 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2579 rdev->gart.table_addr >> 12);
2582 /* enable context1-15 */
2583 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2584 (u32)(rdev->dummy_page.addr >> 12));
2585 WREG32(VM_CONTEXT1_CNTL2, 4);
2586 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
2587 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2588 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2589 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2590 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2591 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2592 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2593 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2594 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2595 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2596 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2597 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2598 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
2600 si_pcie_gart_tlb_flush(rdev);
2601 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2602 (unsigned)(rdev->mc.gtt_size >> 20),
2603 (unsigned long long)rdev->gart.table_addr);
2604 rdev->gart.ready = true;
2608 static void si_pcie_gart_disable(struct radeon_device *rdev)
2610 /* Disable all tables */
2611 WREG32(VM_CONTEXT0_CNTL, 0);
2612 WREG32(VM_CONTEXT1_CNTL, 0);
2613 /* Setup TLB control */
2614 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2615 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2616 /* Setup L2 cache */
2617 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2618 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2619 EFFECTIVE_L2_QUEUE_SIZE(7) |
2620 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2621 WREG32(VM_L2_CNTL2, 0);
2622 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2623 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2624 radeon_gart_table_vram_unpin(rdev);
2627 static void si_pcie_gart_fini(struct radeon_device *rdev)
2629 si_pcie_gart_disable(rdev);
2630 radeon_gart_table_vram_free(rdev);
2631 radeon_gart_fini(rdev);
2635 static bool si_vm_reg_valid(u32 reg)
2637 /* context regs are fine */
2641 /* check config regs */
2643 case GRBM_GFX_INDEX:
2644 case CP_STRMOUT_CNTL:
2645 case VGT_VTX_VECT_EJECT_REG:
2646 case VGT_CACHE_INVALIDATION:
2647 case VGT_ESGS_RING_SIZE:
2648 case VGT_GSVS_RING_SIZE:
2649 case VGT_GS_VERTEX_REUSE:
2650 case VGT_PRIMITIVE_TYPE:
2651 case VGT_INDEX_TYPE:
2652 case VGT_NUM_INDICES:
2653 case VGT_NUM_INSTANCES:
2654 case VGT_TF_RING_SIZE:
2655 case VGT_HS_OFFCHIP_PARAM:
2656 case VGT_TF_MEMORY_BASE:
2658 case PA_SU_LINE_STIPPLE_VALUE:
2659 case PA_SC_LINE_STIPPLE_STATE:
2662 case SPI_STATIC_THREAD_MGMT_1:
2663 case SPI_STATIC_THREAD_MGMT_2:
2664 case SPI_STATIC_THREAD_MGMT_3:
2665 case SPI_PS_MAX_WAVE_ID:
2666 case SPI_CONFIG_CNTL:
2667 case SPI_CONFIG_CNTL_1:
2671 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2676 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2677 u32 *ib, struct radeon_cs_packet *pkt)
2679 switch (pkt->opcode) {
2681 case PACKET3_SET_BASE:
2682 case PACKET3_SET_CE_DE_COUNTERS:
2683 case PACKET3_LOAD_CONST_RAM:
2684 case PACKET3_WRITE_CONST_RAM:
2685 case PACKET3_WRITE_CONST_RAM_OFFSET:
2686 case PACKET3_DUMP_CONST_RAM:
2687 case PACKET3_INCREMENT_CE_COUNTER:
2688 case PACKET3_WAIT_ON_DE_COUNTER:
2689 case PACKET3_CE_WRITE:
2692 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2698 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2699 u32 *ib, struct radeon_cs_packet *pkt)
2701 u32 idx = pkt->idx + 1;
2702 u32 idx_value = ib[idx];
2703 u32 start_reg, end_reg, reg, i;
2706 switch (pkt->opcode) {
2708 case PACKET3_SET_BASE:
2709 case PACKET3_CLEAR_STATE:
2710 case PACKET3_INDEX_BUFFER_SIZE:
2711 case PACKET3_DISPATCH_DIRECT:
2712 case PACKET3_DISPATCH_INDIRECT:
2713 case PACKET3_ALLOC_GDS:
2714 case PACKET3_WRITE_GDS_RAM:
2715 case PACKET3_ATOMIC_GDS:
2716 case PACKET3_ATOMIC:
2717 case PACKET3_OCCLUSION_QUERY:
2718 case PACKET3_SET_PREDICATION:
2719 case PACKET3_COND_EXEC:
2720 case PACKET3_PRED_EXEC:
2721 case PACKET3_DRAW_INDIRECT:
2722 case PACKET3_DRAW_INDEX_INDIRECT:
2723 case PACKET3_INDEX_BASE:
2724 case PACKET3_DRAW_INDEX_2:
2725 case PACKET3_CONTEXT_CONTROL:
2726 case PACKET3_INDEX_TYPE:
2727 case PACKET3_DRAW_INDIRECT_MULTI:
2728 case PACKET3_DRAW_INDEX_AUTO:
2729 case PACKET3_DRAW_INDEX_IMMD:
2730 case PACKET3_NUM_INSTANCES:
2731 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2732 case PACKET3_STRMOUT_BUFFER_UPDATE:
2733 case PACKET3_DRAW_INDEX_OFFSET_2:
2734 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2735 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2736 case PACKET3_MPEG_INDEX:
2737 case PACKET3_WAIT_REG_MEM:
2738 case PACKET3_MEM_WRITE:
2739 case PACKET3_PFP_SYNC_ME:
2740 case PACKET3_SURFACE_SYNC:
2741 case PACKET3_EVENT_WRITE:
2742 case PACKET3_EVENT_WRITE_EOP:
2743 case PACKET3_EVENT_WRITE_EOS:
2744 case PACKET3_SET_CONTEXT_REG:
2745 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2746 case PACKET3_SET_SH_REG:
2747 case PACKET3_SET_SH_REG_OFFSET:
2748 case PACKET3_INCREMENT_DE_COUNTER:
2749 case PACKET3_WAIT_ON_CE_COUNTER:
2750 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2751 case PACKET3_ME_WRITE:
2753 case PACKET3_COPY_DATA:
2754 if ((idx_value & 0xf00) == 0) {
2755 reg = ib[idx + 3] * 4;
2756 if (!si_vm_reg_valid(reg))
2760 case PACKET3_WRITE_DATA:
2761 if ((idx_value & 0xf00) == 0) {
2762 start_reg = ib[idx + 1] * 4;
2763 if (idx_value & 0x10000) {
2764 if (!si_vm_reg_valid(start_reg))
2767 for (i = 0; i < (pkt->count - 2); i++) {
2768 reg = start_reg + (4 * i);
2769 if (!si_vm_reg_valid(reg))
2775 case PACKET3_COND_WRITE:
2776 if (idx_value & 0x100) {
2777 reg = ib[idx + 5] * 4;
2778 if (!si_vm_reg_valid(reg))
2782 case PACKET3_COPY_DW:
2783 if (idx_value & 0x2) {
2784 reg = ib[idx + 3] * 4;
2785 if (!si_vm_reg_valid(reg))
2789 case PACKET3_SET_CONFIG_REG:
2790 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2791 end_reg = 4 * pkt->count + start_reg - 4;
2792 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2793 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2794 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2795 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2798 for (i = 0; i < pkt->count; i++) {
2799 reg = start_reg + (4 * i);
2800 if (!si_vm_reg_valid(reg))
2804 case PACKET3_CP_DMA:
2805 command = ib[idx + 4];
2807 if (command & PACKET3_CP_DMA_CMD_SAS) {
2808 /* src address space is register */
2809 if (((info & 0x60000000) >> 29) == 0) {
2810 start_reg = idx_value << 2;
2811 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2813 if (!si_vm_reg_valid(reg)) {
2814 DRM_ERROR("CP DMA Bad SRC register\n");
2818 for (i = 0; i < (command & 0x1fffff); i++) {
2819 reg = start_reg + (4 * i);
2820 if (!si_vm_reg_valid(reg)) {
2821 DRM_ERROR("CP DMA Bad SRC register\n");
2828 if (command & PACKET3_CP_DMA_CMD_DAS) {
2829 /* dst address space is register */
2830 if (((info & 0x00300000) >> 20) == 0) {
2831 start_reg = ib[idx + 2];
2832 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2834 if (!si_vm_reg_valid(reg)) {
2835 DRM_ERROR("CP DMA Bad DST register\n");
2839 for (i = 0; i < (command & 0x1fffff); i++) {
2840 reg = start_reg + (4 * i);
2841 if (!si_vm_reg_valid(reg)) {
2842 DRM_ERROR("CP DMA Bad DST register\n");
2851 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2857 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2858 u32 *ib, struct radeon_cs_packet *pkt)
2860 u32 idx = pkt->idx + 1;
2861 u32 idx_value = ib[idx];
2862 u32 start_reg, reg, i;
2864 switch (pkt->opcode) {
2866 case PACKET3_SET_BASE:
2867 case PACKET3_CLEAR_STATE:
2868 case PACKET3_DISPATCH_DIRECT:
2869 case PACKET3_DISPATCH_INDIRECT:
2870 case PACKET3_ALLOC_GDS:
2871 case PACKET3_WRITE_GDS_RAM:
2872 case PACKET3_ATOMIC_GDS:
2873 case PACKET3_ATOMIC:
2874 case PACKET3_OCCLUSION_QUERY:
2875 case PACKET3_SET_PREDICATION:
2876 case PACKET3_COND_EXEC:
2877 case PACKET3_PRED_EXEC:
2878 case PACKET3_CONTEXT_CONTROL:
2879 case PACKET3_STRMOUT_BUFFER_UPDATE:
2880 case PACKET3_WAIT_REG_MEM:
2881 case PACKET3_MEM_WRITE:
2882 case PACKET3_PFP_SYNC_ME:
2883 case PACKET3_SURFACE_SYNC:
2884 case PACKET3_EVENT_WRITE:
2885 case PACKET3_EVENT_WRITE_EOP:
2886 case PACKET3_EVENT_WRITE_EOS:
2887 case PACKET3_SET_CONTEXT_REG:
2888 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2889 case PACKET3_SET_SH_REG:
2890 case PACKET3_SET_SH_REG_OFFSET:
2891 case PACKET3_INCREMENT_DE_COUNTER:
2892 case PACKET3_WAIT_ON_CE_COUNTER:
2893 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2894 case PACKET3_ME_WRITE:
2896 case PACKET3_COPY_DATA:
2897 if ((idx_value & 0xf00) == 0) {
2898 reg = ib[idx + 3] * 4;
2899 if (!si_vm_reg_valid(reg))
2903 case PACKET3_WRITE_DATA:
2904 if ((idx_value & 0xf00) == 0) {
2905 start_reg = ib[idx + 1] * 4;
2906 if (idx_value & 0x10000) {
2907 if (!si_vm_reg_valid(start_reg))
2910 for (i = 0; i < (pkt->count - 2); i++) {
2911 reg = start_reg + (4 * i);
2912 if (!si_vm_reg_valid(reg))
2918 case PACKET3_COND_WRITE:
2919 if (idx_value & 0x100) {
2920 reg = ib[idx + 5] * 4;
2921 if (!si_vm_reg_valid(reg))
2925 case PACKET3_COPY_DW:
2926 if (idx_value & 0x2) {
2927 reg = ib[idx + 3] * 4;
2928 if (!si_vm_reg_valid(reg))
2933 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2939 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2943 struct radeon_cs_packet pkt;
2947 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
2948 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
2951 case RADEON_PACKET_TYPE0:
2952 dev_err(rdev->dev, "Packet0 not allowed!\n");
2955 case RADEON_PACKET_TYPE2:
2958 case RADEON_PACKET_TYPE3:
2959 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2960 if (ib->is_const_ib)
2961 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2964 case RADEON_RING_TYPE_GFX_INDEX:
2965 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2967 case CAYMAN_RING_TYPE_CP1_INDEX:
2968 case CAYMAN_RING_TYPE_CP2_INDEX:
2969 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2972 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
2977 idx += pkt.count + 2;
2980 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2986 } while (idx < ib->length_dw);
2994 int si_vm_init(struct radeon_device *rdev)
2997 rdev->vm_manager.nvm = 16;
2998 /* base offset of vram pages */
2999 rdev->vm_manager.vram_base_offset = 0;
3004 void si_vm_fini(struct radeon_device *rdev)
3009 * si_vm_set_page - update the page tables using the CP
3011 * @rdev: radeon_device pointer
3012 * @pe: addr of the page entry
3013 * @addr: dst addr to write into pe
3014 * @count: number of page entries to update
3015 * @incr: increase next addr by incr bytes
3016 * @flags: access flags
3018 * Update the page tables using the CP (cayman-si).
3020 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
3021 uint64_t addr, unsigned count,
3022 uint32_t incr, uint32_t flags)
3024 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
3025 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
3029 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
3031 ndw = 2 + count * 2;
3035 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
3036 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3037 WRITE_DATA_DST_SEL(1)));
3038 radeon_ring_write(ring, pe);
3039 radeon_ring_write(ring, upper_32_bits(pe));
3040 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3041 if (flags & RADEON_VM_PAGE_SYSTEM) {
3042 value = radeon_vm_map_gart(rdev, addr);
3043 value &= 0xFFFFFFFFFFFFF000ULL;
3044 } else if (flags & RADEON_VM_PAGE_VALID) {
3050 value |= r600_flags;
3051 radeon_ring_write(ring, value);
3052 radeon_ring_write(ring, upper_32_bits(value));
3057 if (flags & RADEON_VM_PAGE_SYSTEM) {
3063 /* for non-physically contiguous pages (system) */
3064 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw));
3065 radeon_ring_write(ring, pe);
3066 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
3067 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3068 if (flags & RADEON_VM_PAGE_SYSTEM) {
3069 value = radeon_vm_map_gart(rdev, addr);
3070 value &= 0xFFFFFFFFFFFFF000ULL;
3071 } else if (flags & RADEON_VM_PAGE_VALID) {
3077 value |= r600_flags;
3078 radeon_ring_write(ring, value);
3079 radeon_ring_write(ring, upper_32_bits(value));
3088 if (flags & RADEON_VM_PAGE_VALID)
3092 /* for physically contiguous pages (vram) */
3093 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw));
3094 radeon_ring_write(ring, pe); /* dst addr */
3095 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
3096 radeon_ring_write(ring, r600_flags); /* mask */
3097 radeon_ring_write(ring, 0);
3098 radeon_ring_write(ring, value); /* value */
3099 radeon_ring_write(ring, upper_32_bits(value));
3100 radeon_ring_write(ring, incr); /* increment size */
3101 radeon_ring_write(ring, 0);
3103 addr += (ndw / 2) * incr;
3110 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3112 struct radeon_ring *ring = &rdev->ring[ridx];
3117 /* write new base address */
3118 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3119 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3120 WRITE_DATA_DST_SEL(0)));
3123 radeon_ring_write(ring,
3124 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
3126 radeon_ring_write(ring,
3127 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
3129 radeon_ring_write(ring, 0);
3130 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3132 /* flush hdp cache */
3133 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3134 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3135 WRITE_DATA_DST_SEL(0)));
3136 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3137 radeon_ring_write(ring, 0);
3138 radeon_ring_write(ring, 0x1);
3140 /* bits 0-15 are the VM contexts0-15 */
3141 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3142 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3143 WRITE_DATA_DST_SEL(0)));
3144 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3145 radeon_ring_write(ring, 0);
3146 radeon_ring_write(ring, 1 << vm->id);
3148 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3149 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3150 radeon_ring_write(ring, 0x0);
3153 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3155 struct radeon_ring *ring = &rdev->ring[ridx];
3160 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3162 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3164 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3166 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3168 /* flush hdp cache */
3169 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3170 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3171 radeon_ring_write(ring, 1);
3173 /* bits 0-7 are the VM contexts0-7 */
3174 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3175 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3176 radeon_ring_write(ring, 1 << vm->id);
3182 void si_rlc_fini(struct radeon_device *rdev)
3186 /* save restore block */
3187 if (rdev->rlc.save_restore_obj) {
3188 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3189 if (unlikely(r != 0))
3190 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3191 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3192 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3194 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3195 rdev->rlc.save_restore_obj = NULL;
3198 /* clear state block */
3199 if (rdev->rlc.clear_state_obj) {
3200 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3201 if (unlikely(r != 0))
3202 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3203 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3204 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3206 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3207 rdev->rlc.clear_state_obj = NULL;
3211 int si_rlc_init(struct radeon_device *rdev)
3215 /* save restore block */
3216 if (rdev->rlc.save_restore_obj == NULL) {
3217 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3218 RADEON_GEM_DOMAIN_VRAM, NULL,
3219 &rdev->rlc.save_restore_obj);
3221 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3226 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3227 if (unlikely(r != 0)) {
3231 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3232 &rdev->rlc.save_restore_gpu_addr);
3233 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3235 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3240 /* clear state block */
3241 if (rdev->rlc.clear_state_obj == NULL) {
3242 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3243 RADEON_GEM_DOMAIN_VRAM, NULL,
3244 &rdev->rlc.clear_state_obj);
3246 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3251 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3252 if (unlikely(r != 0)) {
3256 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3257 &rdev->rlc.clear_state_gpu_addr);
3258 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3260 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3268 static void si_rlc_stop(struct radeon_device *rdev)
3270 WREG32(RLC_CNTL, 0);
3273 static void si_rlc_start(struct radeon_device *rdev)
3275 WREG32(RLC_CNTL, RLC_ENABLE);
3278 static int si_rlc_resume(struct radeon_device *rdev)
3281 const __be32 *fw_data;
3288 WREG32(RLC_RL_BASE, 0);
3289 WREG32(RLC_RL_SIZE, 0);
3290 WREG32(RLC_LB_CNTL, 0);
3291 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3292 WREG32(RLC_LB_CNTR_INIT, 0);
3294 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3295 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3297 WREG32(RLC_MC_CNTL, 0);
3298 WREG32(RLC_UCODE_CNTL, 0);
3300 fw_data = (const __be32 *)rdev->rlc_fw->data;
3301 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3302 WREG32(RLC_UCODE_ADDR, i);
3303 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3305 WREG32(RLC_UCODE_ADDR, 0);
3312 static void si_enable_interrupts(struct radeon_device *rdev)
3314 u32 ih_cntl = RREG32(IH_CNTL);
3315 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3317 ih_cntl |= ENABLE_INTR;
3318 ih_rb_cntl |= IH_RB_ENABLE;
3319 WREG32(IH_CNTL, ih_cntl);
3320 WREG32(IH_RB_CNTL, ih_rb_cntl);
3321 rdev->ih.enabled = true;
3324 static void si_disable_interrupts(struct radeon_device *rdev)
3326 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3327 u32 ih_cntl = RREG32(IH_CNTL);
3329 ih_rb_cntl &= ~IH_RB_ENABLE;
3330 ih_cntl &= ~ENABLE_INTR;
3331 WREG32(IH_RB_CNTL, ih_rb_cntl);
3332 WREG32(IH_CNTL, ih_cntl);
3333 /* set rptr, wptr to 0 */
3334 WREG32(IH_RB_RPTR, 0);
3335 WREG32(IH_RB_WPTR, 0);
3336 rdev->ih.enabled = false;
3340 static void si_disable_interrupt_state(struct radeon_device *rdev)
3344 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3345 WREG32(CP_INT_CNTL_RING1, 0);
3346 WREG32(CP_INT_CNTL_RING2, 0);
3347 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3348 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3349 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3350 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
3351 WREG32(GRBM_INT_CNTL, 0);
3352 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3353 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3354 if (rdev->num_crtc >= 4) {
3355 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3356 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3358 if (rdev->num_crtc >= 6) {
3359 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3360 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3363 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3364 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3365 if (rdev->num_crtc >= 4) {
3366 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3367 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3369 if (rdev->num_crtc >= 6) {
3370 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3371 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3374 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3376 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3377 WREG32(DC_HPD1_INT_CONTROL, tmp);
3378 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3379 WREG32(DC_HPD2_INT_CONTROL, tmp);
3380 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3381 WREG32(DC_HPD3_INT_CONTROL, tmp);
3382 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3383 WREG32(DC_HPD4_INT_CONTROL, tmp);
3384 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3385 WREG32(DC_HPD5_INT_CONTROL, tmp);
3386 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3387 WREG32(DC_HPD6_INT_CONTROL, tmp);
3391 static int si_irq_init(struct radeon_device *rdev)
3395 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3398 ret = r600_ih_ring_alloc(rdev);
3403 si_disable_interrupts(rdev);
3406 ret = si_rlc_resume(rdev);
3408 r600_ih_ring_fini(rdev);
3412 /* setup interrupt control */
3413 /* set dummy read address to ring address */
3414 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3415 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3416 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3417 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3419 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3420 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3421 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3422 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3424 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3425 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3427 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3428 IH_WPTR_OVERFLOW_CLEAR |
3431 if (rdev->wb.enabled)
3432 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3434 /* set the writeback address whether it's enabled or not */
3435 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3436 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3438 WREG32(IH_RB_CNTL, ih_rb_cntl);
3440 /* set rptr, wptr to 0 */
3441 WREG32(IH_RB_RPTR, 0);
3442 WREG32(IH_RB_WPTR, 0);
3444 /* Default settings for IH_CNTL (disabled at first) */
3445 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3446 /* RPTR_REARM only works if msi's are enabled */
3447 if (rdev->msi_enabled)
3448 ih_cntl |= RPTR_REARM;
3449 WREG32(IH_CNTL, ih_cntl);
3451 /* force the active interrupt state to all disabled */
3452 si_disable_interrupt_state(rdev);
3454 pci_set_master(rdev->pdev);
3457 si_enable_interrupts(rdev);
3462 int si_irq_set(struct radeon_device *rdev)
3464 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3465 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3466 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3467 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3468 u32 grbm_int_cntl = 0;
3469 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3470 u32 dma_cntl, dma_cntl1;
3472 if (!rdev->irq.installed) {
3473 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3476 /* don't enable anything if the ih is disabled */
3477 if (!rdev->ih.enabled) {
3478 si_disable_interrupts(rdev);
3479 /* force the active interrupt state to all disabled */
3480 si_disable_interrupt_state(rdev);
3484 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3485 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3486 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3487 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3488 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3489 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3491 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3492 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3494 /* enable CP interrupts on all rings */
3495 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3496 DRM_DEBUG("si_irq_set: sw int gfx\n");
3497 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3499 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
3500 DRM_DEBUG("si_irq_set: sw int cp1\n");
3501 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3503 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
3504 DRM_DEBUG("si_irq_set: sw int cp2\n");
3505 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3507 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3508 DRM_DEBUG("si_irq_set: sw int dma\n");
3509 dma_cntl |= TRAP_ENABLE;
3512 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3513 DRM_DEBUG("si_irq_set: sw int dma1\n");
3514 dma_cntl1 |= TRAP_ENABLE;
3516 if (rdev->irq.crtc_vblank_int[0] ||
3517 atomic_read(&rdev->irq.pflip[0])) {
3518 DRM_DEBUG("si_irq_set: vblank 0\n");
3519 crtc1 |= VBLANK_INT_MASK;
3521 if (rdev->irq.crtc_vblank_int[1] ||
3522 atomic_read(&rdev->irq.pflip[1])) {
3523 DRM_DEBUG("si_irq_set: vblank 1\n");
3524 crtc2 |= VBLANK_INT_MASK;
3526 if (rdev->irq.crtc_vblank_int[2] ||
3527 atomic_read(&rdev->irq.pflip[2])) {
3528 DRM_DEBUG("si_irq_set: vblank 2\n");
3529 crtc3 |= VBLANK_INT_MASK;
3531 if (rdev->irq.crtc_vblank_int[3] ||
3532 atomic_read(&rdev->irq.pflip[3])) {
3533 DRM_DEBUG("si_irq_set: vblank 3\n");
3534 crtc4 |= VBLANK_INT_MASK;
3536 if (rdev->irq.crtc_vblank_int[4] ||
3537 atomic_read(&rdev->irq.pflip[4])) {
3538 DRM_DEBUG("si_irq_set: vblank 4\n");
3539 crtc5 |= VBLANK_INT_MASK;
3541 if (rdev->irq.crtc_vblank_int[5] ||
3542 atomic_read(&rdev->irq.pflip[5])) {
3543 DRM_DEBUG("si_irq_set: vblank 5\n");
3544 crtc6 |= VBLANK_INT_MASK;
3546 if (rdev->irq.hpd[0]) {
3547 DRM_DEBUG("si_irq_set: hpd 1\n");
3548 hpd1 |= DC_HPDx_INT_EN;
3550 if (rdev->irq.hpd[1]) {
3551 DRM_DEBUG("si_irq_set: hpd 2\n");
3552 hpd2 |= DC_HPDx_INT_EN;
3554 if (rdev->irq.hpd[2]) {
3555 DRM_DEBUG("si_irq_set: hpd 3\n");
3556 hpd3 |= DC_HPDx_INT_EN;
3558 if (rdev->irq.hpd[3]) {
3559 DRM_DEBUG("si_irq_set: hpd 4\n");
3560 hpd4 |= DC_HPDx_INT_EN;
3562 if (rdev->irq.hpd[4]) {
3563 DRM_DEBUG("si_irq_set: hpd 5\n");
3564 hpd5 |= DC_HPDx_INT_EN;
3566 if (rdev->irq.hpd[5]) {
3567 DRM_DEBUG("si_irq_set: hpd 6\n");
3568 hpd6 |= DC_HPDx_INT_EN;
3571 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3572 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3573 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3575 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3576 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3578 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3580 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3581 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3582 if (rdev->num_crtc >= 4) {
3583 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3584 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3586 if (rdev->num_crtc >= 6) {
3587 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3588 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3591 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3592 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3593 if (rdev->num_crtc >= 4) {
3594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3595 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3597 if (rdev->num_crtc >= 6) {
3598 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3599 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3602 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3603 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3604 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3605 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3606 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3607 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3612 static inline void si_irq_ack(struct radeon_device *rdev)
3616 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3617 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3618 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3619 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3620 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3621 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3622 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3623 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3624 if (rdev->num_crtc >= 4) {
3625 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3626 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3628 if (rdev->num_crtc >= 6) {
3629 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3630 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3633 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3634 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3635 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3636 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3637 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3638 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3639 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3640 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3641 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3642 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3643 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3644 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3646 if (rdev->num_crtc >= 4) {
3647 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3648 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3649 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3650 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3651 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3652 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3653 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3654 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3655 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3656 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3657 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3658 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3661 if (rdev->num_crtc >= 6) {
3662 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3663 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3664 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3665 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3666 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3667 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3668 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3669 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3670 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3671 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3672 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3673 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3676 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3677 tmp = RREG32(DC_HPD1_INT_CONTROL);
3678 tmp |= DC_HPDx_INT_ACK;
3679 WREG32(DC_HPD1_INT_CONTROL, tmp);
3681 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3682 tmp = RREG32(DC_HPD2_INT_CONTROL);
3683 tmp |= DC_HPDx_INT_ACK;
3684 WREG32(DC_HPD2_INT_CONTROL, tmp);
3686 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3687 tmp = RREG32(DC_HPD3_INT_CONTROL);
3688 tmp |= DC_HPDx_INT_ACK;
3689 WREG32(DC_HPD3_INT_CONTROL, tmp);
3691 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3692 tmp = RREG32(DC_HPD4_INT_CONTROL);
3693 tmp |= DC_HPDx_INT_ACK;
3694 WREG32(DC_HPD4_INT_CONTROL, tmp);
3696 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3697 tmp = RREG32(DC_HPD5_INT_CONTROL);
3698 tmp |= DC_HPDx_INT_ACK;
3699 WREG32(DC_HPD5_INT_CONTROL, tmp);
3701 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3702 tmp = RREG32(DC_HPD5_INT_CONTROL);
3703 tmp |= DC_HPDx_INT_ACK;
3704 WREG32(DC_HPD6_INT_CONTROL, tmp);
3708 static void si_irq_disable(struct radeon_device *rdev)
3710 si_disable_interrupts(rdev);
3711 /* Wait and acknowledge irq */
3714 si_disable_interrupt_state(rdev);
3717 static void si_irq_suspend(struct radeon_device *rdev)
3719 si_irq_disable(rdev);
3723 static void si_irq_fini(struct radeon_device *rdev)
3725 si_irq_suspend(rdev);
3726 r600_ih_ring_fini(rdev);
3729 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3733 if (rdev->wb.enabled)
3734 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3736 wptr = RREG32(IH_RB_WPTR);
3738 if (wptr & RB_OVERFLOW) {
3739 /* When a ring buffer overflow happen start parsing interrupt
3740 * from the last not overwritten vector (wptr + 16). Hopefully
3741 * this should allow us to catchup.
3743 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3744 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3745 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3746 tmp = RREG32(IH_RB_CNTL);
3747 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3748 WREG32(IH_RB_CNTL, tmp);
3750 return (wptr & rdev->ih.ptr_mask);
3754 * Each IV ring entry is 128 bits:
3755 * [7:0] - interrupt source id
3757 * [59:32] - interrupt source data
3758 * [63:60] - reserved
3761 * [127:80] - reserved
3763 int si_irq_process(struct radeon_device *rdev)
3767 u32 src_id, src_data, ring_id;
3769 bool queue_hotplug = false;
3771 if (!rdev->ih.enabled || rdev->shutdown)
3774 wptr = si_get_ih_wptr(rdev);
3777 /* is somebody else already processing irqs? */
3778 if (atomic_xchg(&rdev->ih.lock, 1))
3781 rptr = rdev->ih.rptr;
3782 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3784 /* Order reading of wptr vs. reading of IH ring data */
3787 /* display interrupts */
3790 while (rptr != wptr) {
3791 /* wptr/rptr are in bytes! */
3792 ring_index = rptr / 4;
3793 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3794 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3795 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3798 case 1: /* D1 vblank/vline */
3800 case 0: /* D1 vblank */
3801 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3802 if (rdev->irq.crtc_vblank_int[0]) {
3803 drm_handle_vblank(rdev->ddev, 0);
3804 rdev->pm.vblank_sync = true;
3805 wake_up(&rdev->irq.vblank_queue);
3807 if (atomic_read(&rdev->irq.pflip[0]))
3808 radeon_crtc_handle_flip(rdev, 0);
3809 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3810 DRM_DEBUG("IH: D1 vblank\n");
3813 case 1: /* D1 vline */
3814 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3815 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3816 DRM_DEBUG("IH: D1 vline\n");
3820 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3824 case 2: /* D2 vblank/vline */
3826 case 0: /* D2 vblank */
3827 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3828 if (rdev->irq.crtc_vblank_int[1]) {
3829 drm_handle_vblank(rdev->ddev, 1);
3830 rdev->pm.vblank_sync = true;
3831 wake_up(&rdev->irq.vblank_queue);
3833 if (atomic_read(&rdev->irq.pflip[1]))
3834 radeon_crtc_handle_flip(rdev, 1);
3835 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3836 DRM_DEBUG("IH: D2 vblank\n");
3839 case 1: /* D2 vline */
3840 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3841 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3842 DRM_DEBUG("IH: D2 vline\n");
3846 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3850 case 3: /* D3 vblank/vline */
3852 case 0: /* D3 vblank */
3853 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3854 if (rdev->irq.crtc_vblank_int[2]) {
3855 drm_handle_vblank(rdev->ddev, 2);
3856 rdev->pm.vblank_sync = true;
3857 wake_up(&rdev->irq.vblank_queue);
3859 if (atomic_read(&rdev->irq.pflip[2]))
3860 radeon_crtc_handle_flip(rdev, 2);
3861 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3862 DRM_DEBUG("IH: D3 vblank\n");
3865 case 1: /* D3 vline */
3866 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3867 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3868 DRM_DEBUG("IH: D3 vline\n");
3872 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3876 case 4: /* D4 vblank/vline */
3878 case 0: /* D4 vblank */
3879 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3880 if (rdev->irq.crtc_vblank_int[3]) {
3881 drm_handle_vblank(rdev->ddev, 3);
3882 rdev->pm.vblank_sync = true;
3883 wake_up(&rdev->irq.vblank_queue);
3885 if (atomic_read(&rdev->irq.pflip[3]))
3886 radeon_crtc_handle_flip(rdev, 3);
3887 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3888 DRM_DEBUG("IH: D4 vblank\n");
3891 case 1: /* D4 vline */
3892 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3893 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3894 DRM_DEBUG("IH: D4 vline\n");
3898 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3902 case 5: /* D5 vblank/vline */
3904 case 0: /* D5 vblank */
3905 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3906 if (rdev->irq.crtc_vblank_int[4]) {
3907 drm_handle_vblank(rdev->ddev, 4);
3908 rdev->pm.vblank_sync = true;
3909 wake_up(&rdev->irq.vblank_queue);
3911 if (atomic_read(&rdev->irq.pflip[4]))
3912 radeon_crtc_handle_flip(rdev, 4);
3913 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3914 DRM_DEBUG("IH: D5 vblank\n");
3917 case 1: /* D5 vline */
3918 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3919 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3920 DRM_DEBUG("IH: D5 vline\n");
3924 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3928 case 6: /* D6 vblank/vline */
3930 case 0: /* D6 vblank */
3931 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3932 if (rdev->irq.crtc_vblank_int[5]) {
3933 drm_handle_vblank(rdev->ddev, 5);
3934 rdev->pm.vblank_sync = true;
3935 wake_up(&rdev->irq.vblank_queue);
3937 if (atomic_read(&rdev->irq.pflip[5]))
3938 radeon_crtc_handle_flip(rdev, 5);
3939 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3940 DRM_DEBUG("IH: D6 vblank\n");
3943 case 1: /* D6 vline */
3944 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3945 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3946 DRM_DEBUG("IH: D6 vline\n");
3950 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3954 case 42: /* HPD hotplug */
3957 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3958 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3959 queue_hotplug = true;
3960 DRM_DEBUG("IH: HPD1\n");
3964 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3965 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3966 queue_hotplug = true;
3967 DRM_DEBUG("IH: HPD2\n");
3971 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3972 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3973 queue_hotplug = true;
3974 DRM_DEBUG("IH: HPD3\n");
3978 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3979 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3980 queue_hotplug = true;
3981 DRM_DEBUG("IH: HPD4\n");
3985 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3986 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3987 queue_hotplug = true;
3988 DRM_DEBUG("IH: HPD5\n");
3992 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3993 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3994 queue_hotplug = true;
3995 DRM_DEBUG("IH: HPD6\n");
3999 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4005 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4006 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4007 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4008 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4009 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4010 /* reset addr and status */
4011 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4013 case 176: /* RINGID0 CP_INT */
4014 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4016 case 177: /* RINGID1 CP_INT */
4017 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4019 case 178: /* RINGID2 CP_INT */
4020 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4022 case 181: /* CP EOP event */
4023 DRM_DEBUG("IH: CP EOP\n");
4026 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4029 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4032 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4036 case 224: /* DMA trap event */
4037 DRM_DEBUG("IH: DMA trap\n");
4038 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4040 case 233: /* GUI IDLE */
4041 DRM_DEBUG("IH: GUI idle\n");
4043 case 244: /* DMA trap event */
4044 DRM_DEBUG("IH: DMA1 trap\n");
4045 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4048 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4052 /* wptr/rptr are in bytes! */
4054 rptr &= rdev->ih.ptr_mask;
4057 schedule_work(&rdev->hotplug_work);
4058 rdev->ih.rptr = rptr;
4059 WREG32(IH_RB_RPTR, rdev->ih.rptr);
4060 atomic_set(&rdev->ih.lock, 0);
4062 /* make sure wptr hasn't changed while processing */
4063 wptr = si_get_ih_wptr(rdev);
4071 * si_copy_dma - copy pages using the DMA engine
4073 * @rdev: radeon_device pointer
4074 * @src_offset: src GPU address
4075 * @dst_offset: dst GPU address
4076 * @num_gpu_pages: number of GPU pages to xfer
4077 * @fence: radeon fence object
4079 * Copy GPU paging using the DMA engine (SI).
4080 * Used by the radeon ttm implementation to move pages if
4081 * registered as the asic copy callback.
4083 int si_copy_dma(struct radeon_device *rdev,
4084 uint64_t src_offset, uint64_t dst_offset,
4085 unsigned num_gpu_pages,
4086 struct radeon_fence **fence)
4088 struct radeon_semaphore *sem = NULL;
4089 int ring_index = rdev->asic->copy.dma_ring_index;
4090 struct radeon_ring *ring = &rdev->ring[ring_index];
4091 u32 size_in_bytes, cur_size_in_bytes;
4095 r = radeon_semaphore_create(rdev, &sem);
4097 DRM_ERROR("radeon: moving bo (%d).\n", r);
4101 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4102 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4103 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4105 DRM_ERROR("radeon: moving bo (%d).\n", r);
4106 radeon_semaphore_free(rdev, &sem, NULL);
4110 if (radeon_fence_need_sync(*fence, ring->idx)) {
4111 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4113 radeon_fence_note_sync(*fence, ring->idx);
4115 radeon_semaphore_free(rdev, &sem, NULL);
4118 for (i = 0; i < num_loops; i++) {
4119 cur_size_in_bytes = size_in_bytes;
4120 if (cur_size_in_bytes > 0xFFFFF)
4121 cur_size_in_bytes = 0xFFFFF;
4122 size_in_bytes -= cur_size_in_bytes;
4123 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4124 radeon_ring_write(ring, dst_offset & 0xffffffff);
4125 radeon_ring_write(ring, src_offset & 0xffffffff);
4126 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4127 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4128 src_offset += cur_size_in_bytes;
4129 dst_offset += cur_size_in_bytes;
4132 r = radeon_fence_emit(rdev, fence, ring->idx);
4134 radeon_ring_unlock_undo(rdev, ring);
4138 radeon_ring_unlock_commit(rdev, ring);
4139 radeon_semaphore_free(rdev, &sem, *fence);
4145 * startup/shutdown callbacks
4147 static int si_startup(struct radeon_device *rdev)
4149 struct radeon_ring *ring;
4152 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4153 !rdev->rlc_fw || !rdev->mc_fw) {
4154 r = si_init_microcode(rdev);
4156 DRM_ERROR("Failed to load firmware!\n");
4161 r = si_mc_load_microcode(rdev);
4163 DRM_ERROR("Failed to load MC firmware!\n");
4167 r = r600_vram_scratch_init(rdev);
4171 si_mc_program(rdev);
4172 r = si_pcie_gart_enable(rdev);
4178 r = evergreen_blit_init(rdev);
4180 r600_blit_fini(rdev);
4181 rdev->asic->copy = NULL;
4182 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4185 /* allocate rlc buffers */
4186 r = si_rlc_init(rdev);
4188 DRM_ERROR("Failed to init rlc BOs!\n");
4192 /* allocate wb buffer */
4193 r = radeon_wb_init(rdev);
4197 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4199 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4203 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4205 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4209 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4211 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4215 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4217 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4221 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4223 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4228 r = si_irq_init(rdev);
4230 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4231 radeon_irq_kms_fini(rdev);
4236 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4237 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4238 CP_RB0_RPTR, CP_RB0_WPTR,
4239 0, 0xfffff, RADEON_CP_PACKET2);
4243 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4244 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4245 CP_RB1_RPTR, CP_RB1_WPTR,
4246 0, 0xfffff, RADEON_CP_PACKET2);
4250 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4251 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4252 CP_RB2_RPTR, CP_RB2_WPTR,
4253 0, 0xfffff, RADEON_CP_PACKET2);
4257 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4258 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4259 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4260 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4261 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4265 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4266 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4267 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4268 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4269 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4273 r = si_cp_load_microcode(rdev);
4276 r = si_cp_resume(rdev);
4280 r = cayman_dma_resume(rdev);
4284 r = radeon_ib_pool_init(rdev);
4286 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4290 r = radeon_vm_manager_init(rdev);
4292 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
4299 int si_resume(struct radeon_device *rdev)
4303 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4304 * posting will perform necessary task to bring back GPU into good
4308 atom_asic_init(rdev->mode_info.atom_context);
4310 rdev->accel_working = true;
4311 r = si_startup(rdev);
4313 DRM_ERROR("si startup failed on resume\n");
4314 rdev->accel_working = false;
4322 int si_suspend(struct radeon_device *rdev)
4324 si_cp_enable(rdev, false);
4325 cayman_dma_stop(rdev);
4326 si_irq_suspend(rdev);
4327 radeon_wb_disable(rdev);
4328 si_pcie_gart_disable(rdev);
4332 /* Plan is to move initialization in that function and use
4333 * helper function so that radeon_device_init pretty much
4334 * do nothing more than calling asic specific function. This
4335 * should also allow to remove a bunch of callback function
4338 int si_init(struct radeon_device *rdev)
4340 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4344 if (!radeon_get_bios(rdev)) {
4345 if (ASIC_IS_AVIVO(rdev))
4348 /* Must be an ATOMBIOS */
4349 if (!rdev->is_atom_bios) {
4350 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4353 r = radeon_atombios_init(rdev);
4357 /* Post card if necessary */
4358 if (!radeon_card_posted(rdev)) {
4360 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4363 DRM_INFO("GPU not posted. posting now...\n");
4364 atom_asic_init(rdev->mode_info.atom_context);
4366 /* Initialize scratch registers */
4367 si_scratch_init(rdev);
4368 /* Initialize surface registers */
4369 radeon_surface_init(rdev);
4370 /* Initialize clocks */
4371 radeon_get_clock_info(rdev->ddev);
4374 r = radeon_fence_driver_init(rdev);
4378 /* initialize memory controller */
4379 r = si_mc_init(rdev);
4382 /* Memory manager */
4383 r = radeon_bo_init(rdev);
4387 r = radeon_irq_kms_init(rdev);
4391 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4392 ring->ring_obj = NULL;
4393 r600_ring_init(rdev, ring, 1024 * 1024);
4395 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4396 ring->ring_obj = NULL;
4397 r600_ring_init(rdev, ring, 1024 * 1024);
4399 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4400 ring->ring_obj = NULL;
4401 r600_ring_init(rdev, ring, 1024 * 1024);
4403 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4404 ring->ring_obj = NULL;
4405 r600_ring_init(rdev, ring, 64 * 1024);
4407 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4408 ring->ring_obj = NULL;
4409 r600_ring_init(rdev, ring, 64 * 1024);
4411 rdev->ih.ring_obj = NULL;
4412 r600_ih_ring_init(rdev, 64 * 1024);
4414 r = r600_pcie_gart_init(rdev);
4418 rdev->accel_working = true;
4419 r = si_startup(rdev);
4421 dev_err(rdev->dev, "disabling GPU acceleration\n");
4423 cayman_dma_fini(rdev);
4426 radeon_wb_fini(rdev);
4427 radeon_ib_pool_fini(rdev);
4428 radeon_vm_manager_fini(rdev);
4429 radeon_irq_kms_fini(rdev);
4430 si_pcie_gart_fini(rdev);
4431 rdev->accel_working = false;
4434 /* Don't start up if the MC ucode is missing.
4435 * The default clocks and voltages before the MC ucode
4436 * is loaded are not suffient for advanced operations.
4439 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4446 void si_fini(struct radeon_device *rdev)
4449 r600_blit_fini(rdev);
4452 cayman_dma_fini(rdev);
4455 radeon_wb_fini(rdev);
4456 radeon_vm_manager_fini(rdev);
4457 radeon_ib_pool_fini(rdev);
4458 radeon_irq_kms_fini(rdev);
4459 si_pcie_gart_fini(rdev);
4460 r600_vram_scratch_fini(rdev);
4461 radeon_gem_fini(rdev);
4462 radeon_fence_driver_fini(rdev);
4463 radeon_bo_fini(rdev);
4464 radeon_atombios_fini(rdev);
4470 * si_get_gpu_clock - return GPU clock counter snapshot
4472 * @rdev: radeon_device pointer
4474 * Fetches a GPU clock counter snapshot (SI).
4475 * Returns the 64 bit clock counter snapshot.
4477 uint64_t si_get_gpu_clock(struct radeon_device *rdev)
4481 mutex_lock(&rdev->gpu_clock_mutex);
4482 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4483 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4484 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4485 mutex_unlock(&rdev->gpu_clock_mutex);