2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define CG_MULT_THERMAL_STATUS 0x714
28 #define ASIC_MAX_TEMP(x) ((x) << 0)
29 #define ASIC_MAX_TEMP_MASK 0x000001ff
30 #define ASIC_MAX_TEMP_SHIFT 0
31 #define CTF_TEMP(x) ((x) << 9)
32 #define CTF_TEMP_MASK 0x0003fe00
33 #define CTF_TEMP_SHIFT 9
35 #define SI_MAX_SH_GPRS 256
36 #define SI_MAX_TEMP_GPRS 16
37 #define SI_MAX_SH_THREADS 256
38 #define SI_MAX_SH_STACK_ENTRIES 4096
39 #define SI_MAX_FRC_EOV_CNT 16384
40 #define SI_MAX_BACKENDS 8
41 #define SI_MAX_BACKENDS_MASK 0xFF
42 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
43 #define SI_MAX_SIMDS 12
44 #define SI_MAX_SIMDS_MASK 0x0FFF
45 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
46 #define SI_MAX_PIPES 8
47 #define SI_MAX_PIPES_MASK 0xFF
48 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
49 #define SI_MAX_LDS_NUM 0xFFFF
51 #define SI_MAX_TCC_MASK 0xFFFF
53 #define VGA_HDP_CONTROL 0x328
54 #define VGA_MEMORY_DISABLE (1 << 4)
56 #define DMIF_ADDR_CONFIG 0xBD4
58 #define SRBM_STATUS 0xE50
60 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
61 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
63 #define VM_L2_CNTL 0x1400
64 #define ENABLE_L2_CACHE (1 << 0)
65 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
66 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
67 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
68 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
69 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
70 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
71 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
72 #define VM_L2_CNTL2 0x1404
73 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
74 #define INVALIDATE_L2_CACHE (1 << 1)
75 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
76 #define INVALIDATE_PTE_AND_PDE_CACHES 0
77 #define INVALIDATE_ONLY_PTE_CACHES 1
78 #define INVALIDATE_ONLY_PDE_CACHES 2
79 #define VM_L2_CNTL3 0x1408
80 #define BANK_SELECT(x) ((x) << 0)
81 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
82 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
83 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
84 #define VM_L2_STATUS 0x140C
85 #define L2_BUSY (1 << 0)
86 #define VM_CONTEXT0_CNTL 0x1410
87 #define ENABLE_CONTEXT (1 << 0)
88 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
89 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
90 #define VM_CONTEXT1_CNTL 0x1414
91 #define VM_CONTEXT0_CNTL2 0x1430
92 #define VM_CONTEXT1_CNTL2 0x1434
93 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
94 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
95 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
96 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
97 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
98 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
99 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
100 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
102 #define VM_INVALIDATE_REQUEST 0x1478
103 #define VM_INVALIDATE_RESPONSE 0x147c
105 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
106 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
108 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
109 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
110 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
111 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
112 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
113 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
114 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
115 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
116 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
117 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
119 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
120 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
122 #define MC_SHARED_CHMAP 0x2004
123 #define NOOFCHAN_SHIFT 12
124 #define NOOFCHAN_MASK 0x0000f000
125 #define MC_SHARED_CHREMAP 0x2008
127 #define MC_VM_FB_LOCATION 0x2024
128 #define MC_VM_AGP_TOP 0x2028
129 #define MC_VM_AGP_BOT 0x202C
130 #define MC_VM_AGP_BASE 0x2030
131 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
132 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
133 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
135 #define MC_VM_MX_L1_TLB_CNTL 0x2064
136 #define ENABLE_L1_TLB (1 << 0)
137 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
138 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
139 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
140 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
141 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
142 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
143 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
145 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
147 #define MC_ARB_RAMCFG 0x2760
148 #define NOOFBANK_SHIFT 0
149 #define NOOFBANK_MASK 0x00000003
150 #define NOOFRANK_SHIFT 2
151 #define NOOFRANK_MASK 0x00000004
152 #define NOOFROWS_SHIFT 3
153 #define NOOFROWS_MASK 0x00000038
154 #define NOOFCOLS_SHIFT 6
155 #define NOOFCOLS_MASK 0x000000C0
156 #define CHANSIZE_SHIFT 8
157 #define CHANSIZE_MASK 0x00000100
158 #define CHANSIZE_OVERRIDE (1 << 11)
159 #define NOOFGROUPS_SHIFT 12
160 #define NOOFGROUPS_MASK 0x00001000
162 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
163 #define TRAIN_DONE_D0 (1 << 30)
164 #define TRAIN_DONE_D1 (1 << 31)
166 #define MC_SEQ_SUP_CNTL 0x28c8
167 #define RUN_MASK (1 << 0)
168 #define MC_SEQ_SUP_PGM 0x28cc
170 #define MC_IO_PAD_CNTL_D0 0x29d0
171 #define MEM_FALL_OUT_CMD (1 << 8)
173 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
174 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
176 #define HDP_HOST_PATH_CNTL 0x2C00
177 #define HDP_NONSURFACE_BASE 0x2C04
178 #define HDP_NONSURFACE_INFO 0x2C08
179 #define HDP_NONSURFACE_SIZE 0x2C0C
181 #define HDP_ADDR_CONFIG 0x2F48
182 #define HDP_MISC_CNTL 0x2F4C
183 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
185 #define CONFIG_MEMSIZE 0x5428
187 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
189 #define BIF_FB_EN 0x5490
190 #define FB_READ_EN (1 << 0)
191 #define FB_WRITE_EN (1 << 1)
193 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
195 #define DC_LB_MEMORY_SPLIT 0x6b0c
196 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
198 #define PRIORITY_A_CNT 0x6b18
199 #define PRIORITY_MARK_MASK 0x7fff
200 #define PRIORITY_OFF (1 << 16)
201 #define PRIORITY_ALWAYS_ON (1 << 20)
202 #define PRIORITY_B_CNT 0x6b1c
204 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
205 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
206 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
207 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
208 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
210 #define GRBM_CNTL 0x8000
211 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
213 #define GRBM_STATUS2 0x8008
214 #define RLC_RQ_PENDING (1 << 0)
215 #define RLC_BUSY (1 << 8)
216 #define TC_BUSY (1 << 9)
218 #define GRBM_STATUS 0x8010
219 #define CMDFIFO_AVAIL_MASK 0x0000000F
220 #define RING2_RQ_PENDING (1 << 4)
221 #define SRBM_RQ_PENDING (1 << 5)
222 #define RING1_RQ_PENDING (1 << 6)
223 #define CF_RQ_PENDING (1 << 7)
224 #define PF_RQ_PENDING (1 << 8)
225 #define GDS_DMA_RQ_PENDING (1 << 9)
226 #define GRBM_EE_BUSY (1 << 10)
227 #define DB_CLEAN (1 << 12)
228 #define CB_CLEAN (1 << 13)
229 #define TA_BUSY (1 << 14)
230 #define GDS_BUSY (1 << 15)
231 #define VGT_BUSY (1 << 17)
232 #define IA_BUSY_NO_DMA (1 << 18)
233 #define IA_BUSY (1 << 19)
234 #define SX_BUSY (1 << 20)
235 #define SPI_BUSY (1 << 22)
236 #define BCI_BUSY (1 << 23)
237 #define SC_BUSY (1 << 24)
238 #define PA_BUSY (1 << 25)
239 #define DB_BUSY (1 << 26)
240 #define CP_COHERENCY_BUSY (1 << 28)
241 #define CP_BUSY (1 << 29)
242 #define CB_BUSY (1 << 30)
243 #define GUI_ACTIVE (1 << 31)
244 #define GRBM_STATUS_SE0 0x8014
245 #define GRBM_STATUS_SE1 0x8018
246 #define SE_DB_CLEAN (1 << 1)
247 #define SE_CB_CLEAN (1 << 2)
248 #define SE_BCI_BUSY (1 << 22)
249 #define SE_VGT_BUSY (1 << 23)
250 #define SE_PA_BUSY (1 << 24)
251 #define SE_TA_BUSY (1 << 25)
252 #define SE_SX_BUSY (1 << 26)
253 #define SE_SPI_BUSY (1 << 27)
254 #define SE_SC_BUSY (1 << 29)
255 #define SE_DB_BUSY (1 << 30)
256 #define SE_CB_BUSY (1 << 31)
258 #define GRBM_SOFT_RESET 0x8020
259 #define SOFT_RESET_CP (1 << 0)
260 #define SOFT_RESET_CB (1 << 1)
261 #define SOFT_RESET_RLC (1 << 2)
262 #define SOFT_RESET_DB (1 << 3)
263 #define SOFT_RESET_GDS (1 << 4)
264 #define SOFT_RESET_PA (1 << 5)
265 #define SOFT_RESET_SC (1 << 6)
266 #define SOFT_RESET_BCI (1 << 7)
267 #define SOFT_RESET_SPI (1 << 8)
268 #define SOFT_RESET_SX (1 << 10)
269 #define SOFT_RESET_TC (1 << 11)
270 #define SOFT_RESET_TA (1 << 12)
271 #define SOFT_RESET_VGT (1 << 14)
272 #define SOFT_RESET_IA (1 << 15)
274 #define GRBM_GFX_INDEX 0x802C
276 #define SCRATCH_REG0 0x8500
277 #define SCRATCH_REG1 0x8504
278 #define SCRATCH_REG2 0x8508
279 #define SCRATCH_REG3 0x850C
280 #define SCRATCH_REG4 0x8510
281 #define SCRATCH_REG5 0x8514
282 #define SCRATCH_REG6 0x8518
283 #define SCRATCH_REG7 0x851C
285 #define SCRATCH_UMSK 0x8540
286 #define SCRATCH_ADDR 0x8544
288 #define CP_SEM_WAIT_TIMER 0x85BC
290 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
292 #define CP_ME_CNTL 0x86D8
293 #define CP_CE_HALT (1 << 24)
294 #define CP_PFP_HALT (1 << 26)
295 #define CP_ME_HALT (1 << 28)
297 #define CP_RB2_RPTR 0x86f8
298 #define CP_RB1_RPTR 0x86fc
299 #define CP_RB0_RPTR 0x8700
300 #define CP_RB_WPTR_DELAY 0x8704
302 #define CP_QUEUE_THRESHOLDS 0x8760
303 #define ROQ_IB1_START(x) ((x) << 0)
304 #define ROQ_IB2_START(x) ((x) << 8)
305 #define CP_MEQ_THRESHOLDS 0x8764
306 #define MEQ1_START(x) ((x) << 0)
307 #define MEQ2_START(x) ((x) << 8)
309 #define CP_PERFMON_CNTL 0x87FC
311 #define VGT_VTX_VECT_EJECT_REG 0x88B0
313 #define VGT_CACHE_INVALIDATION 0x88C4
314 #define CACHE_INVALIDATION(x) ((x) << 0)
318 #define AUTO_INVLD_EN(x) ((x) << 6)
322 #define ES_AND_GS_AUTO 3
323 #define VGT_ESGS_RING_SIZE 0x88C8
324 #define VGT_GSVS_RING_SIZE 0x88CC
326 #define VGT_GS_VERTEX_REUSE 0x88D4
328 #define VGT_PRIMITIVE_TYPE 0x8958
329 #define VGT_INDEX_TYPE 0x895C
331 #define VGT_NUM_INDICES 0x8970
332 #define VGT_NUM_INSTANCES 0x8974
334 #define VGT_TF_RING_SIZE 0x8988
336 #define VGT_HS_OFFCHIP_PARAM 0x89B0
338 #define VGT_TF_MEMORY_BASE 0x89B8
340 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
341 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
343 #define PA_CL_ENHANCE 0x8A14
344 #define CLIP_VTX_REORDER_ENA (1 << 0)
345 #define NUM_CLIP_SEQ(x) ((x) << 1)
347 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
349 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
351 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
352 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
353 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
355 #define PA_SC_FIFO_SIZE 0x8BCC
356 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
357 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
358 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
359 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
361 #define PA_SC_ENHANCE 0x8BF0
363 #define SQ_CONFIG 0x8C00
365 #define SQC_CACHES 0x8C08
367 #define SX_DEBUG_1 0x9060
369 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
370 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
371 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
372 #define SPI_PS_MAX_WAVE_ID 0x90EC
374 #define SPI_CONFIG_CNTL 0x9100
376 #define SPI_CONFIG_CNTL_1 0x913C
377 #define VTX_DONE_DELAY(x) ((x) << 0)
378 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
380 #define CGTS_TCC_DISABLE 0x9148
381 #define CGTS_USER_TCC_DISABLE 0x914C
382 #define TCC_DISABLE_MASK 0xFFFF0000
383 #define TCC_DISABLE_SHIFT 16
385 #define TA_CNTL_AUX 0x9508
387 #define CC_RB_BACKEND_DISABLE 0x98F4
388 #define BACKEND_DISABLE(x) ((x) << 16)
389 #define GB_ADDR_CONFIG 0x98F8
390 #define NUM_PIPES(x) ((x) << 0)
391 #define NUM_PIPES_MASK 0x00000007
392 #define NUM_PIPES_SHIFT 0
393 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
394 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
395 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
396 #define NUM_SHADER_ENGINES(x) ((x) << 12)
397 #define NUM_SHADER_ENGINES_MASK 0x00003000
398 #define NUM_SHADER_ENGINES_SHIFT 12
399 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
400 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
401 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
402 #define NUM_GPUS(x) ((x) << 20)
403 #define NUM_GPUS_MASK 0x00700000
404 #define NUM_GPUS_SHIFT 20
405 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
406 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
407 #define MULTI_GPU_TILE_SIZE_SHIFT 24
408 #define ROW_SIZE(x) ((x) << 28)
409 #define ROW_SIZE_MASK 0x30000000
410 #define ROW_SIZE_SHIFT 28
412 #define GB_TILE_MODE0 0x9910
413 # define MICRO_TILE_MODE(x) ((x) << 0)
414 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
415 # define ADDR_SURF_THIN_MICRO_TILING 1
416 # define ADDR_SURF_DEPTH_MICRO_TILING 2
417 # define ARRAY_MODE(x) ((x) << 2)
418 # define ARRAY_LINEAR_GENERAL 0
419 # define ARRAY_LINEAR_ALIGNED 1
420 # define ARRAY_1D_TILED_THIN1 2
421 # define ARRAY_2D_TILED_THIN1 4
422 # define PIPE_CONFIG(x) ((x) << 6)
423 # define ADDR_SURF_P2 0
424 # define ADDR_SURF_P4_8x16 4
425 # define ADDR_SURF_P4_16x16 5
426 # define ADDR_SURF_P4_16x32 6
427 # define ADDR_SURF_P4_32x32 7
428 # define ADDR_SURF_P8_16x16_8x16 8
429 # define ADDR_SURF_P8_16x32_8x16 9
430 # define ADDR_SURF_P8_32x32_8x16 10
431 # define ADDR_SURF_P8_16x32_16x16 11
432 # define ADDR_SURF_P8_32x32_16x16 12
433 # define ADDR_SURF_P8_32x32_16x32 13
434 # define ADDR_SURF_P8_32x64_32x32 14
435 # define TILE_SPLIT(x) ((x) << 11)
436 # define ADDR_SURF_TILE_SPLIT_64B 0
437 # define ADDR_SURF_TILE_SPLIT_128B 1
438 # define ADDR_SURF_TILE_SPLIT_256B 2
439 # define ADDR_SURF_TILE_SPLIT_512B 3
440 # define ADDR_SURF_TILE_SPLIT_1KB 4
441 # define ADDR_SURF_TILE_SPLIT_2KB 5
442 # define ADDR_SURF_TILE_SPLIT_4KB 6
443 # define BANK_WIDTH(x) ((x) << 14)
444 # define ADDR_SURF_BANK_WIDTH_1 0
445 # define ADDR_SURF_BANK_WIDTH_2 1
446 # define ADDR_SURF_BANK_WIDTH_4 2
447 # define ADDR_SURF_BANK_WIDTH_8 3
448 # define BANK_HEIGHT(x) ((x) << 16)
449 # define ADDR_SURF_BANK_HEIGHT_1 0
450 # define ADDR_SURF_BANK_HEIGHT_2 1
451 # define ADDR_SURF_BANK_HEIGHT_4 2
452 # define ADDR_SURF_BANK_HEIGHT_8 3
453 # define MACRO_TILE_ASPECT(x) ((x) << 18)
454 # define ADDR_SURF_MACRO_ASPECT_1 0
455 # define ADDR_SURF_MACRO_ASPECT_2 1
456 # define ADDR_SURF_MACRO_ASPECT_4 2
457 # define ADDR_SURF_MACRO_ASPECT_8 3
458 # define NUM_BANKS(x) ((x) << 20)
459 # define ADDR_SURF_2_BANK 0
460 # define ADDR_SURF_4_BANK 1
461 # define ADDR_SURF_8_BANK 2
462 # define ADDR_SURF_16_BANK 3
464 #define CB_PERFCOUNTER0_SELECT0 0x9a20
465 #define CB_PERFCOUNTER0_SELECT1 0x9a24
466 #define CB_PERFCOUNTER1_SELECT0 0x9a28
467 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
468 #define CB_PERFCOUNTER2_SELECT0 0x9a30
469 #define CB_PERFCOUNTER2_SELECT1 0x9a34
470 #define CB_PERFCOUNTER3_SELECT0 0x9a38
471 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
473 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
474 #define BACKEND_DISABLE_MASK 0x00FF0000
475 #define BACKEND_DISABLE_SHIFT 16
477 #define TCP_CHAN_STEER_LO 0xac0c
478 #define TCP_CHAN_STEER_HI 0xac10
480 #define CP_RB0_BASE 0xC100
481 #define CP_RB0_CNTL 0xC104
482 #define RB_BUFSZ(x) ((x) << 0)
483 #define RB_BLKSZ(x) ((x) << 8)
484 #define BUF_SWAP_32BIT (2 << 16)
485 #define RB_NO_UPDATE (1 << 27)
486 #define RB_RPTR_WR_ENA (1 << 31)
488 #define CP_RB0_RPTR_ADDR 0xC10C
489 #define CP_RB0_RPTR_ADDR_HI 0xC110
490 #define CP_RB0_WPTR 0xC114
492 #define CP_PFP_UCODE_ADDR 0xC150
493 #define CP_PFP_UCODE_DATA 0xC154
494 #define CP_ME_RAM_RADDR 0xC158
495 #define CP_ME_RAM_WADDR 0xC15C
496 #define CP_ME_RAM_DATA 0xC160
498 #define CP_CE_UCODE_ADDR 0xC168
499 #define CP_CE_UCODE_DATA 0xC16C
501 #define CP_RB1_BASE 0xC180
502 #define CP_RB1_CNTL 0xC184
503 #define CP_RB1_RPTR_ADDR 0xC188
504 #define CP_RB1_RPTR_ADDR_HI 0xC18C
505 #define CP_RB1_WPTR 0xC190
506 #define CP_RB2_BASE 0xC194
507 #define CP_RB2_CNTL 0xC198
508 #define CP_RB2_RPTR_ADDR 0xC19C
509 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
510 #define CP_RB2_WPTR 0xC1A4
512 #define CP_DEBUG 0xC1FC
517 #define PACKET_TYPE0 0
518 #define PACKET_TYPE1 1
519 #define PACKET_TYPE2 2
520 #define PACKET_TYPE3 3
522 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
523 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
524 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
525 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
526 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
527 (((reg) >> 2) & 0xFFFF) | \
528 ((n) & 0x3FFF) << 16)
529 #define CP_PACKET2 0x80000000
530 #define PACKET2_PAD_SHIFT 0
531 #define PACKET2_PAD_MASK (0x3fffffff << 0)
533 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
535 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
536 (((op) & 0xFF) << 8) | \
537 ((n) & 0x3FFF) << 16)
539 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
542 #define PACKET3_NOP 0x10
543 #define PACKET3_SET_BASE 0x11
544 #define PACKET3_BASE_INDEX(x) ((x) << 0)
545 #define GDS_PARTITION_BASE 2
546 #define CE_PARTITION_BASE 3
547 #define PACKET3_CLEAR_STATE 0x12
548 #define PACKET3_INDEX_BUFFER_SIZE 0x13
549 #define PACKET3_DISPATCH_DIRECT 0x15
550 #define PACKET3_DISPATCH_INDIRECT 0x16
551 #define PACKET3_ALLOC_GDS 0x1B
552 #define PACKET3_WRITE_GDS_RAM 0x1C
553 #define PACKET3_ATOMIC_GDS 0x1D
554 #define PACKET3_ATOMIC 0x1E
555 #define PACKET3_OCCLUSION_QUERY 0x1F
556 #define PACKET3_SET_PREDICATION 0x20
557 #define PACKET3_REG_RMW 0x21
558 #define PACKET3_COND_EXEC 0x22
559 #define PACKET3_PRED_EXEC 0x23
560 #define PACKET3_DRAW_INDIRECT 0x24
561 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
562 #define PACKET3_INDEX_BASE 0x26
563 #define PACKET3_DRAW_INDEX_2 0x27
564 #define PACKET3_CONTEXT_CONTROL 0x28
565 #define PACKET3_INDEX_TYPE 0x2A
566 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
567 #define PACKET3_DRAW_INDEX_AUTO 0x2D
568 #define PACKET3_DRAW_INDEX_IMMD 0x2E
569 #define PACKET3_NUM_INSTANCES 0x2F
570 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
571 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
572 #define PACKET3_INDIRECT_BUFFER 0x32
573 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
574 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
575 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
576 #define PACKET3_WRITE_DATA 0x37
577 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
578 #define PACKET3_MEM_SEMAPHORE 0x39
579 #define PACKET3_MPEG_INDEX 0x3A
580 #define PACKET3_COPY_DW 0x3B
581 #define PACKET3_WAIT_REG_MEM 0x3C
582 #define PACKET3_MEM_WRITE 0x3D
583 #define PACKET3_COPY_DATA 0x40
584 #define PACKET3_PFP_SYNC_ME 0x42
585 #define PACKET3_SURFACE_SYNC 0x43
586 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
587 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
588 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
589 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
590 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
591 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
592 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
593 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
594 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
595 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
596 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
597 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
598 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
599 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
600 # define PACKET3_TC_ACTION_ENA (1 << 23)
601 # define PACKET3_CB_ACTION_ENA (1 << 25)
602 # define PACKET3_DB_ACTION_ENA (1 << 26)
603 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
604 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
605 #define PACKET3_ME_INITIALIZE 0x44
606 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
607 #define PACKET3_COND_WRITE 0x45
608 #define PACKET3_EVENT_WRITE 0x46
609 #define PACKET3_EVENT_WRITE_EOP 0x47
610 #define PACKET3_EVENT_WRITE_EOS 0x48
611 #define PACKET3_PREAMBLE_CNTL 0x4A
612 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
613 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
614 #define PACKET3_ONE_REG_WRITE 0x57
615 #define PACKET3_LOAD_CONFIG_REG 0x5F
616 #define PACKET3_LOAD_CONTEXT_REG 0x60
617 #define PACKET3_LOAD_SH_REG 0x61
618 #define PACKET3_SET_CONFIG_REG 0x68
619 #define PACKET3_SET_CONFIG_REG_START 0x00008000
620 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
621 #define PACKET3_SET_CONTEXT_REG 0x69
622 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
623 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
624 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
625 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
626 #define PACKET3_SET_SH_REG 0x76
627 #define PACKET3_SET_SH_REG_START 0x0000b000
628 #define PACKET3_SET_SH_REG_END 0x0000c000
629 #define PACKET3_SET_SH_REG_OFFSET 0x77
630 #define PACKET3_ME_WRITE 0x7A
631 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
632 #define PACKET3_SCRATCH_RAM_READ 0x7E
633 #define PACKET3_CE_WRITE 0x7F
634 #define PACKET3_LOAD_CONST_RAM 0x80
635 #define PACKET3_WRITE_CONST_RAM 0x81
636 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
637 #define PACKET3_DUMP_CONST_RAM 0x83
638 #define PACKET3_INCREMENT_CE_COUNTER 0x84
639 #define PACKET3_INCREMENT_DE_COUNTER 0x85
640 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
641 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
642 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
643 #define PACKET3_SET_CE_DE_COUNTERS 0x89
644 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A