drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23
  24 #include "rcar_du_crtc.h"
  25 #include "rcar_du_drv.h"
  26 #include "rcar_du_kms.h"
  27 #include "rcar_du_plane.h"
  28 #include "rcar_du_regs.h"
  29
  30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  31 {
  32         struct rcar_du_device *rcdu = rcrtc->group->dev;
  33
  34         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  35 }
  36
  37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  38 {
  39         struct rcar_du_device *rcdu = rcrtc->group->dev;
  40
  41         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  42 }
  43
  44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  45 {
  46         struct rcar_du_device *rcdu = rcrtc->group->dev;
  47
  48         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  49                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  50 }
  51
  52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  53 {
  54         struct rcar_du_device *rcdu = rcrtc->group->dev;
  55
  56         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  57                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  58 }
  59
  60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  61                                  u32 clr, u32 set)
  62 {
  63         struct rcar_du_device *rcdu = rcrtc->group->dev;
  64         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  65
  66         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  67 }
  68
  69 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  70 {
  71         int ret;
  72
  73         ret = clk_prepare_enable(rcrtc->clock);
  74         if (ret < 0)
  75                 return ret;
  76
  77         ret = clk_prepare_enable(rcrtc->extclock);
  78         if (ret < 0)
  79                 goto error_clock;
  80
  81         ret = rcar_du_group_get(rcrtc->group);
  82         if (ret < 0)
  83                 goto error_group;
  84
  85         return 0;
  86
  87 error_group:
  88         clk_disable_unprepare(rcrtc->extclock);
  89 error_clock:
  90         clk_disable_unprepare(rcrtc->clock);
  91         return ret;
  92 }
  93
  94 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  95 {
  96         rcar_du_group_put(rcrtc->group);
  97
  98         clk_disable_unprepare(rcrtc->extclock);
  99         clk_disable_unprepare(rcrtc->clock);
 100 }
 101
 102 /* -----------------------------------------------------------------------------
 103  * Hardware Setup
 104  */
 105
 106 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 107 {
 108         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
 109         unsigned long mode_clock = mode->clock * 1000;
 110         unsigned long clk;
 111         u32 value;
 112         u32 escr;
 113         u32 div;
 114
 115         /* Compute the clock divisor and select the internal or external dot
 116          * clock based on the requested frequency.
 117          */
 118         clk = clk_get_rate(rcrtc->clock);
 119         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 120         div = clamp(div, 1U, 64U) - 1;
 121         escr = div | ESCR_DCLKSEL_CLKS;
 122
 123         if (rcrtc->extclock) {
 124                 unsigned long extclk;
 125                 unsigned long extrate;
 126                 unsigned long rate;
 127                 u32 extdiv;
 128
 129                 extclk = clk_get_rate(rcrtc->extclock);
 130                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 131                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 132
 133                 rate = clk / (div + 1);
 134                 extrate = extclk / (extdiv + 1);
 135
 136                 if (abs((long)extrate - (long)mode_clock) <
 137                     abs((long)rate - (long)mode_clock)) {
 138                         dev_dbg(rcrtc->group->dev->dev,
 139                                 "crtc%u: using external clock\n", rcrtc->index);
 140                         escr = extdiv | ESCR_DCLKSEL_DCLKIN;
 141                 }
 142         }
 143
 144         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 145                             escr);
 146         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 147
 148         /* Signal polarities */
 149         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 150               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 151               | DSMR_DIPM_DE | DSMR_CSPM;
 152         rcar_du_crtc_write(rcrtc, DSMR, value);
 153
 154         /* Display timings */
 155         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 156         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 157                                         mode->hdisplay - 19);
 158         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 159                                         mode->hsync_start - 1);
 160         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 161
 162         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 163                                         mode->crtc_vsync_end - 2);
 164         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 165                                         mode->crtc_vsync_end +
 166                                         mode->crtc_vdisplay - 2);
 167         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 168                                         mode->crtc_vsync_end +
 169                                         mode->crtc_vsync_start - 1);
 170         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 171
 172         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 173         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 174 }
 175
 176 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 177                                enum rcar_du_output output)
 178 {
 179         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 180         struct rcar_du_device *rcdu = rcrtc->group->dev;
 181
 182         /* Store the route from the CRTC output to the DU output. The DU will be
 183          * configured when starting the CRTC.
 184          */
 185         rcrtc->outputs |= BIT(output);
 186
 187         /* Store RGB routing to DPAD0, the hardware will be configured when
 188          * starting the CRTC.
 189          */
 190         if (output == RCAR_DU_OUTPUT_DPAD0)
 191                 rcdu->dpad0_source = rcrtc->index;
 192 }
 193
 194 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 195 {
 196         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 197         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 198         unsigned int num_planes = 0;
 199         unsigned int prio = 0;
 200         unsigned int i;
 201         u32 dptsr = 0;
 202         u32 dspr = 0;
 203
 204         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 205                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 206                 unsigned int j;
 207
 208                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 209                         continue;
 210
 211                 /* Insert the plane in the sorted planes array. */
 212                 for (j = num_planes++; j > 0; --j) {
 213                         if (planes[j-1]->zpos <= plane->zpos)
 214                                 break;
 215                         planes[j] = planes[j-1];
 216                 }
 217
 218                 planes[j] = plane;
 219                 prio += plane->format->planes * 4;
 220         }
 221
 222         for (i = 0; i < num_planes; ++i) {
 223                 struct rcar_du_plane *plane = planes[i];
 224                 unsigned int index = plane->hwindex;
 225
 226                 prio -= 4;
 227                 dspr |= (index + 1) << prio;
 228                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 229
 230                 if (plane->format->planes == 2) {
 231                         index = (index + 1) % 8;
 232
 233                         prio -= 4;
 234                         dspr |= (index + 1) << prio;
 235                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 236                 }
 237         }
 238
 239         /* Select display timing and dot clock generator 2 for planes associated
 240          * with superposition controller 2.
 241          */
 242         if (rcrtc->index % 2) {
 243                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 244
 245                 /* The DPTSR register is updated when the display controller is
 246                  * stopped. We thus need to restart the DU. Once again, sorry
 247                  * for the flicker. One way to mitigate the issue would be to
 248                  * pre-associate planes with CRTCs (either with a fixed 4/4
 249                  * split, or through a module parameter). Flicker would then
 250                  * occur only if we need to break the pre-association.
 251                  */
 252                 if (value != dptsr) {
 253                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 254                         if (rcrtc->group->used_crtcs)
 255                                 rcar_du_group_restart(rcrtc->group);
 256                 }
 257         }
 258
 259         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 260                             dspr);
 261 }
 262
 263 /* -----------------------------------------------------------------------------
 264  * Page Flip
 265  */
 266
 267 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 268                                    struct drm_file *file)
 269 {
 270         struct drm_pending_vblank_event *event;
 271         struct drm_device *dev = rcrtc->crtc.dev;
 272         unsigned long flags;
 273
 274         /* Destroy the pending vertical blanking event associated with the
 275          * pending page flip, if any, and disable vertical blanking interrupts.
 276          */
 277         spin_lock_irqsave(&dev->event_lock, flags);
 278         event = rcrtc->event;
 279         if (event && event->base.file_priv == file) {
 280                 rcrtc->event = NULL;
 281                 event->base.destroy(&event->base);
 282                 drm_vblank_put(dev, rcrtc->index);
 283         }
 284         spin_unlock_irqrestore(&dev->event_lock, flags);
 285 }
 286
 287 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 288 {
 289         struct drm_pending_vblank_event *event;
 290         struct drm_device *dev = rcrtc->crtc.dev;
 291         unsigned long flags;
 292
 293         spin_lock_irqsave(&dev->event_lock, flags);
 294         event = rcrtc->event;
 295         rcrtc->event = NULL;
 296         spin_unlock_irqrestore(&dev->event_lock, flags);
 297
 298         if (event == NULL)
 299                 return;
 300
 301         spin_lock_irqsave(&dev->event_lock, flags);
 302         drm_send_vblank_event(dev, rcrtc->index, event);
 303         wake_up(&rcrtc->flip_wait);
 304         spin_unlock_irqrestore(&dev->event_lock, flags);
 305
 306         drm_vblank_put(dev, rcrtc->index);
 307 }
 308
 309 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 310 {
 311         struct drm_device *dev = rcrtc->crtc.dev;
 312         unsigned long flags;
 313         bool pending;
 314
 315         spin_lock_irqsave(&dev->event_lock, flags);
 316         pending = rcrtc->event != NULL;
 317         spin_unlock_irqrestore(&dev->event_lock, flags);
 318
 319         return pending;
 320 }
 321
 322 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 323 {
 324         struct rcar_du_device *rcdu = rcrtc->group->dev;
 325
 326         if (wait_event_timeout(rcrtc->flip_wait,
 327                                !rcar_du_crtc_page_flip_pending(rcrtc),
 328                                msecs_to_jiffies(50)))
 329                 return;
 330
 331         dev_warn(rcdu->dev, "page flip timeout\n");
 332
 333         rcar_du_crtc_finish_page_flip(rcrtc);
 334 }
 335
 336 /* -----------------------------------------------------------------------------
 337  * Start/Stop and Suspend/Resume
 338  */
 339
 340 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 341 {
 342         struct drm_crtc *crtc = &rcrtc->crtc;
 343         bool interlaced;
 344         unsigned int i;
 345
 346         if (rcrtc->started)
 347                 return;
 348
 349         if (WARN_ON(rcrtc->plane->format == NULL))
 350                 return;
 351
 352         /* Set display off and background to black */
 353         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 354         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 355
 356         /* Configure display timings and output routing */
 357         rcar_du_crtc_set_display_timing(rcrtc);
 358         rcar_du_group_set_routing(rcrtc->group);
 359
 360         mutex_lock(&rcrtc->group->planes.lock);
 361         rcrtc->plane->enabled = true;
 362         rcar_du_crtc_update_planes(crtc);
 363         mutex_unlock(&rcrtc->group->planes.lock);
 364
 365         /* Setup planes. */
 366         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 367                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 368
 369                 if (plane->crtc != crtc || !plane->enabled)
 370                         continue;
 371
 372                 rcar_du_plane_setup(plane);
 373         }
 374
 375         /* Select master sync mode. This enables display operation in master
 376          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 377          * actively driven).
 378          */
 379         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 380         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 381                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 382                              DSYSR_TVM_MASTER);
 383
 384         rcar_du_group_start_stop(rcrtc->group, true);
 385
 386         rcrtc->started = true;
 387 }
 388
 389 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 390 {
 391         struct drm_crtc *crtc = &rcrtc->crtc;
 392
 393         if (!rcrtc->started)
 394                 return;
 395
 396         /* Wait for page flip completion before stopping the CRTC as userspace
 397          * excepts page flips to eventually complete.
 398          */
 399         rcar_du_crtc_wait_page_flip(rcrtc);
 400
 401         mutex_lock(&rcrtc->group->planes.lock);
 402         rcrtc->plane->enabled = false;
 403         rcar_du_crtc_update_planes(crtc);
 404         mutex_unlock(&rcrtc->group->planes.lock);
 405
 406         /* Select switch sync mode. This stops display operation and configures
 407          * the HSYNC and VSYNC signals as inputs.
 408          */
 409         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 410
 411         rcar_du_group_start_stop(rcrtc->group, false);
 412
 413         rcrtc->started = false;
 414 }
 415
 416 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 417 {
 418         rcar_du_crtc_stop(rcrtc);
 419         rcar_du_crtc_put(rcrtc);
 420 }
 421
 422 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 423 {
 424         if (rcrtc->dpms != DRM_MODE_DPMS_ON)
 425                 return;
 426
 427         rcar_du_crtc_get(rcrtc);
 428         rcar_du_crtc_start(rcrtc);
 429 }
 430
 431 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
 432 {
 433         struct drm_crtc *crtc = &rcrtc->crtc;
 434
 435         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 436         rcar_du_plane_update_base(rcrtc->plane);
 437 }
 438
 439 /* -----------------------------------------------------------------------------
 440  * CRTC Functions
 441  */
 442
 443 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
 444 {
 445         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 446
 447         if (mode != DRM_MODE_DPMS_ON)
 448                 mode = DRM_MODE_DPMS_OFF;
 449
 450         if (rcrtc->dpms == mode)
 451                 return;
 452
 453         if (mode == DRM_MODE_DPMS_ON) {
 454                 rcar_du_crtc_get(rcrtc);
 455                 rcar_du_crtc_start(rcrtc);
 456         } else {
 457                 rcar_du_crtc_stop(rcrtc);
 458                 rcar_du_crtc_put(rcrtc);
 459         }
 460
 461         rcrtc->dpms = mode;
 462 }
 463
 464 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 465                                     const struct drm_display_mode *mode,
 466                                     struct drm_display_mode *adjusted_mode)
 467 {
 468         /* TODO Fixup modes */
 469         return true;
 470 }
 471
 472 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
 473 {
 474         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 475
 476         /* We need to access the hardware during mode set, acquire a reference
 477          * to the CRTC.
 478          */
 479         rcar_du_crtc_get(rcrtc);
 480
 481         /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
 482          * result.
 483          */
 484         rcar_du_crtc_stop(rcrtc);
 485         rcar_du_plane_release(rcrtc->plane);
 486
 487         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 488 }
 489
 490 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
 491                                  struct drm_display_mode *mode,
 492                                  struct drm_display_mode *adjusted_mode,
 493                                  int x, int y,
 494                                  struct drm_framebuffer *old_fb)
 495 {
 496         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 497         struct rcar_du_device *rcdu = rcrtc->group->dev;
 498         const struct rcar_du_format_info *format;
 499         int ret;
 500
 501         format = rcar_du_format_info(crtc->primary->fb->pixel_format);
 502         if (format == NULL) {
 503                 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
 504                         crtc->primary->fb->pixel_format);
 505                 ret = -EINVAL;
 506                 goto error;
 507         }
 508
 509         ret = rcar_du_plane_reserve(rcrtc->plane, format);
 510         if (ret < 0)
 511                 goto error;
 512
 513         rcrtc->plane->format = format;
 514
 515         rcrtc->plane->src_x = x;
 516         rcrtc->plane->src_y = y;
 517         rcrtc->plane->width = mode->hdisplay;
 518         rcrtc->plane->height = mode->vdisplay;
 519
 520         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 521
 522         rcrtc->outputs = 0;
 523
 524         return 0;
 525
 526 error:
 527         /* There's no rollback/abort operation to clean up in case of error. We
 528          * thus need to release the reference to the CRTC acquired in prepare()
 529          * here.
 530          */
 531         rcar_du_crtc_put(rcrtc);
 532         return ret;
 533 }
 534
 535 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
 536 {
 537         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 538
 539         /* We're done, restart the CRTC and set the DPMS mode to on. The
 540          * reference to the DU acquired at prepare() time will thus be released
 541          * by the DPMS handler (possibly called by the disable() handler).
 542          */
 543         rcar_du_crtc_start(rcrtc);
 544         rcrtc->dpms = DRM_MODE_DPMS_ON;
 545 }
 546
 547 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 548                                       struct drm_framebuffer *old_fb)
 549 {
 550         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 551
 552         rcrtc->plane->src_x = x;
 553         rcrtc->plane->src_y = y;
 554
 555         rcar_du_crtc_update_base(rcrtc);
 556
 557         return 0;
 558 }
 559
 560 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 561 {
 562         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 563
 564         rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 565         rcar_du_plane_release(rcrtc->plane);
 566 }
 567
 568 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 569         .dpms = rcar_du_crtc_dpms,
 570         .mode_fixup = rcar_du_crtc_mode_fixup,
 571         .prepare = rcar_du_crtc_mode_prepare,
 572         .commit = rcar_du_crtc_mode_commit,
 573         .mode_set = rcar_du_crtc_mode_set,
 574         .mode_set_base = rcar_du_crtc_mode_set_base,
 575         .disable = rcar_du_crtc_disable,
 576 };
 577
 578 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
 579                                   struct drm_framebuffer *fb,
 580                                   struct drm_pending_vblank_event *event,
 581                                   uint32_t page_flip_flags)
 582 {
 583         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 584         struct drm_device *dev = rcrtc->crtc.dev;
 585         unsigned long flags;
 586
 587         spin_lock_irqsave(&dev->event_lock, flags);
 588         if (rcrtc->event != NULL) {
 589                 spin_unlock_irqrestore(&dev->event_lock, flags);
 590                 return -EBUSY;
 591         }
 592         spin_unlock_irqrestore(&dev->event_lock, flags);
 593
 594         crtc->primary->fb = fb;
 595         rcar_du_crtc_update_base(rcrtc);
 596
 597         if (event) {
 598                 event->pipe = rcrtc->index;
 599                 drm_vblank_get(dev, rcrtc->index);
 600                 spin_lock_irqsave(&dev->event_lock, flags);
 601                 rcrtc->event = event;
 602                 spin_unlock_irqrestore(&dev->event_lock, flags);
 603         }
 604
 605         return 0;
 606 }
 607
 608 static const struct drm_crtc_funcs crtc_funcs = {
 609         .destroy = drm_crtc_cleanup,
 610         .set_config = drm_crtc_helper_set_config,
 611         .page_flip = rcar_du_crtc_page_flip,
 612 };
 613
 614 /* -----------------------------------------------------------------------------
 615  * Interrupt Handling
 616  */
 617
 618 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 619 {
 620         struct rcar_du_crtc *rcrtc = arg;
 621         irqreturn_t ret = IRQ_NONE;
 622         u32 status;
 623
 624         status = rcar_du_crtc_read(rcrtc, DSSR);
 625         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 626
 627         if (status & DSSR_FRM) {
 628                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 629                 rcar_du_crtc_finish_page_flip(rcrtc);
 630                 ret = IRQ_HANDLED;
 631         }
 632
 633         return ret;
 634 }
 635
 636 /* -----------------------------------------------------------------------------
 637  * Initialization
 638  */
 639
 640 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 641 {
 642         static const unsigned int mmio_offsets[] = {
 643                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 644         };
 645
 646         struct rcar_du_device *rcdu = rgrp->dev;
 647         struct platform_device *pdev = to_platform_device(rcdu->dev);
 648         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 649         struct drm_crtc *crtc = &rcrtc->crtc;
 650         unsigned int irqflags;
 651         struct clk *clk;
 652         char clk_name[9];
 653         char *name;
 654         int irq;
 655         int ret;
 656
 657         /* Get the CRTC clock and the optional external clock. */
 658         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 659                 sprintf(clk_name, "du.%u", index);
 660                 name = clk_name;
 661         } else {
 662                 name = NULL;
 663         }
 664
 665         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 666         if (IS_ERR(rcrtc->clock)) {
 667                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 668                 return PTR_ERR(rcrtc->clock);
 669         }
 670
 671         sprintf(clk_name, "dclkin.%u", index);
 672         clk = devm_clk_get(rcdu->dev, clk_name);
 673         if (!IS_ERR(clk)) {
 674                 rcrtc->extclock = clk;
 675         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 676                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 677                 return -EPROBE_DEFER;
 678         }
 679
 680         init_waitqueue_head(&rcrtc->flip_wait);
 681
 682         rcrtc->group = rgrp;
 683         rcrtc->mmio_offset = mmio_offsets[index];
 684         rcrtc->index = index;
 685         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 686         rcrtc->plane = &rgrp->planes.planes[index % 2];
 687
 688         rcrtc->plane->crtc = crtc;
 689
 690         ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
 691         if (ret < 0)
 692                 return ret;
 693
 694         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 695
 696         /* Register the interrupt handler. */
 697         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 698                 irq = platform_get_irq(pdev, index);
 699                 irqflags = 0;
 700         } else {
 701                 irq = platform_get_irq(pdev, 0);
 702                 irqflags = IRQF_SHARED;
 703         }
 704
 705         if (irq < 0) {
 706                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 707                 return irq;
 708         }
 709
 710         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 711                                dev_name(rcdu->dev), rcrtc);
 712         if (ret < 0) {
 713                 dev_err(rcdu->dev,
 714                         "failed to register IRQ for CRTC %u\n", index);
 715                 return ret;
 716         }
 717
 718         return 0;
 719 }
 720
 721 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 722 {
 723         if (enable) {
 724                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 725                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 726         } else {
 727                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 728         }
 729 }