drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_fb_cma_helper.h>
  23 #include <drm/drm_gem_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "rcar_du_crtc.h"
  27 #include "rcar_du_drv.h"
  28 #include "rcar_du_kms.h"
  29 #include "rcar_du_plane.h"
  30 #include "rcar_du_regs.h"
  31
  32 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  33 {
  34         struct rcar_du_device *rcdu = rcrtc->group->dev;
  35
  36         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  37 }
  38
  39 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  40 {
  41         struct rcar_du_device *rcdu = rcrtc->group->dev;
  42
  43         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  44 }
  45
  46 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  47 {
  48         struct rcar_du_device *rcdu = rcrtc->group->dev;
  49
  50         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  51                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  52 }
  53
  54 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  55 {
  56         struct rcar_du_device *rcdu = rcrtc->group->dev;
  57
  58         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  59                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  60 }
  61
  62 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  63                                  u32 clr, u32 set)
  64 {
  65         struct rcar_du_device *rcdu = rcrtc->group->dev;
  66         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  67
  68         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  69 }
  70
  71 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  72 {
  73         int ret;
  74
  75         ret = clk_prepare_enable(rcrtc->clock);
  76         if (ret < 0)
  77                 return ret;
  78
  79         ret = clk_prepare_enable(rcrtc->extclock);
  80         if (ret < 0)
  81                 goto error_clock;
  82
  83         ret = rcar_du_group_get(rcrtc->group);
  84         if (ret < 0)
  85                 goto error_group;
  86
  87         return 0;
  88
  89 error_group:
  90         clk_disable_unprepare(rcrtc->extclock);
  91 error_clock:
  92         clk_disable_unprepare(rcrtc->clock);
  93         return ret;
  94 }
  95
  96 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  97 {
  98         rcar_du_group_put(rcrtc->group);
  99
 100         clk_disable_unprepare(rcrtc->extclock);
 101         clk_disable_unprepare(rcrtc->clock);
 102 }
 103
 104 /* -----------------------------------------------------------------------------
 105  * Hardware Setup
 106  */
 107
 108 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 109 {
 110         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 111         unsigned long mode_clock = mode->clock * 1000;
 112         unsigned long clk;
 113         u32 value;
 114         u32 escr;
 115         u32 div;
 116
 117         /* Compute the clock divisor and select the internal or external dot
 118          * clock based on the requested frequency.
 119          */
 120         clk = clk_get_rate(rcrtc->clock);
 121         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 122         div = clamp(div, 1U, 64U) - 1;
 123         escr = div | ESCR_DCLKSEL_CLKS;
 124
 125         if (rcrtc->extclock) {
 126                 unsigned long extclk;
 127                 unsigned long extrate;
 128                 unsigned long rate;
 129                 u32 extdiv;
 130
 131                 extclk = clk_get_rate(rcrtc->extclock);
 132                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 133                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 134
 135                 rate = clk / (div + 1);
 136                 extrate = extclk / (extdiv + 1);
 137
 138                 if (abs((long)extrate - (long)mode_clock) <
 139                     abs((long)rate - (long)mode_clock)) {
 140                         dev_dbg(rcrtc->group->dev->dev,
 141                                 "crtc%u: using external clock\n", rcrtc->index);
 142                         escr = extdiv | ESCR_DCLKSEL_DCLKIN;
 143                 }
 144         }
 145
 146         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 147                             escr);
 148         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 149
 150         /* Signal polarities */
 151         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 152               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 153               | DSMR_DIPM_DE | DSMR_CSPM;
 154         rcar_du_crtc_write(rcrtc, DSMR, value);
 155
 156         /* Display timings */
 157         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 158         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 159                                         mode->hdisplay - 19);
 160         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 161                                         mode->hsync_start - 1);
 162         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 163
 164         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 165                                         mode->crtc_vsync_end - 2);
 166         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 167                                         mode->crtc_vsync_end +
 168                                         mode->crtc_vdisplay - 2);
 169         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 170                                         mode->crtc_vsync_end +
 171                                         mode->crtc_vsync_start - 1);
 172         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 173
 174         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 175         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 176 }
 177
 178 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 179                                enum rcar_du_output output)
 180 {
 181         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 182         struct rcar_du_device *rcdu = rcrtc->group->dev;
 183
 184         /* Store the route from the CRTC output to the DU output. The DU will be
 185          * configured when starting the CRTC.
 186          */
 187         rcrtc->outputs |= BIT(output);
 188
 189         /* Store RGB routing to DPAD0, the hardware will be configured when
 190          * starting the CRTC.
 191          */
 192         if (output == RCAR_DU_OUTPUT_DPAD0)
 193                 rcdu->dpad0_source = rcrtc->index;
 194 }
 195
 196 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 197 {
 198         return to_rcar_du_plane_state(plane->plane.state)->zpos;
 199 }
 200
 201 static void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 202 {
 203         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 204         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 205         unsigned int num_planes = 0;
 206         unsigned int prio = 0;
 207         unsigned int i;
 208         u32 dptsr = 0;
 209         u32 dspr = 0;
 210
 211         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 212                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 213                 unsigned int j;
 214
 215                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 216                         continue;
 217
 218                 /* Insert the plane in the sorted planes array. */
 219                 for (j = num_planes++; j > 0; --j) {
 220                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 221                                 break;
 222                         planes[j] = planes[j-1];
 223                 }
 224
 225                 planes[j] = plane;
 226                 prio += plane->format->planes * 4;
 227         }
 228
 229         for (i = 0; i < num_planes; ++i) {
 230                 struct rcar_du_plane *plane = planes[i];
 231                 unsigned int index = plane->hwindex;
 232
 233                 prio -= 4;
 234                 dspr |= (index + 1) << prio;
 235                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 236
 237                 if (plane->format->planes == 2) {
 238                         index = (index + 1) % 8;
 239
 240                         prio -= 4;
 241                         dspr |= (index + 1) << prio;
 242                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 243                 }
 244         }
 245
 246         /* Select display timing and dot clock generator 2 for planes associated
 247          * with superposition controller 2.
 248          */
 249         if (rcrtc->index % 2) {
 250                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 251
 252                 /* The DPTSR register is updated when the display controller is
 253                  * stopped. We thus need to restart the DU. Once again, sorry
 254                  * for the flicker. One way to mitigate the issue would be to
 255                  * pre-associate planes with CRTCs (either with a fixed 4/4
 256                  * split, or through a module parameter). Flicker would then
 257                  * occur only if we need to break the pre-association.
 258                  */
 259                 if (value != dptsr) {
 260                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 261                         if (rcrtc->group->used_crtcs)
 262                                 rcar_du_group_restart(rcrtc->group);
 263                 }
 264         }
 265
 266         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 267                             dspr);
 268 }
 269
 270 /* -----------------------------------------------------------------------------
 271  * Page Flip
 272  */
 273
 274 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 275                                    struct drm_file *file)
 276 {
 277         struct drm_pending_vblank_event *event;
 278         struct drm_device *dev = rcrtc->crtc.dev;
 279         unsigned long flags;
 280
 281         /* Destroy the pending vertical blanking event associated with the
 282          * pending page flip, if any, and disable vertical blanking interrupts.
 283          */
 284         spin_lock_irqsave(&dev->event_lock, flags);
 285         event = rcrtc->event;
 286         if (event && event->base.file_priv == file) {
 287                 rcrtc->event = NULL;
 288                 event->base.destroy(&event->base);
 289                 drm_crtc_vblank_put(&rcrtc->crtc);
 290         }
 291         spin_unlock_irqrestore(&dev->event_lock, flags);
 292 }
 293
 294 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 295 {
 296         struct drm_pending_vblank_event *event;
 297         struct drm_device *dev = rcrtc->crtc.dev;
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&dev->event_lock, flags);
 301         event = rcrtc->event;
 302         rcrtc->event = NULL;
 303         spin_unlock_irqrestore(&dev->event_lock, flags);
 304
 305         if (event == NULL)
 306                 return;
 307
 308         spin_lock_irqsave(&dev->event_lock, flags);
 309         drm_send_vblank_event(dev, rcrtc->index, event);
 310         wake_up(&rcrtc->flip_wait);
 311         spin_unlock_irqrestore(&dev->event_lock, flags);
 312
 313         drm_crtc_vblank_put(&rcrtc->crtc);
 314 }
 315
 316 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 317 {
 318         struct drm_device *dev = rcrtc->crtc.dev;
 319         unsigned long flags;
 320         bool pending;
 321
 322         spin_lock_irqsave(&dev->event_lock, flags);
 323         pending = rcrtc->event != NULL;
 324         spin_unlock_irqrestore(&dev->event_lock, flags);
 325
 326         return pending;
 327 }
 328
 329 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 330 {
 331         struct rcar_du_device *rcdu = rcrtc->group->dev;
 332
 333         if (wait_event_timeout(rcrtc->flip_wait,
 334                                !rcar_du_crtc_page_flip_pending(rcrtc),
 335                                msecs_to_jiffies(50)))
 336                 return;
 337
 338         dev_warn(rcdu->dev, "page flip timeout\n");
 339
 340         rcar_du_crtc_finish_page_flip(rcrtc);
 341 }
 342
 343 /* -----------------------------------------------------------------------------
 344  * Start/Stop and Suspend/Resume
 345  */
 346
 347 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 348 {
 349         struct drm_crtc *crtc = &rcrtc->crtc;
 350         bool interlaced;
 351         unsigned int i;
 352
 353         if (rcrtc->started)
 354                 return;
 355
 356         if (WARN_ON(rcrtc->plane->format == NULL))
 357                 return;
 358
 359         /* Set display off and background to black */
 360         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 361         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 362
 363         /* Configure display timings and output routing */
 364         rcar_du_crtc_set_display_timing(rcrtc);
 365         rcar_du_group_set_routing(rcrtc->group);
 366
 367         /* FIXME: Commit the planes state. This is required here as the CRTC can
 368          * be started from the system resume handler, which don't go
 369          * through .atomic_plane_update() and .atomic_flush() to commit plane
 370          * state. Additionally, given that the plane state atomic commit occurs
 371          * between CRTC disable and enable, the hardware state could also be
 372          * lost due to runtime PM, requiring a full commit here. This will be
 373          * fixed later after switching to atomic updates completely.
 374          */
 375         mutex_lock(&rcrtc->group->planes.lock);
 376         rcar_du_crtc_update_planes(crtc);
 377         mutex_unlock(&rcrtc->group->planes.lock);
 378
 379         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 380                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 381
 382                 if (plane->crtc != crtc || !plane->enabled)
 383                         continue;
 384
 385                 rcar_du_plane_setup(plane);
 386         }
 387
 388         /* Select master sync mode. This enables display operation in master
 389          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 390          * actively driven).
 391          */
 392         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 393         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 394                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 395                              DSYSR_TVM_MASTER);
 396
 397         rcar_du_group_start_stop(rcrtc->group, true);
 398
 399         /* Turn vertical blanking interrupt reporting back on. */
 400         drm_crtc_vblank_on(crtc);
 401
 402         rcrtc->started = true;
 403 }
 404
 405 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 406 {
 407         struct drm_crtc *crtc = &rcrtc->crtc;
 408
 409         if (!rcrtc->started)
 410                 return;
 411
 412         /* Disable vertical blanking interrupt reporting. We first need to wait
 413          * for page flip completion before stopping the CRTC as userspace
 414          * expects page flips to eventually complete.
 415          */
 416         rcar_du_crtc_wait_page_flip(rcrtc);
 417         drm_crtc_vblank_off(crtc);
 418
 419         /* Select switch sync mode. This stops display operation and configures
 420          * the HSYNC and VSYNC signals as inputs.
 421          */
 422         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 423
 424         rcar_du_group_start_stop(rcrtc->group, false);
 425
 426         rcrtc->started = false;
 427 }
 428
 429 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 430 {
 431         rcar_du_crtc_stop(rcrtc);
 432         rcar_du_crtc_put(rcrtc);
 433 }
 434
 435 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 436 {
 437         if (!rcrtc->enabled)
 438                 return;
 439
 440         rcar_du_crtc_get(rcrtc);
 441         rcar_du_crtc_start(rcrtc);
 442 }
 443
 444 /* -----------------------------------------------------------------------------
 445  * CRTC Functions
 446  */
 447
 448 static void rcar_du_crtc_enable(struct drm_crtc *crtc)
 449 {
 450         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 451
 452         if (rcrtc->enabled)
 453                 return;
 454
 455         rcar_du_crtc_get(rcrtc);
 456         rcar_du_crtc_start(rcrtc);
 457
 458         rcrtc->enabled = true;
 459 }
 460
 461 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 462 {
 463         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 464
 465         if (!rcrtc->enabled)
 466                 return;
 467
 468         rcar_du_crtc_stop(rcrtc);
 469         rcar_du_crtc_put(rcrtc);
 470
 471         rcrtc->enabled = false;
 472         rcrtc->outputs = 0;
 473 }
 474
 475 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 476                                     const struct drm_display_mode *mode,
 477                                     struct drm_display_mode *adjusted_mode)
 478 {
 479         /* TODO Fixup modes */
 480         return true;
 481 }
 482
 483 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
 484 {
 485         struct drm_pending_vblank_event *event = crtc->state->event;
 486         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 487         struct drm_device *dev = rcrtc->crtc.dev;
 488         unsigned long flags;
 489
 490         /* We need to access the hardware during atomic update, acquire a
 491          * reference to the CRTC.
 492          */
 493         rcar_du_crtc_get(rcrtc);
 494
 495         if (event) {
 496                 event->pipe = rcrtc->index;
 497
 498                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 499
 500                 spin_lock_irqsave(&dev->event_lock, flags);
 501                 rcrtc->event = event;
 502                 spin_unlock_irqrestore(&dev->event_lock, flags);
 503         }
 504 }
 505
 506 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
 507 {
 508         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 509
 510         /* We're done, apply the configuration and drop the reference acquired
 511          * in .atomic_begin().
 512          */
 513         mutex_lock(&rcrtc->group->planes.lock);
 514         rcar_du_crtc_update_planes(crtc);
 515         mutex_unlock(&rcrtc->group->planes.lock);
 516
 517         rcar_du_crtc_put(rcrtc);
 518 }
 519
 520 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 521         .mode_fixup = rcar_du_crtc_mode_fixup,
 522         .disable = rcar_du_crtc_disable,
 523         .enable = rcar_du_crtc_enable,
 524         .atomic_begin = rcar_du_crtc_atomic_begin,
 525         .atomic_flush = rcar_du_crtc_atomic_flush,
 526 };
 527
 528 static const struct drm_crtc_funcs crtc_funcs = {
 529         .reset = drm_atomic_helper_crtc_reset,
 530         .destroy = drm_crtc_cleanup,
 531         .set_config = drm_atomic_helper_set_config,
 532         .page_flip = drm_atomic_helper_page_flip,
 533         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 534         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 535 };
 536
 537 /* -----------------------------------------------------------------------------
 538  * Interrupt Handling
 539  */
 540
 541 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 542 {
 543         struct rcar_du_crtc *rcrtc = arg;
 544         irqreturn_t ret = IRQ_NONE;
 545         u32 status;
 546
 547         status = rcar_du_crtc_read(rcrtc, DSSR);
 548         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 549
 550         if (status & DSSR_FRM) {
 551                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 552                 rcar_du_crtc_finish_page_flip(rcrtc);
 553                 ret = IRQ_HANDLED;
 554         }
 555
 556         return ret;
 557 }
 558
 559 /* -----------------------------------------------------------------------------
 560  * Initialization
 561  */
 562
 563 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 564 {
 565         static const unsigned int mmio_offsets[] = {
 566                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 567         };
 568
 569         struct rcar_du_device *rcdu = rgrp->dev;
 570         struct platform_device *pdev = to_platform_device(rcdu->dev);
 571         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 572         struct drm_crtc *crtc = &rcrtc->crtc;
 573         unsigned int irqflags;
 574         struct clk *clk;
 575         char clk_name[9];
 576         char *name;
 577         int irq;
 578         int ret;
 579
 580         /* Get the CRTC clock and the optional external clock. */
 581         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 582                 sprintf(clk_name, "du.%u", index);
 583                 name = clk_name;
 584         } else {
 585                 name = NULL;
 586         }
 587
 588         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 589         if (IS_ERR(rcrtc->clock)) {
 590                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 591                 return PTR_ERR(rcrtc->clock);
 592         }
 593
 594         sprintf(clk_name, "dclkin.%u", index);
 595         clk = devm_clk_get(rcdu->dev, clk_name);
 596         if (!IS_ERR(clk)) {
 597                 rcrtc->extclock = clk;
 598         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 599                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 600                 return -EPROBE_DEFER;
 601         }
 602
 603         init_waitqueue_head(&rcrtc->flip_wait);
 604
 605         rcrtc->group = rgrp;
 606         rcrtc->mmio_offset = mmio_offsets[index];
 607         rcrtc->index = index;
 608         rcrtc->enabled = false;
 609         rcrtc->plane = &rgrp->planes.planes[index % 2];
 610
 611         rcrtc->plane->crtc = crtc;
 612
 613         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, &rcrtc->plane->plane,
 614                                         NULL, &crtc_funcs);
 615         if (ret < 0)
 616                 return ret;
 617
 618         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 619
 620         /* Start with vertical blanking interrupt reporting disabled. */
 621         drm_crtc_vblank_off(crtc);
 622
 623         /* Register the interrupt handler. */
 624         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 625                 irq = platform_get_irq(pdev, index);
 626                 irqflags = 0;
 627         } else {
 628                 irq = platform_get_irq(pdev, 0);
 629                 irqflags = IRQF_SHARED;
 630         }
 631
 632         if (irq < 0) {
 633                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 634                 return irq;
 635         }
 636
 637         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 638                                dev_name(rcdu->dev), rcrtc);
 639         if (ret < 0) {
 640                 dev_err(rcdu->dev,
 641                         "failed to register IRQ for CRTC %u\n", index);
 642                 return ret;
 643         }
 644
 645         return 0;
 646 }
 647
 648 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 649 {
 650         if (enable) {
 651                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 652                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 653         } else {
 654                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 655         }
 656 }