drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_fb_cma_helper.h>
  23 #include <drm/drm_gem_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "rcar_du_crtc.h"
  27 #include "rcar_du_drv.h"
  28 #include "rcar_du_kms.h"
  29 #include "rcar_du_plane.h"
  30 #include "rcar_du_regs.h"
  31
  32 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  33 {
  34         struct rcar_du_device *rcdu = rcrtc->group->dev;
  35
  36         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  37 }
  38
  39 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  40 {
  41         struct rcar_du_device *rcdu = rcrtc->group->dev;
  42
  43         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  44 }
  45
  46 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  47 {
  48         struct rcar_du_device *rcdu = rcrtc->group->dev;
  49
  50         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  51                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  52 }
  53
  54 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  55 {
  56         struct rcar_du_device *rcdu = rcrtc->group->dev;
  57
  58         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  59                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  60 }
  61
  62 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  63                                  u32 clr, u32 set)
  64 {
  65         struct rcar_du_device *rcdu = rcrtc->group->dev;
  66         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  67
  68         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  69 }
  70
  71 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  72 {
  73         int ret;
  74
  75         ret = clk_prepare_enable(rcrtc->clock);
  76         if (ret < 0)
  77                 return ret;
  78
  79         ret = clk_prepare_enable(rcrtc->extclock);
  80         if (ret < 0)
  81                 goto error_clock;
  82
  83         ret = rcar_du_group_get(rcrtc->group);
  84         if (ret < 0)
  85                 goto error_group;
  86
  87         return 0;
  88
  89 error_group:
  90         clk_disable_unprepare(rcrtc->extclock);
  91 error_clock:
  92         clk_disable_unprepare(rcrtc->clock);
  93         return ret;
  94 }
  95
  96 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  97 {
  98         rcar_du_group_put(rcrtc->group);
  99
 100         clk_disable_unprepare(rcrtc->extclock);
 101         clk_disable_unprepare(rcrtc->clock);
 102 }
 103
 104 /* -----------------------------------------------------------------------------
 105  * Hardware Setup
 106  */
 107
 108 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 109 {
 110         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 111         unsigned long mode_clock = mode->clock * 1000;
 112         unsigned long clk;
 113         u32 value;
 114         u32 escr;
 115         u32 div;
 116
 117         /* Compute the clock divisor and select the internal or external dot
 118          * clock based on the requested frequency.
 119          */
 120         clk = clk_get_rate(rcrtc->clock);
 121         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 122         div = clamp(div, 1U, 64U) - 1;
 123         escr = div | ESCR_DCLKSEL_CLKS;
 124
 125         if (rcrtc->extclock) {
 126                 unsigned long extclk;
 127                 unsigned long extrate;
 128                 unsigned long rate;
 129                 u32 extdiv;
 130
 131                 extclk = clk_get_rate(rcrtc->extclock);
 132                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 133                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 134
 135                 rate = clk / (div + 1);
 136                 extrate = extclk / (extdiv + 1);
 137
 138                 if (abs((long)extrate - (long)mode_clock) <
 139                     abs((long)rate - (long)mode_clock)) {
 140                         dev_dbg(rcrtc->group->dev->dev,
 141                                 "crtc%u: using external clock\n", rcrtc->index);
 142                         escr = extdiv | ESCR_DCLKSEL_DCLKIN;
 143                 }
 144         }
 145
 146         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 147                             escr);
 148         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 149
 150         /* Signal polarities */
 151         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 152               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 153               | DSMR_DIPM_DE | DSMR_CSPM;
 154         rcar_du_crtc_write(rcrtc, DSMR, value);
 155
 156         /* Display timings */
 157         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 158         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 159                                         mode->hdisplay - 19);
 160         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 161                                         mode->hsync_start - 1);
 162         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 163
 164         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 165                                         mode->crtc_vsync_end - 2);
 166         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 167                                         mode->crtc_vsync_end +
 168                                         mode->crtc_vdisplay - 2);
 169         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 170                                         mode->crtc_vsync_end +
 171                                         mode->crtc_vsync_start - 1);
 172         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 173
 174         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 175         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 176 }
 177
 178 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 179                                enum rcar_du_output output)
 180 {
 181         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 182         struct rcar_du_device *rcdu = rcrtc->group->dev;
 183
 184         /* Store the route from the CRTC output to the DU output. The DU will be
 185          * configured when starting the CRTC.
 186          */
 187         rcrtc->outputs |= BIT(output);
 188
 189         /* Store RGB routing to DPAD0, the hardware will be configured when
 190          * starting the CRTC.
 191          */
 192         if (output == RCAR_DU_OUTPUT_DPAD0)
 193                 rcdu->dpad0_source = rcrtc->index;
 194 }
 195
 196 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 197 {
 198         return to_rcar_du_plane_state(plane->plane.state)->zpos;
 199 }
 200
 201 static const struct rcar_du_format_info *
 202 plane_format(struct rcar_du_plane *plane)
 203 {
 204         return to_rcar_du_plane_state(plane->plane.state)->format;
 205 }
 206
 207 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 208 {
 209         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 210         unsigned int num_planes = 0;
 211         unsigned int prio = 0;
 212         unsigned int i;
 213         u32 dptsr = 0;
 214         u32 dspr = 0;
 215
 216         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 217                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 218                 unsigned int j;
 219
 220                 if (plane->plane.state->crtc != &rcrtc->crtc)
 221                         continue;
 222
 223                 /* Insert the plane in the sorted planes array. */
 224                 for (j = num_planes++; j > 0; --j) {
 225                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 226                                 break;
 227                         planes[j] = planes[j-1];
 228                 }
 229
 230                 planes[j] = plane;
 231                 prio += plane_format(plane)->planes * 4;
 232         }
 233
 234         for (i = 0; i < num_planes; ++i) {
 235                 struct rcar_du_plane *plane = planes[i];
 236                 unsigned int index = plane->hwindex;
 237
 238                 prio -= 4;
 239                 dspr |= (index + 1) << prio;
 240                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 241
 242                 if (plane_format(plane)->planes == 2) {
 243                         index = (index + 1) % 8;
 244
 245                         prio -= 4;
 246                         dspr |= (index + 1) << prio;
 247                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 248                 }
 249         }
 250
 251         /* Select display timing and dot clock generator 2 for planes associated
 252          * with superposition controller 2.
 253          */
 254         if (rcrtc->index % 2) {
 255                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 256
 257                 /* The DPTSR register is updated when the display controller is
 258                  * stopped. We thus need to restart the DU. Once again, sorry
 259                  * for the flicker. One way to mitigate the issue would be to
 260                  * pre-associate planes with CRTCs (either with a fixed 4/4
 261                  * split, or through a module parameter). Flicker would then
 262                  * occur only if we need to break the pre-association.
 263                  */
 264                 if (value != dptsr) {
 265                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 266                         if (rcrtc->group->used_crtcs)
 267                                 rcar_du_group_restart(rcrtc->group);
 268                 }
 269         }
 270
 271         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 272                             dspr);
 273 }
 274
 275 /* -----------------------------------------------------------------------------
 276  * Page Flip
 277  */
 278
 279 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 280                                    struct drm_file *file)
 281 {
 282         struct drm_pending_vblank_event *event;
 283         struct drm_device *dev = rcrtc->crtc.dev;
 284         unsigned long flags;
 285
 286         /* Destroy the pending vertical blanking event associated with the
 287          * pending page flip, if any, and disable vertical blanking interrupts.
 288          */
 289         spin_lock_irqsave(&dev->event_lock, flags);
 290         event = rcrtc->event;
 291         if (event && event->base.file_priv == file) {
 292                 rcrtc->event = NULL;
 293                 event->base.destroy(&event->base);
 294                 drm_crtc_vblank_put(&rcrtc->crtc);
 295         }
 296         spin_unlock_irqrestore(&dev->event_lock, flags);
 297 }
 298
 299 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 300 {
 301         struct drm_pending_vblank_event *event;
 302         struct drm_device *dev = rcrtc->crtc.dev;
 303         unsigned long flags;
 304
 305         spin_lock_irqsave(&dev->event_lock, flags);
 306         event = rcrtc->event;
 307         rcrtc->event = NULL;
 308         spin_unlock_irqrestore(&dev->event_lock, flags);
 309
 310         if (event == NULL)
 311                 return;
 312
 313         spin_lock_irqsave(&dev->event_lock, flags);
 314         drm_send_vblank_event(dev, rcrtc->index, event);
 315         wake_up(&rcrtc->flip_wait);
 316         spin_unlock_irqrestore(&dev->event_lock, flags);
 317
 318         drm_crtc_vblank_put(&rcrtc->crtc);
 319 }
 320
 321 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 322 {
 323         struct drm_device *dev = rcrtc->crtc.dev;
 324         unsigned long flags;
 325         bool pending;
 326
 327         spin_lock_irqsave(&dev->event_lock, flags);
 328         pending = rcrtc->event != NULL;
 329         spin_unlock_irqrestore(&dev->event_lock, flags);
 330
 331         return pending;
 332 }
 333
 334 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 335 {
 336         struct rcar_du_device *rcdu = rcrtc->group->dev;
 337
 338         if (wait_event_timeout(rcrtc->flip_wait,
 339                                !rcar_du_crtc_page_flip_pending(rcrtc),
 340                                msecs_to_jiffies(50)))
 341                 return;
 342
 343         dev_warn(rcdu->dev, "page flip timeout\n");
 344
 345         rcar_du_crtc_finish_page_flip(rcrtc);
 346 }
 347
 348 /* -----------------------------------------------------------------------------
 349  * Start/Stop and Suspend/Resume
 350  */
 351
 352 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 353 {
 354         struct drm_crtc *crtc = &rcrtc->crtc;
 355         bool interlaced;
 356
 357         if (rcrtc->started)
 358                 return;
 359
 360         /* Set display off and background to black */
 361         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 362         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 363
 364         /* Configure display timings and output routing */
 365         rcar_du_crtc_set_display_timing(rcrtc);
 366         rcar_du_group_set_routing(rcrtc->group);
 367
 368         /* Start with all planes disabled. */
 369         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 370
 371         /* Select master sync mode. This enables display operation in master
 372          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 373          * actively driven).
 374          */
 375         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 376         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 377                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 378                              DSYSR_TVM_MASTER);
 379
 380         rcar_du_group_start_stop(rcrtc->group, true);
 381
 382         /* Turn vertical blanking interrupt reporting back on. */
 383         drm_crtc_vblank_on(crtc);
 384
 385         rcrtc->started = true;
 386 }
 387
 388 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 389 {
 390         struct drm_crtc *crtc = &rcrtc->crtc;
 391
 392         if (!rcrtc->started)
 393                 return;
 394
 395         /* Disable vertical blanking interrupt reporting. We first need to wait
 396          * for page flip completion before stopping the CRTC as userspace
 397          * expects page flips to eventually complete.
 398          */
 399         rcar_du_crtc_wait_page_flip(rcrtc);
 400         drm_crtc_vblank_off(crtc);
 401
 402         /* Select switch sync mode. This stops display operation and configures
 403          * the HSYNC and VSYNC signals as inputs.
 404          */
 405         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 406
 407         rcar_du_group_start_stop(rcrtc->group, false);
 408
 409         rcrtc->started = false;
 410 }
 411
 412 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 413 {
 414         rcar_du_crtc_stop(rcrtc);
 415         rcar_du_crtc_put(rcrtc);
 416 }
 417
 418 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 419 {
 420         unsigned int i;
 421
 422         if (!rcrtc->enabled)
 423                 return;
 424
 425         rcar_du_crtc_get(rcrtc);
 426         rcar_du_crtc_start(rcrtc);
 427
 428         /* Commit the planes state. */
 429         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 430                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 431
 432                 if (plane->plane.state->crtc != &rcrtc->crtc)
 433                         continue;
 434
 435                 rcar_du_plane_setup(plane);
 436         }
 437
 438         mutex_lock(&rcrtc->group->planes.lock);
 439         rcar_du_crtc_update_planes(rcrtc);
 440         mutex_unlock(&rcrtc->group->planes.lock);
 441 }
 442
 443 /* -----------------------------------------------------------------------------
 444  * CRTC Functions
 445  */
 446
 447 static void rcar_du_crtc_enable(struct drm_crtc *crtc)
 448 {
 449         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 450
 451         if (rcrtc->enabled)
 452                 return;
 453
 454         rcar_du_crtc_get(rcrtc);
 455         rcar_du_crtc_start(rcrtc);
 456
 457         rcrtc->enabled = true;
 458 }
 459
 460 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 461 {
 462         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 463
 464         if (!rcrtc->enabled)
 465                 return;
 466
 467         rcar_du_crtc_stop(rcrtc);
 468         rcar_du_crtc_put(rcrtc);
 469
 470         rcrtc->enabled = false;
 471         rcrtc->outputs = 0;
 472 }
 473
 474 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 475                                     const struct drm_display_mode *mode,
 476                                     struct drm_display_mode *adjusted_mode)
 477 {
 478         /* TODO Fixup modes */
 479         return true;
 480 }
 481
 482 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
 483 {
 484         struct drm_pending_vblank_event *event = crtc->state->event;
 485         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 486         struct drm_device *dev = rcrtc->crtc.dev;
 487         unsigned long flags;
 488
 489         if (event) {
 490                 event->pipe = rcrtc->index;
 491
 492                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 493
 494                 spin_lock_irqsave(&dev->event_lock, flags);
 495                 rcrtc->event = event;
 496                 spin_unlock_irqrestore(&dev->event_lock, flags);
 497         }
 498 }
 499
 500 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
 501 {
 502         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 503
 504         mutex_lock(&rcrtc->group->planes.lock);
 505         rcar_du_crtc_update_planes(rcrtc);
 506         mutex_unlock(&rcrtc->group->planes.lock);
 507 }
 508
 509 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 510         .mode_fixup = rcar_du_crtc_mode_fixup,
 511         .disable = rcar_du_crtc_disable,
 512         .enable = rcar_du_crtc_enable,
 513         .atomic_begin = rcar_du_crtc_atomic_begin,
 514         .atomic_flush = rcar_du_crtc_atomic_flush,
 515 };
 516
 517 static const struct drm_crtc_funcs crtc_funcs = {
 518         .reset = drm_atomic_helper_crtc_reset,
 519         .destroy = drm_crtc_cleanup,
 520         .set_config = drm_atomic_helper_set_config,
 521         .page_flip = drm_atomic_helper_page_flip,
 522         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 523         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 524 };
 525
 526 /* -----------------------------------------------------------------------------
 527  * Interrupt Handling
 528  */
 529
 530 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 531 {
 532         struct rcar_du_crtc *rcrtc = arg;
 533         irqreturn_t ret = IRQ_NONE;
 534         u32 status;
 535
 536         status = rcar_du_crtc_read(rcrtc, DSSR);
 537         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 538
 539         if (status & DSSR_FRM) {
 540                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 541                 rcar_du_crtc_finish_page_flip(rcrtc);
 542                 ret = IRQ_HANDLED;
 543         }
 544
 545         return ret;
 546 }
 547
 548 /* -----------------------------------------------------------------------------
 549  * Initialization
 550  */
 551
 552 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 553 {
 554         static const unsigned int mmio_offsets[] = {
 555                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 556         };
 557
 558         struct rcar_du_device *rcdu = rgrp->dev;
 559         struct platform_device *pdev = to_platform_device(rcdu->dev);
 560         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 561         struct drm_crtc *crtc = &rcrtc->crtc;
 562         unsigned int irqflags;
 563         struct clk *clk;
 564         char clk_name[9];
 565         char *name;
 566         int irq;
 567         int ret;
 568
 569         /* Get the CRTC clock and the optional external clock. */
 570         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 571                 sprintf(clk_name, "du.%u", index);
 572                 name = clk_name;
 573         } else {
 574                 name = NULL;
 575         }
 576
 577         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 578         if (IS_ERR(rcrtc->clock)) {
 579                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 580                 return PTR_ERR(rcrtc->clock);
 581         }
 582
 583         sprintf(clk_name, "dclkin.%u", index);
 584         clk = devm_clk_get(rcdu->dev, clk_name);
 585         if (!IS_ERR(clk)) {
 586                 rcrtc->extclock = clk;
 587         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 588                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 589                 return -EPROBE_DEFER;
 590         }
 591
 592         init_waitqueue_head(&rcrtc->flip_wait);
 593
 594         rcrtc->group = rgrp;
 595         rcrtc->mmio_offset = mmio_offsets[index];
 596         rcrtc->index = index;
 597         rcrtc->enabled = false;
 598
 599         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc,
 600                                         &rgrp->planes.planes[index % 2].plane,
 601                                         NULL, &crtc_funcs);
 602         if (ret < 0)
 603                 return ret;
 604
 605         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 606
 607         /* Start with vertical blanking interrupt reporting disabled. */
 608         drm_crtc_vblank_off(crtc);
 609
 610         /* Register the interrupt handler. */
 611         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 612                 irq = platform_get_irq(pdev, index);
 613                 irqflags = 0;
 614         } else {
 615                 irq = platform_get_irq(pdev, 0);
 616                 irqflags = IRQF_SHARED;
 617         }
 618
 619         if (irq < 0) {
 620                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 621                 return irq;
 622         }
 623
 624         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 625                                dev_name(rcdu->dev), rcrtc);
 626         if (ret < 0) {
 627                 dev_err(rcdu->dev,
 628                         "failed to register IRQ for CRTC %u\n", index);
 629                 return ret;
 630         }
 631
 632         return 0;
 633 }
 634
 635 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 636 {
 637         if (enable) {
 638                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 639                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 640         } else {
 641                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 642         }
 643 }