2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/mutex.h>
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_crtc_helper.h>
22 #include <drm/drm_fb_cma_helper.h>
23 #include <drm/drm_gem_cma_helper.h>
24 #include <drm/drm_plane_helper.h>
26 #include "rcar_du_crtc.h"
27 #include "rcar_du_drv.h"
28 #include "rcar_du_kms.h"
29 #include "rcar_du_plane.h"
30 #include "rcar_du_regs.h"
32 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
34 struct rcar_du_device *rcdu = rcrtc->group->dev;
36 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
39 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
41 struct rcar_du_device *rcdu = rcrtc->group->dev;
43 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
46 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
48 struct rcar_du_device *rcdu = rcrtc->group->dev;
50 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
51 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
54 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
56 struct rcar_du_device *rcdu = rcrtc->group->dev;
58 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
59 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
62 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
65 struct rcar_du_device *rcdu = rcrtc->group->dev;
66 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
68 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
71 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
75 ret = clk_prepare_enable(rcrtc->clock);
79 ret = clk_prepare_enable(rcrtc->extclock);
83 ret = rcar_du_group_get(rcrtc->group);
90 clk_disable_unprepare(rcrtc->extclock);
92 clk_disable_unprepare(rcrtc->clock);
96 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
98 rcar_du_group_put(rcrtc->group);
100 clk_disable_unprepare(rcrtc->extclock);
101 clk_disable_unprepare(rcrtc->clock);
104 /* -----------------------------------------------------------------------------
108 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
110 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
111 unsigned long mode_clock = mode->clock * 1000;
117 /* Compute the clock divisor and select the internal or external dot
118 * clock based on the requested frequency.
120 clk = clk_get_rate(rcrtc->clock);
121 div = DIV_ROUND_CLOSEST(clk, mode_clock);
122 div = clamp(div, 1U, 64U) - 1;
123 escr = div | ESCR_DCLKSEL_CLKS;
125 if (rcrtc->extclock) {
126 unsigned long extclk;
127 unsigned long extrate;
131 extclk = clk_get_rate(rcrtc->extclock);
132 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
133 extdiv = clamp(extdiv, 1U, 64U) - 1;
135 rate = clk / (div + 1);
136 extrate = extclk / (extdiv + 1);
138 if (abs((long)extrate - (long)mode_clock) <
139 abs((long)rate - (long)mode_clock)) {
140 dev_dbg(rcrtc->group->dev->dev,
141 "crtc%u: using external clock\n", rcrtc->index);
142 escr = extdiv | ESCR_DCLKSEL_DCLKIN;
146 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
148 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
150 /* Signal polarities */
151 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
152 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
153 | DSMR_DIPM_DE | DSMR_CSPM;
154 rcar_du_crtc_write(rcrtc, DSMR, value);
156 /* Display timings */
157 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
158 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
159 mode->hdisplay - 19);
160 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
161 mode->hsync_start - 1);
162 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
164 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
165 mode->crtc_vsync_end - 2);
166 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
167 mode->crtc_vsync_end +
168 mode->crtc_vdisplay - 2);
169 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
170 mode->crtc_vsync_end +
171 mode->crtc_vsync_start - 1);
172 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
174 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
175 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
178 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
179 enum rcar_du_output output)
181 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
182 struct rcar_du_device *rcdu = rcrtc->group->dev;
184 /* Store the route from the CRTC output to the DU output. The DU will be
185 * configured when starting the CRTC.
187 rcrtc->outputs |= BIT(output);
189 /* Store RGB routing to DPAD0, the hardware will be configured when
192 if (output == RCAR_DU_OUTPUT_DPAD0)
193 rcdu->dpad0_source = rcrtc->index;
196 static unsigned int plane_zpos(struct rcar_du_plane *plane)
198 return to_rcar_du_plane_state(plane->plane.state)->zpos;
201 static const struct rcar_du_format_info *
202 plane_format(struct rcar_du_plane *plane)
204 return to_rcar_du_plane_state(plane->plane.state)->format;
207 static void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
209 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
210 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
211 unsigned int num_planes = 0;
212 unsigned int prio = 0;
217 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
218 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
221 if (plane->plane.state->crtc != &rcrtc->crtc)
224 /* Insert the plane in the sorted planes array. */
225 for (j = num_planes++; j > 0; --j) {
226 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
228 planes[j] = planes[j-1];
232 prio += plane_format(plane)->planes * 4;
235 for (i = 0; i < num_planes; ++i) {
236 struct rcar_du_plane *plane = planes[i];
237 unsigned int index = plane->hwindex;
240 dspr |= (index + 1) << prio;
241 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
243 if (plane_format(plane)->planes == 2) {
244 index = (index + 1) % 8;
247 dspr |= (index + 1) << prio;
248 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
252 /* Select display timing and dot clock generator 2 for planes associated
253 * with superposition controller 2.
255 if (rcrtc->index % 2) {
256 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
258 /* The DPTSR register is updated when the display controller is
259 * stopped. We thus need to restart the DU. Once again, sorry
260 * for the flicker. One way to mitigate the issue would be to
261 * pre-associate planes with CRTCs (either with a fixed 4/4
262 * split, or through a module parameter). Flicker would then
263 * occur only if we need to break the pre-association.
265 if (value != dptsr) {
266 rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
267 if (rcrtc->group->used_crtcs)
268 rcar_du_group_restart(rcrtc->group);
272 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
276 /* -----------------------------------------------------------------------------
280 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
281 struct drm_file *file)
283 struct drm_pending_vblank_event *event;
284 struct drm_device *dev = rcrtc->crtc.dev;
287 /* Destroy the pending vertical blanking event associated with the
288 * pending page flip, if any, and disable vertical blanking interrupts.
290 spin_lock_irqsave(&dev->event_lock, flags);
291 event = rcrtc->event;
292 if (event && event->base.file_priv == file) {
294 event->base.destroy(&event->base);
295 drm_crtc_vblank_put(&rcrtc->crtc);
297 spin_unlock_irqrestore(&dev->event_lock, flags);
300 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
302 struct drm_pending_vblank_event *event;
303 struct drm_device *dev = rcrtc->crtc.dev;
306 spin_lock_irqsave(&dev->event_lock, flags);
307 event = rcrtc->event;
309 spin_unlock_irqrestore(&dev->event_lock, flags);
314 spin_lock_irqsave(&dev->event_lock, flags);
315 drm_send_vblank_event(dev, rcrtc->index, event);
316 wake_up(&rcrtc->flip_wait);
317 spin_unlock_irqrestore(&dev->event_lock, flags);
319 drm_crtc_vblank_put(&rcrtc->crtc);
322 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
324 struct drm_device *dev = rcrtc->crtc.dev;
328 spin_lock_irqsave(&dev->event_lock, flags);
329 pending = rcrtc->event != NULL;
330 spin_unlock_irqrestore(&dev->event_lock, flags);
335 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
337 struct rcar_du_device *rcdu = rcrtc->group->dev;
339 if (wait_event_timeout(rcrtc->flip_wait,
340 !rcar_du_crtc_page_flip_pending(rcrtc),
341 msecs_to_jiffies(50)))
344 dev_warn(rcdu->dev, "page flip timeout\n");
346 rcar_du_crtc_finish_page_flip(rcrtc);
349 /* -----------------------------------------------------------------------------
350 * Start/Stop and Suspend/Resume
353 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
355 struct drm_crtc *crtc = &rcrtc->crtc;
362 /* Set display off and background to black */
363 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
364 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
366 /* Configure display timings and output routing */
367 rcar_du_crtc_set_display_timing(rcrtc);
368 rcar_du_group_set_routing(rcrtc->group);
370 /* FIXME: Commit the planes state. This is required here as the CRTC can
371 * be started from the system resume handler, which don't go
372 * through .atomic_plane_update() and .atomic_flush() to commit plane
373 * state. Additionally, given that the plane state atomic commit occurs
374 * between CRTC disable and enable, the hardware state could also be
375 * lost due to runtime PM, requiring a full commit here. This will be
376 * fixed later after switching to atomic updates completely.
378 mutex_lock(&rcrtc->group->planes.lock);
379 rcar_du_crtc_update_planes(crtc);
380 mutex_unlock(&rcrtc->group->planes.lock);
382 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
383 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
385 if (plane->plane.state->crtc != crtc)
388 rcar_du_plane_setup(plane);
391 /* Select master sync mode. This enables display operation in master
392 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
395 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
396 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
397 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
400 rcar_du_group_start_stop(rcrtc->group, true);
402 /* Turn vertical blanking interrupt reporting back on. */
403 drm_crtc_vblank_on(crtc);
405 rcrtc->started = true;
408 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
410 struct drm_crtc *crtc = &rcrtc->crtc;
415 /* Disable vertical blanking interrupt reporting. We first need to wait
416 * for page flip completion before stopping the CRTC as userspace
417 * expects page flips to eventually complete.
419 rcar_du_crtc_wait_page_flip(rcrtc);
420 drm_crtc_vblank_off(crtc);
422 /* Select switch sync mode. This stops display operation and configures
423 * the HSYNC and VSYNC signals as inputs.
425 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
427 rcar_du_group_start_stop(rcrtc->group, false);
429 rcrtc->started = false;
432 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
434 rcar_du_crtc_stop(rcrtc);
435 rcar_du_crtc_put(rcrtc);
438 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
443 rcar_du_crtc_get(rcrtc);
444 rcar_du_crtc_start(rcrtc);
447 /* -----------------------------------------------------------------------------
451 static void rcar_du_crtc_enable(struct drm_crtc *crtc)
453 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
458 rcar_du_crtc_get(rcrtc);
459 rcar_du_crtc_start(rcrtc);
461 rcrtc->enabled = true;
464 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
466 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
471 rcar_du_crtc_stop(rcrtc);
472 rcar_du_crtc_put(rcrtc);
474 rcrtc->enabled = false;
478 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
479 const struct drm_display_mode *mode,
480 struct drm_display_mode *adjusted_mode)
482 /* TODO Fixup modes */
486 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
488 struct drm_pending_vblank_event *event = crtc->state->event;
489 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
490 struct drm_device *dev = rcrtc->crtc.dev;
493 /* We need to access the hardware during atomic update, acquire a
494 * reference to the CRTC.
496 rcar_du_crtc_get(rcrtc);
499 event->pipe = rcrtc->index;
501 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
503 spin_lock_irqsave(&dev->event_lock, flags);
504 rcrtc->event = event;
505 spin_unlock_irqrestore(&dev->event_lock, flags);
509 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
511 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
513 /* We're done, apply the configuration and drop the reference acquired
514 * in .atomic_begin().
516 mutex_lock(&rcrtc->group->planes.lock);
517 rcar_du_crtc_update_planes(crtc);
518 mutex_unlock(&rcrtc->group->planes.lock);
520 rcar_du_crtc_put(rcrtc);
523 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
524 .mode_fixup = rcar_du_crtc_mode_fixup,
525 .disable = rcar_du_crtc_disable,
526 .enable = rcar_du_crtc_enable,
527 .atomic_begin = rcar_du_crtc_atomic_begin,
528 .atomic_flush = rcar_du_crtc_atomic_flush,
531 static const struct drm_crtc_funcs crtc_funcs = {
532 .reset = drm_atomic_helper_crtc_reset,
533 .destroy = drm_crtc_cleanup,
534 .set_config = drm_atomic_helper_set_config,
535 .page_flip = drm_atomic_helper_page_flip,
536 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
537 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
540 /* -----------------------------------------------------------------------------
544 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
546 struct rcar_du_crtc *rcrtc = arg;
547 irqreturn_t ret = IRQ_NONE;
550 status = rcar_du_crtc_read(rcrtc, DSSR);
551 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
553 if (status & DSSR_FRM) {
554 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
555 rcar_du_crtc_finish_page_flip(rcrtc);
562 /* -----------------------------------------------------------------------------
566 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
568 static const unsigned int mmio_offsets[] = {
569 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
572 struct rcar_du_device *rcdu = rgrp->dev;
573 struct platform_device *pdev = to_platform_device(rcdu->dev);
574 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
575 struct drm_crtc *crtc = &rcrtc->crtc;
576 unsigned int irqflags;
583 /* Get the CRTC clock and the optional external clock. */
584 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
585 sprintf(clk_name, "du.%u", index);
591 rcrtc->clock = devm_clk_get(rcdu->dev, name);
592 if (IS_ERR(rcrtc->clock)) {
593 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
594 return PTR_ERR(rcrtc->clock);
597 sprintf(clk_name, "dclkin.%u", index);
598 clk = devm_clk_get(rcdu->dev, clk_name);
600 rcrtc->extclock = clk;
601 } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
602 dev_info(rcdu->dev, "can't get external clock %u\n", index);
603 return -EPROBE_DEFER;
606 init_waitqueue_head(&rcrtc->flip_wait);
609 rcrtc->mmio_offset = mmio_offsets[index];
610 rcrtc->index = index;
611 rcrtc->enabled = false;
613 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc,
614 &rgrp->planes.planes[index % 2].plane,
619 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
621 /* Start with vertical blanking interrupt reporting disabled. */
622 drm_crtc_vblank_off(crtc);
624 /* Register the interrupt handler. */
625 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
626 irq = platform_get_irq(pdev, index);
629 irq = platform_get_irq(pdev, 0);
630 irqflags = IRQF_SHARED;
634 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
638 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
639 dev_name(rcdu->dev), rcrtc);
642 "failed to register IRQ for CRTC %u\n", index);
649 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
652 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
653 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
655 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);