drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23
  24 #include "rcar_du_crtc.h"
  25 #include "rcar_du_drv.h"
  26 #include "rcar_du_kms.h"
  27 #include "rcar_du_plane.h"
  28 #include "rcar_du_regs.h"
  29
  30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  31 {
  32         struct rcar_du_device *rcdu = rcrtc->group->dev;
  33
  34         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  35 }
  36
  37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  38 {
  39         struct rcar_du_device *rcdu = rcrtc->group->dev;
  40
  41         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  42 }
  43
  44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  45 {
  46         struct rcar_du_device *rcdu = rcrtc->group->dev;
  47
  48         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  49                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  50 }
  51
  52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  53 {
  54         struct rcar_du_device *rcdu = rcrtc->group->dev;
  55
  56         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  57                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  58 }
  59
  60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  61                                  u32 clr, u32 set)
  62 {
  63         struct rcar_du_device *rcdu = rcrtc->group->dev;
  64         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  65
  66         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  67 }
  68
  69 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  70 {
  71         int ret;
  72
  73         ret = clk_prepare_enable(rcrtc->clock);
  74         if (ret < 0)
  75                 return ret;
  76
  77         ret = clk_prepare_enable(rcrtc->extclock);
  78         if (ret < 0)
  79                 goto error_clock;
  80
  81         ret = rcar_du_group_get(rcrtc->group);
  82         if (ret < 0)
  83                 goto error_group;
  84
  85         return 0;
  86
  87 error_group:
  88         clk_disable_unprepare(rcrtc->extclock);
  89 error_clock:
  90         clk_disable_unprepare(rcrtc->clock);
  91         return ret;
  92 }
  93
  94 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  95 {
  96         rcar_du_group_put(rcrtc->group);
  97
  98         clk_disable_unprepare(rcrtc->extclock);
  99         clk_disable_unprepare(rcrtc->clock);
 100 }
 101
 102 /* -----------------------------------------------------------------------------
 103  * Hardware Setup
 104  */
 105
 106 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 107 {
 108         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 109         unsigned long mode_clock = mode->clock * 1000;
 110         unsigned long clk;
 111         u32 value;
 112         u32 escr;
 113         u32 div;
 114
 115         /* Compute the clock divisor and select the internal or external dot
 116          * clock based on the requested frequency.
 117          */
 118         clk = clk_get_rate(rcrtc->clock);
 119         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 120         div = clamp(div, 1U, 64U) - 1;
 121         escr = div | ESCR_DCLKSEL_CLKS;
 122
 123         if (rcrtc->extclock) {
 124                 unsigned long extclk;
 125                 unsigned long extrate;
 126                 unsigned long rate;
 127                 u32 extdiv;
 128
 129                 extclk = clk_get_rate(rcrtc->extclock);
 130                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 131                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 132
 133                 rate = clk / (div + 1);
 134                 extrate = extclk / (extdiv + 1);
 135
 136                 if (abs((long)extrate - (long)mode_clock) <
 137                     abs((long)rate - (long)mode_clock)) {
 138                         dev_dbg(rcrtc->group->dev->dev,
 139                                 "crtc%u: using external clock\n", rcrtc->index);
 140                         escr = extdiv | ESCR_DCLKSEL_DCLKIN;
 141                 }
 142         }
 143
 144         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 145                             escr);
 146         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 147
 148         /* Signal polarities */
 149         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 150               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 151               | DSMR_DIPM_DE | DSMR_CSPM;
 152         rcar_du_crtc_write(rcrtc, DSMR, value);
 153
 154         /* Display timings */
 155         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 156         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 157                                         mode->hdisplay - 19);
 158         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 159                                         mode->hsync_start - 1);
 160         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 161
 162         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 163                                         mode->crtc_vsync_end - 2);
 164         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 165                                         mode->crtc_vsync_end +
 166                                         mode->crtc_vdisplay - 2);
 167         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 168                                         mode->crtc_vsync_end +
 169                                         mode->crtc_vsync_start - 1);
 170         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 171
 172         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 173         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 174 }
 175
 176 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 177                                enum rcar_du_output output)
 178 {
 179         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 180         struct rcar_du_device *rcdu = rcrtc->group->dev;
 181
 182         /* Store the route from the CRTC output to the DU output. The DU will be
 183          * configured when starting the CRTC.
 184          */
 185         rcrtc->outputs |= BIT(output);
 186
 187         /* Store RGB routing to DPAD0, the hardware will be configured when
 188          * starting the CRTC.
 189          */
 190         if (output == RCAR_DU_OUTPUT_DPAD0)
 191                 rcdu->dpad0_source = rcrtc->index;
 192 }
 193
 194 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 195 {
 196         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 197         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 198         unsigned int num_planes = 0;
 199         unsigned int prio = 0;
 200         unsigned int i;
 201         u32 dptsr = 0;
 202         u32 dspr = 0;
 203
 204         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 205                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 206                 unsigned int j;
 207
 208                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 209                         continue;
 210
 211                 /* Insert the plane in the sorted planes array. */
 212                 for (j = num_planes++; j > 0; --j) {
 213                         if (planes[j-1]->zpos <= plane->zpos)
 214                                 break;
 215                         planes[j] = planes[j-1];
 216                 }
 217
 218                 planes[j] = plane;
 219                 prio += plane->format->planes * 4;
 220         }
 221
 222         for (i = 0; i < num_planes; ++i) {
 223                 struct rcar_du_plane *plane = planes[i];
 224                 unsigned int index = plane->hwindex;
 225
 226                 prio -= 4;
 227                 dspr |= (index + 1) << prio;
 228                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 229
 230                 if (plane->format->planes == 2) {
 231                         index = (index + 1) % 8;
 232
 233                         prio -= 4;
 234                         dspr |= (index + 1) << prio;
 235                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 236                 }
 237         }
 238
 239         /* Select display timing and dot clock generator 2 for planes associated
 240          * with superposition controller 2.
 241          */
 242         if (rcrtc->index % 2) {
 243                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 244
 245                 /* The DPTSR register is updated when the display controller is
 246                  * stopped. We thus need to restart the DU. Once again, sorry
 247                  * for the flicker. One way to mitigate the issue would be to
 248                  * pre-associate planes with CRTCs (either with a fixed 4/4
 249                  * split, or through a module parameter). Flicker would then
 250                  * occur only if we need to break the pre-association.
 251                  */
 252                 if (value != dptsr) {
 253                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 254                         if (rcrtc->group->used_crtcs)
 255                                 rcar_du_group_restart(rcrtc->group);
 256                 }
 257         }
 258
 259         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 260                             dspr);
 261 }
 262
 263 /* -----------------------------------------------------------------------------
 264  * Page Flip
 265  */
 266
 267 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 268                                    struct drm_file *file)
 269 {
 270         struct drm_pending_vblank_event *event;
 271         struct drm_device *dev = rcrtc->crtc.dev;
 272         unsigned long flags;
 273
 274         /* Destroy the pending vertical blanking event associated with the
 275          * pending page flip, if any, and disable vertical blanking interrupts.
 276          */
 277         spin_lock_irqsave(&dev->event_lock, flags);
 278         event = rcrtc->event;
 279         if (event && event->base.file_priv == file) {
 280                 rcrtc->event = NULL;
 281                 event->base.destroy(&event->base);
 282                 drm_crtc_vblank_put(&rcrtc->crtc);
 283         }
 284         spin_unlock_irqrestore(&dev->event_lock, flags);
 285 }
 286
 287 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 288 {
 289         struct drm_pending_vblank_event *event;
 290         struct drm_device *dev = rcrtc->crtc.dev;
 291         unsigned long flags;
 292
 293         spin_lock_irqsave(&dev->event_lock, flags);
 294         event = rcrtc->event;
 295         rcrtc->event = NULL;
 296         spin_unlock_irqrestore(&dev->event_lock, flags);
 297
 298         if (event == NULL)
 299                 return;
 300
 301         spin_lock_irqsave(&dev->event_lock, flags);
 302         drm_send_vblank_event(dev, rcrtc->index, event);
 303         wake_up(&rcrtc->flip_wait);
 304         spin_unlock_irqrestore(&dev->event_lock, flags);
 305
 306         drm_crtc_vblank_put(&rcrtc->crtc);
 307 }
 308
 309 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 310 {
 311         struct drm_device *dev = rcrtc->crtc.dev;
 312         unsigned long flags;
 313         bool pending;
 314
 315         spin_lock_irqsave(&dev->event_lock, flags);
 316         pending = rcrtc->event != NULL;
 317         spin_unlock_irqrestore(&dev->event_lock, flags);
 318
 319         return pending;
 320 }
 321
 322 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 323 {
 324         struct rcar_du_device *rcdu = rcrtc->group->dev;
 325
 326         if (wait_event_timeout(rcrtc->flip_wait,
 327                                !rcar_du_crtc_page_flip_pending(rcrtc),
 328                                msecs_to_jiffies(50)))
 329                 return;
 330
 331         dev_warn(rcdu->dev, "page flip timeout\n");
 332
 333         rcar_du_crtc_finish_page_flip(rcrtc);
 334 }
 335
 336 /* -----------------------------------------------------------------------------
 337  * Start/Stop and Suspend/Resume
 338  */
 339
 340 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 341 {
 342         struct drm_crtc *crtc = &rcrtc->crtc;
 343         bool interlaced;
 344         unsigned int i;
 345
 346         if (rcrtc->started)
 347                 return;
 348
 349         if (WARN_ON(rcrtc->plane->format == NULL))
 350                 return;
 351
 352         /* Set display off and background to black */
 353         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 354         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 355
 356         /* Configure display timings and output routing */
 357         rcar_du_crtc_set_display_timing(rcrtc);
 358         rcar_du_group_set_routing(rcrtc->group);
 359
 360         /* FIXME: Commit the planes state. This is required here as the CRTC can
 361          * be started from the DPMS and system resume handler, which don't go
 362          * through .atomic_plane_update() and .atomic_flush() to commit plane
 363          * state. Similarly a mode set operation without any update to planes
 364          * will not go through atomic plane configuration either. Additionally,
 365          * given that the plane state atomic commit occurs between CRTC disable
 366          * and enable, the hardware state could also be lost due to runtime PM,
 367          * requiring a full commit here. This will be fixed later after
 368          * switching to atomic updates completely.
 369          */
 370         mutex_lock(&rcrtc->group->planes.lock);
 371         rcar_du_crtc_update_planes(crtc);
 372         mutex_unlock(&rcrtc->group->planes.lock);
 373
 374         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 375                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 376
 377                 if (plane->crtc != crtc || !plane->enabled)
 378                         continue;
 379
 380                 rcar_du_plane_setup(plane);
 381         }
 382
 383         /* Select master sync mode. This enables display operation in master
 384          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 385          * actively driven).
 386          */
 387         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 388         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 389                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 390                              DSYSR_TVM_MASTER);
 391
 392         rcar_du_group_start_stop(rcrtc->group, true);
 393
 394         /* Turn vertical blanking interrupt reporting back on. */
 395         drm_crtc_vblank_on(crtc);
 396
 397         rcrtc->started = true;
 398 }
 399
 400 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 401 {
 402         struct drm_crtc *crtc = &rcrtc->crtc;
 403
 404         if (!rcrtc->started)
 405                 return;
 406
 407         /* Disable vertical blanking interrupt reporting. We first need to wait
 408          * for page flip completion before stopping the CRTC as userspace
 409          * expects page flips to eventually complete.
 410          */
 411         rcar_du_crtc_wait_page_flip(rcrtc);
 412         drm_crtc_vblank_off(crtc);
 413
 414         /* Select switch sync mode. This stops display operation and configures
 415          * the HSYNC and VSYNC signals as inputs.
 416          */
 417         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 418
 419         rcar_du_group_start_stop(rcrtc->group, false);
 420
 421         rcrtc->started = false;
 422 }
 423
 424 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 425 {
 426         rcar_du_crtc_stop(rcrtc);
 427         rcar_du_crtc_put(rcrtc);
 428 }
 429
 430 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 431 {
 432         if (rcrtc->dpms != DRM_MODE_DPMS_ON)
 433                 return;
 434
 435         rcar_du_crtc_get(rcrtc);
 436         rcar_du_crtc_start(rcrtc);
 437 }
 438
 439 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
 440 {
 441         struct drm_crtc *crtc = &rcrtc->crtc;
 442
 443         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 444         rcar_du_plane_update_base(rcrtc->plane);
 445 }
 446
 447 /* -----------------------------------------------------------------------------
 448  * CRTC Functions
 449  */
 450
 451 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
 452 {
 453         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 454
 455         if (mode != DRM_MODE_DPMS_ON)
 456                 mode = DRM_MODE_DPMS_OFF;
 457
 458         if (rcrtc->dpms == mode)
 459                 return;
 460
 461         if (mode == DRM_MODE_DPMS_ON) {
 462                 rcar_du_crtc_get(rcrtc);
 463                 rcar_du_crtc_start(rcrtc);
 464         } else {
 465                 rcar_du_crtc_stop(rcrtc);
 466                 rcar_du_crtc_put(rcrtc);
 467         }
 468
 469         rcrtc->dpms = mode;
 470 }
 471
 472 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 473                                     const struct drm_display_mode *mode,
 474                                     struct drm_display_mode *adjusted_mode)
 475 {
 476         /* TODO Fixup modes */
 477         return true;
 478 }
 479
 480 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
 481 {
 482         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 483
 484         /* We need to access the hardware during mode set, acquire a reference
 485          * to the CRTC.
 486          */
 487         rcar_du_crtc_get(rcrtc);
 488
 489         /* Stop the CRTC, force the DPMS mode to off as a result. */
 490         rcar_du_crtc_stop(rcrtc);
 491
 492         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 493         rcrtc->outputs = 0;
 494 }
 495
 496 static void rcar_du_crtc_mode_set_nofb(struct drm_crtc *crtc)
 497 {
 498         /* No-op. We should configure the display timings here, but as we're
 499          * called with the CRTC disabled clocks might be off, and we thus can't
 500          * access the hardware. Let's just configure everything when enabling
 501          * the CRTC.
 502          */
 503 }
 504
 505 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
 506 {
 507         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 508
 509         /* We're done, restart the CRTC and set the DPMS mode to on. The
 510          * reference to the DU acquired at prepare() time will thus be released
 511          * by the DPMS handler (possibly called by the disable() handler).
 512          */
 513         rcar_du_crtc_start(rcrtc);
 514         rcrtc->dpms = DRM_MODE_DPMS_ON;
 515 }
 516
 517 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 518 {
 519         rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 520 }
 521
 522 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
 523 {
 524         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 525
 526         /* We need to access the hardware during atomic update, acquire a
 527          * reference to the CRTC.
 528          */
 529         rcar_du_crtc_get(rcrtc);
 530 }
 531
 532 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
 533 {
 534         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 535
 536         /* We're done, apply the configuration and drop the reference acquired
 537          * in .atomic_begin().
 538          */
 539         mutex_lock(&rcrtc->group->planes.lock);
 540         rcar_du_crtc_update_planes(crtc);
 541         mutex_unlock(&rcrtc->group->planes.lock);
 542
 543         rcar_du_crtc_put(rcrtc);
 544 }
 545
 546 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 547         .dpms = rcar_du_crtc_dpms,
 548         .mode_fixup = rcar_du_crtc_mode_fixup,
 549         .prepare = rcar_du_crtc_mode_prepare,
 550         .commit = rcar_du_crtc_mode_commit,
 551         .mode_set = drm_helper_crtc_mode_set,
 552         .mode_set_nofb = rcar_du_crtc_mode_set_nofb,
 553         .mode_set_base = drm_helper_crtc_mode_set_base,
 554         .disable = rcar_du_crtc_disable,
 555         .atomic_begin = rcar_du_crtc_atomic_begin,
 556         .atomic_flush = rcar_du_crtc_atomic_flush,
 557 };
 558
 559 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
 560                                   struct drm_framebuffer *fb,
 561                                   struct drm_pending_vblank_event *event,
 562                                   uint32_t page_flip_flags)
 563 {
 564         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 565         struct drm_device *dev = rcrtc->crtc.dev;
 566         unsigned long flags;
 567
 568         spin_lock_irqsave(&dev->event_lock, flags);
 569         if (rcrtc->event != NULL) {
 570                 spin_unlock_irqrestore(&dev->event_lock, flags);
 571                 return -EBUSY;
 572         }
 573         spin_unlock_irqrestore(&dev->event_lock, flags);
 574
 575         crtc->primary->fb = fb;
 576         rcar_du_crtc_update_base(rcrtc);
 577
 578         if (event) {
 579                 event->pipe = rcrtc->index;
 580                 drm_crtc_vblank_get(crtc);
 581                 spin_lock_irqsave(&dev->event_lock, flags);
 582                 rcrtc->event = event;
 583                 spin_unlock_irqrestore(&dev->event_lock, flags);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static const struct drm_crtc_funcs crtc_funcs = {
 590         .destroy = drm_crtc_cleanup,
 591         .set_config = drm_crtc_helper_set_config,
 592         .page_flip = rcar_du_crtc_page_flip,
 593 };
 594
 595 /* -----------------------------------------------------------------------------
 596  * Interrupt Handling
 597  */
 598
 599 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 600 {
 601         struct rcar_du_crtc *rcrtc = arg;
 602         irqreturn_t ret = IRQ_NONE;
 603         u32 status;
 604
 605         status = rcar_du_crtc_read(rcrtc, DSSR);
 606         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 607
 608         if (status & DSSR_FRM) {
 609                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 610                 rcar_du_crtc_finish_page_flip(rcrtc);
 611                 ret = IRQ_HANDLED;
 612         }
 613
 614         return ret;
 615 }
 616
 617 /* -----------------------------------------------------------------------------
 618  * Initialization
 619  */
 620
 621 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 622 {
 623         static const unsigned int mmio_offsets[] = {
 624                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 625         };
 626
 627         struct rcar_du_device *rcdu = rgrp->dev;
 628         struct platform_device *pdev = to_platform_device(rcdu->dev);
 629         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 630         struct drm_crtc *crtc = &rcrtc->crtc;
 631         unsigned int irqflags;
 632         struct clk *clk;
 633         char clk_name[9];
 634         char *name;
 635         int irq;
 636         int ret;
 637
 638         /* Get the CRTC clock and the optional external clock. */
 639         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 640                 sprintf(clk_name, "du.%u", index);
 641                 name = clk_name;
 642         } else {
 643                 name = NULL;
 644         }
 645
 646         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 647         if (IS_ERR(rcrtc->clock)) {
 648                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 649                 return PTR_ERR(rcrtc->clock);
 650         }
 651
 652         sprintf(clk_name, "dclkin.%u", index);
 653         clk = devm_clk_get(rcdu->dev, clk_name);
 654         if (!IS_ERR(clk)) {
 655                 rcrtc->extclock = clk;
 656         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 657                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 658                 return -EPROBE_DEFER;
 659         }
 660
 661         init_waitqueue_head(&rcrtc->flip_wait);
 662
 663         rcrtc->group = rgrp;
 664         rcrtc->mmio_offset = mmio_offsets[index];
 665         rcrtc->index = index;
 666         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 667         rcrtc->plane = &rgrp->planes.planes[index % 2];
 668
 669         rcrtc->plane->crtc = crtc;
 670
 671         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, &rcrtc->plane->plane,
 672                                         NULL, &crtc_funcs);
 673         if (ret < 0)
 674                 return ret;
 675
 676         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 677
 678         /* Start with vertical blanking interrupt reporting disabled. */
 679         drm_crtc_vblank_off(crtc);
 680
 681         /* Register the interrupt handler. */
 682         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 683                 irq = platform_get_irq(pdev, index);
 684                 irqflags = 0;
 685         } else {
 686                 irq = platform_get_irq(pdev, 0);
 687                 irqflags = IRQF_SHARED;
 688         }
 689
 690         if (irq < 0) {
 691                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 692                 return irq;
 693         }
 694
 695         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 696                                dev_name(rcdu->dev), rcrtc);
 697         if (ret < 0) {
 698                 dev_err(rcdu->dev,
 699                         "failed to register IRQ for CRTC %u\n", index);
 700                 return ret;
 701         }
 702
 703         return 0;
 704 }
 705
 706 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 707 {
 708         if (enable) {
 709                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 710                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 711         } else {
 712                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 713         }
 714 }