2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/mutex.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
22 #include <drm/drm_plane_helper.h>
24 #include "rcar_du_crtc.h"
25 #include "rcar_du_drv.h"
26 #include "rcar_du_kms.h"
27 #include "rcar_du_plane.h"
28 #include "rcar_du_regs.h"
30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
32 struct rcar_du_device *rcdu = rcrtc->group->dev;
34 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
39 struct rcar_du_device *rcdu = rcrtc->group->dev;
41 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
46 struct rcar_du_device *rcdu = rcrtc->group->dev;
48 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
49 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
54 struct rcar_du_device *rcdu = rcrtc->group->dev;
56 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
57 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
63 struct rcar_du_device *rcdu = rcrtc->group->dev;
64 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
66 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
69 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
73 ret = clk_prepare_enable(rcrtc->clock);
77 ret = clk_prepare_enable(rcrtc->extclock);
81 ret = rcar_du_group_get(rcrtc->group);
88 clk_disable_unprepare(rcrtc->extclock);
90 clk_disable_unprepare(rcrtc->clock);
94 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
96 rcar_du_group_put(rcrtc->group);
98 clk_disable_unprepare(rcrtc->extclock);
99 clk_disable_unprepare(rcrtc->clock);
102 /* -----------------------------------------------------------------------------
106 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
108 const struct drm_display_mode *mode = &rcrtc->crtc.mode;
109 unsigned long mode_clock = mode->clock * 1000;
115 /* Compute the clock divisor and select the internal or external dot
116 * clock based on the requested frequency.
118 clk = clk_get_rate(rcrtc->clock);
119 div = DIV_ROUND_CLOSEST(clk, mode_clock);
120 div = clamp(div, 1U, 64U) - 1;
121 escr = div | ESCR_DCLKSEL_CLKS;
123 if (rcrtc->extclock) {
124 unsigned long extclk;
125 unsigned long extrate;
129 extclk = clk_get_rate(rcrtc->extclock);
130 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
131 extdiv = clamp(extdiv, 1U, 64U) - 1;
133 rate = clk / (div + 1);
134 extrate = extclk / (extdiv + 1);
136 if (abs((long)extrate - (long)mode_clock) <
137 abs((long)rate - (long)mode_clock)) {
138 dev_dbg(rcrtc->group->dev->dev,
139 "crtc%u: using external clock\n", rcrtc->index);
140 escr = extdiv | ESCR_DCLKSEL_DCLKIN;
144 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
146 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
148 /* Signal polarities */
149 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
150 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
151 | DSMR_DIPM_DE | DSMR_CSPM;
152 rcar_du_crtc_write(rcrtc, DSMR, value);
154 /* Display timings */
155 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
156 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
157 mode->hdisplay - 19);
158 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
159 mode->hsync_start - 1);
160 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
162 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
163 mode->crtc_vsync_end - 2);
164 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
165 mode->crtc_vsync_end +
166 mode->crtc_vdisplay - 2);
167 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
168 mode->crtc_vsync_end +
169 mode->crtc_vsync_start - 1);
170 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
172 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
173 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
176 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
177 enum rcar_du_output output)
179 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
180 struct rcar_du_device *rcdu = rcrtc->group->dev;
182 /* Store the route from the CRTC output to the DU output. The DU will be
183 * configured when starting the CRTC.
185 rcrtc->outputs |= BIT(output);
187 /* Store RGB routing to DPAD0, the hardware will be configured when
190 if (output == RCAR_DU_OUTPUT_DPAD0)
191 rcdu->dpad0_source = rcrtc->index;
194 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
196 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
197 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
198 unsigned int num_planes = 0;
199 unsigned int prio = 0;
204 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
205 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
208 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
211 /* Insert the plane in the sorted planes array. */
212 for (j = num_planes++; j > 0; --j) {
213 if (planes[j-1]->zpos <= plane->zpos)
215 planes[j] = planes[j-1];
219 prio += plane->format->planes * 4;
222 for (i = 0; i < num_planes; ++i) {
223 struct rcar_du_plane *plane = planes[i];
224 unsigned int index = plane->hwindex;
227 dspr |= (index + 1) << prio;
228 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
230 if (plane->format->planes == 2) {
231 index = (index + 1) % 8;
234 dspr |= (index + 1) << prio;
235 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
239 /* Select display timing and dot clock generator 2 for planes associated
240 * with superposition controller 2.
242 if (rcrtc->index % 2) {
243 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
245 /* The DPTSR register is updated when the display controller is
246 * stopped. We thus need to restart the DU. Once again, sorry
247 * for the flicker. One way to mitigate the issue would be to
248 * pre-associate planes with CRTCs (either with a fixed 4/4
249 * split, or through a module parameter). Flicker would then
250 * occur only if we need to break the pre-association.
252 if (value != dptsr) {
253 rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
254 if (rcrtc->group->used_crtcs)
255 rcar_du_group_restart(rcrtc->group);
259 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
263 /* -----------------------------------------------------------------------------
267 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
268 struct drm_file *file)
270 struct drm_pending_vblank_event *event;
271 struct drm_device *dev = rcrtc->crtc.dev;
274 /* Destroy the pending vertical blanking event associated with the
275 * pending page flip, if any, and disable vertical blanking interrupts.
277 spin_lock_irqsave(&dev->event_lock, flags);
278 event = rcrtc->event;
279 if (event && event->base.file_priv == file) {
281 event->base.destroy(&event->base);
282 drm_crtc_vblank_put(&rcrtc->crtc);
284 spin_unlock_irqrestore(&dev->event_lock, flags);
287 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
289 struct drm_pending_vblank_event *event;
290 struct drm_device *dev = rcrtc->crtc.dev;
293 spin_lock_irqsave(&dev->event_lock, flags);
294 event = rcrtc->event;
296 spin_unlock_irqrestore(&dev->event_lock, flags);
301 spin_lock_irqsave(&dev->event_lock, flags);
302 drm_send_vblank_event(dev, rcrtc->index, event);
303 wake_up(&rcrtc->flip_wait);
304 spin_unlock_irqrestore(&dev->event_lock, flags);
306 drm_crtc_vblank_put(&rcrtc->crtc);
309 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
311 struct drm_device *dev = rcrtc->crtc.dev;
315 spin_lock_irqsave(&dev->event_lock, flags);
316 pending = rcrtc->event != NULL;
317 spin_unlock_irqrestore(&dev->event_lock, flags);
322 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
324 struct rcar_du_device *rcdu = rcrtc->group->dev;
326 if (wait_event_timeout(rcrtc->flip_wait,
327 !rcar_du_crtc_page_flip_pending(rcrtc),
328 msecs_to_jiffies(50)))
331 dev_warn(rcdu->dev, "page flip timeout\n");
333 rcar_du_crtc_finish_page_flip(rcrtc);
336 /* -----------------------------------------------------------------------------
337 * Start/Stop and Suspend/Resume
340 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
342 struct drm_crtc *crtc = &rcrtc->crtc;
349 if (WARN_ON(rcrtc->plane->format == NULL))
352 /* Set display off and background to black */
353 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
354 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
356 /* Configure display timings and output routing */
357 rcar_du_crtc_set_display_timing(rcrtc);
358 rcar_du_group_set_routing(rcrtc->group);
360 /* FIXME: Commit the planes state. This is required here as the CRTC can
361 * be started from the DPMS and system resume handler, which don't go
362 * through .atomic_plane_update() and .atomic_flush() to commit plane
363 * state. Similarly a mode set operation without any update to planes
364 * will not go through atomic plane configuration either. Additionally,
365 * given that the plane state atomic commit occurs between CRTC disable
366 * and enable, the hardware state could also be lost due to runtime PM,
367 * requiring a full commit here. This will be fixed later after
368 * switching to atomic updates completely.
370 mutex_lock(&rcrtc->group->planes.lock);
371 rcrtc->plane->enabled = true;
372 rcar_du_crtc_update_planes(crtc);
373 mutex_unlock(&rcrtc->group->planes.lock);
375 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
376 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
378 if (plane->crtc != crtc || !plane->enabled)
381 rcar_du_plane_setup(plane);
384 /* Select master sync mode. This enables display operation in master
385 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
388 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
389 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
390 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
393 rcar_du_group_start_stop(rcrtc->group, true);
395 /* Turn vertical blanking interrupt reporting back on. */
396 drm_crtc_vblank_on(crtc);
398 rcrtc->started = true;
401 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
403 struct drm_crtc *crtc = &rcrtc->crtc;
408 /* Disable vertical blanking interrupt reporting. We first need to wait
409 * for page flip completion before stopping the CRTC as userspace
410 * expects page flips to eventually complete.
412 rcar_du_crtc_wait_page_flip(rcrtc);
413 drm_crtc_vblank_off(crtc);
415 mutex_lock(&rcrtc->group->planes.lock);
416 rcrtc->plane->enabled = false;
417 rcar_du_crtc_update_planes(crtc);
418 mutex_unlock(&rcrtc->group->planes.lock);
420 /* Select switch sync mode. This stops display operation and configures
421 * the HSYNC and VSYNC signals as inputs.
423 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
425 rcar_du_group_start_stop(rcrtc->group, false);
427 rcrtc->started = false;
430 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
432 rcar_du_crtc_stop(rcrtc);
433 rcar_du_crtc_put(rcrtc);
436 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
438 if (rcrtc->dpms != DRM_MODE_DPMS_ON)
441 rcar_du_crtc_get(rcrtc);
442 rcar_du_crtc_start(rcrtc);
445 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
447 struct drm_crtc *crtc = &rcrtc->crtc;
449 rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
450 rcar_du_plane_update_base(rcrtc->plane);
453 /* -----------------------------------------------------------------------------
457 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
459 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
461 if (mode != DRM_MODE_DPMS_ON)
462 mode = DRM_MODE_DPMS_OFF;
464 if (rcrtc->dpms == mode)
467 if (mode == DRM_MODE_DPMS_ON) {
468 rcar_du_crtc_get(rcrtc);
469 rcar_du_crtc_start(rcrtc);
471 rcar_du_crtc_stop(rcrtc);
472 rcar_du_crtc_put(rcrtc);
478 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
479 const struct drm_display_mode *mode,
480 struct drm_display_mode *adjusted_mode)
482 /* TODO Fixup modes */
486 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
488 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
490 /* We need to access the hardware during mode set, acquire a reference
493 rcar_du_crtc_get(rcrtc);
495 /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
498 rcar_du_crtc_stop(rcrtc);
499 rcar_du_plane_release(rcrtc->plane);
501 rcrtc->dpms = DRM_MODE_DPMS_OFF;
504 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
505 struct drm_display_mode *mode,
506 struct drm_display_mode *adjusted_mode,
508 struct drm_framebuffer *old_fb)
510 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
511 struct rcar_du_device *rcdu = rcrtc->group->dev;
512 const struct rcar_du_format_info *format;
515 format = rcar_du_format_info(crtc->primary->fb->pixel_format);
516 if (format == NULL) {
517 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
518 crtc->primary->fb->pixel_format);
523 ret = rcar_du_plane_reserve(rcrtc->plane, format);
527 rcrtc->plane->format = format;
529 rcrtc->plane->src_x = x;
530 rcrtc->plane->src_y = y;
531 rcrtc->plane->width = mode->hdisplay;
532 rcrtc->plane->height = mode->vdisplay;
534 rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
541 /* There's no rollback/abort operation to clean up in case of error. We
542 * thus need to release the reference to the CRTC acquired in prepare()
545 rcar_du_crtc_put(rcrtc);
549 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
551 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
553 /* We're done, restart the CRTC and set the DPMS mode to on. The
554 * reference to the DU acquired at prepare() time will thus be released
555 * by the DPMS handler (possibly called by the disable() handler).
557 rcar_du_crtc_start(rcrtc);
558 rcrtc->dpms = DRM_MODE_DPMS_ON;
561 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
562 struct drm_framebuffer *old_fb)
564 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
566 rcrtc->plane->src_x = x;
567 rcrtc->plane->src_y = y;
569 rcar_du_crtc_update_base(rcrtc);
574 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
576 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
578 rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
579 rcar_du_plane_release(rcrtc->plane);
582 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
584 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
586 /* We need to access the hardware during atomic update, acquire a
587 * reference to the CRTC.
589 rcar_du_crtc_get(rcrtc);
592 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
594 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
596 /* We're done, apply the configuration and drop the reference acquired
597 * in .atomic_begin().
599 mutex_lock(&rcrtc->group->planes.lock);
600 rcar_du_crtc_update_planes(crtc);
601 mutex_unlock(&rcrtc->group->planes.lock);
603 rcar_du_crtc_put(rcrtc);
606 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
607 .dpms = rcar_du_crtc_dpms,
608 .mode_fixup = rcar_du_crtc_mode_fixup,
609 .prepare = rcar_du_crtc_mode_prepare,
610 .commit = rcar_du_crtc_mode_commit,
611 .mode_set = rcar_du_crtc_mode_set,
612 .mode_set_base = rcar_du_crtc_mode_set_base,
613 .disable = rcar_du_crtc_disable,
614 .atomic_begin = rcar_du_crtc_atomic_begin,
615 .atomic_flush = rcar_du_crtc_atomic_flush,
618 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
619 struct drm_framebuffer *fb,
620 struct drm_pending_vblank_event *event,
621 uint32_t page_flip_flags)
623 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
624 struct drm_device *dev = rcrtc->crtc.dev;
627 spin_lock_irqsave(&dev->event_lock, flags);
628 if (rcrtc->event != NULL) {
629 spin_unlock_irqrestore(&dev->event_lock, flags);
632 spin_unlock_irqrestore(&dev->event_lock, flags);
634 crtc->primary->fb = fb;
635 rcar_du_crtc_update_base(rcrtc);
638 event->pipe = rcrtc->index;
639 drm_crtc_vblank_get(crtc);
640 spin_lock_irqsave(&dev->event_lock, flags);
641 rcrtc->event = event;
642 spin_unlock_irqrestore(&dev->event_lock, flags);
648 static const struct drm_crtc_funcs crtc_funcs = {
649 .destroy = drm_crtc_cleanup,
650 .set_config = drm_crtc_helper_set_config,
651 .page_flip = rcar_du_crtc_page_flip,
654 /* -----------------------------------------------------------------------------
658 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
660 struct rcar_du_crtc *rcrtc = arg;
661 irqreturn_t ret = IRQ_NONE;
664 status = rcar_du_crtc_read(rcrtc, DSSR);
665 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
667 if (status & DSSR_FRM) {
668 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
669 rcar_du_crtc_finish_page_flip(rcrtc);
676 /* -----------------------------------------------------------------------------
680 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
682 static const unsigned int mmio_offsets[] = {
683 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
686 struct rcar_du_device *rcdu = rgrp->dev;
687 struct platform_device *pdev = to_platform_device(rcdu->dev);
688 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
689 struct drm_crtc *crtc = &rcrtc->crtc;
690 unsigned int irqflags;
697 /* Get the CRTC clock and the optional external clock. */
698 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
699 sprintf(clk_name, "du.%u", index);
705 rcrtc->clock = devm_clk_get(rcdu->dev, name);
706 if (IS_ERR(rcrtc->clock)) {
707 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
708 return PTR_ERR(rcrtc->clock);
711 sprintf(clk_name, "dclkin.%u", index);
712 clk = devm_clk_get(rcdu->dev, clk_name);
714 rcrtc->extclock = clk;
715 } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
716 dev_info(rcdu->dev, "can't get external clock %u\n", index);
717 return -EPROBE_DEFER;
720 init_waitqueue_head(&rcrtc->flip_wait);
723 rcrtc->mmio_offset = mmio_offsets[index];
724 rcrtc->index = index;
725 rcrtc->dpms = DRM_MODE_DPMS_OFF;
726 rcrtc->plane = &rgrp->planes.planes[index % 2];
728 rcrtc->plane->crtc = crtc;
730 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, &rcrtc->plane->plane,
735 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
737 /* Start with vertical blanking interrupt reporting disabled. */
738 drm_crtc_vblank_off(crtc);
740 /* Register the interrupt handler. */
741 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
742 irq = platform_get_irq(pdev, index);
745 irq = platform_get_irq(pdev, 0);
746 irqflags = IRQF_SHARED;
750 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
754 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
755 dev_name(rcdu->dev), rcrtc);
758 "failed to register IRQ for CRTC %u\n", index);
765 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
768 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
769 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
771 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);