drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_fb_cma_helper.h>
  23 #include <drm/drm_gem_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "rcar_du_crtc.h"
  27 #include "rcar_du_drv.h"
  28 #include "rcar_du_kms.h"
  29 #include "rcar_du_plane.h"
  30 #include "rcar_du_regs.h"
  31
  32 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  33 {
  34         struct rcar_du_device *rcdu = rcrtc->group->dev;
  35
  36         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  37 }
  38
  39 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  40 {
  41         struct rcar_du_device *rcdu = rcrtc->group->dev;
  42
  43         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  44 }
  45
  46 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  47 {
  48         struct rcar_du_device *rcdu = rcrtc->group->dev;
  49
  50         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  51                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  52 }
  53
  54 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  55 {
  56         struct rcar_du_device *rcdu = rcrtc->group->dev;
  57
  58         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  59                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  60 }
  61
  62 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  63                                  u32 clr, u32 set)
  64 {
  65         struct rcar_du_device *rcdu = rcrtc->group->dev;
  66         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  67
  68         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  69 }
  70
  71 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  72 {
  73         int ret;
  74
  75         ret = clk_prepare_enable(rcrtc->clock);
  76         if (ret < 0)
  77                 return ret;
  78
  79         ret = clk_prepare_enable(rcrtc->extclock);
  80         if (ret < 0)
  81                 goto error_clock;
  82
  83         ret = rcar_du_group_get(rcrtc->group);
  84         if (ret < 0)
  85                 goto error_group;
  86
  87         return 0;
  88
  89 error_group:
  90         clk_disable_unprepare(rcrtc->extclock);
  91 error_clock:
  92         clk_disable_unprepare(rcrtc->clock);
  93         return ret;
  94 }
  95
  96 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  97 {
  98         rcar_du_group_put(rcrtc->group);
  99
 100         clk_disable_unprepare(rcrtc->extclock);
 101         clk_disable_unprepare(rcrtc->clock);
 102 }
 103
 104 /* -----------------------------------------------------------------------------
 105  * Hardware Setup
 106  */
 107
 108 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 109 {
 110         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 111         unsigned long mode_clock = mode->clock * 1000;
 112         unsigned long clk;
 113         u32 value;
 114         u32 escr;
 115         u32 div;
 116
 117         /* Compute the clock divisor and select the internal or external dot
 118          * clock based on the requested frequency.
 119          */
 120         clk = clk_get_rate(rcrtc->clock);
 121         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 122         div = clamp(div, 1U, 64U) - 1;
 123         escr = div | ESCR_DCLKSEL_CLKS;
 124
 125         if (rcrtc->extclock) {
 126                 unsigned long extclk;
 127                 unsigned long extrate;
 128                 unsigned long rate;
 129                 u32 extdiv;
 130
 131                 extclk = clk_get_rate(rcrtc->extclock);
 132                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 133                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 134
 135                 rate = clk / (div + 1);
 136                 extrate = extclk / (extdiv + 1);
 137
 138                 if (abs((long)extrate - (long)mode_clock) <
 139                     abs((long)rate - (long)mode_clock)) {
 140                         dev_dbg(rcrtc->group->dev->dev,
 141                                 "crtc%u: using external clock\n", rcrtc->index);
 142                         escr = extdiv | ESCR_DCLKSEL_DCLKIN;
 143                 }
 144         }
 145
 146         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 147                             escr);
 148         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 149
 150         /* Signal polarities */
 151         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 152               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 153               | DSMR_DIPM_DE | DSMR_CSPM;
 154         rcar_du_crtc_write(rcrtc, DSMR, value);
 155
 156         /* Display timings */
 157         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 158         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 159                                         mode->hdisplay - 19);
 160         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 161                                         mode->hsync_start - 1);
 162         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 163
 164         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 165                                         mode->crtc_vsync_end - 2);
 166         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 167                                         mode->crtc_vsync_end +
 168                                         mode->crtc_vdisplay - 2);
 169         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 170                                         mode->crtc_vsync_end +
 171                                         mode->crtc_vsync_start - 1);
 172         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 173
 174         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 175         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 176 }
 177
 178 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 179                                enum rcar_du_output output)
 180 {
 181         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 182         struct rcar_du_device *rcdu = rcrtc->group->dev;
 183
 184         /* Store the route from the CRTC output to the DU output. The DU will be
 185          * configured when starting the CRTC.
 186          */
 187         rcrtc->outputs |= BIT(output);
 188
 189         /* Store RGB routing to DPAD0, the hardware will be configured when
 190          * starting the CRTC.
 191          */
 192         if (output == RCAR_DU_OUTPUT_DPAD0)
 193                 rcdu->dpad0_source = rcrtc->index;
 194 }
 195
 196 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 197 {
 198         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 199         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 200         unsigned int num_planes = 0;
 201         unsigned int prio = 0;
 202         unsigned int i;
 203         u32 dptsr = 0;
 204         u32 dspr = 0;
 205
 206         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 207                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 208                 unsigned int j;
 209
 210                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 211                         continue;
 212
 213                 /* Insert the plane in the sorted planes array. */
 214                 for (j = num_planes++; j > 0; --j) {
 215                         if (planes[j-1]->zpos <= plane->zpos)
 216                                 break;
 217                         planes[j] = planes[j-1];
 218                 }
 219
 220                 planes[j] = plane;
 221                 prio += plane->format->planes * 4;
 222         }
 223
 224         for (i = 0; i < num_planes; ++i) {
 225                 struct rcar_du_plane *plane = planes[i];
 226                 unsigned int index = plane->hwindex;
 227
 228                 prio -= 4;
 229                 dspr |= (index + 1) << prio;
 230                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 231
 232                 if (plane->format->planes == 2) {
 233                         index = (index + 1) % 8;
 234
 235                         prio -= 4;
 236                         dspr |= (index + 1) << prio;
 237                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 238                 }
 239         }
 240
 241         /* Select display timing and dot clock generator 2 for planes associated
 242          * with superposition controller 2.
 243          */
 244         if (rcrtc->index % 2) {
 245                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 246
 247                 /* The DPTSR register is updated when the display controller is
 248                  * stopped. We thus need to restart the DU. Once again, sorry
 249                  * for the flicker. One way to mitigate the issue would be to
 250                  * pre-associate planes with CRTCs (either with a fixed 4/4
 251                  * split, or through a module parameter). Flicker would then
 252                  * occur only if we need to break the pre-association.
 253                  */
 254                 if (value != dptsr) {
 255                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 256                         if (rcrtc->group->used_crtcs)
 257                                 rcar_du_group_restart(rcrtc->group);
 258                 }
 259         }
 260
 261         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 262                             dspr);
 263 }
 264
 265 /* -----------------------------------------------------------------------------
 266  * Page Flip
 267  */
 268
 269 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 270                                    struct drm_file *file)
 271 {
 272         struct drm_pending_vblank_event *event;
 273         struct drm_device *dev = rcrtc->crtc.dev;
 274         unsigned long flags;
 275
 276         /* Destroy the pending vertical blanking event associated with the
 277          * pending page flip, if any, and disable vertical blanking interrupts.
 278          */
 279         spin_lock_irqsave(&dev->event_lock, flags);
 280         event = rcrtc->event;
 281         if (event && event->base.file_priv == file) {
 282                 rcrtc->event = NULL;
 283                 event->base.destroy(&event->base);
 284                 drm_crtc_vblank_put(&rcrtc->crtc);
 285         }
 286         spin_unlock_irqrestore(&dev->event_lock, flags);
 287 }
 288
 289 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 290 {
 291         struct drm_pending_vblank_event *event;
 292         struct drm_device *dev = rcrtc->crtc.dev;
 293         unsigned long flags;
 294
 295         spin_lock_irqsave(&dev->event_lock, flags);
 296         event = rcrtc->event;
 297         rcrtc->event = NULL;
 298         spin_unlock_irqrestore(&dev->event_lock, flags);
 299
 300         if (event == NULL)
 301                 return;
 302
 303         spin_lock_irqsave(&dev->event_lock, flags);
 304         drm_send_vblank_event(dev, rcrtc->index, event);
 305         wake_up(&rcrtc->flip_wait);
 306         spin_unlock_irqrestore(&dev->event_lock, flags);
 307
 308         drm_crtc_vblank_put(&rcrtc->crtc);
 309 }
 310
 311 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 312 {
 313         struct drm_device *dev = rcrtc->crtc.dev;
 314         unsigned long flags;
 315         bool pending;
 316
 317         spin_lock_irqsave(&dev->event_lock, flags);
 318         pending = rcrtc->event != NULL;
 319         spin_unlock_irqrestore(&dev->event_lock, flags);
 320
 321         return pending;
 322 }
 323
 324 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 325 {
 326         struct rcar_du_device *rcdu = rcrtc->group->dev;
 327
 328         if (wait_event_timeout(rcrtc->flip_wait,
 329                                !rcar_du_crtc_page_flip_pending(rcrtc),
 330                                msecs_to_jiffies(50)))
 331                 return;
 332
 333         dev_warn(rcdu->dev, "page flip timeout\n");
 334
 335         rcar_du_crtc_finish_page_flip(rcrtc);
 336 }
 337
 338 /* -----------------------------------------------------------------------------
 339  * Start/Stop and Suspend/Resume
 340  */
 341
 342 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 343 {
 344         struct drm_crtc *crtc = &rcrtc->crtc;
 345         bool interlaced;
 346         unsigned int i;
 347
 348         if (rcrtc->started)
 349                 return;
 350
 351         if (WARN_ON(rcrtc->plane->format == NULL))
 352                 return;
 353
 354         /* Set display off and background to black */
 355         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 356         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 357
 358         /* Configure display timings and output routing */
 359         rcar_du_crtc_set_display_timing(rcrtc);
 360         rcar_du_group_set_routing(rcrtc->group);
 361
 362         /* FIXME: Commit the planes state. This is required here as the CRTC can
 363          * be started from the DPMS and system resume handler, which don't go
 364          * through .atomic_plane_update() and .atomic_flush() to commit plane
 365          * state. Additionally, given that the plane state atomic commit occurs
 366          * between CRTC disable and enable, the hardware state could also be
 367          * lost due to runtime PM, requiring a full commit here. This will be
 368          * fixed later after switching to atomic updates completely.
 369          */
 370         mutex_lock(&rcrtc->group->planes.lock);
 371         rcar_du_crtc_update_planes(crtc);
 372         mutex_unlock(&rcrtc->group->planes.lock);
 373
 374         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 375                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 376
 377                 if (plane->crtc != crtc || !plane->enabled)
 378                         continue;
 379
 380                 rcar_du_plane_setup(plane);
 381         }
 382
 383         /* Select master sync mode. This enables display operation in master
 384          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 385          * actively driven).
 386          */
 387         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 388         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 389                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 390                              DSYSR_TVM_MASTER);
 391
 392         rcar_du_group_start_stop(rcrtc->group, true);
 393
 394         /* Turn vertical blanking interrupt reporting back on. */
 395         drm_crtc_vblank_on(crtc);
 396
 397         rcrtc->started = true;
 398 }
 399
 400 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 401 {
 402         struct drm_crtc *crtc = &rcrtc->crtc;
 403
 404         if (!rcrtc->started)
 405                 return;
 406
 407         /* Disable vertical blanking interrupt reporting. We first need to wait
 408          * for page flip completion before stopping the CRTC as userspace
 409          * expects page flips to eventually complete.
 410          */
 411         rcar_du_crtc_wait_page_flip(rcrtc);
 412         drm_crtc_vblank_off(crtc);
 413
 414         /* Select switch sync mode. This stops display operation and configures
 415          * the HSYNC and VSYNC signals as inputs.
 416          */
 417         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 418
 419         rcar_du_group_start_stop(rcrtc->group, false);
 420
 421         rcrtc->started = false;
 422 }
 423
 424 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 425 {
 426         rcar_du_crtc_stop(rcrtc);
 427         rcar_du_crtc_put(rcrtc);
 428 }
 429
 430 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 431 {
 432         if (!rcrtc->enabled)
 433                 return;
 434
 435         rcar_du_crtc_get(rcrtc);
 436         rcar_du_crtc_start(rcrtc);
 437 }
 438
 439 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
 440 {
 441         struct drm_crtc *crtc = &rcrtc->crtc;
 442
 443         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 444         rcar_du_plane_update_base(rcrtc->plane);
 445 }
 446
 447 /* -----------------------------------------------------------------------------
 448  * CRTC Functions
 449  */
 450
 451 static void rcar_du_crtc_enable(struct drm_crtc *crtc)
 452 {
 453         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 454
 455         if (rcrtc->enabled)
 456                 return;
 457
 458         rcar_du_crtc_get(rcrtc);
 459         rcar_du_crtc_start(rcrtc);
 460
 461         rcrtc->enabled = true;
 462 }
 463
 464 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 465 {
 466         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 467
 468         if (!rcrtc->enabled)
 469                 return;
 470
 471         rcar_du_crtc_stop(rcrtc);
 472         rcar_du_crtc_put(rcrtc);
 473
 474         rcrtc->enabled = false;
 475         rcrtc->outputs = 0;
 476 }
 477
 478 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
 479 {
 480         if (mode == DRM_MODE_DPMS_ON)
 481                 rcar_du_crtc_enable(crtc);
 482         else
 483                 rcar_du_crtc_disable(crtc);
 484 }
 485
 486 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 487                                     const struct drm_display_mode *mode,
 488                                     struct drm_display_mode *adjusted_mode)
 489 {
 490         /* TODO Fixup modes */
 491         return true;
 492 }
 493
 494 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
 495 {
 496         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 497
 498         /* We need to access the hardware during atomic update, acquire a
 499          * reference to the CRTC.
 500          */
 501         rcar_du_crtc_get(rcrtc);
 502 }
 503
 504 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
 505 {
 506         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 507
 508         /* We're done, apply the configuration and drop the reference acquired
 509          * in .atomic_begin().
 510          */
 511         mutex_lock(&rcrtc->group->planes.lock);
 512         rcar_du_crtc_update_planes(crtc);
 513         mutex_unlock(&rcrtc->group->planes.lock);
 514
 515         rcar_du_crtc_put(rcrtc);
 516 }
 517
 518 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 519         .dpms = rcar_du_crtc_dpms,
 520         .mode_fixup = rcar_du_crtc_mode_fixup,
 521         .disable = rcar_du_crtc_disable,
 522         .enable = rcar_du_crtc_enable,
 523         .atomic_begin = rcar_du_crtc_atomic_begin,
 524         .atomic_flush = rcar_du_crtc_atomic_flush,
 525 };
 526
 527 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
 528                                   struct drm_framebuffer *fb,
 529                                   struct drm_pending_vblank_event *event,
 530                                   uint32_t page_flip_flags)
 531 {
 532         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 533         struct drm_device *dev = rcrtc->crtc.dev;
 534         unsigned long flags;
 535
 536         spin_lock_irqsave(&dev->event_lock, flags);
 537         if (rcrtc->event != NULL) {
 538                 spin_unlock_irqrestore(&dev->event_lock, flags);
 539                 return -EBUSY;
 540         }
 541         spin_unlock_irqrestore(&dev->event_lock, flags);
 542
 543         drm_atomic_set_fb_for_plane(crtc->primary->state, fb);
 544
 545         crtc->primary->fb = fb;
 546         rcar_du_crtc_update_base(rcrtc);
 547
 548         if (event) {
 549                 event->pipe = rcrtc->index;
 550                 drm_crtc_vblank_get(crtc);
 551                 spin_lock_irqsave(&dev->event_lock, flags);
 552                 rcrtc->event = event;
 553                 spin_unlock_irqrestore(&dev->event_lock, flags);
 554         }
 555
 556         return 0;
 557 }
 558
 559 static const struct drm_crtc_funcs crtc_funcs = {
 560         .reset = drm_atomic_helper_crtc_reset,
 561         .destroy = drm_crtc_cleanup,
 562         .set_config = drm_atomic_helper_set_config,
 563         .page_flip = rcar_du_crtc_page_flip,
 564         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 565         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 566 };
 567
 568 /* -----------------------------------------------------------------------------
 569  * Interrupt Handling
 570  */
 571
 572 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 573 {
 574         struct rcar_du_crtc *rcrtc = arg;
 575         irqreturn_t ret = IRQ_NONE;
 576         u32 status;
 577
 578         status = rcar_du_crtc_read(rcrtc, DSSR);
 579         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 580
 581         if (status & DSSR_FRM) {
 582                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 583                 rcar_du_crtc_finish_page_flip(rcrtc);
 584                 ret = IRQ_HANDLED;
 585         }
 586
 587         return ret;
 588 }
 589
 590 /* -----------------------------------------------------------------------------
 591  * Initialization
 592  */
 593
 594 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 595 {
 596         static const unsigned int mmio_offsets[] = {
 597                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 598         };
 599
 600         struct rcar_du_device *rcdu = rgrp->dev;
 601         struct platform_device *pdev = to_platform_device(rcdu->dev);
 602         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 603         struct drm_crtc *crtc = &rcrtc->crtc;
 604         unsigned int irqflags;
 605         struct clk *clk;
 606         char clk_name[9];
 607         char *name;
 608         int irq;
 609         int ret;
 610
 611         /* Get the CRTC clock and the optional external clock. */
 612         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 613                 sprintf(clk_name, "du.%u", index);
 614                 name = clk_name;
 615         } else {
 616                 name = NULL;
 617         }
 618
 619         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 620         if (IS_ERR(rcrtc->clock)) {
 621                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 622                 return PTR_ERR(rcrtc->clock);
 623         }
 624
 625         sprintf(clk_name, "dclkin.%u", index);
 626         clk = devm_clk_get(rcdu->dev, clk_name);
 627         if (!IS_ERR(clk)) {
 628                 rcrtc->extclock = clk;
 629         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 630                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 631                 return -EPROBE_DEFER;
 632         }
 633
 634         init_waitqueue_head(&rcrtc->flip_wait);
 635
 636         rcrtc->group = rgrp;
 637         rcrtc->mmio_offset = mmio_offsets[index];
 638         rcrtc->index = index;
 639         rcrtc->enabled = false;
 640         rcrtc->plane = &rgrp->planes.planes[index % 2];
 641
 642         rcrtc->plane->crtc = crtc;
 643
 644         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, &rcrtc->plane->plane,
 645                                         NULL, &crtc_funcs);
 646         if (ret < 0)
 647                 return ret;
 648
 649         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 650
 651         /* Start with vertical blanking interrupt reporting disabled. */
 652         drm_crtc_vblank_off(crtc);
 653
 654         /* Register the interrupt handler. */
 655         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 656                 irq = platform_get_irq(pdev, index);
 657                 irqflags = 0;
 658         } else {
 659                 irq = platform_get_irq(pdev, 0);
 660                 irqflags = IRQF_SHARED;
 661         }
 662
 663         if (irq < 0) {
 664                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 665                 return irq;
 666         }
 667
 668         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 669                                dev_name(rcdu->dev), rcrtc);
 670         if (ret < 0) {
 671                 dev_err(rcdu->dev,
 672                         "failed to register IRQ for CRTC %u\n", index);
 673                 return ret;
 674         }
 675
 676         return 0;
 677 }
 678
 679 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 680 {
 681         if (enable) {
 682                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 683                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 684         } else {
 685                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 686         }
 687 }