2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Chris Zhong <zyw@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/bitops.h>
20 #define ADDR_IMEM 0x10000
21 #define ADDR_DMEM 0x20000
25 #define XT_INT_CTRL 0x04
26 #define MAILBOX_FULL_ADDR 0x08
27 #define MAILBOX_EMPTY_ADDR 0x0c
28 #define MAILBOX0_WR_DATA 0x10
29 #define MAILBOX0_RD_DATA 0x14
30 #define KEEP_ALIVE 0x18
33 #define VER_LIB_L_ADDR 0x24
34 #define VER_LIB_H_ADDR 0x28
35 #define SW_DEBUG_L 0x2c
36 #define SW_DEBUG_H 0x30
37 #define MAILBOX_INT_MASK 0x34
38 #define MAILBOX_INT_STATUS 0x38
41 #define SW_EVENTS0 0x44
42 #define SW_EVENTS1 0x48
43 #define SW_EVENTS2 0x4c
44 #define SW_EVENTS3 0x50
45 #define XT_OCD_CTRL 0x60
46 #define APB_INT_MASK 0x6c
47 #define APB_STATUS_MASK 0x70
49 /* audio decoder addr */
50 #define AUDIO_SRC_CNTL 0x30000
51 #define AUDIO_SRC_CNFG 0x30004
52 #define COM_CH_STTS_BITS 0x30008
53 #define STTS_BIT_CH(x) (0x3000c + ((x) << 2))
54 #define SPDIF_CTRL_ADDR 0x3004c
55 #define SPDIF_CH1_CS_3100_ADDR 0x30050
56 #define SPDIF_CH1_CS_6332_ADDR 0x30054
57 #define SPDIF_CH1_CS_9564_ADDR 0x30058
58 #define SPDIF_CH1_CS_12796_ADDR 0x3005c
59 #define SPDIF_CH1_CS_159128_ADDR 0x30060
60 #define SPDIF_CH1_CS_191160_ADDR 0x30064
61 #define SPDIF_CH2_CS_3100_ADDR 0x30068
62 #define SPDIF_CH2_CS_6332_ADDR 0x3006c
63 #define SPDIF_CH2_CS_9564_ADDR 0x30070
64 #define SPDIF_CH2_CS_12796_ADDR 0x30074
65 #define SPDIF_CH2_CS_159128_ADDR 0x30078
66 #define SPDIF_CH2_CS_191160_ADDR 0x3007c
67 #define SMPL2PKT_CNTL 0x30080
68 #define SMPL2PKT_CNFG 0x30084
69 #define FIFO_CNTL 0x30088
70 #define FIFO_STTS 0x3008c
73 #define SOURCE_PIF_WR_ADDR 0x30800
74 #define SOURCE_PIF_WR_REQ 0x30804
75 #define SOURCE_PIF_RD_ADDR 0x30808
76 #define SOURCE_PIF_RD_REQ 0x3080c
77 #define SOURCE_PIF_DATA_WR 0x30810
78 #define SOURCE_PIF_DATA_RD 0x30814
79 #define SOURCE_PIF_FIFO1_FLUSH 0x30818
80 #define SOURCE_PIF_FIFO2_FLUSH 0x3081c
81 #define SOURCE_PIF_STATUS 0x30820
82 #define SOURCE_PIF_INTERRUPT_SOURCE 0x30824
83 #define SOURCE_PIF_INTERRUPT_MASK 0x30828
84 #define SOURCE_PIF_PKT_ALLOC_REG 0x3082c
85 #define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830
86 #define SOURCE_PIF_SW_RESET 0x30834
88 /* bellow registers need access by mailbox */
90 #define SOURCE_HDTX_CAR 0x0900
91 #define SOURCE_DPTX_CAR 0x0904
92 #define SOURCE_PHY_CAR 0x0908
93 #define SOURCE_CEC_CAR 0x090c
94 #define SOURCE_CBUS_CAR 0x0910
95 #define SOURCE_PKT_CAR 0x0918
96 #define SOURCE_AIF_CAR 0x091c
97 #define SOURCE_CIPHER_CAR 0x0920
98 #define SOURCE_CRYPTO_CAR 0x0924
100 /* clock meters addr */
101 #define CM_CTRL 0x0a00
102 #define CM_I2S_CTRL 0x0a04
103 #define CM_SPDIF_CTRL 0x0a08
104 #define CM_VID_CTRL 0x0a0c
105 #define CM_LANE_CTRL 0x0a10
106 #define I2S_NM_STABLE 0x0a14
107 #define I2S_NCTS_STABLE 0x0a18
108 #define SPDIF_NM_STABLE 0x0a1c
109 #define SPDIF_NCTS_STABLE 0x0a20
110 #define NMVID_MEAS_STABLE 0x0a24
111 #define I2S_MEAS 0x0a40
112 #define SPDIF_MEAS 0x0a80
113 #define NMVID_MEAS 0x0ac0
115 /* source vif addr */
116 #define BND_HSYNC2VSYNC 0x0b00
117 #define HSYNC2VSYNC_F1_L1 0x0b04
118 #define HSYNC2VSYNC_F2_L1 0x0b08
119 #define HSYNC2VSYNC_STATUS 0x0b0c
120 #define HSYNC2VSYNC_POL_CTRL 0x0b10
123 #define DP_TX_PHY_CONFIG_REG 0x2000
124 #define DP_TX_PHY_STATUS_REG 0x2004
125 #define DP_TX_PHY_SW_RESET 0x2008
126 #define DP_TX_PHY_SCRAMBLER_SEED 0x200c
127 #define DP_TX_PHY_TRAINING_01_04 0x2010
128 #define DP_TX_PHY_TRAINING_05_08 0x2014
129 #define DP_TX_PHY_TRAINING_09_10 0x2018
130 #define TEST_COR 0x23fc
133 #define HPD_IRQ_DET_MIN_TIMER 0x2100
134 #define HPD_IRQ_DET_MAX_TIMER 0x2104
135 #define HPD_UNPLGED_DET_MIN_TIMER 0x2108
136 #define HPD_STABLE_TIMER 0x210c
137 #define HPD_FILTER_TIMER 0x2110
138 #define HPD_EVENT_MASK 0x211c
139 #define HPD_EVENT_DET 0x2120
141 /* dpyx framer addr */
142 #define DP_FRAMER_GLOBAL_CONFIG 0x2200
143 #define DP_SW_RESET 0x2204
144 #define DP_FRAMER_TU 0x2208
145 #define DP_FRAMER_PXL_REPR 0x220c
146 #define DP_FRAMER_SP 0x2210
147 #define AUDIO_PACK_CONTROL 0x2214
148 #define DP_VC_TABLE(x) (0x2218 + ((x) << 2))
149 #define DP_VB_ID 0x2258
150 #define DP_MTPH_LVP_CONTROL 0x225c
151 #define DP_MTPH_SYMBOL_VALUES 0x2260
152 #define DP_MTPH_ECF_CONTROL 0x2264
153 #define DP_MTPH_ACT_CONTROL 0x2268
154 #define DP_MTPH_STATUS 0x226c
155 #define DP_INTERRUPT_SOURCE 0x2270
156 #define DP_INTERRUPT_MASK 0x2274
157 #define DP_FRONT_BACK_PORCH 0x2278
158 #define DP_BYTE_COUNT 0x227c
160 /* dptx stream addr */
161 #define MSA_HORIZONTAL_0 0x2280
162 #define MSA_HORIZONTAL_1 0x2284
163 #define MSA_VERTICAL_0 0x2288
164 #define MSA_VERTICAL_1 0x228c
165 #define MSA_MISC 0x2290
166 #define STREAM_CONFIG 0x2294
167 #define AUDIO_PACK_STATUS 0x2298
168 #define VIF_STATUS 0x229c
169 #define PCK_STUFF_STATUS_0 0x22a0
170 #define PCK_STUFF_STATUS_1 0x22a4
171 #define INFO_PACK_STATUS 0x22a8
172 #define RATE_GOVERNOR_STATUS 0x22ac
173 #define DP_HORIZONTAL 0x22b0
174 #define DP_VERTICAL_0 0x22b4
175 #define DP_VERTICAL_1 0x22b8
176 #define DP_BLOCK_SDP 0x22bc
179 #define DPTX_LANE_EN 0x2300
180 #define DPTX_ENHNCD 0x2304
181 #define DPTX_INT_MASK 0x2308
182 #define DPTX_INT_STATUS 0x230c
185 #define DP_AUX_HOST_CONTROL 0x2800
186 #define DP_AUX_INTERRUPT_SOURCE 0x2804
187 #define DP_AUX_INTERRUPT_MASK 0x2808
188 #define DP_AUX_SWAP_INVERSION_CONTROL 0x280c
189 #define DP_AUX_SEND_NACK_TRANSACTION 0x2810
190 #define DP_AUX_CLEAR_RX 0x2814
191 #define DP_AUX_CLEAR_TX 0x2818
192 #define DP_AUX_TIMER_STOP 0x281c
193 #define DP_AUX_TIMER_CLEAR 0x2820
194 #define DP_AUX_RESET_SW 0x2824
195 #define DP_AUX_DIVIDE_2M 0x2828
196 #define DP_AUX_TX_PREACHARGE_LENGTH 0x282c
197 #define DP_AUX_FREQUENCY_1M_MAX 0x2830
198 #define DP_AUX_FREQUENCY_1M_MIN 0x2834
199 #define DP_AUX_RX_PRE_MIN 0x2838
200 #define DP_AUX_RX_PRE_MAX 0x283c
201 #define DP_AUX_TIMER_PRESET 0x2840
202 #define DP_AUX_NACK_FORMAT 0x2844
203 #define DP_AUX_TX_DATA 0x2848
204 #define DP_AUX_RX_DATA 0x284c
205 #define DP_AUX_TX_STATUS 0x2850
206 #define DP_AUX_RX_STATUS 0x2854
207 #define DP_AUX_RX_CYCLE_COUNTER 0x2858
208 #define DP_AUX_MAIN_STATES 0x285c
209 #define DP_AUX_MAIN_TIMER 0x2860
210 #define DP_AUX_AFE_OUT 0x2864
213 #define CRYPTO_HDCP_REVISION 0x5800
214 #define HDCP_CRYPTO_CONFIG 0x5804
215 #define CRYPTO_INTERRUPT_SOURCE 0x5808
216 #define CRYPTO_INTERRUPT_MASK 0x580c
217 #define CRYPTO22_CONFIG 0x5818
218 #define CRYPTO22_STATUS 0x581c
219 #define SHA_256_DATA_IN 0x583c
220 #define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2))
221 #define AES_32_KEY_(x) (0x5870 + ((x) << 2))
222 #define AES_32_DATA_IN 0x5880
223 #define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2))
224 #define CRYPTO14_CONFIG 0x58a0
225 #define CRYPTO14_STATUS 0x58a4
226 #define CRYPTO14_PRNM_OUT 0x58a8
227 #define CRYPTO14_KM_0 0x58ac
228 #define CRYPTO14_KM_1 0x58b0
229 #define CRYPTO14_AN_0 0x58b4
230 #define CRYPTO14_AN_1 0x58b8
231 #define CRYPTO14_YOUR_KSV_0 0x58bc
232 #define CRYPTO14_YOUR_KSV_1 0x58c0
233 #define CRYPTO14_MI_0 0x58c4
234 #define CRYPTO14_MI_1 0x58c8
235 #define CRYPTO14_TI_0 0x58cc
236 #define CRYPTO14_KI_0 0x58d0
237 #define CRYPTO14_KI_1 0x58d4
238 #define CRYPTO14_BLOCKS_NUM 0x58d8
239 #define CRYPTO14_KEY_MEM_DATA_0 0x58dc
240 #define CRYPTO14_KEY_MEM_DATA_1 0x58e0
241 #define CRYPTO14_SHA1_MSG_DATA 0x58e4
242 #define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2))
243 #define TRNG_CTRL 0x58fc
244 #define TRNG_DATA_RDY 0x5900
245 #define TRNG_DATA 0x5904
248 #define HDCP_REVISION 0x60000
249 #define INTERRUPT_SOURCE 0x60004
250 #define INTERRUPT_MASK 0x60008
251 #define HDCP_CIPHER_CONFIG 0x6000c
252 #define AES_128_KEY_0 0x60010
253 #define AES_128_KEY_1 0x60014
254 #define AES_128_KEY_2 0x60018
255 #define AES_128_KEY_3 0x6001c
256 #define AES_128_RANDOM_0 0x60020
257 #define AES_128_RANDOM_1 0x60024
258 #define CIPHER14_KM_0 0x60028
259 #define CIPHER14_KM_1 0x6002c
260 #define CIPHER14_STATUS 0x60030
261 #define CIPHER14_RI_PJ_STATUS 0x60034
262 #define CIPHER_MODE 0x60038
263 #define CIPHER14_AN_0 0x6003c
264 #define CIPHER14_AN_1 0x60040
265 #define CIPHER22_AUTH 0x60044
266 #define CIPHER14_R0_DP_STATUS 0x60048
267 #define CIPHER14_BOOTSTRAP 0x6004c
269 #define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11)
270 #define DPTX_FRMR_DATA_CLK_EN BIT(10)
271 #define DPTX_PHY_DATA_RSTN_EN BIT(9)
272 #define DPTX_PHY_DATA_CLK_EN BIT(8)
273 #define DPTX_PHY_CHAR_RSTN_EN BIT(7)
274 #define DPTX_PHY_CHAR_CLK_EN BIT(6)
275 #define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5)
276 #define SOURCE_AUX_SYS_CLK_EN BIT(4)
277 #define DPTX_SYS_CLK_RSTN_EN BIT(3)
278 #define DPTX_SYS_CLK_EN BIT(2)
279 #define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1)
280 #define CFG_DPTX_VIF_CLK_EN BIT(0)
282 #define SOURCE_PHY_RSTN_EN BIT(1)
283 #define SOURCE_PHY_CLK_EN BIT(0)
285 #define SOURCE_PKT_SYS_RSTN_EN BIT(3)
286 #define SOURCE_PKT_SYS_CLK_EN BIT(2)
287 #define SOURCE_PKT_DATA_RSTN_EN BIT(1)
288 #define SOURCE_PKT_DATA_CLK_EN BIT(0)
290 #define SPDIF_CDR_CLK_RSTN_EN BIT(5)
291 #define SPDIF_CDR_CLK_EN BIT(4)
292 #define SOURCE_AIF_SYS_RSTN_EN BIT(3)
293 #define SOURCE_AIF_SYS_CLK_EN BIT(2)
294 #define SOURCE_AIF_CLK_RSTN_EN BIT(1)
295 #define SOURCE_AIF_CLK_EN BIT(0)
297 #define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3)
298 #define SOURCE_CIPHER_SYS_CLK_EN BIT(2)
299 #define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1)
300 #define SOURCE_CIPHER_CHAR_CLK_EN BIT(0)
302 #define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1)
303 #define SOURCE_CRYPTO_SYS_CLK_EN BIT(0)
305 #define APB_IRAM_PATH BIT(2)
306 #define APB_DRAM_PATH BIT(1)
307 #define APB_XT_RESET BIT(0)
309 #define MAILBOX_INT_MASK_BIT BIT(1)
310 #define PIF_INT_MASK_BIT BIT(0)
311 #define ALL_INT_MASK 3
314 #define MB_OPCODE_ID 0
315 #define MB_MODULE_ID 1
316 #define MB_SIZE_MSB_ID 2
317 #define MB_SIZE_LSB_ID 3
320 #define MB_MODULE_ID_DP_TX 0x01
321 #define MB_MODULE_ID_HDCP_TX 0x07
322 #define MB_MODULE_ID_HDCP_RX 0x08
323 #define MB_MODULE_ID_HDCP_GENERAL 0x09
324 #define MB_MODULE_ID_GENERAL 0x0a
327 #define GENERAL_MAIN_CONTROL 0x01
328 #define GENERAL_TEST_ECHO 0x02
329 #define GENERAL_BUS_SETTINGS 0x03
330 #define GENERAL_TEST_ACCESS 0x04
332 #define DPTX_SET_POWER_MNG 0x00
333 #define DPTX_SET_HOST_CAPABILITIES 0x01
334 #define DPTX_GET_EDID 0x02
335 #define DPTX_READ_DPCD 0x03
336 #define DPTX_WRITE_DPCD 0x04
337 #define DPTX_ENABLE_EVENT 0x05
338 #define DPTX_WRITE_REGISTER 0x06
339 #define DPTX_READ_REGISTER 0x07
340 #define DPTX_WRITE_FIELD 0x08
341 #define DPTX_TRAINING_CONTROL 0x09
342 #define DPTX_READ_EVENT 0x0a
343 #define DPTX_READ_LINK_STAT 0x0b
344 #define DPTX_SET_VIDEO 0x0c
345 #define DPTX_SET_AUDIO 0x0d
346 #define DPTX_GET_LAST_AUX_STAUS 0x0e
347 #define DPTX_SET_LINK_BREAK_POINT 0x0f
348 #define DPTX_FORCE_LANES 0x10
349 #define DPTX_HPD_STATE 0x11
354 #define DPTX_EVENT_ENABLE_HPD BIT(0)
355 #define DPTX_EVENT_ENABLE_TRAINING BIT(1)
357 #define LINK_TRAINING_NOT_ACTIVE 0
358 #define LINK_TRAINING_RUN 1
359 #define LINK_TRAINING_RESTART 2
361 #define CONTROL_VIDEO_IDLE 0
362 #define CONTROL_VIDEO_VALID 1
364 #define TU_CNT_RST_EN BIT(15)
365 #define VIF_BYPASS_INTERLACE BIT(13)
366 #define INTERLACE_FMT_DET BIT(12)
367 #define INTERLACE_DTCT_WIN 0x20
369 #define DP_FRAMER_SP_INTERLACE_EN BIT(2)
370 #define DP_FRAMER_SP_HSP BIT(1)
371 #define DP_FRAMER_SP_VSP BIT(0)
374 #define AUX_HOST_INVERT 3
375 #define FAST_LT_SUPPORT 1
376 #define FAST_LT_NOT_SUPPORT 0
377 #define LANE_MAPPING_NORMAL 0x1b
378 #define LANE_MAPPING_FLIPPED 0xe4
380 #define SCRAMBLER_EN BIT(4)
382 #define FULL_LT_STARTED BIT(0)
383 #define FASE_LT_STARTED BIT(1)
384 #define CLK_RECOVERY_FINISHED BIT(2)
385 #define EQ_PHASE_FINISHED BIT(3)
386 #define FASE_LT_START_FINISHED BIT(4)
387 #define CLK_RECOVERY_FAILED BIT(5)
388 #define EQ_PHASE_FAILED BIT(6)
389 #define FASE_LT_FAILED BIT(7)
391 #define DPTX_HPD_EVENT BIT(0)
392 #define DPTX_TRAINING_EVENT BIT(1)
393 #define HDCP_TX_STATUS_EVENT BIT(4)
394 #define HDCP2_TX_IS_KM_STORED_EVENT BIT(5)
395 #define HDCP2_TX_STORE_KM_EVENT BIT(6)
396 #define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7)
399 #define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4
402 #define AUDIO_PACK_EN BIT(8)
403 #define SAMPLING_FREQ(x) (((x) & 0xf) << 16)
404 #define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24)
405 #define SYNC_WR_TO_CH_ZERO BIT(1)
406 #define I2S_DEC_START BIT(1)
407 #define AUDIO_SW_RST BIT(0)
408 #define SMPL2PKT_EN BIT(1)
409 #define MAX_NUM_CH(x) (((x) & 0x1f) - 1)
410 #define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)
411 #define AUDIO_TYPE_LPCM (2 << 7)
412 #define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)
413 #define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)
414 #define TRANS_SMPL_WIDTH_16 0
415 #define TRANS_SMPL_WIDTH_24 BIT(11)
416 #define TRANS_SMPL_WIDTH_32 (2 << 11)
417 #define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17)
418 #define SPDIF_ENABLE BIT(21)
419 #define SPDIF_AVG_SEL BIT(20)
420 #define SPDIF_JITTER_BYPASS BIT(19)
421 #define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11)
422 #define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3)
423 #define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7)
425 /* Reference cycles when using lane clock as reference */
426 #define LANE_REF_CYC 0xf000
428 enum voltage_swing_level {
435 enum pre_emphasis_level {
436 PRE_EMPHASIS_LEVEL_0,
437 PRE_EMPHASIS_LEVEL_1,
438 PRE_EMPHASIS_LEVEL_2,
439 PRE_EMPHASIS_LEVEL_3,
450 enum vic_color_depth {
463 void cdn_dp_clock_reset(struct cdn_dp_device *dp);
465 void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, u32 clk);
466 int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
467 u32 i_size, const u32 *d_mem, u32 d_size);
468 int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable);
469 int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
470 int cdn_dp_event_config(struct cdn_dp_device *dp);
471 u32 cdn_dp_get_event(struct cdn_dp_device *dp);
472 int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
473 int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
474 int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
475 int cdn_dp_get_edid_block(void *dp, u8 *edid,
476 unsigned int block, size_t length);
477 int cdn_dp_train_link(struct cdn_dp_device *dp);
478 int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active);
479 int cdn_dp_config_video(struct cdn_dp_device *dp);
480 int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
481 int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
482 int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
483 #endif /* _CDN_DP_REG_H */