drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3288_GRF_SOC_CON9             0x0268
  40
  41 #define RK3288_GRF_SOC_CON14            0x027c
  42 #define RK3288_TXRX_BASEDIR             BIT(15)
  43 #define RK3288_TXRX_MASTERSLAVEZ        BIT(14)
  44 #define RK3288_TXRX_CLKEN               BIT(12)
  45
  46 #define RK3366_GRF_SOC_CON0             0x0400
  47 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  48
  49 #define RK3399_GRF_SOC_CON19            0x6250
  50 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  51 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  52
  53 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  54 #define RK3399_GRF_SOC_CON22            0x6258
  55 #define RK3399_GRF_DSI0_MODE            0xffff0000
  56 /* disable turndisable, forcetxstopmode, forcerxmode, enable */
  57 #define RK3399_GRF_SOC_CON23            0x625c
  58 #define RK3399_GRF_DSI1_MODE1           0xffff0000
  59 #define RK3399_GRF_DSI1_ENABLE          0x000f000f
  60 /* disable basedir and enable clk*/
  61 #define RK3399_GRF_SOC_CON24            0x6260
  62 #define RK3399_TXRX_MASTERSLAVEZ        BIT(7)
  63 #define RK3399_TXRX_ENABLECLK           BIT(6)
  64 #define RK3399_TXRX_BASEDIR             BIT(5)
  65 #define RK3399_GRF_DSI1_MODE2           0x00600040
  66
  67 #define DSI_VERSION                     0x00
  68 #define DSI_PWR_UP                      0x04
  69 #define RESET                           0
  70 #define POWERUP                         BIT(0)
  71
  72 #define DSI_CLKMGR_CFG                  0x08
  73 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  74 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  75
  76 #define DSI_DPI_VCID                    0x0c
  77 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  78
  79 #define DSI_DPI_COLOR_CODING            0x10
  80 #define EN18_LOOSELY                    BIT(8)
  81 #define DPI_COLOR_CODING_16BIT_1        0x0
  82 #define DPI_COLOR_CODING_16BIT_2        0x1
  83 #define DPI_COLOR_CODING_16BIT_3        0x2
  84 #define DPI_COLOR_CODING_18BIT_1        0x3
  85 #define DPI_COLOR_CODING_18BIT_2        0x4
  86 #define DPI_COLOR_CODING_24BIT          0x5
  87
  88 #define DSI_DPI_CFG_POL                 0x14
  89 #define COLORM_ACTIVE_LOW               BIT(4)
  90 #define SHUTD_ACTIVE_LOW                BIT(3)
  91 #define HSYNC_ACTIVE_LOW                BIT(2)
  92 #define VSYNC_ACTIVE_LOW                BIT(1)
  93 #define DATAEN_ACTIVE_LOW               BIT(0)
  94
  95 #define DSI_DPI_LP_CMD_TIM              0x18
  96 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  97 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  98
  99 #define DSI_DBI_CFG                     0x20
 100 #define DSI_DBI_CMDSIZE                 0x28
 101
 102 #define DSI_PCKHDL_CFG                  0x2c
 103 #define EN_CRC_RX                       BIT(4)
 104 #define EN_ECC_RX                       BIT(3)
 105 #define EN_BTA                          BIT(2)
 106 #define EN_EOTP_RX                      BIT(1)
 107 #define EN_EOTP_TX                      BIT(0)
 108
 109 #define DSI_MODE_CFG                    0x34
 110 #define ENABLE_VIDEO_MODE               0
 111 #define ENABLE_CMD_MODE                 BIT(0)
 112
 113 #define DSI_VID_MODE_CFG                0x38
 114 #define VPG_EN                          BIT(16)
 115 #define FRAME_BTA_ACK                   BIT(14)
 116 #define LP_HFP_EN                       BIT(13)
 117 #define LP_HBP_EN                       BIT(12)
 118 #define ENABLE_LOW_POWER                (0xf << 8)
 119 #define ENABLE_LOW_POWER_MASK           (0xf << 8)
 120 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 121 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 122 #define VID_MODE_TYPE_BURST             0x2
 123
 124 #define DSI_VID_PKT_SIZE                0x3c
 125 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 126 #define VID_PKT_MAX_SIZE                0x3fff
 127
 128 #define DSI_VID_NUM_CHUMKS              0x40
 129 #define DSI_VID_NULL_PKT_SIZE           0x44
 130 #define DSI_VID_HSA_TIME                0x48
 131 #define DSI_VID_HBP_TIME                0x4c
 132 #define DSI_VID_HLINE_TIME              0x50
 133 #define DSI_VID_VSA_LINES               0x54
 134 #define DSI_VID_VBP_LINES               0x58
 135 #define DSI_VID_VFP_LINES               0x5c
 136 #define DSI_VID_VACTIVE_LINES           0x60
 137 #define DSI_CMD_MODE_CFG                0x68
 138 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 139 #define DCS_LW_TX_LP                    BIT(19)
 140 #define DCS_SR_0P_TX_LP                 BIT(18)
 141 #define DCS_SW_1P_TX_LP                 BIT(17)
 142 #define DCS_SW_0P_TX_LP                 BIT(16)
 143 #define GEN_LW_TX_LP                    BIT(14)
 144 #define GEN_SR_2P_TX_LP                 BIT(13)
 145 #define GEN_SR_1P_TX_LP                 BIT(12)
 146 #define GEN_SR_0P_TX_LP                 BIT(11)
 147 #define GEN_SW_2P_TX_LP                 BIT(10)
 148 #define GEN_SW_1P_TX_LP                 BIT(9)
 149 #define GEN_SW_0P_TX_LP                 BIT(8)
 150 #define EN_ACK_RQST                     BIT(1)
 151 #define EN_TEAR_FX                      BIT(0)
 152
 153 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 154                                          DCS_LW_TX_LP | \
 155                                          DCS_SR_0P_TX_LP | \
 156                                          DCS_SW_1P_TX_LP | \
 157                                          DCS_SW_0P_TX_LP | \
 158                                          GEN_LW_TX_LP | \
 159                                          GEN_SR_2P_TX_LP | \
 160                                          GEN_SR_1P_TX_LP | \
 161                                          GEN_SR_0P_TX_LP | \
 162                                          GEN_SW_2P_TX_LP | \
 163                                          GEN_SW_1P_TX_LP | \
 164                                          GEN_SW_0P_TX_LP)
 165
 166 #define DSI_GEN_HDR                     0x6c
 167 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 168 #define GEN_HDATA_MASK                  (0xffff << 8)
 169 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 170 #define GEN_HTYPE_MASK                  0xff
 171
 172 #define DSI_GEN_PLD_DATA                0x70
 173
 174 #define DSI_CMD_PKT_STATUS              0x74
 175 #define GEN_CMD_EMPTY                   BIT(0)
 176 #define GEN_CMD_FULL                    BIT(1)
 177 #define GEN_PLD_W_EMPTY                 BIT(2)
 178 #define GEN_PLD_W_FULL                  BIT(3)
 179 #define GEN_PLD_R_EMPTY                 BIT(4)
 180 #define GEN_PLD_R_FULL                  BIT(5)
 181 #define GEN_RD_CMD_BUSY                 BIT(6)
 182
 183 #define DSI_TO_CNT_CFG                  0x78
 184 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 185 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 186
 187 #define DSI_BTA_TO_CNT                  0x8c
 188 #define DSI_LPCLK_CTRL                  0x94
 189 #define AUTO_CLKLANE_CTRL               BIT(1)
 190 #define PHY_TXREQUESTCLKHS              BIT(0)
 191
 192 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 193 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 194 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 195
 196 #define DSI_PHY_TMR_CFG                 0x9c
 197 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 198 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 199 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 200
 201 #define DSI_PHY_RSTZ                    0xa0
 202 #define PHY_DISFORCEPLL                 0
 203 #define PHY_ENFORCEPLL                  BIT(3)
 204 #define PHY_DISABLECLK                  0
 205 #define PHY_ENABLECLK                   BIT(2)
 206 #define PHY_RSTZ                        0
 207 #define PHY_UNRSTZ                      BIT(1)
 208 #define PHY_SHUTDOWNZ                   0
 209 #define PHY_UNSHUTDOWNZ                 BIT(0)
 210
 211 #define DSI_PHY_IF_CFG                  0xa4
 212 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 213 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 214
 215 #define DSI_PHY_STATUS                  0xb0
 216 #define LOCK                            BIT(0)
 217 #define STOP_STATE_CLK_LANE             BIT(2)
 218
 219 #define DSI_PHY_TST_CTRL0               0xb4
 220 #define PHY_TESTCLK                     BIT(1)
 221 #define PHY_UNTESTCLK                   0
 222 #define PHY_TESTCLR                     BIT(0)
 223 #define PHY_UNTESTCLR                   0
 224
 225 #define DSI_PHY_TST_CTRL1               0xb8
 226 #define PHY_TESTEN                      BIT(16)
 227 #define PHY_UNTESTEN                    0
 228 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 229 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 230
 231 #define DSI_INT_ST0                     0xbc
 232 #define DSI_INT_ST1                     0xc0
 233 #define DSI_INT_MSK0                    0xc4
 234 #define DSI_INT_MSK1                    0xc8
 235
 236 #define PHY_STATUS_TIMEOUT_US           10000
 237 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 238
 239 #define BYPASS_VCO_RANGE        BIT(7)
 240 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 241 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 242 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 243 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 244 #define REF_BIAS_CUR_SEL        BIT(0)
 245
 246 #define CP_CURRENT_3MA          BIT(3)
 247 #define CP_PROGRAM_EN           BIT(7)
 248 #define LPF_PROGRAM_EN          BIT(6)
 249 #define LPF_RESISTORS_20_KOHM   0
 250
 251 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 252
 253 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 254 #define LOW_PROGRAM_EN          0
 255 #define HIGH_PROGRAM_EN         BIT(7)
 256 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 257 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 258 #define PLL_LOOP_DIV_EN         BIT(5)
 259 #define PLL_INPUT_DIV_EN        BIT(4)
 260
 261 #define POWER_CONTROL           BIT(6)
 262 #define INTERNAL_REG_CURRENT    BIT(3)
 263 #define BIAS_BLOCK_ON           BIT(2)
 264 #define BANDGAP_ON              BIT(0)
 265
 266 #define TER_RESISTOR_HIGH       BIT(7)
 267 #define TER_RESISTOR_LOW        0
 268 #define LEVEL_SHIFTERS_ON       BIT(6)
 269 #define TER_CAL_DONE            BIT(5)
 270 #define SETRD_MAX               (0x7 << 2)
 271 #define POWER_MANAGE            BIT(1)
 272 #define TER_RESISTORS_ON        BIT(0)
 273
 274 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 275 #define BANDGAP_SEL(val)        ((val) & 0x7)
 276 #define TLP_PROGRAM_EN          BIT(7)
 277 #define THS_PRE_PROGRAM_EN      BIT(7)
 278 #define THS_ZERO_PROGRAM_EN     BIT(6)
 279
 280 enum {
 281         BANDGAP_97_07,
 282         BANDGAP_98_05,
 283         BANDGAP_99_02,
 284         BANDGAP_100_00,
 285         BANDGAP_93_17,
 286         BANDGAP_94_15,
 287         BANDGAP_95_12,
 288         BANDGAP_96_10,
 289 };
 290
 291 enum {
 292         BIASEXTR_87_1,
 293         BIASEXTR_91_5,
 294         BIASEXTR_95_9,
 295         BIASEXTR_100,
 296         BIASEXTR_105_94,
 297         BIASEXTR_111_88,
 298         BIASEXTR_118_8,
 299         BIASEXTR_127_7,
 300 };
 301
 302 struct dw_mipi_dsi_plat_data {
 303         u32 dsi0_en_bit;
 304         u32 dsi1_en_bit;
 305         u32 grf_switch_reg;
 306         u32 grf_dsi0_mode;
 307         u32 grf_dsi0_mode_reg;
 308         u32 grf_dsi1_mode;
 309         u32 grf_dsi1_mode_reg1;
 310         u32 dsi1_basedir;
 311         u32 dsi1_masterslavez;
 312         u32 dsi1_enableclk;
 313         u32 grf_dsi1_mode_reg2;
 314         u32 grf_dsi1_cfg_reg;
 315         unsigned int max_data_lanes;
 316         u32 max_bit_rate_per_lane;
 317         bool has_vop_sel;
 318         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 319                                            struct drm_display_mode *mode);
 320 };
 321
 322 struct mipi_dphy {
 323         /* SNPS PHY */
 324         struct clk *cfg_clk;
 325         struct clk *ref_clk;
 326         u16 input_div;
 327         u16 feedback_div;
 328
 329         /* Non-SNPS PHY */
 330         struct phy *phy;
 331         struct clk *hs_clk;
 332 };
 333
 334 struct dw_mipi_dsi {
 335         struct drm_encoder encoder;
 336         struct drm_connector connector;
 337         struct mipi_dsi_host dsi_host;
 338         struct mipi_dphy dphy;
 339         struct drm_panel *panel;
 340         struct device *dev;
 341         struct regmap *grf_regmap;
 342         struct reset_control *rst;
 343         void __iomem *base;
 344         struct clk *pclk;
 345
 346         /* dual-channel */
 347         struct dw_mipi_dsi *master;
 348         struct dw_mipi_dsi *slave;
 349         struct device_node *panel_node;
 350         int id;
 351
 352         unsigned long mode_flags;
 353         unsigned int lane_mbps; /* per lane */
 354         u32 channel;
 355         u32 lanes;
 356         u32 format;
 357         struct drm_display_mode mode;
 358
 359         const struct dw_mipi_dsi_plat_data *pdata;
 360 };
 361
 362 enum dw_mipi_dsi_mode {
 363         DSI_COMMAND_MODE,
 364         DSI_VIDEO_MODE,
 365 };
 366
 367 struct dphy_pll_testdin_map {
 368         unsigned int max_mbps;
 369         u8 testdin;
 370 };
 371
 372 /* The table is based on 27MHz DPHY pll reference clock. */
 373 static const struct dphy_pll_testdin_map dptdin_map[] = {
 374         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 375         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 376         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 377         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 378         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 379         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 380         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 381         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 382         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 383         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 384 };
 385
 386 static int max_mbps_to_testdin(unsigned int max_mbps)
 387 {
 388         int i;
 389
 390         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 391                 if (dptdin_map[i].max_mbps > max_mbps)
 392                         return dptdin_map[i].testdin;
 393
 394         return -EINVAL;
 395 }
 396
 397 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 398 {
 399         return container_of(host, struct dw_mipi_dsi, dsi_host);
 400 }
 401
 402 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 403 {
 404         return container_of(con, struct dw_mipi_dsi, connector);
 405 }
 406
 407 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 408 {
 409         return container_of(encoder, struct dw_mipi_dsi, encoder);
 410 }
 411 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 412 {
 413         writel(val, dsi->base + reg);
 414 }
 415
 416 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 417 {
 418         return readl(dsi->base + reg);
 419 }
 420
 421 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 422 {
 423         u32 sts;
 424         int ret;
 425
 426         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 427                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 428                                  CMD_PKT_STATUS_TIMEOUT_US);
 429         if (ret < 0) {
 430                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 431                 return ret;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 438 {
 439         u32 sts;
 440         int ret;
 441
 442         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 443                                  sts, !(sts & GEN_CMD_FULL), 10,
 444                                  CMD_PKT_STATUS_TIMEOUT_US);
 445         if (ret < 0) {
 446                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 447                 return ret;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 454 {
 455         u32 sts;
 456         u32 mask;
 457         int ret;
 458
 459         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 460         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 461                                  sts, (sts & mask) == mask, 10,
 462                                  CMD_PKT_STATUS_TIMEOUT_US);
 463         if (ret < 0) {
 464                 dev_err(dsi->dev, "generic write fifo is full\n");
 465                 return ret;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 472                                  u8 test_data)
 473 {
 474         /*
 475          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 476          * is latched internally as the current test code. Test data is
 477          * programmed internally by rising edge on TESTCLK.
 478          */
 479         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 480
 481         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 482                                           PHY_TESTDIN(test_code));
 483
 484         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 485
 486         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 487                                           PHY_TESTDIN(test_data));
 488
 489         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 490 }
 491
 492 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 493 {
 494         int ret, testdin, vco, val;
 495
 496         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 497
 498         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 499         if (testdin < 0) {
 500                 dev_err(dsi->dev,
 501                         "failed to get testdin for %dmbps lane clock\n",
 502                         dsi->lane_mbps);
 503                 return testdin;
 504         }
 505
 506         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 507
 508         if (!IS_ERR(dsi->dphy.cfg_clk)) {
 509                 ret = clk_prepare_enable(dsi->dphy.cfg_clk);
 510                 if (ret) {
 511                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 512                         return ret;
 513                 }
 514         }
 515
 516         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 517                                          VCO_RANGE_CON_SEL(vco) |
 518                                          VCO_IN_CAP_CON_LOW |
 519                                          REF_BIAS_CUR_SEL);
 520
 521         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 522         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 523                                          LPF_RESISTORS_20_KOHM);
 524
 525         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 526
 527         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
 528         val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
 529         dw_mipi_dsi_phy_write(dsi, 0x18, val);
 530         val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
 531         dw_mipi_dsi_phy_write(dsi, 0x18, val);
 532         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 533
 534         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 535                                          BIAS_BLOCK_ON | BANDGAP_ON);
 536
 537         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 538                                          SETRD_MAX | TER_RESISTORS_ON);
 539         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 540                                          SETRD_MAX | POWER_MANAGE |
 541                                          TER_RESISTORS_ON);
 542
 543         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 544                                          BIASEXTR_SEL(BIASEXTR_127_7));
 545         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 546                                          BANDGAP_SEL(BANDGAP_96_10));
 547
 548         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 549         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 550         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 551
 552         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 553                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 554
 555         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 556                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 557         if (ret < 0) {
 558                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 559                 goto phy_init_end;
 560         }
 561
 562         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 563                                  val, val & STOP_STATE_CLK_LANE, 1000,
 564                                  PHY_STATUS_TIMEOUT_US);
 565         if (ret < 0)
 566                 dev_err(dsi->dev,
 567                         "failed to wait for phy clk lane stop state\n");
 568
 569 phy_init_end:
 570         if (!IS_ERR(dsi->dphy.cfg_clk))
 571                 clk_disable_unprepare(dsi->dphy.cfg_clk);
 572
 573         return ret;
 574 }
 575
 576 static unsigned long rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
 577 {
 578         int bpp;
 579         unsigned long mpclk, tmp;
 580         unsigned long target_mbps = 1000;
 581         unsigned int value;
 582         struct device_node *np = dsi->dev->of_node;
 583         unsigned int max_mbps;
 584         int lanes;
 585
 586         /* optional override of the desired bandwidth */
 587         if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
 588                 return value;
 589
 590         max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
 591
 592         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 593         if (bpp < 0) {
 594                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 595                         dsi->format);
 596                 bpp = 24;
 597         }
 598
 599         lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
 600
 601         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 602         if (mpclk) {
 603                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 604                 tmp = mpclk * (bpp / lanes) * 10 / 9;
 605                 if (tmp < max_mbps)
 606                         target_mbps = tmp;
 607                 else
 608                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 609         }
 610
 611         return target_mbps;
 612 }
 613
 614 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 615 {
 616         unsigned int i, pre;
 617         unsigned long pllref, tmp;
 618         unsigned int m = 1, n = 1;
 619         unsigned long target_mbps;
 620
 621         if (dsi->master)
 622                 return 0;
 623
 624         target_mbps = rockchip_dsi_calc_bandwidth(dsi);
 625
 626         pllref = DIV_ROUND_UP(clk_get_rate(dsi->dphy.ref_clk), USEC_PER_SEC);
 627         tmp = pllref;
 628
 629         for (i = 1; i < 6; i++) {
 630                 pre = pllref / i;
 631                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 632                         tmp = target_mbps % pre;
 633                         n = i;
 634                         m = target_mbps / pre;
 635                 }
 636                 if (tmp == 0)
 637                         break;
 638         }
 639
 640         dsi->lane_mbps = pllref / n * m;
 641         dsi->dphy.input_div = n;
 642         dsi->dphy.feedback_div = m;
 643         if (dsi->slave) {
 644                 dsi->slave->lane_mbps = dsi->lane_mbps;
 645                 dsi->slave->dphy.input_div = n;
 646                 dsi->slave->dphy.feedback_div = m;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static void rockchip_dsi_set_hs_clk(struct dw_mipi_dsi *dsi)
 653 {
 654         int ret;
 655         unsigned long target_mbps;
 656         unsigned long bw, rate;
 657
 658         target_mbps = rockchip_dsi_calc_bandwidth(dsi);
 659         bw = target_mbps * USEC_PER_SEC;
 660
 661         rate = clk_round_rate(dsi->dphy.hs_clk, bw);
 662         ret = clk_set_rate(dsi->dphy.hs_clk, rate);
 663         if (ret)
 664                 dev_err(dsi->dev, "failed to set hs clock rate: %lu\n",
 665                         rate);
 666
 667         clk_prepare_enable(dsi->dphy.hs_clk);
 668
 669         dsi->lane_mbps = rate / USEC_PER_SEC;
 670 }
 671
 672 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 673                                    struct mipi_dsi_device *device)
 674 {
 675         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 676         int lanes;
 677
 678         if (dsi->master)
 679                 return 0;
 680
 681         lanes = dsi->slave ? device->lanes / 2 : device->lanes;
 682
 683         if (lanes > dsi->pdata->max_data_lanes) {
 684                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 685                                 lanes);
 686                 return -EINVAL;
 687         }
 688
 689         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 690                 dev_err(dsi->dev, "device mode is unsupported\n");
 691                 return -EINVAL;
 692         }
 693
 694         dsi->lanes = lanes;
 695         dsi->channel = device->channel;
 696         dsi->format = device->format;
 697         dsi->mode_flags = device->mode_flags;
 698
 699         if (dsi->slave) {
 700                 dsi->slave->lanes = lanes;
 701                 dsi->slave->channel = device->channel;
 702                 dsi->slave->format = device->format;
 703                 dsi->slave->mode_flags = device->mode_flags;
 704         }
 705
 706         dsi->panel = of_drm_find_panel(device->dev.of_node);
 707         if (!dsi->panel) {
 708                 DRM_ERROR("failed to find panel\n");
 709                 return -ENODEV;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 716                                    struct mipi_dsi_device *device)
 717 {
 718         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 719
 720         if (dsi->panel)
 721                 drm_panel_detach(dsi->panel);
 722
 723         dsi->panel = NULL;
 724         return 0;
 725 }
 726
 727 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 728 {
 729         if (flags & MIPI_DSI_MSG_USE_LPM) {
 730                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 731                 dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 732         } else {
 733                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 734                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 735         }
 736 }
 737
 738 static ssize_t rockchip_dsi_send_packet(struct dw_mipi_dsi *dsi,
 739                                         const struct mipi_dsi_msg *msg)
 740 {
 741         struct mipi_dsi_packet packet;
 742         int ret;
 743         int val;
 744         int len = msg->tx_len;
 745
 746         /* create a packet to the DSI protocol */
 747         ret = mipi_dsi_create_packet(&packet, msg);
 748         if (ret) {
 749                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 750                 return ret;
 751         }
 752
 753         rockchip_set_transfer_mode(dsi, msg->flags);
 754
 755         /* Send payload,  */
 756         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 757                 /*
 758                  * Alternatively, you can always keep the FIFO
 759                  * nearly full by monitoring the FIFO state until
 760                  * it is not full, and then writea single word of data.
 761                  * This solution is more resource consuming
 762                  * but it simultaneously avoids FIFO starvation,
 763                  * making it possible to use FIFO sizes smaller than
 764                  * the amount of data of the longest packet to be written.
 765                  */
 766                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 767                 if (ret)
 768                         return ret;
 769
 770                 if (packet.payload_length < 4) {
 771                         /* send residu payload */
 772                         val = 0;
 773                         memcpy(&val, packet.payload, packet.payload_length);
 774                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 775                         packet.payload_length = 0;
 776                 } else {
 777                         val = get_unaligned_le32(packet.payload);
 778                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 779                         packet.payload += 4;
 780                         packet.payload_length -= 4;
 781                 }
 782         }
 783
 784         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 785         if (ret)
 786                 return ret;
 787
 788         /* Send packet header */
 789         val = get_unaligned_le32(packet.header);
 790         dsi_write(dsi, DSI_GEN_HDR, val);
 791
 792         ret = rockchip_wait_write_fifo_empty(dsi);
 793         if (ret)
 794                 return ret;
 795
 796         if (dsi->slave)
 797                 rockchip_dsi_send_packet(dsi->slave, msg);
 798
 799         return len;
 800 }
 801
 802 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 803                                          const struct mipi_dsi_msg *msg)
 804 {
 805         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 806
 807         return rockchip_dsi_send_packet(dsi, msg);
 808 }
 809
 810 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 811         .attach = dw_mipi_dsi_host_attach,
 812         .detach = dw_mipi_dsi_host_detach,
 813         .transfer = dw_mipi_dsi_host_transfer,
 814 };
 815
 816 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 817 {
 818         u32 val;
 819
 820         val = LP_HFP_EN | ENABLE_LOW_POWER;
 821
 822         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 823                 val |= VID_MODE_TYPE_BURST;
 824         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 825                 val |= VID_MODE_TYPE_BURST_SYNC_PULSES;
 826         else
 827                 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS;
 828
 829         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 830 }
 831
 832 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 833                                  enum dw_mipi_dsi_mode mode)
 834 {
 835         if (mode == DSI_COMMAND_MODE) {
 836                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 837         } else {
 838                 dsi_write(dsi, DSI_PWR_UP, RESET);
 839                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 840                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 841                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 842         }
 843 }
 844
 845 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 846 {
 847         u32 esc_clk_div;
 848
 849         dsi_write(dsi, DSI_PWR_UP, RESET);
 850         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 851                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 852
 853         /* The maximum value of the escape clock frequency is 20MHz */
 854         esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
 855         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 856                   TX_ESC_CLK_DIVIDSION(esc_clk_div));
 857 }
 858
 859 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 860                                    struct drm_display_mode *mode)
 861 {
 862         u32 val = 0, color = 0;
 863
 864         switch (dsi->format) {
 865         case MIPI_DSI_FMT_RGB888:
 866                 color = DPI_COLOR_CODING_24BIT;
 867                 break;
 868         case MIPI_DSI_FMT_RGB666:
 869                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 870                 break;
 871         case MIPI_DSI_FMT_RGB666_PACKED:
 872                 color = DPI_COLOR_CODING_18BIT_1;
 873                 break;
 874         case MIPI_DSI_FMT_RGB565:
 875                 color = DPI_COLOR_CODING_16BIT_1;
 876                 break;
 877         }
 878
 879         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 880                 val |= VSYNC_ACTIVE_LOW;
 881         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 882                 val |= HSYNC_ACTIVE_LOW;
 883
 884         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 885         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 886         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 887         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 888                   | INVACT_LPCMD_TIME(4));
 889 }
 890
 891 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 892 {
 893         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 894 }
 895
 896 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 897                                             struct drm_display_mode *mode)
 898 {
 899         int pkt_size;
 900
 901         if (dsi->slave || dsi->master)
 902                 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2 + 4);
 903         else
 904                 pkt_size = VID_PKT_SIZE(mode->hdisplay);
 905
 906         dsi_write(dsi, DSI_VID_PKT_SIZE, pkt_size);
 907 }
 908
 909 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 910 {
 911         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 912         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 913 }
 914
 915 /* Get lane byte clock cycles. */
 916 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 917                                            u32 hcomponent)
 918 {
 919         u32 lbcc;
 920
 921         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 922
 923         if (dsi->mode.clock == 0) {
 924                 dev_err(dsi->dev, "dsi mode clock is 0!\n");
 925                 return 0;
 926         }
 927
 928         return DIV_ROUND_CLOSEST_ULL(lbcc, dsi->mode.clock);
 929 }
 930
 931 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 932 {
 933         u32 htotal, hsa, hbp, lbcc;
 934         struct drm_display_mode *mode = &dsi->mode;
 935
 936         htotal = mode->htotal;
 937         hsa = mode->hsync_end - mode->hsync_start;
 938         hbp = mode->htotal - mode->hsync_end;
 939
 940         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 941         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 942
 943         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 944         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 945
 946         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 947         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 948 }
 949
 950 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 951 {
 952         u32 vactive, vsa, vfp, vbp;
 953         struct drm_display_mode *mode = &dsi->mode;
 954
 955         vactive = mode->vdisplay;
 956         vsa = mode->vsync_end - mode->vsync_start;
 957         vfp = mode->vsync_start - mode->vdisplay;
 958         vbp = mode->vtotal - mode->vsync_end;
 959
 960         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 961         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 962         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 963         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 964 }
 965
 966 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 967 {
 968         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 969                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 970
 971         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 972                   | PHY_CLKLP2HS_TIME(0x40));
 973 }
 974
 975 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 976 {
 977         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 978                   N_LANES(dsi->lanes));
 979 }
 980
 981 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 982 {
 983         dsi_read(dsi, DSI_INT_ST0);
 984         dsi_read(dsi, DSI_INT_ST1);
 985         dsi_write(dsi, DSI_INT_MSK0, 0);
 986         dsi_write(dsi, DSI_INT_MSK1, 0);
 987 }
 988
 989 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 990                                         struct drm_display_mode *mode,
 991                                         struct drm_display_mode *adjusted_mode)
 992 {
 993         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 994
 995         drm_mode_copy(&dsi->mode, adjusted_mode);
 996
 997         if (dsi->slave)
 998                 drm_mode_copy(&dsi->slave->mode, adjusted_mode);
 999 }
1000
1001 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
1002 {
1003         if (clk_prepare_enable(dsi->pclk)) {
1004                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
1005                 return;
1006         }
1007
1008         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
1009
1010         if (dsi->slave)
1011                 rockchip_dsi_pre_disable(dsi->slave);
1012 }
1013
1014 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
1015 {
1016         /* host */
1017         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
1018         dsi_write(dsi, DSI_PWR_UP, RESET);
1019
1020         /* phy */
1021         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
1022         if (dsi->dphy.phy) {
1023                 clk_disable_unprepare(dsi->dphy.hs_clk);
1024                 phy_power_off(dsi->dphy.phy);
1025         }
1026
1027         pm_runtime_put(dsi->dev);
1028         clk_disable_unprepare(dsi->pclk);
1029
1030         if (dsi->slave)
1031                 rockchip_dsi_disable(dsi->slave);
1032 }
1033
1034 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
1035 {
1036         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1037
1038         if (dsi->panel)
1039                 drm_panel_disable(dsi->panel);
1040
1041         rockchip_dsi_pre_disable(dsi);
1042
1043         if (dsi->panel)
1044                 drm_panel_unprepare(dsi->panel);
1045
1046         rockchip_dsi_disable(dsi);
1047 }
1048
1049 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
1050                                         const struct drm_display_mode *mode,
1051                                         struct drm_display_mode *adjusted_mode)
1052 {
1053         return true;
1054 }
1055
1056 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
1057 {
1058         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
1059         int val = 0;
1060
1061         if (dsi->slave) {
1062                 if (vop_id)
1063                         val = pdata->dsi0_en_bit |
1064                               (pdata->dsi0_en_bit << 16) |
1065                               pdata->dsi1_en_bit |
1066                               (pdata->dsi1_en_bit << 16);
1067                 else
1068                         val = (pdata->dsi0_en_bit << 16) |
1069                               (pdata->dsi1_en_bit << 16);
1070
1071                 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1072                 val = pdata->dsi1_masterslavez |
1073                       (pdata->dsi1_masterslavez << 16) |
1074                       (pdata->dsi1_basedir << 16);
1075                 regmap_write(dsi->grf_regmap, pdata->grf_dsi1_cfg_reg, val);
1076
1077                 if (pdata->grf_dsi0_mode_reg)
1078                         regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
1079                                      pdata->grf_dsi0_mode);
1080                 if (pdata->grf_dsi1_mode_reg1)
1081                         regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg1,
1082                                      pdata->grf_dsi1_mode);
1083                 if (pdata->grf_dsi1_mode_reg2)
1084                         regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg2,
1085                                      RK3399_GRF_DSI1_MODE2);
1086                 if (pdata->grf_dsi1_mode_reg1)
1087                         regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg1,
1088                                      RK3399_GRF_DSI1_ENABLE);
1089         } else {
1090                 if (vop_id)
1091                         val = pdata->dsi0_en_bit |
1092                               (pdata->dsi0_en_bit << 16);
1093                 else
1094                         val = pdata->dsi0_en_bit << 16;
1095
1096                 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1097
1098         }
1099
1100         dev_info(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
1101 }
1102
1103 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
1104 {
1105         if (clk_prepare_enable(dsi->pclk)) {
1106                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
1107                 return;
1108         }
1109
1110         if (clk_prepare_enable(dsi->dphy.ref_clk)) {
1111                 dev_err(dsi->dev, "Failed to enable pllref_clk\n");
1112                 return;
1113         }
1114
1115         if (dsi->dphy.phy) {
1116                 rockchip_dsi_set_hs_clk(dsi);
1117                 phy_power_on(dsi->dphy.phy);
1118         } else {
1119                 dw_mipi_dsi_get_lane_bps(dsi);
1120         }
1121
1122         pm_runtime_get_sync(dsi->dev);
1123
1124         if (dsi->rst) {
1125                 /* MIPI DSI APB software reset request. */
1126                 reset_control_assert(dsi->rst);
1127                 udelay(10);
1128                 reset_control_deassert(dsi->rst);
1129                 udelay(10);
1130         }
1131
1132         dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
1133                  dsi->lane_mbps, dsi->lanes);
1134 }
1135
1136 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
1137 {
1138         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
1139
1140         dw_mipi_dsi_init(dsi);
1141         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
1142         dw_mipi_dsi_packet_handler_config(dsi);
1143         dw_mipi_dsi_video_mode_config(dsi);
1144         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
1145         dw_mipi_dsi_command_mode_config(dsi);
1146         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
1147         dw_mipi_dsi_line_timer_config(dsi);
1148         dw_mipi_dsi_vertical_timing_config(dsi);
1149         dw_mipi_dsi_dphy_timing_config(dsi);
1150         dw_mipi_dsi_dphy_interface_config(dsi);
1151         dw_mipi_dsi_clear_err(dsi);
1152
1153                 if (pdata->grf_dsi0_mode_reg)
1154                         regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
1155                                      pdata->grf_dsi0_mode);
1156
1157
1158 }
1159
1160 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
1161 {
1162         rockchip_dsi_pre_init(dsi);
1163         rockchip_dsi_host_init(dsi);
1164         dw_mipi_dsi_phy_init(dsi);
1165
1166         if (dsi->slave)
1167                 rockchip_dsi_init(dsi->slave);
1168 }
1169
1170 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
1171 {
1172         dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
1173         clk_disable_unprepare(dsi->dphy.ref_clk);
1174         clk_disable_unprepare(dsi->pclk);
1175
1176         if (dsi->slave)
1177                 rockchip_dsi_enable(dsi->slave);
1178 }
1179
1180 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
1181 {
1182         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1183         int vop_id;
1184
1185         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
1186
1187         rockchip_dsi_init(dsi);
1188
1189         if (dsi->panel)
1190                 drm_panel_prepare(dsi->panel);
1191
1192         rockchip_dsi_enable(dsi);
1193
1194         if (dsi->panel)
1195                 drm_panel_enable(dsi->panel);
1196
1197         rockchip_dsi_grf_config(dsi, vop_id);
1198 }
1199
1200 static int
1201 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1202                                  struct drm_crtc_state *crtc_state,
1203                                  struct drm_connector_state *conn_state)
1204 {
1205         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1206         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1207         struct drm_connector *connector = conn_state->connector;
1208         struct drm_display_info *info = &connector->display_info;
1209
1210         switch (dsi->format) {
1211         case MIPI_DSI_FMT_RGB888:
1212                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1213                 break;
1214         case MIPI_DSI_FMT_RGB666:
1215                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1216                 break;
1217         case MIPI_DSI_FMT_RGB565:
1218                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1219                 break;
1220         default:
1221                 WARN_ON(1);
1222                 return -EINVAL;
1223         }
1224
1225         s->output_type = DRM_MODE_CONNECTOR_DSI;
1226         if (info->num_bus_formats)
1227                 s->bus_format = info->bus_formats[0];
1228
1229         if (dsi->slave)
1230                 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL;
1231
1232         return 0;
1233 }
1234
1235 static struct drm_encoder_helper_funcs
1236 dw_mipi_dsi_encoder_helper_funcs = {
1237         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1238         .mode_set = dw_mipi_dsi_encoder_mode_set,
1239         .enable = dw_mipi_dsi_encoder_enable,
1240         .disable = dw_mipi_dsi_encoder_disable,
1241         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1242 };
1243
1244 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1245         .destroy = drm_encoder_cleanup,
1246 };
1247
1248 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1249 {
1250         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1251
1252         return drm_panel_get_modes(dsi->panel);
1253 }
1254
1255 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1256                                         struct drm_connector *connector,
1257                                         struct drm_display_mode *mode)
1258 {
1259         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1260
1261         enum drm_mode_status mode_status = MODE_OK;
1262
1263         if (dsi->pdata->mode_valid)
1264                 mode_status = dsi->pdata->mode_valid(connector, mode);
1265
1266         return mode_status;
1267 }
1268
1269 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1270                                         struct drm_connector *connector)
1271 {
1272         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1273
1274         return &dsi->encoder;
1275 }
1276
1277 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1278 {
1279         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1280
1281         if (dsi->panel)
1282                 drm_panel_loader_protect(dsi->panel, on);
1283         if (on)
1284                 pm_runtime_get_sync(dsi->dev);
1285         else
1286                 pm_runtime_put(dsi->dev);
1287
1288         return 0;
1289 }
1290
1291 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1292         .loader_protect = dw_mipi_loader_protect,
1293         .get_modes = dw_mipi_dsi_connector_get_modes,
1294         .mode_valid = dw_mipi_dsi_mode_valid,
1295         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1296 };
1297
1298 static enum drm_connector_status
1299 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1300 {
1301         return connector_status_connected;
1302 }
1303
1304 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1305 {
1306         drm_connector_unregister(connector);
1307         drm_connector_cleanup(connector);
1308 }
1309
1310 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1311         .dpms = drm_atomic_helper_connector_dpms,
1312         .fill_modes = drm_helper_probe_single_connector_modes,
1313         .detect = dw_mipi_dsi_detect,
1314         .destroy = dw_mipi_dsi_drm_connector_destroy,
1315         .reset = drm_atomic_helper_connector_reset,
1316         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1317         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1318 };
1319
1320 static int rockchip_dsi_dual_channel_probe(struct dw_mipi_dsi *dsi)
1321 {
1322         struct device_node *np;
1323         struct platform_device *secondary;
1324
1325         np = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0);
1326         if (np) {
1327                 secondary = of_find_device_by_node(np);
1328                 dsi->slave = platform_get_drvdata(secondary);
1329                 of_node_put(np);
1330
1331                 if (!dsi->slave)
1332                         return -EPROBE_DEFER;
1333
1334                 dsi->slave->master = dsi;
1335         }
1336
1337         return 0;
1338 }
1339
1340 static int dw_mipi_dsi_register(struct drm_device *drm,
1341                                       struct dw_mipi_dsi *dsi)
1342 {
1343         struct drm_encoder *encoder = &dsi->encoder;
1344         struct drm_connector *connector = &dsi->connector;
1345         struct device *dev = dsi->dev;
1346         int ret;
1347
1348         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1349                                                              dev->of_node);
1350         /*
1351          * If we failed to find the CRTC(s) which this encoder is
1352          * supposed to be connected to, it's because the CRTC has
1353          * not been registered yet.  Defer probing, and hope that
1354          * the required CRTC is added later.
1355          */
1356         if (encoder->possible_crtcs == 0)
1357                 return -EPROBE_DEFER;
1358
1359         drm_encoder_helper_add(&dsi->encoder,
1360                                &dw_mipi_dsi_encoder_helper_funcs);
1361         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1362                          DRM_MODE_ENCODER_DSI, NULL);
1363         if (ret) {
1364                 dev_err(dev, "Failed to initialize encoder with drm\n");
1365                 return ret;
1366         }
1367
1368         drm_connector_helper_add(connector,
1369                         &dw_mipi_dsi_connector_helper_funcs);
1370
1371         drm_connector_init(drm, &dsi->connector,
1372                            &dw_mipi_dsi_atomic_connector_funcs,
1373                            DRM_MODE_CONNECTOR_DSI);
1374
1375         drm_panel_attach(dsi->panel, &dsi->connector);
1376
1377         dsi->connector.port = dev->of_node;
1378
1379         drm_mode_connector_attach_encoder(connector, encoder);
1380
1381         return 0;
1382 }
1383
1384 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1385         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1386         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1387         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1388         .dsi1_basedir = RK3288_TXRX_BASEDIR,
1389         .dsi1_masterslavez = RK3288_TXRX_MASTERSLAVEZ,
1390         .grf_dsi1_cfg_reg = RK3288_GRF_SOC_CON14,
1391         .max_data_lanes = 4,
1392         .max_bit_rate_per_lane = 1500000000,
1393         .has_vop_sel = true,
1394 };
1395
1396 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1397         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1398         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1399         .max_data_lanes = 4,
1400         .max_bit_rate_per_lane = 1000000000,
1401         .has_vop_sel = true,
1402 };
1403
1404 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1405         .max_data_lanes = 4,
1406         .max_bit_rate_per_lane = 1000000000,
1407 };
1408
1409 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1410         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1411         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1412         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1413         .grf_dsi0_mode = RK3399_GRF_DSI0_MODE,
1414         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1415         .grf_dsi1_mode = RK3399_GRF_DSI1_MODE1,
1416         .grf_dsi1_mode_reg1 = RK3399_GRF_SOC_CON23,
1417         .dsi1_basedir = RK3399_TXRX_BASEDIR,
1418         .dsi1_masterslavez = RK3399_TXRX_MASTERSLAVEZ,
1419         .dsi1_enableclk = RK3399_TXRX_ENABLECLK,
1420         .grf_dsi1_mode_reg2 = RK3399_GRF_SOC_CON24,
1421         .max_data_lanes = 4,
1422         .max_bit_rate_per_lane = 1500000000,
1423         .has_vop_sel = true,
1424 };
1425
1426 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1427         {
1428          .compatible = "rockchip,rk3288-mipi-dsi",
1429          .data = &rk3288_mipi_dsi_drv_data,
1430         }, {
1431          .compatible = "rockchip,rk3366-mipi-dsi",
1432          .data = &rk3366_mipi_dsi_drv_data,
1433         }, {
1434          .compatible = "rockchip,rk3368-mipi-dsi",
1435          .data = &rk3368_mipi_dsi_drv_data,
1436         }, {
1437          .compatible = "rockchip,rk3399-mipi-dsi",
1438          .data = &rk3399_mipi_dsi_drv_data,
1439         },
1440         { /* sentinel */ }
1441 };
1442 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1443
1444 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1445                              void *data)
1446 {
1447         struct drm_device *drm = data;
1448         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1449         int ret;
1450
1451         ret = rockchip_dsi_dual_channel_probe(dsi);
1452         if (ret)
1453                 return ret;
1454
1455         if (dsi->master)
1456                 return 0;
1457
1458         if (!dsi->panel)
1459                 return -EPROBE_DEFER;
1460
1461         ret = dw_mipi_dsi_register(drm, dsi);
1462         if (ret) {
1463                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1464                 return ret;
1465         }
1466
1467         dev_set_drvdata(dev, dsi);
1468
1469         pm_runtime_enable(dev);
1470         if (dsi->slave)
1471                 pm_runtime_enable(dsi->slave->dev);
1472
1473         return ret;
1474 }
1475
1476 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1477         void *data)
1478 {
1479         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1480
1481         pm_runtime_disable(dev);
1482         if (dsi->slave)
1483                 pm_runtime_disable(dsi->slave->dev);
1484 }
1485
1486 static const struct component_ops dw_mipi_dsi_ops = {
1487         .bind   = dw_mipi_dsi_bind,
1488         .unbind = dw_mipi_dsi_unbind,
1489 };
1490
1491 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
1492 {
1493         struct device *dev = dsi->dev;
1494
1495         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1496         if (IS_ERR(dsi->rst)) {
1497                 dev_info(dev, "no reset control specified\n");
1498                 dsi->rst = NULL;
1499         }
1500
1501         return 0;
1502 }
1503
1504 static int rockchip_dsi_grf_regmap(struct dw_mipi_dsi *dsi)
1505 {
1506         struct device_node *np = dsi->dev->of_node;
1507
1508         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1509         if (IS_ERR(dsi->grf_regmap)) {
1510                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1511                 return PTR_ERR(dsi->grf_regmap);
1512         }
1513
1514         return 0;
1515 }
1516
1517 static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
1518 {
1519         struct device *dev = dsi->dev;
1520         int ret;
1521
1522         dsi->pclk = devm_clk_get(dev, "pclk");
1523         if (IS_ERR(dsi->pclk)) {
1524                 ret = PTR_ERR(dsi->pclk);
1525                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1526                 return ret;
1527         }
1528
1529         return 0;
1530 }
1531
1532 static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
1533 {
1534         struct device *dev = dsi->dev;
1535         int ret;
1536
1537         dsi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");
1538         if (IS_ERR(dsi->dphy.phy)) {
1539                 ret = PTR_ERR(dsi->dphy.phy);
1540                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1541                 return ret;
1542         }
1543
1544         if (dsi->dphy.phy) {
1545                 dev_dbg(dev, "Use Non-SNPS PHY\n");
1546
1547                 dsi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");
1548                 if (IS_ERR(dsi->dphy.hs_clk)) {
1549                         dev_err(dev, "failed to get PHY high-speed clock\n");
1550                         return PTR_ERR(dsi->dphy.hs_clk);
1551                 }
1552         } else {
1553                 dev_dbg(dev, "Use SNPS PHY\n");
1554
1555                 dsi->dphy.ref_clk = devm_clk_get(dev, "ref");
1556                 if (IS_ERR(dsi->dphy.ref_clk)) {
1557                         dev_err(dev, "failed to get PHY reference clock\n");
1558                         return PTR_ERR(dsi->dphy.ref_clk);
1559                 }
1560
1561                 /* Check if cfg_clk provided */
1562                 dsi->dphy.cfg_clk = devm_clk_get(dev, "phy_cfg");
1563                 if (IS_ERR(dsi->dphy.cfg_clk)) {
1564                         if (PTR_ERR(dsi->dphy.cfg_clk) != -ENOENT) {
1565                                 dev_err(dev, "failed to get PHY config clk\n");
1566                                 return PTR_ERR(dsi->dphy.cfg_clk);
1567                         }
1568
1569                         /* Otherwise mark the cfg_clk pointer to NULL */
1570                         dsi->dphy.cfg_clk = NULL;
1571                 }
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int rockchip_dsi_ioremap_resource(struct platform_device *pdev,
1578                                          struct dw_mipi_dsi *dsi)
1579 {
1580         struct device *dev = &pdev->dev;
1581         struct resource *res;
1582
1583         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1584         if (!res)
1585                 return -ENODEV;
1586
1587         dsi->base = devm_ioremap_resource(dev, res);
1588         if (IS_ERR(dsi->base))
1589                 return PTR_ERR(dsi->base);
1590
1591         return 0;
1592 }
1593
1594 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1595 {
1596         struct device *dev = &pdev->dev;
1597         const struct of_device_id *of_id =
1598                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1599         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1600         struct dw_mipi_dsi *dsi;
1601         struct device_node *np = dev->of_node;
1602         int ret;
1603         int dsi_id;
1604
1605         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1606         if (!dsi)
1607                 return -ENOMEM;
1608
1609         dsi_id = of_alias_get_id(np, "dsi");
1610         if (dsi_id < 0)
1611                 dsi_id = 0;
1612
1613         dsi->id = dsi_id;
1614         dsi->dev = dev;
1615         dsi->pdata = pdata;
1616
1617         rockchip_dsi_ioremap_resource(pdev, dsi);
1618         rockchip_dsi_clk_get(dsi);
1619         rockchip_dsi_dphy_parse(dsi);
1620         rockchip_dsi_grf_regmap(dsi);
1621         rockchip_dsi_get_reset_handle(dsi);
1622
1623         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1624         dsi->dsi_host.dev = &pdev->dev;
1625
1626         ret = mipi_dsi_host_register(&dsi->dsi_host);
1627         if (ret)
1628                 return ret;
1629
1630         platform_set_drvdata(pdev, dsi);
1631         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1632         if (ret)
1633                 mipi_dsi_host_unregister(&dsi->dsi_host);
1634
1635         return ret;
1636 }
1637
1638 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1639 {
1640         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1641
1642         if (dsi)
1643                 mipi_dsi_host_unregister(&dsi->dsi_host);
1644         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1645         return 0;
1646 }
1647
1648 static struct platform_driver dw_mipi_dsi_driver = {
1649         .probe          = dw_mipi_dsi_probe,
1650         .remove         = dw_mipi_dsi_remove,
1651         .driver         = {
1652                 .of_match_table = dw_mipi_dsi_dt_ids,
1653                 .name   = DRIVER_NAME,
1654         },
1655 };
1656 module_platform_driver(dw_mipi_dsi_driver);
1657
1658 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1659 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1660 MODULE_LICENSE("GPL");
1661 MODULE_ALIAS("platform:" DRIVER_NAME);