2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/component.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/mfd/syscon.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_crtc.h>
20 #include <drm/drm_crtc_helper.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_panel.h>
25 #include <video/mipi_display.h>
27 #include "rockchip_drm_drv.h"
28 #include "rockchip_drm_vop.h"
30 #define DRIVER_NAME "dw-mipi-dsi"
32 #define RK3288_GRF_SOC_CON6 0x025c
33 #define RK3288_DSI0_SEL_VOP_LIT BIT(6)
34 #define RK3288_DSI1_SEL_VOP_LIT BIT(9)
36 #define RK3399_GRF_SOC_CON19 0x6250
37 #define RK3399_DSI0_SEL_VOP_LIT BIT(0)
38 #define RK3399_DSI1_SEL_VOP_LIT BIT(4)
40 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
41 #define RK3399_GRF_SOC_CON22 0x6258
42 #define RK3399_GRF_DSI_MODE 0xffff0000
44 #define DSI_VERSION 0x00
45 #define DSI_PWR_UP 0x04
47 #define POWERUP BIT(0)
49 #define DSI_CLKMGR_CFG 0x08
50 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
51 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
53 #define DSI_DPI_VCID 0x0c
54 #define DPI_VID(vid) (((vid) & 0x3) << 0)
56 #define DSI_DPI_COLOR_CODING 0x10
57 #define EN18_LOOSELY BIT(8)
58 #define DPI_COLOR_CODING_16BIT_1 0x0
59 #define DPI_COLOR_CODING_16BIT_2 0x1
60 #define DPI_COLOR_CODING_16BIT_3 0x2
61 #define DPI_COLOR_CODING_18BIT_1 0x3
62 #define DPI_COLOR_CODING_18BIT_2 0x4
63 #define DPI_COLOR_CODING_24BIT 0x5
65 #define DSI_DPI_CFG_POL 0x14
66 #define COLORM_ACTIVE_LOW BIT(4)
67 #define SHUTD_ACTIVE_LOW BIT(3)
68 #define HSYNC_ACTIVE_LOW BIT(2)
69 #define VSYNC_ACTIVE_LOW BIT(1)
70 #define DATAEN_ACTIVE_LOW BIT(0)
72 #define DSI_DPI_LP_CMD_TIM 0x18
73 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
74 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
76 #define DSI_DBI_CFG 0x20
77 #define DSI_DBI_CMDSIZE 0x28
79 #define DSI_PCKHDL_CFG 0x2c
80 #define EN_CRC_RX BIT(4)
81 #define EN_ECC_RX BIT(3)
83 #define EN_EOTP_RX BIT(1)
84 #define EN_EOTP_TX BIT(0)
86 #define DSI_MODE_CFG 0x34
87 #define ENABLE_VIDEO_MODE 0
88 #define ENABLE_CMD_MODE BIT(0)
90 #define DSI_VID_MODE_CFG 0x38
91 #define FRAME_BTA_ACK BIT(14)
92 #define ENABLE_LOW_POWER (0x3f << 8)
93 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
94 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
95 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
96 #define VID_MODE_TYPE_BURST 0x2
98 #define DSI_VID_PKT_SIZE 0x3c
99 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
100 #define VID_PKT_MAX_SIZE 0x3fff
102 #define DSI_VID_NUM_CHUMKS 0x40
103 #define DSI_VID_NULL_PKT_SIZE 0x44
104 #define DSI_VID_HSA_TIME 0x48
105 #define DSI_VID_HBP_TIME 0x4c
106 #define DSI_VID_HLINE_TIME 0x50
107 #define DSI_VID_VSA_LINES 0x54
108 #define DSI_VID_VBP_LINES 0x58
109 #define DSI_VID_VFP_LINES 0x5c
110 #define DSI_VID_VACTIVE_LINES 0x60
111 #define DSI_CMD_MODE_CFG 0x68
112 #define MAX_RD_PKT_SIZE_LP BIT(24)
113 #define DCS_LW_TX_LP BIT(19)
114 #define DCS_SR_0P_TX_LP BIT(18)
115 #define DCS_SW_1P_TX_LP BIT(17)
116 #define DCS_SW_0P_TX_LP BIT(16)
117 #define GEN_LW_TX_LP BIT(14)
118 #define GEN_SR_2P_TX_LP BIT(13)
119 #define GEN_SR_1P_TX_LP BIT(12)
120 #define GEN_SR_0P_TX_LP BIT(11)
121 #define GEN_SW_2P_TX_LP BIT(10)
122 #define GEN_SW_1P_TX_LP BIT(9)
123 #define GEN_SW_0P_TX_LP BIT(8)
124 #define EN_ACK_RQST BIT(1)
125 #define EN_TEAR_FX BIT(0)
127 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
140 #define DSI_GEN_HDR 0x6c
141 #define GEN_HDATA(data) (((data) & 0xffff) << 8)
142 #define GEN_HDATA_MASK (0xffff << 8)
143 #define GEN_HTYPE(type) (((type) & 0xff) << 0)
144 #define GEN_HTYPE_MASK 0xff
146 #define DSI_GEN_PLD_DATA 0x70
148 #define DSI_CMD_PKT_STATUS 0x74
149 #define GEN_CMD_EMPTY BIT(0)
150 #define GEN_CMD_FULL BIT(1)
151 #define GEN_PLD_W_EMPTY BIT(2)
152 #define GEN_PLD_W_FULL BIT(3)
153 #define GEN_PLD_R_EMPTY BIT(4)
154 #define GEN_PLD_R_FULL BIT(5)
155 #define GEN_RD_CMD_BUSY BIT(6)
157 #define DSI_TO_CNT_CFG 0x78
158 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
159 #define LPRX_TO_CNT(p) ((p) & 0xffff)
161 #define DSI_BTA_TO_CNT 0x8c
162 #define DSI_LPCLK_CTRL 0x94
163 #define AUTO_CLKLANE_CTRL BIT(1)
164 #define PHY_TXREQUESTCLKHS BIT(0)
166 #define DSI_PHY_TMR_LPCLK_CFG 0x98
167 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
168 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
170 #define DSI_PHY_TMR_CFG 0x9c
171 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
172 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
173 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
175 #define DSI_PHY_RSTZ 0xa0
176 #define PHY_DISFORCEPLL 0
177 #define PHY_ENFORCEPLL BIT(3)
178 #define PHY_DISABLECLK 0
179 #define PHY_ENABLECLK BIT(2)
181 #define PHY_UNRSTZ BIT(1)
182 #define PHY_SHUTDOWNZ 0
183 #define PHY_UNSHUTDOWNZ BIT(0)
185 #define DSI_PHY_IF_CFG 0xa4
186 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
187 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
189 #define DSI_PHY_STATUS 0xb0
191 #define STOP_STATE_CLK_LANE BIT(2)
193 #define DSI_PHY_TST_CTRL0 0xb4
194 #define PHY_TESTCLK BIT(1)
195 #define PHY_UNTESTCLK 0
196 #define PHY_TESTCLR BIT(0)
197 #define PHY_UNTESTCLR 0
199 #define DSI_PHY_TST_CTRL1 0xb8
200 #define PHY_TESTEN BIT(16)
201 #define PHY_UNTESTEN 0
202 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
203 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
205 #define DSI_INT_ST0 0xbc
206 #define DSI_INT_ST1 0xc0
207 #define DSI_INT_MSK0 0xc4
208 #define DSI_INT_MSK1 0xc8
210 #define PHY_STATUS_TIMEOUT_US 10000
211 #define CMD_PKT_STATUS_TIMEOUT_US 20000
213 #define BYPASS_VCO_RANGE BIT(7)
214 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
215 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
216 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
217 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
218 #define REF_BIAS_CUR_SEL BIT(0)
220 #define CP_CURRENT_3MA BIT(3)
221 #define CP_PROGRAM_EN BIT(7)
222 #define LPF_PROGRAM_EN BIT(6)
223 #define LPF_RESISTORS_20_KOHM 0
225 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
227 #define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
228 #define LOW_PROGRAM_EN 0
229 #define HIGH_PROGRAM_EN BIT(7)
230 #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
231 #define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
232 #define PLL_LOOP_DIV_EN BIT(5)
233 #define PLL_INPUT_DIV_EN BIT(4)
235 #define POWER_CONTROL BIT(6)
236 #define INTERNAL_REG_CURRENT BIT(3)
237 #define BIAS_BLOCK_ON BIT(2)
238 #define BANDGAP_ON BIT(0)
240 #define TER_RESISTOR_HIGH BIT(7)
241 #define TER_RESISTOR_LOW 0
242 #define LEVEL_SHIFTERS_ON BIT(6)
243 #define TER_CAL_DONE BIT(5)
244 #define SETRD_MAX (0x7 << 2)
245 #define POWER_MANAGE BIT(1)
246 #define TER_RESISTORS_ON BIT(0)
248 #define BIASEXTR_SEL(val) ((val) & 0x7)
249 #define BANDGAP_SEL(val) ((val) & 0x7)
250 #define TLP_PROGRAM_EN BIT(7)
251 #define THS_PRE_PROGRAM_EN BIT(7)
252 #define THS_ZERO_PROGRAM_EN BIT(6)
276 struct dw_mipi_dsi_plat_data {
281 u32 grf_dsi0_mode_reg;
282 unsigned int max_data_lanes;
283 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
284 struct drm_display_mode *mode);
288 struct drm_encoder encoder;
289 struct drm_connector connector;
290 struct mipi_dsi_host dsi_host;
291 struct drm_panel *panel;
293 struct regmap *grf_regmap;
296 struct clk *pllref_clk;
298 struct clk *phy_cfg_clk;
301 unsigned int lane_mbps; /* per lane */
307 struct drm_display_mode *mode;
309 const struct dw_mipi_dsi_plat_data *pdata;
312 enum dw_mipi_dsi_mode {
313 DW_MIPI_DSI_CMD_MODE,
314 DW_MIPI_DSI_VID_MODE,
317 struct dphy_pll_testdin_map {
318 unsigned int max_mbps;
322 /* The table is based on 27MHz DPHY pll reference clock. */
323 static const struct dphy_pll_testdin_map dptdin_map[] = {
324 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
325 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
326 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
327 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
328 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
329 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
330 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
331 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
332 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
333 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
336 static int max_mbps_to_testdin(unsigned int max_mbps)
340 for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
341 if (dptdin_map[i].max_mbps > max_mbps)
342 return dptdin_map[i].testdin;
348 * The controller should generate 2 frames before
349 * preparing the peripheral.
351 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
353 int refresh, two_frames;
355 refresh = drm_mode_vrefresh(dsi->mode);
356 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
360 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
362 return container_of(host, struct dw_mipi_dsi, dsi_host);
365 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
367 return container_of(con, struct dw_mipi_dsi, connector);
370 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
372 return container_of(encoder, struct dw_mipi_dsi, encoder);
374 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
376 writel(val, dsi->base + reg);
379 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
381 return readl(dsi->base + reg);
384 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
388 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
389 * is latched internally as the current test code. Test data is
390 * programmed internally by rising edge on TESTCLK.
392 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
394 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
395 PHY_TESTDIN(test_code));
397 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
399 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
400 PHY_TESTDIN(test_data));
402 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
405 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
407 int ret, testdin, vco, val;
409 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
411 testdin = max_mbps_to_testdin(dsi->lane_mbps);
414 "failed to get testdin for %dmbps lane clock\n",
419 dsi_write(dsi, DSI_PWR_UP, POWERUP);
421 if (!IS_ERR(dsi->phy_cfg_clk)) {
422 ret = clk_prepare_enable(dsi->phy_cfg_clk);
424 dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
429 dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
430 VCO_RANGE_CON_SEL(vco) |
434 dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
435 dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
436 LPF_RESISTORS_20_KOHM);
438 dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
440 dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
441 dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
442 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
444 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
447 dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
448 BIAS_BLOCK_ON | BANDGAP_ON);
450 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
451 SETRD_MAX | TER_RESISTORS_ON);
452 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
453 SETRD_MAX | POWER_MANAGE |
456 dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
457 BIASEXTR_SEL(BIASEXTR_127_7));
458 dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
459 BANDGAP_SEL(BANDGAP_96_10));
461 dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
462 dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
463 dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
465 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
466 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
469 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
470 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
472 dev_err(dsi->dev, "failed to wait for phy lock state\n");
476 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
477 val, val & STOP_STATE_CLK_LANE, 1000,
478 PHY_STATUS_TIMEOUT_US);
481 "failed to wait for phy clk lane stop state\n");
484 if (!IS_ERR(dsi->phy_cfg_clk))
485 clk_disable_unprepare(dsi->phy_cfg_clk);
490 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
493 unsigned long mpclk, pllref, tmp;
494 unsigned int m = 1, n = 1, target_mbps = 1000;
495 unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
498 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
500 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
505 mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
507 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
508 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
512 dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
515 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
518 for (i = 1; i < 6; i++) {
520 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
521 tmp = target_mbps % pre;
523 m = target_mbps / pre;
529 dsi->lane_mbps = pllref / n * m;
531 dsi->feedback_div = m;
536 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
537 struct mipi_dsi_device *device)
539 struct dw_mipi_dsi *dsi = host_to_dsi(host);
541 if (device->lanes > dsi->pdata->max_data_lanes) {
542 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
547 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
548 !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
549 dev_err(dsi->dev, "device mode is unsupported\n");
553 dsi->lanes = device->lanes;
554 dsi->channel = device->channel;
555 dsi->format = device->format;
556 dsi->panel = of_drm_find_panel(device->dev.of_node);
558 DRM_ERROR("failed to find panel\n");
565 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
566 struct mipi_dsi_device *device)
568 struct dw_mipi_dsi *dsi = host_to_dsi(host);
571 drm_panel_detach(dsi->panel);
577 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
582 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
583 sts, !(sts & GEN_CMD_FULL), 1000,
584 CMD_PKT_STATUS_TIMEOUT_US);
587 dev_err(dsi->dev, "failed to get available command FIFO\n");
591 dsi_write(dsi, DSI_GEN_HDR, val);
593 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
594 sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
595 1000, CMD_PKT_STATUS_TIMEOUT_US);
598 dev_err(dsi->dev, "failed to write command FIFO\n");
605 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
606 const struct mipi_dsi_msg *msg)
608 const u16 *tx_buf = msg->tx_buf;
609 u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
611 if (msg->tx_len > 2) {
612 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
617 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
620 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
621 const struct mipi_dsi_msg *msg)
623 const u32 *tx_buf = msg->tx_buf;
624 int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
625 u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
629 if (msg->tx_len < 3) {
630 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
635 while (DIV_ROUND_UP(len, pld_data_bytes)) {
636 if (len < pld_data_bytes) {
637 memcpy(&remainder, tx_buf, len);
638 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
641 dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
643 len -= pld_data_bytes;
646 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
647 sts, !(sts & GEN_PLD_W_FULL), 1000,
648 CMD_PKT_STATUS_TIMEOUT_US);
651 "failed to get available write payload FIFO\n");
656 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
659 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
660 const struct mipi_dsi_msg *msg)
662 struct dw_mipi_dsi *dsi = host_to_dsi(host);
666 case MIPI_DSI_DCS_SHORT_WRITE:
667 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
668 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
669 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
670 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
671 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
672 ret = dw_mipi_dsi_short_write(dsi, msg);
674 case MIPI_DSI_DCS_LONG_WRITE:
675 case MIPI_DSI_GENERIC_LONG_WRITE:
676 ret = dw_mipi_dsi_long_write(dsi, msg);
679 dev_err(dsi->dev, "unsupported message type\n");
686 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
687 .attach = dw_mipi_dsi_host_attach,
688 .detach = dw_mipi_dsi_host_detach,
689 .transfer = dw_mipi_dsi_host_transfer,
692 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
696 val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
698 dsi_write(dsi, DSI_VID_MODE_CFG, val);
701 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
702 enum dw_mipi_dsi_mode mode)
704 if (mode == DW_MIPI_DSI_CMD_MODE) {
705 dsi_write(dsi, DSI_PWR_UP, RESET);
706 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
707 dsi_write(dsi, DSI_PWR_UP, POWERUP);
709 dsi_write(dsi, DSI_PWR_UP, RESET);
710 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
711 dw_mipi_dsi_video_mode_config(dsi);
712 dsi_write(dsi, DSI_PWR_UP, POWERUP);
716 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
718 dsi_write(dsi, DSI_PWR_UP, RESET);
719 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
722 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
724 dsi_write(dsi, DSI_PWR_UP, RESET);
725 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
726 | PHY_RSTZ | PHY_SHUTDOWNZ);
727 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
728 TX_ESC_CLK_DIVIDSION(7));
729 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
732 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
733 struct drm_display_mode *mode)
735 u32 val = 0, color = 0;
737 switch (dsi->format) {
738 case MIPI_DSI_FMT_RGB888:
739 color = DPI_COLOR_CODING_24BIT;
741 case MIPI_DSI_FMT_RGB666:
742 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
744 case MIPI_DSI_FMT_RGB666_PACKED:
745 color = DPI_COLOR_CODING_18BIT_1;
747 case MIPI_DSI_FMT_RGB565:
748 color = DPI_COLOR_CODING_16BIT_1;
752 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
753 val |= VSYNC_ACTIVE_LOW;
754 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
755 val |= HSYNC_ACTIVE_LOW;
757 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
758 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
759 dsi_write(dsi, DSI_DPI_CFG_POL, val);
760 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
761 | INVACT_LPCMD_TIME(4));
764 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
766 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
769 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
770 struct drm_display_mode *mode)
772 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
775 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
777 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
778 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
779 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
780 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
783 /* Get lane byte clock cycles. */
784 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
789 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
791 frac = lbcc % dsi->mode->clock;
792 lbcc = lbcc / dsi->mode->clock;
799 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
801 u32 htotal, hsa, hbp, lbcc;
802 struct drm_display_mode *mode = dsi->mode;
804 htotal = mode->htotal;
805 hsa = mode->hsync_end - mode->hsync_start;
806 hbp = mode->htotal - mode->hsync_end;
808 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
809 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
811 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
812 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
814 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
815 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
818 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
820 u32 vactive, vsa, vfp, vbp;
821 struct drm_display_mode *mode = dsi->mode;
823 vactive = mode->vdisplay;
824 vsa = mode->vsync_end - mode->vsync_start;
825 vfp = mode->vsync_start - mode->vdisplay;
826 vbp = mode->vtotal - mode->vsync_end;
828 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
829 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
830 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
831 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
834 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
836 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
837 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
839 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
840 | PHY_CLKLP2HS_TIME(0x40));
843 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
845 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
846 N_LANES(dsi->lanes));
849 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
851 dsi_read(dsi, DSI_INT_ST0);
852 dsi_read(dsi, DSI_INT_ST1);
853 dsi_write(dsi, DSI_INT_MSK0, 0);
854 dsi_write(dsi, DSI_INT_MSK1, 0);
857 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
858 struct drm_display_mode *mode,
859 struct drm_display_mode *adjusted_mode)
861 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
864 if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
867 dsi->mode = adjusted_mode;
869 ret = dw_mipi_dsi_get_lane_bps(dsi);
873 if (clk_prepare_enable(dsi->pclk)) {
874 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
878 pm_runtime_get_sync(dsi->dev);
880 dw_mipi_dsi_init(dsi);
881 dw_mipi_dsi_dpi_config(dsi, mode);
882 dw_mipi_dsi_packet_handler_config(dsi);
883 dw_mipi_dsi_video_mode_config(dsi);
884 dw_mipi_dsi_video_packet_config(dsi, mode);
885 dw_mipi_dsi_command_mode_config(dsi);
886 dw_mipi_dsi_line_timer_config(dsi);
887 dw_mipi_dsi_vertical_timing_config(dsi);
888 dw_mipi_dsi_dphy_timing_config(dsi);
889 dw_mipi_dsi_dphy_interface_config(dsi);
890 dw_mipi_dsi_clear_err(dsi);
891 if (drm_panel_prepare(dsi->panel))
892 dev_err(dsi->dev, "failed to prepare panel\n");
894 clk_disable_unprepare(dsi->pclk);
897 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
899 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
901 if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
904 drm_panel_disable(dsi->panel);
906 if (clk_prepare_enable(dsi->pclk)) {
907 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
911 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
912 drm_panel_unprepare(dsi->panel);
913 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
916 * This is necessary to make sure the peripheral will be driven
917 * normally when the display is enabled again later.
921 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
922 dw_mipi_dsi_disable(dsi);
923 pm_runtime_put(dsi->dev);
924 clk_disable_unprepare(dsi->pclk);
925 dsi->dpms_mode = DRM_MODE_DPMS_OFF;
928 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
929 const struct drm_display_mode *mode,
930 struct drm_display_mode *adjusted_mode)
935 static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
937 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
938 const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
939 int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
942 if (clk_prepare_enable(dsi->pclk)) {
943 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
947 if (pdata->grf_dsi0_mode_reg)
948 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
949 pdata->grf_dsi0_mode);
951 dw_mipi_dsi_phy_init(dsi);
952 dw_mipi_dsi_wait_for_two_frames(dsi);
954 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
955 drm_panel_enable(dsi->panel);
957 clk_disable_unprepare(dsi->pclk);
960 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
962 val = pdata->dsi0_en_bit << 16;
964 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
965 dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
966 dsi->dpms_mode = DRM_MODE_DPMS_ON;
970 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
971 struct drm_crtc_state *crtc_state,
972 struct drm_connector_state *conn_state)
974 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
975 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
976 struct drm_connector *connector = conn_state->connector;
977 struct drm_display_info *info = &connector->display_info;
979 switch (dsi->format) {
980 case MIPI_DSI_FMT_RGB888:
981 s->output_mode = ROCKCHIP_OUT_MODE_P888;
983 case MIPI_DSI_FMT_RGB666:
984 s->output_mode = ROCKCHIP_OUT_MODE_P666;
986 case MIPI_DSI_FMT_RGB565:
987 s->output_mode = ROCKCHIP_OUT_MODE_P565;
994 s->output_type = DRM_MODE_CONNECTOR_DSI;
995 if (info->num_bus_formats)
996 s->bus_format = info->bus_formats[0];
1001 static struct drm_encoder_helper_funcs
1002 dw_mipi_dsi_encoder_helper_funcs = {
1003 .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1004 .commit = dw_mipi_dsi_encoder_commit,
1005 .mode_set = dw_mipi_dsi_encoder_mode_set,
1006 .disable = dw_mipi_dsi_encoder_disable,
1007 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1010 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1011 .destroy = drm_encoder_cleanup,
1014 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1016 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1018 return drm_panel_get_modes(dsi->panel);
1021 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1022 struct drm_connector *connector,
1023 struct drm_display_mode *mode)
1025 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1027 enum drm_mode_status mode_status = MODE_OK;
1029 if (dsi->pdata->mode_valid)
1030 mode_status = dsi->pdata->mode_valid(connector, mode);
1035 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1036 struct drm_connector *connector)
1038 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1040 return &dsi->encoder;
1043 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1044 .get_modes = dw_mipi_dsi_connector_get_modes,
1045 .mode_valid = dw_mipi_dsi_mode_valid,
1046 .best_encoder = dw_mipi_dsi_connector_best_encoder,
1049 static enum drm_connector_status
1050 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1052 return connector_status_connected;
1055 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1057 drm_connector_unregister(connector);
1058 drm_connector_cleanup(connector);
1061 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1062 .dpms = drm_atomic_helper_connector_dpms,
1063 .fill_modes = drm_helper_probe_single_connector_modes,
1064 .detect = dw_mipi_dsi_detect,
1065 .destroy = dw_mipi_dsi_drm_connector_destroy,
1066 .reset = drm_atomic_helper_connector_reset,
1067 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1068 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1071 static int dw_mipi_dsi_register(struct drm_device *drm,
1072 struct dw_mipi_dsi *dsi)
1074 struct drm_encoder *encoder = &dsi->encoder;
1075 struct drm_connector *connector = &dsi->connector;
1076 struct device *dev = dsi->dev;
1079 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1082 * If we failed to find the CRTC(s) which this encoder is
1083 * supposed to be connected to, it's because the CRTC has
1084 * not been registered yet. Defer probing, and hope that
1085 * the required CRTC is added later.
1087 if (encoder->possible_crtcs == 0)
1088 return -EPROBE_DEFER;
1090 drm_encoder_helper_add(&dsi->encoder,
1091 &dw_mipi_dsi_encoder_helper_funcs);
1092 ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1093 DRM_MODE_ENCODER_DSI, NULL);
1095 dev_err(dev, "Failed to initialize encoder with drm\n");
1099 drm_connector_helper_add(connector,
1100 &dw_mipi_dsi_connector_helper_funcs);
1102 drm_connector_init(drm, &dsi->connector,
1103 &dw_mipi_dsi_atomic_connector_funcs,
1104 DRM_MODE_CONNECTOR_DSI);
1106 drm_panel_attach(dsi->panel, &dsi->connector);
1108 dsi->connector.port = dev->of_node;
1110 drm_mode_connector_attach_encoder(connector, encoder);
1115 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1117 struct device_node *np = dsi->dev->of_node;
1119 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1120 if (IS_ERR(dsi->grf_regmap)) {
1121 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1122 return PTR_ERR(dsi->grf_regmap);
1128 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1129 .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1130 .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1131 .grf_switch_reg = RK3288_GRF_SOC_CON6,
1132 .max_data_lanes = 4,
1135 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1136 .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1137 .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1138 .grf_switch_reg = RK3399_GRF_SOC_CON19,
1139 .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1140 .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1141 .max_data_lanes = 4,
1144 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1146 .compatible = "rockchip,rk3288-mipi-dsi",
1147 .data = &rk3288_mipi_dsi_drv_data,
1149 .compatible = "rockchip,rk3399-mipi-dsi",
1150 .data = &rk3399_mipi_dsi_drv_data,
1154 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1156 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1159 struct platform_device *pdev = to_platform_device(dev);
1160 struct drm_device *drm = data;
1161 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1162 struct resource *res;
1165 dsi->dpms_mode = DRM_MODE_DPMS_OFF;
1168 return -EPROBE_DEFER;
1170 ret = rockchip_mipi_parse_dt(dsi);
1174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1178 dsi->base = devm_ioremap_resource(dev, res);
1179 if (IS_ERR(dsi->base))
1180 return PTR_ERR(dsi->base);
1182 dsi->pllref_clk = devm_clk_get(dev, "ref");
1183 if (IS_ERR(dsi->pllref_clk)) {
1184 ret = PTR_ERR(dsi->pllref_clk);
1185 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1189 dsi->pclk = devm_clk_get(dev, "pclk");
1190 if (IS_ERR(dsi->pclk)) {
1191 ret = PTR_ERR(dsi->pclk);
1192 dev_err(dev, "Unable to get pclk: %d\n", ret);
1196 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1197 if (IS_ERR(dsi->phy_cfg_clk))
1198 dev_dbg(dev, "have not phy_cfg_clk\n");
1200 ret = clk_prepare_enable(dsi->pllref_clk);
1202 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1206 ret = dw_mipi_dsi_register(drm, dsi);
1208 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1212 dev_set_drvdata(dev, dsi);
1214 pm_runtime_enable(dev);
1219 clk_disable_unprepare(dsi->pllref_clk);
1223 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1226 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1228 pm_runtime_disable(dev);
1229 clk_disable_unprepare(dsi->pllref_clk);
1232 static const struct component_ops dw_mipi_dsi_ops = {
1233 .bind = dw_mipi_dsi_bind,
1234 .unbind = dw_mipi_dsi_unbind,
1237 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1239 struct device *dev = &pdev->dev;
1240 const struct of_device_id *of_id =
1241 of_match_device(dw_mipi_dsi_dt_ids, dev);
1242 const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1243 struct dw_mipi_dsi *dsi;
1246 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1252 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1253 dsi->dsi_host.dev = &pdev->dev;
1255 ret = mipi_dsi_host_register(&dsi->dsi_host);
1259 platform_set_drvdata(pdev, dsi);
1260 ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1262 mipi_dsi_host_unregister(&dsi->dsi_host);
1267 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1269 struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1272 mipi_dsi_host_unregister(&dsi->dsi_host);
1273 component_del(&pdev->dev, &dw_mipi_dsi_ops);
1277 static struct platform_driver dw_mipi_dsi_driver = {
1278 .probe = dw_mipi_dsi_probe,
1279 .remove = dw_mipi_dsi_remove,
1281 .of_match_table = dw_mipi_dsi_dt_ids,
1282 .name = DRIVER_NAME,
1285 module_platform_driver(dw_mipi_dsi_driver);
1287 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1288 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1289 MODULE_LICENSE("GPL");
1290 MODULE_ALIAS("platform:" DRIVER_NAME);