2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/component.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/phy/phy.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/mfd/syscon.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_crtc.h>
22 #include <drm/drm_crtc_helper.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
27 #include <video/mipi_display.h>
29 #include "rockchip_drm_drv.h"
30 #include "rockchip_drm_vop.h"
32 #define DRIVER_NAME "dw-mipi-dsi"
34 #define RK3288_GRF_SOC_CON6 0x025c
35 #define RK3288_DSI0_SEL_VOP_LIT BIT(6)
36 #define RK3288_DSI1_SEL_VOP_LIT BIT(9)
38 #define RK3366_GRF_SOC_CON0 0x0400
39 #define RK3366_DSI_SEL_VOP_LIT BIT(2)
41 #define RK3399_GRF_SOC_CON19 0x6250
42 #define RK3399_DSI0_SEL_VOP_LIT BIT(0)
43 #define RK3399_DSI1_SEL_VOP_LIT BIT(4)
45 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
46 #define RK3399_GRF_SOC_CON22 0x6258
47 #define RK3399_GRF_DSI_MODE 0xffff0000
49 #define DSI_VERSION 0x00
50 #define DSI_PWR_UP 0x04
52 #define POWERUP BIT(0)
54 #define DSI_CLKMGR_CFG 0x08
55 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
56 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
58 #define DSI_DPI_VCID 0x0c
59 #define DPI_VID(vid) (((vid) & 0x3) << 0)
61 #define DSI_DPI_COLOR_CODING 0x10
62 #define EN18_LOOSELY BIT(8)
63 #define DPI_COLOR_CODING_16BIT_1 0x0
64 #define DPI_COLOR_CODING_16BIT_2 0x1
65 #define DPI_COLOR_CODING_16BIT_3 0x2
66 #define DPI_COLOR_CODING_18BIT_1 0x3
67 #define DPI_COLOR_CODING_18BIT_2 0x4
68 #define DPI_COLOR_CODING_24BIT 0x5
70 #define DSI_DPI_CFG_POL 0x14
71 #define COLORM_ACTIVE_LOW BIT(4)
72 #define SHUTD_ACTIVE_LOW BIT(3)
73 #define HSYNC_ACTIVE_LOW BIT(2)
74 #define VSYNC_ACTIVE_LOW BIT(1)
75 #define DATAEN_ACTIVE_LOW BIT(0)
77 #define DSI_DPI_LP_CMD_TIM 0x18
78 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
79 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
81 #define DSI_DBI_CFG 0x20
82 #define DSI_DBI_CMDSIZE 0x28
84 #define DSI_PCKHDL_CFG 0x2c
85 #define EN_CRC_RX BIT(4)
86 #define EN_ECC_RX BIT(3)
88 #define EN_EOTP_RX BIT(1)
89 #define EN_EOTP_TX BIT(0)
91 #define DSI_MODE_CFG 0x34
92 #define ENABLE_VIDEO_MODE 0
93 #define ENABLE_CMD_MODE BIT(0)
95 #define DSI_VID_MODE_CFG 0x38
96 #define FRAME_BTA_ACK BIT(14)
97 #define ENABLE_LOW_POWER (0x3f << 8)
98 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
99 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
100 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
101 #define VID_MODE_TYPE_BURST 0x2
103 #define DSI_VID_PKT_SIZE 0x3c
104 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
105 #define VID_PKT_MAX_SIZE 0x3fff
107 #define DSI_VID_NUM_CHUMKS 0x40
108 #define DSI_VID_NULL_PKT_SIZE 0x44
109 #define DSI_VID_HSA_TIME 0x48
110 #define DSI_VID_HBP_TIME 0x4c
111 #define DSI_VID_HLINE_TIME 0x50
112 #define DSI_VID_VSA_LINES 0x54
113 #define DSI_VID_VBP_LINES 0x58
114 #define DSI_VID_VFP_LINES 0x5c
115 #define DSI_VID_VACTIVE_LINES 0x60
116 #define DSI_CMD_MODE_CFG 0x68
117 #define MAX_RD_PKT_SIZE_LP BIT(24)
118 #define DCS_LW_TX_LP BIT(19)
119 #define DCS_SR_0P_TX_LP BIT(18)
120 #define DCS_SW_1P_TX_LP BIT(17)
121 #define DCS_SW_0P_TX_LP BIT(16)
122 #define GEN_LW_TX_LP BIT(14)
123 #define GEN_SR_2P_TX_LP BIT(13)
124 #define GEN_SR_1P_TX_LP BIT(12)
125 #define GEN_SR_0P_TX_LP BIT(11)
126 #define GEN_SW_2P_TX_LP BIT(10)
127 #define GEN_SW_1P_TX_LP BIT(9)
128 #define GEN_SW_0P_TX_LP BIT(8)
129 #define EN_ACK_RQST BIT(1)
130 #define EN_TEAR_FX BIT(0)
132 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
145 #define DSI_GEN_HDR 0x6c
146 #define GEN_HDATA(data) (((data) & 0xffff) << 8)
147 #define GEN_HDATA_MASK (0xffff << 8)
148 #define GEN_HTYPE(type) (((type) & 0xff) << 0)
149 #define GEN_HTYPE_MASK 0xff
151 #define DSI_GEN_PLD_DATA 0x70
153 #define DSI_CMD_PKT_STATUS 0x74
154 #define GEN_CMD_EMPTY BIT(0)
155 #define GEN_CMD_FULL BIT(1)
156 #define GEN_PLD_W_EMPTY BIT(2)
157 #define GEN_PLD_W_FULL BIT(3)
158 #define GEN_PLD_R_EMPTY BIT(4)
159 #define GEN_PLD_R_FULL BIT(5)
160 #define GEN_RD_CMD_BUSY BIT(6)
162 #define DSI_TO_CNT_CFG 0x78
163 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
164 #define LPRX_TO_CNT(p) ((p) & 0xffff)
166 #define DSI_BTA_TO_CNT 0x8c
167 #define DSI_LPCLK_CTRL 0x94
168 #define AUTO_CLKLANE_CTRL BIT(1)
169 #define PHY_TXREQUESTCLKHS BIT(0)
171 #define DSI_PHY_TMR_LPCLK_CFG 0x98
172 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
173 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
175 #define DSI_PHY_TMR_CFG 0x9c
176 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
177 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
178 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
180 #define DSI_PHY_RSTZ 0xa0
181 #define PHY_DISFORCEPLL 0
182 #define PHY_ENFORCEPLL BIT(3)
183 #define PHY_DISABLECLK 0
184 #define PHY_ENABLECLK BIT(2)
186 #define PHY_UNRSTZ BIT(1)
187 #define PHY_SHUTDOWNZ 0
188 #define PHY_UNSHUTDOWNZ BIT(0)
190 #define DSI_PHY_IF_CFG 0xa4
191 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
192 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
194 #define DSI_PHY_STATUS 0xb0
196 #define STOP_STATE_CLK_LANE BIT(2)
198 #define DSI_PHY_TST_CTRL0 0xb4
199 #define PHY_TESTCLK BIT(1)
200 #define PHY_UNTESTCLK 0
201 #define PHY_TESTCLR BIT(0)
202 #define PHY_UNTESTCLR 0
204 #define DSI_PHY_TST_CTRL1 0xb8
205 #define PHY_TESTEN BIT(16)
206 #define PHY_UNTESTEN 0
207 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
208 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
210 #define DSI_INT_ST0 0xbc
211 #define DSI_INT_ST1 0xc0
212 #define DSI_INT_MSK0 0xc4
213 #define DSI_INT_MSK1 0xc8
215 #define PHY_STATUS_TIMEOUT_US 10000
216 #define CMD_PKT_STATUS_TIMEOUT_US 20000
218 #define BYPASS_VCO_RANGE BIT(7)
219 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
220 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
221 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
222 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
223 #define REF_BIAS_CUR_SEL BIT(0)
225 #define CP_CURRENT_3MA BIT(3)
226 #define CP_PROGRAM_EN BIT(7)
227 #define LPF_PROGRAM_EN BIT(6)
228 #define LPF_RESISTORS_20_KOHM 0
230 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
232 #define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
233 #define LOW_PROGRAM_EN 0
234 #define HIGH_PROGRAM_EN BIT(7)
235 #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
236 #define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
237 #define PLL_LOOP_DIV_EN BIT(5)
238 #define PLL_INPUT_DIV_EN BIT(4)
240 #define POWER_CONTROL BIT(6)
241 #define INTERNAL_REG_CURRENT BIT(3)
242 #define BIAS_BLOCK_ON BIT(2)
243 #define BANDGAP_ON BIT(0)
245 #define TER_RESISTOR_HIGH BIT(7)
246 #define TER_RESISTOR_LOW 0
247 #define LEVEL_SHIFTERS_ON BIT(6)
248 #define TER_CAL_DONE BIT(5)
249 #define SETRD_MAX (0x7 << 2)
250 #define POWER_MANAGE BIT(1)
251 #define TER_RESISTORS_ON BIT(0)
253 #define BIASEXTR_SEL(val) ((val) & 0x7)
254 #define BANDGAP_SEL(val) ((val) & 0x7)
255 #define TLP_PROGRAM_EN BIT(7)
256 #define THS_PRE_PROGRAM_EN BIT(7)
257 #define THS_ZERO_PROGRAM_EN BIT(6)
281 struct dw_mipi_dsi_plat_data {
286 u32 grf_dsi0_mode_reg;
287 unsigned int max_data_lanes;
288 u32 max_bit_rate_per_lane;
290 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
291 struct drm_display_mode *mode);
295 struct drm_encoder encoder;
296 struct drm_connector connector;
297 struct mipi_dsi_host dsi_host;
299 struct drm_panel *panel;
301 struct regmap *grf_regmap;
302 struct reset_control *rst;
305 struct clk *pllref_clk;
307 struct clk *phy_cfg_clk;
309 unsigned int lane_mbps; /* per lane */
315 struct drm_display_mode mode;
317 const struct dw_mipi_dsi_plat_data *pdata;
320 enum dw_mipi_dsi_mode {
321 DW_MIPI_DSI_CMD_MODE,
322 DW_MIPI_DSI_VID_MODE,
325 struct dphy_pll_testdin_map {
326 unsigned int max_mbps;
330 /* The table is based on 27MHz DPHY pll reference clock. */
331 static const struct dphy_pll_testdin_map dptdin_map[] = {
332 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
333 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
334 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
335 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
336 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
337 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
338 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
339 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
340 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
341 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
344 static int max_mbps_to_testdin(unsigned int max_mbps)
348 for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
349 if (dptdin_map[i].max_mbps > max_mbps)
350 return dptdin_map[i].testdin;
356 * The controller should generate 2 frames before
357 * preparing the peripheral.
359 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
361 int refresh, two_frames;
363 refresh = drm_mode_vrefresh(&dsi->mode);
364 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
368 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
370 return container_of(host, struct dw_mipi_dsi, dsi_host);
373 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
375 return container_of(con, struct dw_mipi_dsi, connector);
378 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
380 return container_of(encoder, struct dw_mipi_dsi, encoder);
382 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
384 writel(val, dsi->base + reg);
387 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
389 return readl(dsi->base + reg);
392 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
396 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
397 * is latched internally as the current test code. Test data is
398 * programmed internally by rising edge on TESTCLK.
400 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
402 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
403 PHY_TESTDIN(test_code));
405 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
407 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
408 PHY_TESTDIN(test_data));
410 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
413 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
415 int ret, testdin, vco, val;
417 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
419 testdin = max_mbps_to_testdin(dsi->lane_mbps);
422 "failed to get testdin for %dmbps lane clock\n",
427 dsi_write(dsi, DSI_PWR_UP, POWERUP);
429 if (!IS_ERR(dsi->phy_cfg_clk)) {
430 ret = clk_prepare_enable(dsi->phy_cfg_clk);
432 dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
437 dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
438 VCO_RANGE_CON_SEL(vco) |
442 dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
443 dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
444 LPF_RESISTORS_20_KOHM);
446 dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
448 dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
449 dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
450 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
452 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
455 dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
456 BIAS_BLOCK_ON | BANDGAP_ON);
458 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
459 SETRD_MAX | TER_RESISTORS_ON);
460 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
461 SETRD_MAX | POWER_MANAGE |
464 dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
465 BIASEXTR_SEL(BIASEXTR_127_7));
466 dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
467 BANDGAP_SEL(BANDGAP_96_10));
469 dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
470 dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
471 dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
473 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
474 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
477 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
478 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
480 dev_err(dsi->dev, "failed to wait for phy lock state\n");
484 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
485 val, val & STOP_STATE_CLK_LANE, 1000,
486 PHY_STATUS_TIMEOUT_US);
489 "failed to wait for phy clk lane stop state\n");
492 if (!IS_ERR(dsi->phy_cfg_clk))
493 clk_disable_unprepare(dsi->phy_cfg_clk);
498 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
501 unsigned long mpclk, pllref, tmp;
502 unsigned int m = 1, n = 1, target_mbps = 1000;
503 unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
506 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
508 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
513 mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
515 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
516 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
520 dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
523 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
526 for (i = 1; i < 6; i++) {
528 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
529 tmp = target_mbps % pre;
531 m = target_mbps / pre;
537 dsi->lane_mbps = pllref / n * m;
539 dsi->feedback_div = m;
544 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
545 struct mipi_dsi_device *device)
547 struct dw_mipi_dsi *dsi = host_to_dsi(host);
549 if (device->lanes > dsi->pdata->max_data_lanes) {
550 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
555 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
556 dev_err(dsi->dev, "device mode is unsupported\n");
560 dsi->lanes = device->lanes;
561 dsi->channel = device->channel;
562 dsi->format = device->format;
563 dsi->panel = of_drm_find_panel(device->dev.of_node);
565 DRM_ERROR("failed to find panel\n");
572 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
573 struct mipi_dsi_device *device)
575 struct dw_mipi_dsi *dsi = host_to_dsi(host);
578 drm_panel_detach(dsi->panel);
584 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
589 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
590 sts, !(sts & GEN_CMD_FULL), 1000,
591 CMD_PKT_STATUS_TIMEOUT_US);
594 dev_err(dsi->dev, "failed to get available command FIFO\n");
598 dsi_write(dsi, DSI_GEN_HDR, val);
600 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
601 sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
602 1000, CMD_PKT_STATUS_TIMEOUT_US);
605 dev_err(dsi->dev, "failed to write command FIFO\n");
612 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
613 const struct mipi_dsi_msg *msg)
615 const u16 *tx_buf = msg->tx_buf;
616 u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
618 if (msg->tx_len > 2) {
619 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
624 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
627 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
628 const struct mipi_dsi_msg *msg)
630 const u32 *tx_buf = msg->tx_buf;
631 int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
632 u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
636 if (msg->tx_len < 3) {
637 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
642 while (DIV_ROUND_UP(len, pld_data_bytes)) {
643 if (len < pld_data_bytes) {
644 memcpy(&remainder, tx_buf, len);
645 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
648 dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
650 len -= pld_data_bytes;
653 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
654 sts, !(sts & GEN_PLD_W_FULL), 1000,
655 CMD_PKT_STATUS_TIMEOUT_US);
658 "failed to get available write payload FIFO\n");
663 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
666 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
667 const struct mipi_dsi_msg *msg)
669 struct dw_mipi_dsi *dsi = host_to_dsi(host);
673 case MIPI_DSI_DCS_SHORT_WRITE:
674 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
675 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
676 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
677 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
678 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
679 ret = dw_mipi_dsi_short_write(dsi, msg);
681 case MIPI_DSI_DCS_LONG_WRITE:
682 case MIPI_DSI_GENERIC_LONG_WRITE:
683 ret = dw_mipi_dsi_long_write(dsi, msg);
686 dev_err(dsi->dev, "unsupported message type\n");
693 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
694 .attach = dw_mipi_dsi_host_attach,
695 .detach = dw_mipi_dsi_host_detach,
696 .transfer = dw_mipi_dsi_host_transfer,
699 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
703 val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
705 dsi_write(dsi, DSI_VID_MODE_CFG, val);
708 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
709 enum dw_mipi_dsi_mode mode)
711 if (mode == DW_MIPI_DSI_CMD_MODE) {
712 dsi_write(dsi, DSI_PWR_UP, RESET);
713 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
714 dsi_write(dsi, DSI_PWR_UP, POWERUP);
716 dsi_write(dsi, DSI_PWR_UP, RESET);
717 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
718 dw_mipi_dsi_video_mode_config(dsi);
719 dsi_write(dsi, DSI_PWR_UP, POWERUP);
723 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
725 dsi_write(dsi, DSI_PWR_UP, RESET);
726 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
729 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
731 dsi_write(dsi, DSI_PWR_UP, RESET);
732 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
733 | PHY_RSTZ | PHY_SHUTDOWNZ);
734 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
735 TX_ESC_CLK_DIVIDSION(7));
736 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
739 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
740 struct drm_display_mode *mode)
742 u32 val = 0, color = 0;
744 switch (dsi->format) {
745 case MIPI_DSI_FMT_RGB888:
746 color = DPI_COLOR_CODING_24BIT;
748 case MIPI_DSI_FMT_RGB666:
749 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
751 case MIPI_DSI_FMT_RGB666_PACKED:
752 color = DPI_COLOR_CODING_18BIT_1;
754 case MIPI_DSI_FMT_RGB565:
755 color = DPI_COLOR_CODING_16BIT_1;
759 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
760 val |= VSYNC_ACTIVE_LOW;
761 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
762 val |= HSYNC_ACTIVE_LOW;
764 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
765 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
766 dsi_write(dsi, DSI_DPI_CFG_POL, val);
767 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
768 | INVACT_LPCMD_TIME(4));
771 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
773 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
776 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
777 struct drm_display_mode *mode)
779 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
782 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
784 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
785 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
786 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
787 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
790 /* Get lane byte clock cycles. */
791 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
796 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
798 frac = lbcc % dsi->mode.clock;
799 lbcc = lbcc / dsi->mode.clock;
806 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
808 u32 htotal, hsa, hbp, lbcc;
809 struct drm_display_mode *mode = &dsi->mode;
811 htotal = mode->htotal;
812 hsa = mode->hsync_end - mode->hsync_start;
813 hbp = mode->htotal - mode->hsync_end;
815 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
816 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
818 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
819 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
821 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
822 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
825 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
827 u32 vactive, vsa, vfp, vbp;
828 struct drm_display_mode *mode = &dsi->mode;
830 vactive = mode->vdisplay;
831 vsa = mode->vsync_end - mode->vsync_start;
832 vfp = mode->vsync_start - mode->vdisplay;
833 vbp = mode->vtotal - mode->vsync_end;
835 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
836 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
837 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
838 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
841 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
843 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
844 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
846 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
847 | PHY_CLKLP2HS_TIME(0x40));
850 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
852 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
853 N_LANES(dsi->lanes));
856 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
858 dsi_read(dsi, DSI_INT_ST0);
859 dsi_read(dsi, DSI_INT_ST1);
860 dsi_write(dsi, DSI_INT_MSK0, 0);
861 dsi_write(dsi, DSI_INT_MSK1, 0);
864 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
865 struct drm_display_mode *mode,
866 struct drm_display_mode *adjusted_mode)
868 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
870 drm_mode_copy(&dsi->mode, adjusted_mode);
873 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
875 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
877 drm_panel_disable(dsi->panel);
879 if (clk_prepare_enable(dsi->pclk)) {
880 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
884 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
885 drm_panel_unprepare(dsi->panel);
886 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
889 * This is necessary to make sure the peripheral will be driven
890 * normally when the display is enabled again later.
894 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
895 dw_mipi_dsi_disable(dsi);
896 phy_power_off(dsi->phy);
897 pm_runtime_put(dsi->dev);
898 clk_disable_unprepare(dsi->pclk);
901 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
902 const struct drm_display_mode *mode,
903 struct drm_display_mode *adjusted_mode)
908 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
910 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
911 const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
912 int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
916 if (clk_prepare_enable(dsi->pclk)) {
917 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
922 /* MIPI DSI APB software reset request. */
923 reset_control_assert(dsi->rst);
925 reset_control_deassert(dsi->rst);
929 pm_runtime_get_sync(dsi->dev);
931 phy_power_on(dsi->phy);
935 * If using the third party PHY, we get the lane
936 * rate information from PHY.
938 dsi->lane_mbps = phy_get_bus_width(dsi->phy);
940 ret = dw_mipi_dsi_get_lane_bps(dsi);
945 dw_mipi_dsi_init(dsi);
946 dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
947 dw_mipi_dsi_packet_handler_config(dsi);
948 dw_mipi_dsi_video_mode_config(dsi);
949 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
950 dw_mipi_dsi_command_mode_config(dsi);
951 dw_mipi_dsi_line_timer_config(dsi);
952 dw_mipi_dsi_vertical_timing_config(dsi);
953 dw_mipi_dsi_dphy_timing_config(dsi);
954 dw_mipi_dsi_dphy_interface_config(dsi);
955 dw_mipi_dsi_clear_err(dsi);
956 if (drm_panel_prepare(dsi->panel))
957 dev_err(dsi->dev, "failed to prepare panel\n");
959 if (pdata->grf_dsi0_mode_reg)
960 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
961 pdata->grf_dsi0_mode);
964 dw_mipi_dsi_phy_init(dsi);
966 dw_mipi_dsi_wait_for_two_frames(dsi);
968 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
969 drm_panel_enable(dsi->panel);
971 clk_disable_unprepare(dsi->pclk);
973 if (!pdata->has_vop_sel)
977 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
979 val = pdata->dsi0_en_bit << 16;
981 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
982 dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
986 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
987 struct drm_crtc_state *crtc_state,
988 struct drm_connector_state *conn_state)
990 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
991 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
992 struct drm_connector *connector = conn_state->connector;
993 struct drm_display_info *info = &connector->display_info;
995 switch (dsi->format) {
996 case MIPI_DSI_FMT_RGB888:
997 s->output_mode = ROCKCHIP_OUT_MODE_P888;
999 case MIPI_DSI_FMT_RGB666:
1000 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1002 case MIPI_DSI_FMT_RGB565:
1003 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1010 s->output_type = DRM_MODE_CONNECTOR_DSI;
1011 if (info->num_bus_formats)
1012 s->bus_format = info->bus_formats[0];
1017 static struct drm_encoder_helper_funcs
1018 dw_mipi_dsi_encoder_helper_funcs = {
1019 .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1020 .mode_set = dw_mipi_dsi_encoder_mode_set,
1021 .enable = dw_mipi_dsi_encoder_enable,
1022 .disable = dw_mipi_dsi_encoder_disable,
1023 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1026 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1027 .destroy = drm_encoder_cleanup,
1030 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1032 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1034 return drm_panel_get_modes(dsi->panel);
1037 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1038 struct drm_connector *connector,
1039 struct drm_display_mode *mode)
1041 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1043 enum drm_mode_status mode_status = MODE_OK;
1045 if (dsi->pdata->mode_valid)
1046 mode_status = dsi->pdata->mode_valid(connector, mode);
1051 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1052 struct drm_connector *connector)
1054 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1056 return &dsi->encoder;
1059 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1061 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1064 drm_panel_loader_protect(dsi->panel, on);
1066 pm_runtime_get_sync(dsi->dev);
1068 pm_runtime_put(dsi->dev);
1073 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1074 .loader_protect = dw_mipi_loader_protect,
1075 .get_modes = dw_mipi_dsi_connector_get_modes,
1076 .mode_valid = dw_mipi_dsi_mode_valid,
1077 .best_encoder = dw_mipi_dsi_connector_best_encoder,
1080 static enum drm_connector_status
1081 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1083 return connector_status_connected;
1086 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1088 drm_connector_unregister(connector);
1089 drm_connector_cleanup(connector);
1092 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1093 .dpms = drm_atomic_helper_connector_dpms,
1094 .fill_modes = drm_helper_probe_single_connector_modes,
1095 .detect = dw_mipi_dsi_detect,
1096 .destroy = dw_mipi_dsi_drm_connector_destroy,
1097 .reset = drm_atomic_helper_connector_reset,
1098 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1099 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1102 static int dw_mipi_dsi_register(struct drm_device *drm,
1103 struct dw_mipi_dsi *dsi)
1105 struct drm_encoder *encoder = &dsi->encoder;
1106 struct drm_connector *connector = &dsi->connector;
1107 struct device *dev = dsi->dev;
1110 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1113 * If we failed to find the CRTC(s) which this encoder is
1114 * supposed to be connected to, it's because the CRTC has
1115 * not been registered yet. Defer probing, and hope that
1116 * the required CRTC is added later.
1118 if (encoder->possible_crtcs == 0)
1119 return -EPROBE_DEFER;
1121 drm_encoder_helper_add(&dsi->encoder,
1122 &dw_mipi_dsi_encoder_helper_funcs);
1123 ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1124 DRM_MODE_ENCODER_DSI, NULL);
1126 dev_err(dev, "Failed to initialize encoder with drm\n");
1130 drm_connector_helper_add(connector,
1131 &dw_mipi_dsi_connector_helper_funcs);
1133 drm_connector_init(drm, &dsi->connector,
1134 &dw_mipi_dsi_atomic_connector_funcs,
1135 DRM_MODE_CONNECTOR_DSI);
1137 drm_panel_attach(dsi->panel, &dsi->connector);
1139 dsi->connector.port = dev->of_node;
1141 drm_mode_connector_attach_encoder(connector, encoder);
1146 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1148 struct device_node *np = dsi->dev->of_node;
1150 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1151 if (IS_ERR(dsi->grf_regmap)) {
1152 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1153 return PTR_ERR(dsi->grf_regmap);
1159 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1160 .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1161 .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1162 .grf_switch_reg = RK3288_GRF_SOC_CON6,
1163 .max_data_lanes = 4,
1164 .max_bit_rate_per_lane = 1500000000,
1165 .has_vop_sel = true,
1168 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1169 .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1170 .grf_switch_reg = RK3366_GRF_SOC_CON0,
1171 .max_data_lanes = 4,
1172 .max_bit_rate_per_lane = 1000000000,
1173 .has_vop_sel = true,
1176 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1177 .max_data_lanes = 4,
1178 .max_bit_rate_per_lane = 1000000000,
1181 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1182 .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1183 .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1184 .grf_switch_reg = RK3399_GRF_SOC_CON19,
1185 .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1186 .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1187 .max_data_lanes = 4,
1188 .max_bit_rate_per_lane = 1500000000,
1189 .has_vop_sel = true,
1192 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1194 .compatible = "rockchip,rk3288-mipi-dsi",
1195 .data = &rk3288_mipi_dsi_drv_data,
1197 .compatible = "rockchip,rk3366-mipi-dsi",
1198 .data = &rk3366_mipi_dsi_drv_data,
1200 .compatible = "rockchip,rk3368-mipi-dsi",
1201 .data = &rk3368_mipi_dsi_drv_data,
1203 .compatible = "rockchip,rk3399-mipi-dsi",
1204 .data = &rk3399_mipi_dsi_drv_data,
1208 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1210 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1213 struct platform_device *pdev = to_platform_device(dev);
1214 struct drm_device *drm = data;
1215 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1216 struct resource *res;
1220 return -EPROBE_DEFER;
1222 ret = rockchip_mipi_parse_dt(dsi);
1226 dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
1227 if (IS_ERR(dsi->phy)) {
1228 ret = PTR_ERR(dsi->phy);
1229 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1233 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1237 dsi->base = devm_ioremap_resource(dev, res);
1238 if (IS_ERR(dsi->base))
1239 return PTR_ERR(dsi->base);
1241 dsi->pclk = devm_clk_get(dev, "pclk");
1242 if (IS_ERR(dsi->pclk)) {
1243 ret = PTR_ERR(dsi->pclk);
1244 dev_err(dev, "Unable to get pclk: %d\n", ret);
1249 dsi->pllref_clk = devm_clk_get(dev, "ref");
1250 if (IS_ERR(dsi->pllref_clk)) {
1251 dev_info(dev, "No PHY reference clock specified\n");
1252 dsi->pllref_clk = NULL;
1256 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1257 if (IS_ERR(dsi->phy_cfg_clk)) {
1258 dev_info(dev, "No PHY APB clock specified\n");
1259 dsi->phy_cfg_clk = NULL;
1262 ret = clk_prepare_enable(dsi->pllref_clk);
1264 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1268 dsi->rst = devm_reset_control_get_optional(dev, "apb");
1269 if (IS_ERR(dsi->rst)) {
1270 dev_info(dev, "no reset control specified\n");
1274 ret = dw_mipi_dsi_register(drm, dsi);
1276 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1280 dev_set_drvdata(dev, dsi);
1282 pm_runtime_enable(dev);
1287 clk_disable_unprepare(dsi->pllref_clk);
1291 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1294 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1296 pm_runtime_disable(dev);
1297 clk_disable_unprepare(dsi->pllref_clk);
1300 static const struct component_ops dw_mipi_dsi_ops = {
1301 .bind = dw_mipi_dsi_bind,
1302 .unbind = dw_mipi_dsi_unbind,
1305 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1307 struct device *dev = &pdev->dev;
1308 const struct of_device_id *of_id =
1309 of_match_device(dw_mipi_dsi_dt_ids, dev);
1310 const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1311 struct dw_mipi_dsi *dsi;
1314 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1320 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1321 dsi->dsi_host.dev = &pdev->dev;
1323 ret = mipi_dsi_host_register(&dsi->dsi_host);
1327 platform_set_drvdata(pdev, dsi);
1328 ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1330 mipi_dsi_host_unregister(&dsi->dsi_host);
1335 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1337 struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1340 mipi_dsi_host_unregister(&dsi->dsi_host);
1341 component_del(&pdev->dev, &dw_mipi_dsi_ops);
1345 static struct platform_driver dw_mipi_dsi_driver = {
1346 .probe = dw_mipi_dsi_probe,
1347 .remove = dw_mipi_dsi_remove,
1349 .of_match_table = dw_mipi_dsi_dt_ids,
1350 .name = DRIVER_NAME,
1353 module_platform_driver(dw_mipi_dsi_driver);
1355 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1356 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1357 MODULE_LICENSE("GPL");
1358 MODULE_ALIAS("platform:" DRIVER_NAME);