drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28
  29 #include "rockchip_drm_drv.h"
  30 #include "rockchip_drm_vop.h"
  31
  32 #define DRIVER_NAME    "dw-mipi-dsi"
  33
  34 #define RK3288_GRF_SOC_CON6             0x025c
  35 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  36 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  37
  38 #define RK3399_GRF_SOC_CON19            0x6250
  39 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  40 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  41
  42 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  43 #define RK3399_GRF_SOC_CON22            0x6258
  44 #define RK3399_GRF_DSI_MODE             0xffff0000
  45
  46 #define DSI_VERSION                     0x00
  47 #define DSI_PWR_UP                      0x04
  48 #define RESET                           0
  49 #define POWERUP                         BIT(0)
  50
  51 #define DSI_CLKMGR_CFG                  0x08
  52 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  53 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  54
  55 #define DSI_DPI_VCID                    0x0c
  56 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  57
  58 #define DSI_DPI_COLOR_CODING            0x10
  59 #define EN18_LOOSELY                    BIT(8)
  60 #define DPI_COLOR_CODING_16BIT_1        0x0
  61 #define DPI_COLOR_CODING_16BIT_2        0x1
  62 #define DPI_COLOR_CODING_16BIT_3        0x2
  63 #define DPI_COLOR_CODING_18BIT_1        0x3
  64 #define DPI_COLOR_CODING_18BIT_2        0x4
  65 #define DPI_COLOR_CODING_24BIT          0x5
  66
  67 #define DSI_DPI_CFG_POL                 0x14
  68 #define COLORM_ACTIVE_LOW               BIT(4)
  69 #define SHUTD_ACTIVE_LOW                BIT(3)
  70 #define HSYNC_ACTIVE_LOW                BIT(2)
  71 #define VSYNC_ACTIVE_LOW                BIT(1)
  72 #define DATAEN_ACTIVE_LOW               BIT(0)
  73
  74 #define DSI_DPI_LP_CMD_TIM              0x18
  75 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  76 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  77
  78 #define DSI_DBI_CFG                     0x20
  79 #define DSI_DBI_CMDSIZE                 0x28
  80
  81 #define DSI_PCKHDL_CFG                  0x2c
  82 #define EN_CRC_RX                       BIT(4)
  83 #define EN_ECC_RX                       BIT(3)
  84 #define EN_BTA                          BIT(2)
  85 #define EN_EOTP_RX                      BIT(1)
  86 #define EN_EOTP_TX                      BIT(0)
  87
  88 #define DSI_MODE_CFG                    0x34
  89 #define ENABLE_VIDEO_MODE               0
  90 #define ENABLE_CMD_MODE                 BIT(0)
  91
  92 #define DSI_VID_MODE_CFG                0x38
  93 #define FRAME_BTA_ACK                   BIT(14)
  94 #define ENABLE_LOW_POWER                (0x3f << 8)
  95 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  96 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
  97 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
  98 #define VID_MODE_TYPE_BURST             0x2
  99
 100 #define DSI_VID_PKT_SIZE                0x3c
 101 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 102 #define VID_PKT_MAX_SIZE                0x3fff
 103
 104 #define DSI_VID_NUM_CHUMKS              0x40
 105 #define DSI_VID_NULL_PKT_SIZE           0x44
 106 #define DSI_VID_HSA_TIME                0x48
 107 #define DSI_VID_HBP_TIME                0x4c
 108 #define DSI_VID_HLINE_TIME              0x50
 109 #define DSI_VID_VSA_LINES               0x54
 110 #define DSI_VID_VBP_LINES               0x58
 111 #define DSI_VID_VFP_LINES               0x5c
 112 #define DSI_VID_VACTIVE_LINES           0x60
 113 #define DSI_CMD_MODE_CFG                0x68
 114 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 115 #define DCS_LW_TX_LP                    BIT(19)
 116 #define DCS_SR_0P_TX_LP                 BIT(18)
 117 #define DCS_SW_1P_TX_LP                 BIT(17)
 118 #define DCS_SW_0P_TX_LP                 BIT(16)
 119 #define GEN_LW_TX_LP                    BIT(14)
 120 #define GEN_SR_2P_TX_LP                 BIT(13)
 121 #define GEN_SR_1P_TX_LP                 BIT(12)
 122 #define GEN_SR_0P_TX_LP                 BIT(11)
 123 #define GEN_SW_2P_TX_LP                 BIT(10)
 124 #define GEN_SW_1P_TX_LP                 BIT(9)
 125 #define GEN_SW_0P_TX_LP                 BIT(8)
 126 #define EN_ACK_RQST                     BIT(1)
 127 #define EN_TEAR_FX                      BIT(0)
 128
 129 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 130                                          DCS_LW_TX_LP | \
 131                                          DCS_SR_0P_TX_LP | \
 132                                          DCS_SW_1P_TX_LP | \
 133                                          DCS_SW_0P_TX_LP | \
 134                                          GEN_LW_TX_LP | \
 135                                          GEN_SR_2P_TX_LP | \
 136                                          GEN_SR_1P_TX_LP | \
 137                                          GEN_SR_0P_TX_LP | \
 138                                          GEN_SW_2P_TX_LP | \
 139                                          GEN_SW_1P_TX_LP | \
 140                                          GEN_SW_0P_TX_LP)
 141
 142 #define DSI_GEN_HDR                     0x6c
 143 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 144 #define GEN_HDATA_MASK                  (0xffff << 8)
 145 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 146 #define GEN_HTYPE_MASK                  0xff
 147
 148 #define DSI_GEN_PLD_DATA                0x70
 149
 150 #define DSI_CMD_PKT_STATUS              0x74
 151 #define GEN_CMD_EMPTY                   BIT(0)
 152 #define GEN_CMD_FULL                    BIT(1)
 153 #define GEN_PLD_W_EMPTY                 BIT(2)
 154 #define GEN_PLD_W_FULL                  BIT(3)
 155 #define GEN_PLD_R_EMPTY                 BIT(4)
 156 #define GEN_PLD_R_FULL                  BIT(5)
 157 #define GEN_RD_CMD_BUSY                 BIT(6)
 158
 159 #define DSI_TO_CNT_CFG                  0x78
 160 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 161 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 162
 163 #define DSI_BTA_TO_CNT                  0x8c
 164 #define DSI_LPCLK_CTRL                  0x94
 165 #define AUTO_CLKLANE_CTRL               BIT(1)
 166 #define PHY_TXREQUESTCLKHS              BIT(0)
 167
 168 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 169 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 170 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 171
 172 #define DSI_PHY_TMR_CFG                 0x9c
 173 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 174 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 175 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 176
 177 #define DSI_PHY_RSTZ                    0xa0
 178 #define PHY_DISFORCEPLL                 0
 179 #define PHY_ENFORCEPLL                  BIT(3)
 180 #define PHY_DISABLECLK                  0
 181 #define PHY_ENABLECLK                   BIT(2)
 182 #define PHY_RSTZ                        0
 183 #define PHY_UNRSTZ                      BIT(1)
 184 #define PHY_SHUTDOWNZ                   0
 185 #define PHY_UNSHUTDOWNZ                 BIT(0)
 186
 187 #define DSI_PHY_IF_CFG                  0xa4
 188 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 189 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 190
 191 #define DSI_PHY_STATUS                  0xb0
 192 #define LOCK                            BIT(0)
 193 #define STOP_STATE_CLK_LANE             BIT(2)
 194
 195 #define DSI_PHY_TST_CTRL0               0xb4
 196 #define PHY_TESTCLK                     BIT(1)
 197 #define PHY_UNTESTCLK                   0
 198 #define PHY_TESTCLR                     BIT(0)
 199 #define PHY_UNTESTCLR                   0
 200
 201 #define DSI_PHY_TST_CTRL1               0xb8
 202 #define PHY_TESTEN                      BIT(16)
 203 #define PHY_UNTESTEN                    0
 204 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 205 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 206
 207 #define DSI_INT_ST0                     0xbc
 208 #define DSI_INT_ST1                     0xc0
 209 #define DSI_INT_MSK0                    0xc4
 210 #define DSI_INT_MSK1                    0xc8
 211
 212 #define PHY_STATUS_TIMEOUT_US           10000
 213 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 214
 215 #define BYPASS_VCO_RANGE        BIT(7)
 216 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 217 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 218 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 219 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 220 #define REF_BIAS_CUR_SEL        BIT(0)
 221
 222 #define CP_CURRENT_3MA          BIT(3)
 223 #define CP_PROGRAM_EN           BIT(7)
 224 #define LPF_PROGRAM_EN          BIT(6)
 225 #define LPF_RESISTORS_20_KOHM   0
 226
 227 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 228
 229 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 230 #define LOW_PROGRAM_EN          0
 231 #define HIGH_PROGRAM_EN         BIT(7)
 232 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 233 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 234 #define PLL_LOOP_DIV_EN         BIT(5)
 235 #define PLL_INPUT_DIV_EN        BIT(4)
 236
 237 #define POWER_CONTROL           BIT(6)
 238 #define INTERNAL_REG_CURRENT    BIT(3)
 239 #define BIAS_BLOCK_ON           BIT(2)
 240 #define BANDGAP_ON              BIT(0)
 241
 242 #define TER_RESISTOR_HIGH       BIT(7)
 243 #define TER_RESISTOR_LOW        0
 244 #define LEVEL_SHIFTERS_ON       BIT(6)
 245 #define TER_CAL_DONE            BIT(5)
 246 #define SETRD_MAX               (0x7 << 2)
 247 #define POWER_MANAGE            BIT(1)
 248 #define TER_RESISTORS_ON        BIT(0)
 249
 250 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 251 #define BANDGAP_SEL(val)        ((val) & 0x7)
 252 #define TLP_PROGRAM_EN          BIT(7)
 253 #define THS_PRE_PROGRAM_EN      BIT(7)
 254 #define THS_ZERO_PROGRAM_EN     BIT(6)
 255
 256 enum {
 257         BANDGAP_97_07,
 258         BANDGAP_98_05,
 259         BANDGAP_99_02,
 260         BANDGAP_100_00,
 261         BANDGAP_93_17,
 262         BANDGAP_94_15,
 263         BANDGAP_95_12,
 264         BANDGAP_96_10,
 265 };
 266
 267 enum {
 268         BIASEXTR_87_1,
 269         BIASEXTR_91_5,
 270         BIASEXTR_95_9,
 271         BIASEXTR_100,
 272         BIASEXTR_105_94,
 273         BIASEXTR_111_88,
 274         BIASEXTR_118_8,
 275         BIASEXTR_127_7,
 276 };
 277
 278 struct dw_mipi_dsi_plat_data {
 279         u32 dsi0_en_bit;
 280         u32 dsi1_en_bit;
 281         u32 grf_switch_reg;
 282         u32 grf_dsi0_mode;
 283         u32 grf_dsi0_mode_reg;
 284         unsigned int max_data_lanes;
 285         u32 max_bit_rate_per_lane;
 286         bool has_vop_sel;
 287         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 288                                            struct drm_display_mode *mode);
 289 };
 290
 291 struct dw_mipi_dsi {
 292         struct drm_encoder encoder;
 293         struct drm_connector connector;
 294         struct mipi_dsi_host dsi_host;
 295         struct phy *phy;
 296         struct drm_panel *panel;
 297         struct device *dev;
 298         struct regmap *grf_regmap;
 299         struct reset_control *rst;
 300         void __iomem *base;
 301
 302         struct clk *pllref_clk;
 303         struct clk *pclk;
 304         struct clk *phy_cfg_clk;
 305
 306         unsigned int lane_mbps; /* per lane */
 307         u32 channel;
 308         u32 lanes;
 309         u32 format;
 310         u16 input_div;
 311         u16 feedback_div;
 312         struct drm_display_mode mode;
 313
 314         const struct dw_mipi_dsi_plat_data *pdata;
 315 };
 316
 317 enum dw_mipi_dsi_mode {
 318         DW_MIPI_DSI_CMD_MODE,
 319         DW_MIPI_DSI_VID_MODE,
 320 };
 321
 322 struct dphy_pll_testdin_map {
 323         unsigned int max_mbps;
 324         u8 testdin;
 325 };
 326
 327 /* The table is based on 27MHz DPHY pll reference clock. */
 328 static const struct dphy_pll_testdin_map dptdin_map[] = {
 329         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 330         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 331         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 332         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 333         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 334         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 335         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 336         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 337         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 338         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 339 };
 340
 341 static int max_mbps_to_testdin(unsigned int max_mbps)
 342 {
 343         int i;
 344
 345         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 346                 if (dptdin_map[i].max_mbps > max_mbps)
 347                         return dptdin_map[i].testdin;
 348
 349         return -EINVAL;
 350 }
 351
 352 /*
 353  * The controller should generate 2 frames before
 354  * preparing the peripheral.
 355  */
 356 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
 357 {
 358         int refresh, two_frames;
 359
 360         refresh = drm_mode_vrefresh(&dsi->mode);
 361         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 362         msleep(two_frames);
 363 }
 364
 365 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 366 {
 367         return container_of(host, struct dw_mipi_dsi, dsi_host);
 368 }
 369
 370 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 371 {
 372         return container_of(con, struct dw_mipi_dsi, connector);
 373 }
 374
 375 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 376 {
 377         return container_of(encoder, struct dw_mipi_dsi, encoder);
 378 }
 379 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 380 {
 381         writel(val, dsi->base + reg);
 382 }
 383
 384 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 385 {
 386         return readl(dsi->base + reg);
 387 }
 388
 389 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 390                                  u8 test_data)
 391 {
 392         /*
 393          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 394          * is latched internally as the current test code. Test data is
 395          * programmed internally by rising edge on TESTCLK.
 396          */
 397         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 398
 399         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 400                                           PHY_TESTDIN(test_code));
 401
 402         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 403
 404         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 405                                           PHY_TESTDIN(test_data));
 406
 407         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 408 }
 409
 410 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 411 {
 412         int ret, testdin, vco, val;
 413
 414         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 415
 416         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 417         if (testdin < 0) {
 418                 dev_err(dsi->dev,
 419                         "failed to get testdin for %dmbps lane clock\n",
 420                         dsi->lane_mbps);
 421                 return testdin;
 422         }
 423
 424         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 425
 426         if (!IS_ERR(dsi->phy_cfg_clk)) {
 427                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 428                 if (ret) {
 429                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 430                         return ret;
 431                 }
 432         }
 433
 434         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 435                                          VCO_RANGE_CON_SEL(vco) |
 436                                          VCO_IN_CAP_CON_LOW |
 437                                          REF_BIAS_CUR_SEL);
 438
 439         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 440         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 441                                          LPF_RESISTORS_20_KOHM);
 442
 443         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 444
 445         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 446         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 447         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 448                                          LOW_PROGRAM_EN);
 449         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 450                                          HIGH_PROGRAM_EN);
 451
 452         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 453                                          BIAS_BLOCK_ON | BANDGAP_ON);
 454
 455         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 456                                          SETRD_MAX | TER_RESISTORS_ON);
 457         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 458                                          SETRD_MAX | POWER_MANAGE |
 459                                          TER_RESISTORS_ON);
 460
 461         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 462                                          BIASEXTR_SEL(BIASEXTR_127_7));
 463         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 464                                          BANDGAP_SEL(BANDGAP_96_10));
 465
 466         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 467         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 468         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 469
 470         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 471                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 472
 473
 474         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 475                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 476         if (ret < 0) {
 477                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 478                 goto phy_init_end;
 479         }
 480
 481         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 482                                  val, val & STOP_STATE_CLK_LANE, 1000,
 483                                  PHY_STATUS_TIMEOUT_US);
 484         if (ret < 0)
 485                 dev_err(dsi->dev,
 486                         "failed to wait for phy clk lane stop state\n");
 487
 488 phy_init_end:
 489         if (!IS_ERR(dsi->phy_cfg_clk))
 490                 clk_disable_unprepare(dsi->phy_cfg_clk);
 491
 492         return ret;
 493 }
 494
 495 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 496 {
 497         unsigned int i, pre;
 498         unsigned long mpclk, pllref, tmp;
 499         unsigned int m = 1, n = 1, target_mbps = 1000;
 500         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 501         int bpp;
 502
 503         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 504         if (bpp < 0) {
 505                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 506                         dsi->format);
 507                 return bpp;
 508         }
 509
 510         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 511         if (mpclk) {
 512                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 513                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 514                 if (tmp < max_mbps)
 515                         target_mbps = tmp;
 516                 else
 517                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 518         }
 519
 520         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 521         tmp = pllref;
 522
 523         for (i = 1; i < 6; i++) {
 524                 pre = pllref / i;
 525                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 526                         tmp = target_mbps % pre;
 527                         n = i;
 528                         m = target_mbps / pre;
 529                 }
 530                 if (tmp == 0)
 531                         break;
 532         }
 533
 534         dsi->lane_mbps = pllref / n * m;
 535         dsi->input_div = n;
 536         dsi->feedback_div = m;
 537
 538         return 0;
 539 }
 540
 541 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 542                                    struct mipi_dsi_device *device)
 543 {
 544         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 545
 546         if (device->lanes > dsi->pdata->max_data_lanes) {
 547                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 548                                 device->lanes);
 549                 return -EINVAL;
 550         }
 551
 552         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 553                 dev_err(dsi->dev, "device mode is unsupported\n");
 554                 return -EINVAL;
 555         }
 556
 557         dsi->lanes = device->lanes;
 558         dsi->channel = device->channel;
 559         dsi->format = device->format;
 560         dsi->panel = of_drm_find_panel(device->dev.of_node);
 561         if (!dsi->panel) {
 562                 DRM_ERROR("failed to find panel\n");
 563                 return -ENODEV;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 570                                    struct mipi_dsi_device *device)
 571 {
 572         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 573
 574         if (dsi->panel)
 575                 drm_panel_detach(dsi->panel);
 576
 577         dsi->panel = NULL;
 578         return 0;
 579 }
 580
 581 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 582 {
 583         int ret;
 584         int sts = 0;
 585
 586         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 587                                  sts, !(sts & GEN_CMD_FULL), 1000,
 588                                  CMD_PKT_STATUS_TIMEOUT_US);
 589
 590         if (ret < 0) {
 591                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 592                 return ret;
 593         }
 594
 595         dsi_write(dsi, DSI_GEN_HDR, val);
 596
 597         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 598                                  sts, sts & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
 599                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 600
 601         if (ret < 0) {
 602                 dev_err(dsi->dev, "failed to write command FIFO\n");
 603                 return ret;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int dw_mipi_dsi_short_write(struct dw_mipi_dsi *dsi,
 610                                    const struct mipi_dsi_msg *msg)
 611 {
 612         const u16 *tx_buf = msg->tx_buf;
 613         u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
 614
 615         if (msg->tx_len > 2) {
 616                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 617                         msg->tx_len);
 618                 return -EINVAL;
 619         }
 620
 621         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 622 }
 623
 624 static int dw_mipi_dsi_long_write(struct dw_mipi_dsi *dsi,
 625                                   const struct mipi_dsi_msg *msg)
 626 {
 627         const u32 *tx_buf = msg->tx_buf;
 628         int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
 629         u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 630         u32 remainder = 0;
 631         u32 sts = 0;
 632
 633         if (msg->tx_len < 3) {
 634                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 635                         msg->tx_len);
 636                 return -EINVAL;
 637         }
 638
 639         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 640                 if (len < pld_data_bytes) {
 641                         memcpy(&remainder, tx_buf, len);
 642                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 643                         len = 0;
 644                 } else {
 645                         dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
 646                         tx_buf++;
 647                         len -= pld_data_bytes;
 648                 }
 649
 650                 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 651                                          sts, !(sts & GEN_PLD_W_FULL), 1000,
 652                                          CMD_PKT_STATUS_TIMEOUT_US);
 653                 if (ret < 0) {
 654                         dev_err(dsi->dev,
 655                                 "failed to get available write payload FIFO\n");
 656                         return ret;
 657                 }
 658         }
 659
 660         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 661 }
 662
 663 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 664                                          const struct mipi_dsi_msg *msg)
 665 {
 666         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 667         int ret;
 668
 669         switch (msg->type) {
 670         case MIPI_DSI_DCS_SHORT_WRITE:
 671         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 672         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 673         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 674         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 675         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 676                 ret = dw_mipi_dsi_short_write(dsi, msg);
 677                 break;
 678         case MIPI_DSI_DCS_LONG_WRITE:
 679         case MIPI_DSI_GENERIC_LONG_WRITE:
 680                 ret = dw_mipi_dsi_long_write(dsi, msg);
 681                 break;
 682         default:
 683                 dev_err(dsi->dev, "unsupported message type\n");
 684                 ret = -EINVAL;
 685         }
 686
 687         return ret;
 688 }
 689
 690 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 691         .attach = dw_mipi_dsi_host_attach,
 692         .detach = dw_mipi_dsi_host_detach,
 693         .transfer = dw_mipi_dsi_host_transfer,
 694 };
 695
 696 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 697 {
 698         u32 val;
 699
 700         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 701
 702         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 703 }
 704
 705 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 706                                  enum dw_mipi_dsi_mode mode)
 707 {
 708         if (mode == DW_MIPI_DSI_CMD_MODE) {
 709                 dsi_write(dsi, DSI_PWR_UP, RESET);
 710                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 711                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 712         } else {
 713                 dsi_write(dsi, DSI_PWR_UP, RESET);
 714                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 715                 dw_mipi_dsi_video_mode_config(dsi);
 716                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 717         }
 718 }
 719
 720 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 721 {
 722         dsi_write(dsi, DSI_PWR_UP, RESET);
 723         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 724 }
 725
 726 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 727 {
 728         dsi_write(dsi, DSI_PWR_UP, RESET);
 729         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 730                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 731         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 732                   TX_ESC_CLK_DIVIDSION(7));
 733         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 734 }
 735
 736 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 737                                    struct drm_display_mode *mode)
 738 {
 739         u32 val = 0, color = 0;
 740
 741         switch (dsi->format) {
 742         case MIPI_DSI_FMT_RGB888:
 743                 color = DPI_COLOR_CODING_24BIT;
 744                 break;
 745         case MIPI_DSI_FMT_RGB666:
 746                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 747                 break;
 748         case MIPI_DSI_FMT_RGB666_PACKED:
 749                 color = DPI_COLOR_CODING_18BIT_1;
 750                 break;
 751         case MIPI_DSI_FMT_RGB565:
 752                 color = DPI_COLOR_CODING_16BIT_1;
 753                 break;
 754         }
 755
 756         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 757                 val |= VSYNC_ACTIVE_LOW;
 758         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 759                 val |= HSYNC_ACTIVE_LOW;
 760
 761         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 762         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 763         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 764         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 765                   | INVACT_LPCMD_TIME(4));
 766 }
 767
 768 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 769 {
 770         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 771 }
 772
 773 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 774                                             struct drm_display_mode *mode)
 775 {
 776         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 777 }
 778
 779 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 780 {
 781         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 782         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 783         dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 784         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 785 }
 786
 787 /* Get lane byte clock cycles. */
 788 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 789                                            u32 hcomponent)
 790 {
 791         u32 frac, lbcc;
 792
 793         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 794
 795         frac = lbcc % dsi->mode.clock;
 796         lbcc = lbcc / dsi->mode.clock;
 797         if (frac)
 798                 lbcc++;
 799
 800         return lbcc;
 801 }
 802
 803 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 804 {
 805         u32 htotal, hsa, hbp, lbcc;
 806         struct drm_display_mode *mode = &dsi->mode;
 807
 808         htotal = mode->htotal;
 809         hsa = mode->hsync_end - mode->hsync_start;
 810         hbp = mode->htotal - mode->hsync_end;
 811
 812         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 813         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 814
 815         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 816         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 817
 818         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 819         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 820 }
 821
 822 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 823 {
 824         u32 vactive, vsa, vfp, vbp;
 825         struct drm_display_mode *mode = &dsi->mode;
 826
 827         vactive = mode->vdisplay;
 828         vsa = mode->vsync_end - mode->vsync_start;
 829         vfp = mode->vsync_start - mode->vdisplay;
 830         vbp = mode->vtotal - mode->vsync_end;
 831
 832         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 833         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 834         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 835         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 836 }
 837
 838 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 839 {
 840         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 841                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 842
 843         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 844                   | PHY_CLKLP2HS_TIME(0x40));
 845 }
 846
 847 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 848 {
 849         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 850                   N_LANES(dsi->lanes));
 851 }
 852
 853 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 854 {
 855         dsi_read(dsi, DSI_INT_ST0);
 856         dsi_read(dsi, DSI_INT_ST1);
 857         dsi_write(dsi, DSI_INT_MSK0, 0);
 858         dsi_write(dsi, DSI_INT_MSK1, 0);
 859 }
 860
 861 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 862                                         struct drm_display_mode *mode,
 863                                         struct drm_display_mode *adjusted_mode)
 864 {
 865         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 866
 867         drm_mode_copy(&dsi->mode, adjusted_mode);
 868 }
 869
 870 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 871 {
 872         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 873
 874         drm_panel_disable(dsi->panel);
 875
 876         if (clk_prepare_enable(dsi->pclk)) {
 877                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 878                 return;
 879         }
 880
 881         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 882         drm_panel_unprepare(dsi->panel);
 883         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 884
 885         /*
 886          * This is necessary to make sure the peripheral will be driven
 887          * normally when the display is enabled again later.
 888          */
 889         msleep(120);
 890
 891         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 892         dw_mipi_dsi_disable(dsi);
 893         phy_power_off(dsi->phy);
 894         pm_runtime_put(dsi->dev);
 895         clk_disable_unprepare(dsi->pclk);
 896 }
 897
 898 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 899                                         const struct drm_display_mode *mode,
 900                                         struct drm_display_mode *adjusted_mode)
 901 {
 902         return true;
 903 }
 904
 905 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 906 {
 907         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 908         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 909         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 910         int ret;
 911         u32 val;
 912
 913         if (clk_prepare_enable(dsi->pclk)) {
 914                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 915                 return;
 916         }
 917
 918         if (dsi->rst) {
 919                 /* MIPI DSI APB software reset request. */
 920                 reset_control_assert(dsi->rst);
 921                 udelay(10);
 922                 reset_control_deassert(dsi->rst);
 923                 udelay(10);
 924         }
 925
 926         pm_runtime_get_sync(dsi->dev);
 927
 928         phy_power_on(dsi->phy);
 929
 930         if (dsi->phy) {
 931                 /*
 932                  * If using the third party PHY, we get the lane
 933                  * rate information from PHY.
 934                  */
 935                 dsi->lane_mbps = phy_get_bus_width(dsi->phy);
 936         } else {
 937                 ret = dw_mipi_dsi_get_lane_bps(dsi);
 938                 if (ret < 0)
 939                         return;
 940         }
 941
 942         dw_mipi_dsi_init(dsi);
 943         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 944         dw_mipi_dsi_packet_handler_config(dsi);
 945         dw_mipi_dsi_video_mode_config(dsi);
 946         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 947         dw_mipi_dsi_command_mode_config(dsi);
 948         dw_mipi_dsi_line_timer_config(dsi);
 949         dw_mipi_dsi_vertical_timing_config(dsi);
 950         dw_mipi_dsi_dphy_timing_config(dsi);
 951         dw_mipi_dsi_dphy_interface_config(dsi);
 952         dw_mipi_dsi_clear_err(dsi);
 953         if (drm_panel_prepare(dsi->panel))
 954                 dev_err(dsi->dev, "failed to prepare panel\n");
 955
 956         if (pdata->grf_dsi0_mode_reg)
 957                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 958                              pdata->grf_dsi0_mode);
 959
 960         if (!dsi->phy)
 961                 dw_mipi_dsi_phy_init(dsi);
 962
 963         dw_mipi_dsi_wait_for_two_frames(dsi);
 964
 965         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 966         drm_panel_enable(dsi->panel);
 967
 968         clk_disable_unprepare(dsi->pclk);
 969
 970         if (!pdata->has_vop_sel)
 971                 return;
 972
 973         if (mux)
 974                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 975         else
 976                 val = pdata->dsi0_en_bit << 16;
 977
 978         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 979         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 980 }
 981
 982 static int
 983 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 984                                  struct drm_crtc_state *crtc_state,
 985                                  struct drm_connector_state *conn_state)
 986 {
 987         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 988         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 989         struct drm_connector *connector = conn_state->connector;
 990         struct drm_display_info *info = &connector->display_info;
 991
 992         switch (dsi->format) {
 993         case MIPI_DSI_FMT_RGB888:
 994                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 995                 break;
 996         case MIPI_DSI_FMT_RGB666:
 997                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 998                 break;
 999         case MIPI_DSI_FMT_RGB565:
1000                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1001                 break;
1002         default:
1003                 WARN_ON(1);
1004                 return -EINVAL;
1005         }
1006
1007         s->output_type = DRM_MODE_CONNECTOR_DSI;
1008         if (info->num_bus_formats)
1009                 s->bus_format = info->bus_formats[0];
1010
1011         return 0;
1012 }
1013
1014 static struct drm_encoder_helper_funcs
1015 dw_mipi_dsi_encoder_helper_funcs = {
1016         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1017         .mode_set = dw_mipi_dsi_encoder_mode_set,
1018         .enable = dw_mipi_dsi_encoder_enable,
1019         .disable = dw_mipi_dsi_encoder_disable,
1020         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1021 };
1022
1023 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1024         .destroy = drm_encoder_cleanup,
1025 };
1026
1027 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1028 {
1029         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1030
1031         return drm_panel_get_modes(dsi->panel);
1032 }
1033
1034 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1035                                         struct drm_connector *connector,
1036                                         struct drm_display_mode *mode)
1037 {
1038         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1039
1040         enum drm_mode_status mode_status = MODE_OK;
1041
1042         if (dsi->pdata->mode_valid)
1043                 mode_status = dsi->pdata->mode_valid(connector, mode);
1044
1045         return mode_status;
1046 }
1047
1048 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1049                                         struct drm_connector *connector)
1050 {
1051         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1052
1053         return &dsi->encoder;
1054 }
1055
1056 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1057 {
1058         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1059
1060         if (on)
1061                 pm_runtime_get_sync(dsi->dev);
1062         else
1063                 pm_runtime_put(dsi->dev);
1064
1065         return 0;
1066 }
1067
1068 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1069         .loader_protect = dw_mipi_loader_protect,
1070         .get_modes = dw_mipi_dsi_connector_get_modes,
1071         .mode_valid = dw_mipi_dsi_mode_valid,
1072         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1073 };
1074
1075 static enum drm_connector_status
1076 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1077 {
1078         return connector_status_connected;
1079 }
1080
1081 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1082 {
1083         drm_connector_unregister(connector);
1084         drm_connector_cleanup(connector);
1085 }
1086
1087 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1088         .dpms = drm_atomic_helper_connector_dpms,
1089         .fill_modes = drm_helper_probe_single_connector_modes,
1090         .detect = dw_mipi_dsi_detect,
1091         .destroy = dw_mipi_dsi_drm_connector_destroy,
1092         .reset = drm_atomic_helper_connector_reset,
1093         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1094         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1095 };
1096
1097 static int dw_mipi_dsi_register(struct drm_device *drm,
1098                                       struct dw_mipi_dsi *dsi)
1099 {
1100         struct drm_encoder *encoder = &dsi->encoder;
1101         struct drm_connector *connector = &dsi->connector;
1102         struct device *dev = dsi->dev;
1103         int ret;
1104
1105         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1106                                                              dev->of_node);
1107         /*
1108          * If we failed to find the CRTC(s) which this encoder is
1109          * supposed to be connected to, it's because the CRTC has
1110          * not been registered yet.  Defer probing, and hope that
1111          * the required CRTC is added later.
1112          */
1113         if (encoder->possible_crtcs == 0)
1114                 return -EPROBE_DEFER;
1115
1116         drm_encoder_helper_add(&dsi->encoder,
1117                                &dw_mipi_dsi_encoder_helper_funcs);
1118         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1119                          DRM_MODE_ENCODER_DSI, NULL);
1120         if (ret) {
1121                 dev_err(dev, "Failed to initialize encoder with drm\n");
1122                 return ret;
1123         }
1124
1125         drm_connector_helper_add(connector,
1126                         &dw_mipi_dsi_connector_helper_funcs);
1127
1128         drm_connector_init(drm, &dsi->connector,
1129                            &dw_mipi_dsi_atomic_connector_funcs,
1130                            DRM_MODE_CONNECTOR_DSI);
1131
1132         drm_panel_attach(dsi->panel, &dsi->connector);
1133
1134         dsi->connector.port = dev->of_node;
1135
1136         drm_mode_connector_attach_encoder(connector, encoder);
1137
1138         return 0;
1139 }
1140
1141 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1142 {
1143         struct device_node *np = dsi->dev->of_node;
1144
1145         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1146         if (IS_ERR(dsi->grf_regmap)) {
1147                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1148                 return PTR_ERR(dsi->grf_regmap);
1149         }
1150
1151         return 0;
1152 }
1153
1154 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1155         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1156         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1157         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1158         .max_data_lanes = 4,
1159         .max_bit_rate_per_lane = 1500000000,
1160         .has_vop_sel = true,
1161 };
1162
1163 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1164         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1165         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1166         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1167         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1168         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1169         .max_data_lanes = 4,
1170         .max_bit_rate_per_lane = 1500000000,
1171         .has_vop_sel = true,
1172 };
1173
1174 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1175         .max_data_lanes = 4,
1176         .max_bit_rate_per_lane = 1000000000,
1177 };
1178
1179 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1180         {
1181          .compatible = "rockchip,rk3288-mipi-dsi",
1182          .data = &rk3288_mipi_dsi_drv_data,
1183         },{
1184          .compatible = "rockchip,rk3399-mipi-dsi",
1185          .data = &rk3399_mipi_dsi_drv_data,
1186         }, {
1187          .compatible = "rockchip,rk3368-mipi-dsi",
1188          .data = &rk3368_mipi_dsi_drv_data,
1189         },
1190         { /* sentinel */ }
1191 };
1192 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1193
1194 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1195                              void *data)
1196 {
1197         struct platform_device *pdev = to_platform_device(dev);
1198         struct drm_device *drm = data;
1199         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1200         struct resource *res;
1201         int ret;
1202
1203         if (!dsi->panel)
1204                 return -EPROBE_DEFER;
1205
1206         ret = rockchip_mipi_parse_dt(dsi);
1207         if (ret)
1208                 return ret;
1209
1210         dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
1211         if (IS_ERR(dsi->phy)) {
1212                 ret = PTR_ERR(dsi->phy);
1213                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1214                 return ret;
1215         }
1216
1217         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1218         if (!res)
1219                 return -ENODEV;
1220
1221         dsi->base = devm_ioremap_resource(dev, res);
1222         if (IS_ERR(dsi->base))
1223                 return PTR_ERR(dsi->base);
1224
1225         dsi->pclk = devm_clk_get(dev, "pclk");
1226         if (IS_ERR(dsi->pclk)) {
1227                 ret = PTR_ERR(dsi->pclk);
1228                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1229                 return ret;
1230         }
1231
1232         /* optional */
1233         dsi->pllref_clk = devm_clk_get(dev, "ref");
1234         if (IS_ERR(dsi->pllref_clk)) {
1235                 dev_info(dev, "No PHY reference clock specified\n");
1236                 dsi->pllref_clk = NULL;
1237         }
1238
1239         /* optional */
1240         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1241         if (IS_ERR(dsi->phy_cfg_clk)) {
1242                 dev_info(dev, "No PHY APB clock specified\n");
1243                 dsi->phy_cfg_clk = NULL;
1244         }
1245
1246         ret = clk_prepare_enable(dsi->pllref_clk);
1247         if (ret) {
1248                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1249                 return ret;
1250         }
1251
1252         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1253         if (IS_ERR(dsi->rst)) {
1254                 dev_info(dev, "no reset control specified\n");
1255                 dsi->rst = NULL;
1256         }
1257
1258         ret = dw_mipi_dsi_register(drm, dsi);
1259         if (ret) {
1260                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1261                 goto err_pllref;
1262         }
1263
1264         dev_set_drvdata(dev, dsi);
1265
1266         pm_runtime_enable(dev);
1267
1268         return 0;
1269
1270 err_pllref:
1271         clk_disable_unprepare(dsi->pllref_clk);
1272         return ret;
1273 }
1274
1275 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1276         void *data)
1277 {
1278         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1279
1280         pm_runtime_disable(dev);
1281         clk_disable_unprepare(dsi->pllref_clk);
1282 }
1283
1284 static const struct component_ops dw_mipi_dsi_ops = {
1285         .bind   = dw_mipi_dsi_bind,
1286         .unbind = dw_mipi_dsi_unbind,
1287 };
1288
1289 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1290 {
1291         struct device *dev = &pdev->dev;
1292         const struct of_device_id *of_id =
1293                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1294         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1295         struct dw_mipi_dsi *dsi;
1296         int ret;
1297
1298         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1299         if (!dsi)
1300                 return -ENOMEM;
1301
1302         dsi->dev = dev;
1303         dsi->pdata = pdata;
1304         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1305         dsi->dsi_host.dev = &pdev->dev;
1306
1307         ret = mipi_dsi_host_register(&dsi->dsi_host);
1308         if (ret)
1309                 return ret;
1310
1311         platform_set_drvdata(pdev, dsi);
1312         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1313         if (ret)
1314                 mipi_dsi_host_unregister(&dsi->dsi_host);
1315
1316         return ret;
1317 }
1318
1319 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1320 {
1321         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1322
1323         if (dsi)
1324                 mipi_dsi_host_unregister(&dsi->dsi_host);
1325         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1326         return 0;
1327 }
1328
1329 static struct platform_driver dw_mipi_dsi_driver = {
1330         .probe          = dw_mipi_dsi_probe,
1331         .remove         = dw_mipi_dsi_remove,
1332         .driver         = {
1333                 .of_match_table = dw_mipi_dsi_dt_ids,
1334                 .name   = DRIVER_NAME,
1335         },
1336 };
1337 module_platform_driver(dw_mipi_dsi_driver);
1338
1339 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1340 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1341 MODULE_LICENSE("GPL");
1342 MODULE_ALIAS("platform:" DRIVER_NAME);