2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/component.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/phy/phy.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/mfd/syscon.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_crtc.h>
22 #include <drm/drm_crtc_helper.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
27 #include <video/mipi_display.h>
28 #include <asm/unaligned.h>
30 #include "rockchip_drm_drv.h"
31 #include "rockchip_drm_vop.h"
33 #define DRIVER_NAME "dw-mipi-dsi"
35 #define RK3288_GRF_SOC_CON6 0x025c
36 #define RK3288_DSI0_SEL_VOP_LIT BIT(6)
37 #define RK3288_DSI1_SEL_VOP_LIT BIT(9)
39 #define RK3288_GRF_SOC_CON9 0x0268
41 #define RK3288_GRF_SOC_CON14 0x027c
42 #define RK3288_TXRX_BASEDIR BIT(15)
43 #define RK3288_TXRX_MASTERSLAVEZ BIT(14)
44 #define RK3288_TXRX_CLKEN BIT(12)
46 #define RK3366_GRF_SOC_CON0 0x0400
47 #define RK3366_DSI_SEL_VOP_LIT BIT(2)
49 #define RK3399_GRF_SOC_CON19 0x6250
50 #define RK3399_DSI0_SEL_VOP_LIT BIT(0)
51 #define RK3399_DSI1_SEL_VOP_LIT BIT(4)
53 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
54 #define RK3399_GRF_SOC_CON22 0x6258
55 #define RK3399_GRF_DSI_MODE 0xffff0000
57 #define DSI_VERSION 0x00
58 #define DSI_PWR_UP 0x04
60 #define POWERUP BIT(0)
62 #define DSI_CLKMGR_CFG 0x08
63 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
64 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
66 #define DSI_DPI_VCID 0x0c
67 #define DPI_VID(vid) (((vid) & 0x3) << 0)
69 #define DSI_DPI_COLOR_CODING 0x10
70 #define EN18_LOOSELY BIT(8)
71 #define DPI_COLOR_CODING_16BIT_1 0x0
72 #define DPI_COLOR_CODING_16BIT_2 0x1
73 #define DPI_COLOR_CODING_16BIT_3 0x2
74 #define DPI_COLOR_CODING_18BIT_1 0x3
75 #define DPI_COLOR_CODING_18BIT_2 0x4
76 #define DPI_COLOR_CODING_24BIT 0x5
78 #define DSI_DPI_CFG_POL 0x14
79 #define COLORM_ACTIVE_LOW BIT(4)
80 #define SHUTD_ACTIVE_LOW BIT(3)
81 #define HSYNC_ACTIVE_LOW BIT(2)
82 #define VSYNC_ACTIVE_LOW BIT(1)
83 #define DATAEN_ACTIVE_LOW BIT(0)
85 #define DSI_DPI_LP_CMD_TIM 0x18
86 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
87 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
89 #define DSI_DBI_CFG 0x20
90 #define DSI_DBI_CMDSIZE 0x28
92 #define DSI_PCKHDL_CFG 0x2c
93 #define EN_CRC_RX BIT(4)
94 #define EN_ECC_RX BIT(3)
96 #define EN_EOTP_RX BIT(1)
97 #define EN_EOTP_TX BIT(0)
99 #define DSI_MODE_CFG 0x34
100 #define ENABLE_VIDEO_MODE 0
101 #define ENABLE_CMD_MODE BIT(0)
103 #define DSI_VID_MODE_CFG 0x38
104 #define VPG_EN BIT(16)
105 #define FRAME_BTA_ACK BIT(14)
106 #define LP_HFP_EN BIT(13)
107 #define LP_HBP_EN BIT(12)
108 #define ENABLE_LOW_POWER (0xf << 8)
109 #define ENABLE_LOW_POWER_MASK (0xf << 8)
110 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
111 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
112 #define VID_MODE_TYPE_BURST 0x2
114 #define DSI_VID_PKT_SIZE 0x3c
115 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
116 #define VID_PKT_MAX_SIZE 0x3fff
118 #define DSI_VID_NUM_CHUMKS 0x40
119 #define DSI_VID_NULL_PKT_SIZE 0x44
120 #define DSI_VID_HSA_TIME 0x48
121 #define DSI_VID_HBP_TIME 0x4c
122 #define DSI_VID_HLINE_TIME 0x50
123 #define DSI_VID_VSA_LINES 0x54
124 #define DSI_VID_VBP_LINES 0x58
125 #define DSI_VID_VFP_LINES 0x5c
126 #define DSI_VID_VACTIVE_LINES 0x60
127 #define DSI_CMD_MODE_CFG 0x68
128 #define MAX_RD_PKT_SIZE_LP BIT(24)
129 #define DCS_LW_TX_LP BIT(19)
130 #define DCS_SR_0P_TX_LP BIT(18)
131 #define DCS_SW_1P_TX_LP BIT(17)
132 #define DCS_SW_0P_TX_LP BIT(16)
133 #define GEN_LW_TX_LP BIT(14)
134 #define GEN_SR_2P_TX_LP BIT(13)
135 #define GEN_SR_1P_TX_LP BIT(12)
136 #define GEN_SR_0P_TX_LP BIT(11)
137 #define GEN_SW_2P_TX_LP BIT(10)
138 #define GEN_SW_1P_TX_LP BIT(9)
139 #define GEN_SW_0P_TX_LP BIT(8)
140 #define EN_ACK_RQST BIT(1)
141 #define EN_TEAR_FX BIT(0)
143 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
156 #define DSI_GEN_HDR 0x6c
157 #define GEN_HDATA(data) (((data) & 0xffff) << 8)
158 #define GEN_HDATA_MASK (0xffff << 8)
159 #define GEN_HTYPE(type) (((type) & 0xff) << 0)
160 #define GEN_HTYPE_MASK 0xff
162 #define DSI_GEN_PLD_DATA 0x70
164 #define DSI_CMD_PKT_STATUS 0x74
165 #define GEN_CMD_EMPTY BIT(0)
166 #define GEN_CMD_FULL BIT(1)
167 #define GEN_PLD_W_EMPTY BIT(2)
168 #define GEN_PLD_W_FULL BIT(3)
169 #define GEN_PLD_R_EMPTY BIT(4)
170 #define GEN_PLD_R_FULL BIT(5)
171 #define GEN_RD_CMD_BUSY BIT(6)
173 #define DSI_TO_CNT_CFG 0x78
174 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
175 #define LPRX_TO_CNT(p) ((p) & 0xffff)
177 #define DSI_BTA_TO_CNT 0x8c
178 #define DSI_LPCLK_CTRL 0x94
179 #define AUTO_CLKLANE_CTRL BIT(1)
180 #define PHY_TXREQUESTCLKHS BIT(0)
182 #define DSI_PHY_TMR_LPCLK_CFG 0x98
183 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
184 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
186 #define DSI_PHY_TMR_CFG 0x9c
187 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
188 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
189 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
191 #define DSI_PHY_RSTZ 0xa0
192 #define PHY_DISFORCEPLL 0
193 #define PHY_ENFORCEPLL BIT(3)
194 #define PHY_DISABLECLK 0
195 #define PHY_ENABLECLK BIT(2)
197 #define PHY_UNRSTZ BIT(1)
198 #define PHY_SHUTDOWNZ 0
199 #define PHY_UNSHUTDOWNZ BIT(0)
201 #define DSI_PHY_IF_CFG 0xa4
202 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
203 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
205 #define DSI_PHY_STATUS 0xb0
207 #define STOP_STATE_CLK_LANE BIT(2)
209 #define DSI_PHY_TST_CTRL0 0xb4
210 #define PHY_TESTCLK BIT(1)
211 #define PHY_UNTESTCLK 0
212 #define PHY_TESTCLR BIT(0)
213 #define PHY_UNTESTCLR 0
215 #define DSI_PHY_TST_CTRL1 0xb8
216 #define PHY_TESTEN BIT(16)
217 #define PHY_UNTESTEN 0
218 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
219 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
221 #define DSI_INT_ST0 0xbc
222 #define DSI_INT_ST1 0xc0
223 #define DSI_INT_MSK0 0xc4
224 #define DSI_INT_MSK1 0xc8
226 #define PHY_STATUS_TIMEOUT_US 10000
227 #define CMD_PKT_STATUS_TIMEOUT_US 20000
229 #define BYPASS_VCO_RANGE BIT(7)
230 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
231 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
232 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
233 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
234 #define REF_BIAS_CUR_SEL BIT(0)
236 #define CP_CURRENT_3MA BIT(3)
237 #define CP_PROGRAM_EN BIT(7)
238 #define LPF_PROGRAM_EN BIT(6)
239 #define LPF_RESISTORS_20_KOHM 0
241 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
243 #define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
244 #define LOW_PROGRAM_EN 0
245 #define HIGH_PROGRAM_EN BIT(7)
246 #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
247 #define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
248 #define PLL_LOOP_DIV_EN BIT(5)
249 #define PLL_INPUT_DIV_EN BIT(4)
251 #define POWER_CONTROL BIT(6)
252 #define INTERNAL_REG_CURRENT BIT(3)
253 #define BIAS_BLOCK_ON BIT(2)
254 #define BANDGAP_ON BIT(0)
256 #define TER_RESISTOR_HIGH BIT(7)
257 #define TER_RESISTOR_LOW 0
258 #define LEVEL_SHIFTERS_ON BIT(6)
259 #define TER_CAL_DONE BIT(5)
260 #define SETRD_MAX (0x7 << 2)
261 #define POWER_MANAGE BIT(1)
262 #define TER_RESISTORS_ON BIT(0)
264 #define BIASEXTR_SEL(val) ((val) & 0x7)
265 #define BANDGAP_SEL(val) ((val) & 0x7)
266 #define TLP_PROGRAM_EN BIT(7)
267 #define THS_PRE_PROGRAM_EN BIT(7)
268 #define THS_ZERO_PROGRAM_EN BIT(6)
292 struct dw_mipi_dsi_plat_data {
297 u32 grf_dsi0_mode_reg;
299 u32 dsi1_masterslavez;
300 u32 grf_dsi1_cfg_reg;
301 unsigned int max_data_lanes;
302 u32 max_bit_rate_per_lane;
304 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
305 struct drm_display_mode *mode);
321 struct drm_encoder encoder;
322 struct drm_connector connector;
323 struct mipi_dsi_host dsi_host;
324 struct mipi_dphy dphy;
325 struct drm_panel *panel;
327 struct regmap *grf_regmap;
328 struct reset_control *rst;
333 struct dw_mipi_dsi *master;
334 struct dw_mipi_dsi *slave;
335 struct device_node *panel_node;
338 unsigned long mode_flags;
339 unsigned int lane_mbps; /* per lane */
343 struct drm_display_mode mode;
345 const struct dw_mipi_dsi_plat_data *pdata;
348 enum dw_mipi_dsi_mode {
353 struct dphy_pll_testdin_map {
354 unsigned int max_mbps;
358 /* The table is based on 27MHz DPHY pll reference clock. */
359 static const struct dphy_pll_testdin_map dptdin_map[] = {
360 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
361 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
362 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
363 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
364 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
365 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
366 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
367 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
368 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
369 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
372 static int max_mbps_to_testdin(unsigned int max_mbps)
376 for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
377 if (dptdin_map[i].max_mbps > max_mbps)
378 return dptdin_map[i].testdin;
383 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
385 return container_of(host, struct dw_mipi_dsi, dsi_host);
388 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
390 return container_of(con, struct dw_mipi_dsi, connector);
393 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
395 return container_of(encoder, struct dw_mipi_dsi, encoder);
397 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
399 writel(val, dsi->base + reg);
402 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
404 return readl(dsi->base + reg);
407 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
412 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
413 sts, !(sts & GEN_PLD_W_FULL), 10,
414 CMD_PKT_STATUS_TIMEOUT_US);
416 dev_err(dsi->dev, "generic write payload fifo is full\n");
423 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
428 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
429 sts, !(sts & GEN_CMD_FULL), 10,
430 CMD_PKT_STATUS_TIMEOUT_US);
432 dev_err(dsi->dev, "generic write cmd fifo is full\n");
439 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
445 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
446 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
447 sts, (sts & mask) == mask, 10,
448 CMD_PKT_STATUS_TIMEOUT_US);
450 dev_err(dsi->dev, "generic write fifo is full\n");
457 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
461 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
462 * is latched internally as the current test code. Test data is
463 * programmed internally by rising edge on TESTCLK.
465 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
467 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
468 PHY_TESTDIN(test_code));
470 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
472 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
473 PHY_TESTDIN(test_data));
475 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
478 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
480 int ret, testdin, vco, val;
482 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
484 testdin = max_mbps_to_testdin(dsi->lane_mbps);
487 "failed to get testdin for %dmbps lane clock\n",
492 dsi_write(dsi, DSI_PWR_UP, POWERUP);
494 if (!IS_ERR(dsi->dphy.cfg_clk)) {
495 ret = clk_prepare_enable(dsi->dphy.cfg_clk);
497 dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
502 dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
503 VCO_RANGE_CON_SEL(vco) |
507 dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
508 dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
509 LPF_RESISTORS_20_KOHM);
511 dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
513 dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
514 val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
515 dw_mipi_dsi_phy_write(dsi, 0x18, val);
516 val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
517 dw_mipi_dsi_phy_write(dsi, 0x18, val);
518 dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
520 dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
521 BIAS_BLOCK_ON | BANDGAP_ON);
523 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
524 SETRD_MAX | TER_RESISTORS_ON);
525 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
526 SETRD_MAX | POWER_MANAGE |
529 dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
530 BIASEXTR_SEL(BIASEXTR_127_7));
531 dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
532 BANDGAP_SEL(BANDGAP_96_10));
534 dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
535 dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
536 dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
538 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
539 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
541 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
542 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
544 dev_err(dsi->dev, "failed to wait for phy lock state\n");
548 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
549 val, val & STOP_STATE_CLK_LANE, 1000,
550 PHY_STATUS_TIMEOUT_US);
553 "failed to wait for phy clk lane stop state\n");
556 if (!IS_ERR(dsi->dphy.cfg_clk))
557 clk_disable_unprepare(dsi->dphy.cfg_clk);
562 static unsigned long rockchip_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
565 unsigned long mpclk, tmp;
566 unsigned long target_mbps = 1000;
568 struct device_node *np = dsi->dev->of_node;
569 unsigned int max_mbps;
572 /* optional override of the desired bandwidth */
573 if (!of_property_read_u32(np, "rockchip,lane-rate", &value))
576 max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
578 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
580 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
585 lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
587 mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
589 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
590 tmp = mpclk * (bpp / lanes) * 10 / 9;
594 dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
600 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
603 unsigned long pllref, tmp;
604 unsigned int m = 1, n = 1;
605 unsigned long target_mbps;
610 target_mbps = rockchip_dsi_calc_bandwidth(dsi);
612 pllref = DIV_ROUND_UP(clk_get_rate(dsi->dphy.ref_clk), USEC_PER_SEC);
615 for (i = 1; i < 6; i++) {
617 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
618 tmp = target_mbps % pre;
620 m = target_mbps / pre;
626 dsi->lane_mbps = pllref / n * m;
627 dsi->dphy.input_div = n;
628 dsi->dphy.feedback_div = m;
630 dsi->slave->lane_mbps = dsi->lane_mbps;
631 dsi->slave->dphy.input_div = n;
632 dsi->slave->dphy.feedback_div = m;
638 static void rockchip_dsi_set_hs_clk(struct dw_mipi_dsi *dsi)
641 unsigned long target_mbps;
642 unsigned long bw, rate;
644 target_mbps = rockchip_dsi_calc_bandwidth(dsi);
645 bw = target_mbps * USEC_PER_SEC;
647 rate = clk_round_rate(dsi->dphy.hs_clk, bw);
648 ret = clk_set_rate(dsi->dphy.hs_clk, rate);
650 dev_err(dsi->dev, "failed to set hs clock rate: %lu\n",
653 clk_prepare_enable(dsi->dphy.hs_clk);
655 dsi->lane_mbps = rate / USEC_PER_SEC;
658 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
659 struct mipi_dsi_device *device)
661 struct dw_mipi_dsi *dsi = host_to_dsi(host);
667 lanes = dsi->slave ? device->lanes / 2 : device->lanes;
669 if (lanes > dsi->pdata->max_data_lanes) {
670 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
675 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
676 dev_err(dsi->dev, "device mode is unsupported\n");
681 dsi->channel = device->channel;
682 dsi->format = device->format;
683 dsi->mode_flags = device->mode_flags;
686 dsi->slave->lanes = lanes;
687 dsi->slave->channel = device->channel;
688 dsi->slave->format = device->format;
689 dsi->slave->mode_flags = device->mode_flags;
692 dsi->panel = of_drm_find_panel(device->dev.of_node);
694 DRM_ERROR("failed to find panel\n");
701 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
702 struct mipi_dsi_device *device)
704 struct dw_mipi_dsi *dsi = host_to_dsi(host);
707 drm_panel_detach(dsi->panel);
713 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
715 if (flags & MIPI_DSI_MSG_USE_LPM) {
716 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
717 dsi_write(dsi, DSI_LPCLK_CTRL, 0);
719 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
720 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
724 static ssize_t rockchip_dsi_send_packet(struct dw_mipi_dsi *dsi,
725 const struct mipi_dsi_msg *msg)
727 struct mipi_dsi_packet packet;
730 int len = msg->tx_len;
732 /* create a packet to the DSI protocol */
733 ret = mipi_dsi_create_packet(&packet, msg);
735 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
739 rockchip_set_transfer_mode(dsi, msg->flags);
742 while (DIV_ROUND_UP(packet.payload_length, 4)) {
744 * Alternatively, you can always keep the FIFO
745 * nearly full by monitoring the FIFO state until
746 * it is not full, and then writea single word of data.
747 * This solution is more resource consuming
748 * but it simultaneously avoids FIFO starvation,
749 * making it possible to use FIFO sizes smaller than
750 * the amount of data of the longest packet to be written.
752 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
756 if (packet.payload_length < 4) {
757 /* send residu payload */
759 memcpy(&val, packet.payload, packet.payload_length);
760 dsi_write(dsi, DSI_GEN_PLD_DATA, val);
761 packet.payload_length = 0;
763 val = get_unaligned_le32(packet.payload);
764 dsi_write(dsi, DSI_GEN_PLD_DATA, val);
766 packet.payload_length -= 4;
770 ret = rockchip_wait_cmd_fifo_not_full(dsi);
774 /* Send packet header */
775 val = get_unaligned_le32(packet.header);
776 dsi_write(dsi, DSI_GEN_HDR, val);
778 ret = rockchip_wait_write_fifo_empty(dsi);
783 rockchip_dsi_send_packet(dsi->slave, msg);
788 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
789 const struct mipi_dsi_msg *msg)
791 struct dw_mipi_dsi *dsi = host_to_dsi(host);
793 return rockchip_dsi_send_packet(dsi, msg);
796 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
797 .attach = dw_mipi_dsi_host_attach,
798 .detach = dw_mipi_dsi_host_detach,
799 .transfer = dw_mipi_dsi_host_transfer,
802 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
806 val = LP_HFP_EN | ENABLE_LOW_POWER;
808 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
809 val |= VID_MODE_TYPE_BURST;
810 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
811 val |= VID_MODE_TYPE_BURST_SYNC_PULSES;
813 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS;
815 dsi_write(dsi, DSI_VID_MODE_CFG, val);
818 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
819 enum dw_mipi_dsi_mode mode)
821 if (mode == DSI_COMMAND_MODE)
822 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
824 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
827 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
831 dsi_write(dsi, DSI_PWR_UP, RESET);
832 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
833 | PHY_RSTZ | PHY_SHUTDOWNZ);
835 /* The maximum value of the escape clock frequency is 20MHz */
836 esc_clk_div = DIV_ROUND_UP(dsi->lane_mbps >> 3, 20);
837 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
838 TX_ESC_CLK_DIVIDSION(esc_clk_div));
841 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
842 struct drm_display_mode *mode)
844 u32 val = 0, color = 0;
846 switch (dsi->format) {
847 case MIPI_DSI_FMT_RGB888:
848 color = DPI_COLOR_CODING_24BIT;
850 case MIPI_DSI_FMT_RGB666:
851 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
853 case MIPI_DSI_FMT_RGB666_PACKED:
854 color = DPI_COLOR_CODING_18BIT_1;
856 case MIPI_DSI_FMT_RGB565:
857 color = DPI_COLOR_CODING_16BIT_1;
861 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
862 val |= VSYNC_ACTIVE_LOW;
863 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
864 val |= HSYNC_ACTIVE_LOW;
866 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
867 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
868 dsi_write(dsi, DSI_DPI_CFG_POL, val);
869 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
870 | INVACT_LPCMD_TIME(4));
873 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
875 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
878 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
879 struct drm_display_mode *mode)
883 if (dsi->slave || dsi->master)
884 pkt_size = VID_PKT_SIZE(mode->hdisplay / 2 + 4);
886 pkt_size = VID_PKT_SIZE(mode->hdisplay);
888 dsi_write(dsi, DSI_VID_PKT_SIZE, pkt_size);
891 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
893 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
894 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
897 /* Get lane byte clock cycles. */
898 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
903 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
905 if (dsi->mode.clock == 0) {
906 dev_err(dsi->dev, "dsi mode clock is 0!\n");
910 return DIV_ROUND_CLOSEST_ULL(lbcc, dsi->mode.clock);
913 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
915 u32 htotal, hsa, hbp, lbcc;
916 struct drm_display_mode *mode = &dsi->mode;
918 htotal = mode->htotal;
919 hsa = mode->hsync_end - mode->hsync_start;
920 hbp = mode->htotal - mode->hsync_end;
922 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
923 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
925 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
926 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
928 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
929 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
932 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
934 u32 vactive, vsa, vfp, vbp;
935 struct drm_display_mode *mode = &dsi->mode;
937 vactive = mode->vdisplay;
938 vsa = mode->vsync_end - mode->vsync_start;
939 vfp = mode->vsync_start - mode->vdisplay;
940 vbp = mode->vtotal - mode->vsync_end;
942 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
943 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
944 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
945 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
948 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
950 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
951 | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
953 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
954 | PHY_CLKLP2HS_TIME(0x40));
957 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
959 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
960 N_LANES(dsi->lanes));
963 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
965 dsi_read(dsi, DSI_INT_ST0);
966 dsi_read(dsi, DSI_INT_ST1);
967 dsi_write(dsi, DSI_INT_MSK0, 0);
968 dsi_write(dsi, DSI_INT_MSK1, 0);
971 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
972 struct drm_display_mode *mode,
973 struct drm_display_mode *adjusted_mode)
975 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
977 drm_mode_copy(&dsi->mode, adjusted_mode);
980 drm_mode_copy(&dsi->slave->mode, adjusted_mode);
983 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
985 if (clk_prepare_enable(dsi->pclk)) {
986 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
990 dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
993 rockchip_dsi_pre_disable(dsi->slave);
996 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
999 dsi_write(dsi, DSI_LPCLK_CTRL, 0);
1000 dsi_write(dsi, DSI_PWR_UP, RESET);
1003 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
1004 if (dsi->dphy.phy) {
1005 clk_disable_unprepare(dsi->dphy.hs_clk);
1006 phy_power_off(dsi->dphy.phy);
1009 pm_runtime_put(dsi->dev);
1010 clk_disable_unprepare(dsi->pclk);
1013 rockchip_dsi_disable(dsi->slave);
1016 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
1018 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1021 drm_panel_disable(dsi->panel);
1023 rockchip_dsi_pre_disable(dsi);
1026 drm_panel_unprepare(dsi->panel);
1028 rockchip_dsi_disable(dsi);
1031 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
1032 const struct drm_display_mode *mode,
1033 struct drm_display_mode *adjusted_mode)
1038 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
1040 const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
1045 val = pdata->dsi0_en_bit |
1046 (pdata->dsi0_en_bit << 16) |
1047 pdata->dsi1_en_bit |
1048 (pdata->dsi1_en_bit << 16);
1050 val = (pdata->dsi0_en_bit << 16) |
1051 (pdata->dsi1_en_bit << 16);
1053 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1054 val = pdata->dsi1_masterslavez |
1055 (pdata->dsi1_masterslavez << 16) |
1056 (pdata->dsi1_basedir << 16);
1057 regmap_write(dsi->grf_regmap, pdata->grf_dsi1_cfg_reg, val);
1060 val = pdata->dsi0_en_bit |
1061 (pdata->dsi0_en_bit << 16);
1063 val = pdata->dsi0_en_bit << 16;
1065 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1068 dev_info(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
1071 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
1073 if (clk_prepare_enable(dsi->pclk)) {
1074 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
1078 if (clk_prepare_enable(dsi->dphy.ref_clk)) {
1079 dev_err(dsi->dev, "Failed to enable pllref_clk\n");
1083 pm_runtime_get_sync(dsi->dev);
1086 /* MIPI DSI APB software reset request. */
1087 reset_control_assert(dsi->rst);
1089 reset_control_deassert(dsi->rst);
1093 if (dsi->dphy.phy) {
1094 rockchip_dsi_set_hs_clk(dsi);
1095 phy_power_on(dsi->dphy.phy);
1097 dw_mipi_dsi_get_lane_bps(dsi);
1100 dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
1101 dsi->lane_mbps, dsi->lanes);
1104 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
1106 dw_mipi_dsi_init(dsi);
1107 dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
1108 dw_mipi_dsi_packet_handler_config(dsi);
1109 dw_mipi_dsi_video_mode_config(dsi);
1110 dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
1111 dw_mipi_dsi_command_mode_config(dsi);
1112 dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
1113 dw_mipi_dsi_line_timer_config(dsi);
1114 dw_mipi_dsi_vertical_timing_config(dsi);
1115 dw_mipi_dsi_dphy_timing_config(dsi);
1116 dw_mipi_dsi_dphy_interface_config(dsi);
1117 dw_mipi_dsi_clear_err(dsi);
1120 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
1122 rockchip_dsi_pre_init(dsi);
1123 rockchip_dsi_host_init(dsi);
1124 dw_mipi_dsi_phy_init(dsi);
1127 rockchip_dsi_init(dsi->slave);
1130 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
1132 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
1133 dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
1134 clk_disable_unprepare(dsi->dphy.ref_clk);
1135 clk_disable_unprepare(dsi->pclk);
1138 rockchip_dsi_enable(dsi->slave);
1141 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
1143 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1146 vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
1148 rockchip_dsi_grf_config(dsi, vop_id);
1149 rockchip_dsi_init(dsi);
1152 drm_panel_prepare(dsi->panel);
1154 rockchip_dsi_enable(dsi);
1157 drm_panel_enable(dsi->panel);
1161 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1162 struct drm_crtc_state *crtc_state,
1163 struct drm_connector_state *conn_state)
1165 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1166 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1167 struct drm_connector *connector = conn_state->connector;
1168 struct drm_display_info *info = &connector->display_info;
1170 switch (dsi->format) {
1171 case MIPI_DSI_FMT_RGB888:
1172 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1174 case MIPI_DSI_FMT_RGB666:
1175 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1177 case MIPI_DSI_FMT_RGB565:
1178 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1185 s->output_type = DRM_MODE_CONNECTOR_DSI;
1186 if (info->num_bus_formats)
1187 s->bus_format = info->bus_formats[0];
1190 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL;
1195 static struct drm_encoder_helper_funcs
1196 dw_mipi_dsi_encoder_helper_funcs = {
1197 .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1198 .mode_set = dw_mipi_dsi_encoder_mode_set,
1199 .enable = dw_mipi_dsi_encoder_enable,
1200 .disable = dw_mipi_dsi_encoder_disable,
1201 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1204 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1205 .destroy = drm_encoder_cleanup,
1208 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1210 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1212 return drm_panel_get_modes(dsi->panel);
1215 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1216 struct drm_connector *connector,
1217 struct drm_display_mode *mode)
1219 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1221 enum drm_mode_status mode_status = MODE_OK;
1223 if (dsi->pdata->mode_valid)
1224 mode_status = dsi->pdata->mode_valid(connector, mode);
1229 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1230 struct drm_connector *connector)
1232 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1234 return &dsi->encoder;
1237 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1239 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1242 drm_panel_loader_protect(dsi->panel, on);
1244 pm_runtime_get_sync(dsi->dev);
1246 pm_runtime_put(dsi->dev);
1251 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1252 .loader_protect = dw_mipi_loader_protect,
1253 .get_modes = dw_mipi_dsi_connector_get_modes,
1254 .mode_valid = dw_mipi_dsi_mode_valid,
1255 .best_encoder = dw_mipi_dsi_connector_best_encoder,
1258 static enum drm_connector_status
1259 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1261 return connector_status_connected;
1264 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1266 drm_connector_unregister(connector);
1267 drm_connector_cleanup(connector);
1270 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1271 .dpms = drm_atomic_helper_connector_dpms,
1272 .fill_modes = drm_helper_probe_single_connector_modes,
1273 .detect = dw_mipi_dsi_detect,
1274 .destroy = dw_mipi_dsi_drm_connector_destroy,
1275 .reset = drm_atomic_helper_connector_reset,
1276 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1277 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1280 static int rockchip_dsi_dual_channel_probe(struct dw_mipi_dsi *dsi)
1282 struct device_node *np;
1283 struct platform_device *secondary;
1285 np = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0);
1287 secondary = of_find_device_by_node(np);
1288 dsi->slave = platform_get_drvdata(secondary);
1292 return -EPROBE_DEFER;
1294 dsi->slave->master = dsi;
1300 static int dw_mipi_dsi_register(struct drm_device *drm,
1301 struct dw_mipi_dsi *dsi)
1303 struct drm_encoder *encoder = &dsi->encoder;
1304 struct drm_connector *connector = &dsi->connector;
1305 struct device *dev = dsi->dev;
1308 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1311 * If we failed to find the CRTC(s) which this encoder is
1312 * supposed to be connected to, it's because the CRTC has
1313 * not been registered yet. Defer probing, and hope that
1314 * the required CRTC is added later.
1316 if (encoder->possible_crtcs == 0)
1317 return -EPROBE_DEFER;
1319 drm_encoder_helper_add(&dsi->encoder,
1320 &dw_mipi_dsi_encoder_helper_funcs);
1321 ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1322 DRM_MODE_ENCODER_DSI, NULL);
1324 dev_err(dev, "Failed to initialize encoder with drm\n");
1328 drm_connector_helper_add(connector,
1329 &dw_mipi_dsi_connector_helper_funcs);
1331 drm_connector_init(drm, &dsi->connector,
1332 &dw_mipi_dsi_atomic_connector_funcs,
1333 DRM_MODE_CONNECTOR_DSI);
1335 drm_panel_attach(dsi->panel, &dsi->connector);
1337 dsi->connector.port = dev->of_node;
1339 drm_mode_connector_attach_encoder(connector, encoder);
1344 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1345 .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1346 .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1347 .grf_switch_reg = RK3288_GRF_SOC_CON6,
1348 .dsi1_basedir = RK3288_TXRX_BASEDIR,
1349 .dsi1_masterslavez = RK3288_TXRX_MASTERSLAVEZ,
1350 .grf_dsi1_cfg_reg = RK3288_GRF_SOC_CON14,
1351 .max_data_lanes = 4,
1352 .max_bit_rate_per_lane = 1500000000,
1353 .has_vop_sel = true,
1356 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1357 .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1358 .grf_switch_reg = RK3366_GRF_SOC_CON0,
1359 .max_data_lanes = 4,
1360 .max_bit_rate_per_lane = 1000000000,
1361 .has_vop_sel = true,
1364 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1365 .max_data_lanes = 4,
1366 .max_bit_rate_per_lane = 1000000000,
1369 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1370 .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1371 .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1372 .grf_switch_reg = RK3399_GRF_SOC_CON19,
1373 .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1374 .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1375 .max_data_lanes = 4,
1376 .max_bit_rate_per_lane = 1500000000,
1377 .has_vop_sel = true,
1380 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1382 .compatible = "rockchip,rk3288-mipi-dsi",
1383 .data = &rk3288_mipi_dsi_drv_data,
1385 .compatible = "rockchip,rk3366-mipi-dsi",
1386 .data = &rk3366_mipi_dsi_drv_data,
1388 .compatible = "rockchip,rk3368-mipi-dsi",
1389 .data = &rk3368_mipi_dsi_drv_data,
1391 .compatible = "rockchip,rk3399-mipi-dsi",
1392 .data = &rk3399_mipi_dsi_drv_data,
1396 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1398 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1401 struct drm_device *drm = data;
1402 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1405 ret = rockchip_dsi_dual_channel_probe(dsi);
1413 return -EPROBE_DEFER;
1415 ret = dw_mipi_dsi_register(drm, dsi);
1417 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1421 dev_set_drvdata(dev, dsi);
1423 pm_runtime_enable(dev);
1425 pm_runtime_enable(dsi->slave->dev);
1430 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1433 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1435 pm_runtime_disable(dev);
1437 pm_runtime_disable(dsi->slave->dev);
1440 static const struct component_ops dw_mipi_dsi_ops = {
1441 .bind = dw_mipi_dsi_bind,
1442 .unbind = dw_mipi_dsi_unbind,
1445 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
1447 struct device *dev = dsi->dev;
1449 dsi->rst = devm_reset_control_get_optional(dev, "apb");
1450 if (IS_ERR(dsi->rst)) {
1451 dev_info(dev, "no reset control specified\n");
1458 static int rockchip_dsi_grf_regmap(struct dw_mipi_dsi *dsi)
1460 struct device_node *np = dsi->dev->of_node;
1462 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1463 if (IS_ERR(dsi->grf_regmap)) {
1464 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1465 return PTR_ERR(dsi->grf_regmap);
1471 static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
1473 struct device *dev = dsi->dev;
1476 dsi->pclk = devm_clk_get(dev, "pclk");
1477 if (IS_ERR(dsi->pclk)) {
1478 ret = PTR_ERR(dsi->pclk);
1479 dev_err(dev, "Unable to get pclk: %d\n", ret);
1486 static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
1488 struct device *dev = dsi->dev;
1491 dsi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");
1492 if (IS_ERR(dsi->dphy.phy)) {
1493 ret = PTR_ERR(dsi->dphy.phy);
1494 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1498 if (dsi->dphy.phy) {
1499 dev_dbg(dev, "Use Non-SNPS PHY\n");
1501 dsi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");
1502 if (IS_ERR(dsi->dphy.hs_clk)) {
1503 dev_err(dev, "failed to get PHY high-speed clock\n");
1504 return PTR_ERR(dsi->dphy.hs_clk);
1507 dev_dbg(dev, "Use SNPS PHY\n");
1509 dsi->dphy.ref_clk = devm_clk_get(dev, "ref");
1510 if (IS_ERR(dsi->dphy.ref_clk)) {
1511 dev_err(dev, "failed to get PHY reference clock\n");
1512 return PTR_ERR(dsi->dphy.ref_clk);
1515 /* Check if cfg_clk provided */
1516 dsi->dphy.cfg_clk = devm_clk_get(dev, "phy_cfg");
1517 if (IS_ERR(dsi->dphy.cfg_clk)) {
1518 if (PTR_ERR(dsi->dphy.cfg_clk) != -ENOENT) {
1519 dev_err(dev, "failed to get PHY config clk\n");
1520 return PTR_ERR(dsi->dphy.cfg_clk);
1523 /* Otherwise mark the cfg_clk pointer to NULL */
1524 dsi->dphy.cfg_clk = NULL;
1531 static int rockchip_dsi_ioremap_resource(struct platform_device *pdev,
1532 struct dw_mipi_dsi *dsi)
1534 struct device *dev = &pdev->dev;
1535 struct resource *res;
1537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1541 dsi->base = devm_ioremap_resource(dev, res);
1542 if (IS_ERR(dsi->base))
1543 return PTR_ERR(dsi->base);
1548 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1550 struct device *dev = &pdev->dev;
1551 const struct of_device_id *of_id =
1552 of_match_device(dw_mipi_dsi_dt_ids, dev);
1553 const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1554 struct dw_mipi_dsi *dsi;
1555 struct device_node *np = dev->of_node;
1559 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1563 dsi_id = of_alias_get_id(np, "dsi");
1571 rockchip_dsi_ioremap_resource(pdev, dsi);
1572 rockchip_dsi_clk_get(dsi);
1573 rockchip_dsi_dphy_parse(dsi);
1574 rockchip_dsi_grf_regmap(dsi);
1575 rockchip_dsi_get_reset_handle(dsi);
1577 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1578 dsi->dsi_host.dev = &pdev->dev;
1580 ret = mipi_dsi_host_register(&dsi->dsi_host);
1584 platform_set_drvdata(pdev, dsi);
1585 ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1587 mipi_dsi_host_unregister(&dsi->dsi_host);
1592 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1594 struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1597 mipi_dsi_host_unregister(&dsi->dsi_host);
1598 component_del(&pdev->dev, &dw_mipi_dsi_ops);
1602 static struct platform_driver dw_mipi_dsi_driver = {
1603 .probe = dw_mipi_dsi_probe,
1604 .remove = dw_mipi_dsi_remove,
1606 .of_match_table = dw_mipi_dsi_dt_ids,
1607 .name = DRIVER_NAME,
1610 module_platform_driver(dw_mipi_dsi_driver);
1612 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1613 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1614 MODULE_LICENSE("GPL");
1615 MODULE_ALIAS("platform:" DRIVER_NAME);