2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/component.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/regmap.h>
16 #include <linux/mfd/syscon.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_panel.h>
24 #include <video/mipi_display.h>
26 #include "rockchip_drm_drv.h"
27 #include "rockchip_drm_vop.h"
29 #define DRIVER_NAME "dw-mipi-dsi"
31 #define RK3288_GRF_SOC_CON6 0x025c
32 #define RK3288_DSI0_SEL_VOP_LIT BIT(6)
33 #define RK3288_DSI1_SEL_VOP_LIT BIT(9)
35 #define RK3399_GRF_SOC_CON19 0x6250
36 #define RK3399_DSI0_SEL_VOP_LIT BIT(0)
37 #define RK3399_DSI1_SEL_VOP_LIT BIT(4)
39 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
40 #define RK3399_GRF_SOC_CON22 0x6258
41 #define RK3399_GRF_DSI_MODE 0xffff0000
43 #define DSI_VERSION 0x00
44 #define DSI_PWR_UP 0x04
46 #define POWERUP BIT(0)
48 #define DSI_CLKMGR_CFG 0x08
49 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
50 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
52 #define DSI_DPI_VCID 0x0c
53 #define DPI_VID(vid) (((vid) & 0x3) << 0)
55 #define DSI_DPI_COLOR_CODING 0x10
56 #define EN18_LOOSELY BIT(8)
57 #define DPI_COLOR_CODING_16BIT_1 0x0
58 #define DPI_COLOR_CODING_16BIT_2 0x1
59 #define DPI_COLOR_CODING_16BIT_3 0x2
60 #define DPI_COLOR_CODING_18BIT_1 0x3
61 #define DPI_COLOR_CODING_18BIT_2 0x4
62 #define DPI_COLOR_CODING_24BIT 0x5
64 #define DSI_DPI_CFG_POL 0x14
65 #define COLORM_ACTIVE_LOW BIT(4)
66 #define SHUTD_ACTIVE_LOW BIT(3)
67 #define HSYNC_ACTIVE_LOW BIT(2)
68 #define VSYNC_ACTIVE_LOW BIT(1)
69 #define DATAEN_ACTIVE_LOW BIT(0)
71 #define DSI_DPI_LP_CMD_TIM 0x18
72 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
73 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
75 #define DSI_DBI_CFG 0x20
76 #define DSI_DBI_CMDSIZE 0x28
78 #define DSI_PCKHDL_CFG 0x2c
79 #define EN_CRC_RX BIT(4)
80 #define EN_ECC_RX BIT(3)
82 #define EN_EOTP_RX BIT(1)
83 #define EN_EOTP_TX BIT(0)
85 #define DSI_MODE_CFG 0x34
86 #define ENABLE_VIDEO_MODE 0
87 #define ENABLE_CMD_MODE BIT(0)
89 #define DSI_VID_MODE_CFG 0x38
90 #define FRAME_BTA_ACK BIT(14)
91 #define ENABLE_LOW_POWER (0x3f << 8)
92 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
93 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x2
94 #define VID_MODE_TYPE_MASK 0x3
96 #define DSI_VID_PKT_SIZE 0x3c
97 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
98 #define VID_PKT_MAX_SIZE 0x3fff
100 #define DSI_VID_HSA_TIME 0x48
101 #define DSI_VID_HBP_TIME 0x4c
102 #define DSI_VID_HLINE_TIME 0x50
103 #define DSI_VID_VSA_LINES 0x54
104 #define DSI_VID_VBP_LINES 0x58
105 #define DSI_VID_VFP_LINES 0x5c
106 #define DSI_VID_VACTIVE_LINES 0x60
107 #define DSI_CMD_MODE_CFG 0x68
108 #define MAX_RD_PKT_SIZE_LP BIT(24)
109 #define DCS_LW_TX_LP BIT(19)
110 #define DCS_SR_0P_TX_LP BIT(18)
111 #define DCS_SW_1P_TX_LP BIT(17)
112 #define DCS_SW_0P_TX_LP BIT(16)
113 #define GEN_LW_TX_LP BIT(14)
114 #define GEN_SR_2P_TX_LP BIT(13)
115 #define GEN_SR_1P_TX_LP BIT(12)
116 #define GEN_SR_0P_TX_LP BIT(11)
117 #define GEN_SW_2P_TX_LP BIT(10)
118 #define GEN_SW_1P_TX_LP BIT(9)
119 #define GEN_SW_0P_TX_LP BIT(8)
120 #define EN_ACK_RQST BIT(1)
121 #define EN_TEAR_FX BIT(0)
123 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
136 #define DSI_GEN_HDR 0x6c
137 #define GEN_HDATA(data) (((data) & 0xffff) << 8)
138 #define GEN_HDATA_MASK (0xffff << 8)
139 #define GEN_HTYPE(type) (((type) & 0xff) << 0)
140 #define GEN_HTYPE_MASK 0xff
142 #define DSI_GEN_PLD_DATA 0x70
144 #define DSI_CMD_PKT_STATUS 0x74
145 #define GEN_CMD_EMPTY BIT(0)
146 #define GEN_CMD_FULL BIT(1)
147 #define GEN_PLD_W_EMPTY BIT(2)
148 #define GEN_PLD_W_FULL BIT(3)
149 #define GEN_PLD_R_EMPTY BIT(4)
150 #define GEN_PLD_R_FULL BIT(5)
151 #define GEN_RD_CMD_BUSY BIT(6)
153 #define DSI_TO_CNT_CFG 0x78
154 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
155 #define LPRX_TO_CNT(p) ((p) & 0xffff)
157 #define DSI_BTA_TO_CNT 0x8c
158 #define DSI_LPCLK_CTRL 0x94
159 #define AUTO_CLKLANE_CTRL BIT(1)
160 #define PHY_TXREQUESTCLKHS BIT(0)
162 #define DSI_PHY_TMR_LPCLK_CFG 0x98
163 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
164 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
166 #define DSI_PHY_TMR_CFG 0x9c
167 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
168 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
169 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
171 #define DSI_PHY_RSTZ 0xa0
172 #define PHY_DISFORCEPLL 0
173 #define PHY_ENFORCEPLL BIT(3)
174 #define PHY_DISABLECLK 0
175 #define PHY_ENABLECLK BIT(2)
177 #define PHY_UNRSTZ BIT(1)
178 #define PHY_SHUTDOWNZ 0
179 #define PHY_UNSHUTDOWNZ BIT(0)
181 #define DSI_PHY_IF_CFG 0xa4
182 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
183 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
185 #define DSI_PHY_STATUS 0xb0
187 #define STOP_STATE_CLK_LANE BIT(2)
189 #define DSI_PHY_TST_CTRL0 0xb4
190 #define PHY_TESTCLK BIT(1)
191 #define PHY_UNTESTCLK 0
192 #define PHY_TESTCLR BIT(0)
193 #define PHY_UNTESTCLR 0
195 #define DSI_PHY_TST_CTRL1 0xb8
196 #define PHY_TESTEN BIT(16)
197 #define PHY_UNTESTEN 0
198 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
199 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
201 #define DSI_INT_ST0 0xbc
202 #define DSI_INT_ST1 0xc0
203 #define DSI_INT_MSK0 0xc4
204 #define DSI_INT_MSK1 0xc8
206 #define PHY_STATUS_TIMEOUT_US 10000
207 #define CMD_PKT_STATUS_TIMEOUT_US 20000
209 #define BYPASS_VCO_RANGE BIT(7)
210 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
211 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
212 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
213 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
214 #define REF_BIAS_CUR_SEL BIT(0)
216 #define CP_CURRENT_3MA BIT(3)
217 #define CP_PROGRAM_EN BIT(7)
218 #define LPF_PROGRAM_EN BIT(6)
219 #define LPF_RESISTORS_20_KOHM 0
221 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
223 #define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
224 #define LOW_PROGRAM_EN 0
225 #define HIGH_PROGRAM_EN BIT(7)
226 #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
227 #define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
228 #define PLL_LOOP_DIV_EN BIT(5)
229 #define PLL_INPUT_DIV_EN BIT(4)
231 #define POWER_CONTROL BIT(6)
232 #define INTERNAL_REG_CURRENT BIT(3)
233 #define BIAS_BLOCK_ON BIT(2)
234 #define BANDGAP_ON BIT(0)
236 #define TER_RESISTOR_HIGH BIT(7)
237 #define TER_RESISTOR_LOW 0
238 #define LEVEL_SHIFTERS_ON BIT(6)
239 #define TER_CAL_DONE BIT(5)
240 #define SETRD_MAX (0x7 << 2)
241 #define POWER_MANAGE BIT(1)
242 #define TER_RESISTORS_ON BIT(0)
244 #define BIASEXTR_SEL(val) ((val) & 0x7)
245 #define BANDGAP_SEL(val) ((val) & 0x7)
246 #define TLP_PROGRAM_EN BIT(7)
247 #define THS_PRE_PROGRAM_EN BIT(7)
248 #define THS_ZERO_PROGRAM_EN BIT(6)
272 struct dw_mipi_dsi_plat_data {
277 u32 grf_dsi0_mode_reg;
278 unsigned int max_data_lanes;
279 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
280 struct drm_display_mode *mode);
284 struct drm_encoder encoder;
285 struct drm_connector connector;
286 struct mipi_dsi_host dsi_host;
287 struct drm_panel *panel;
289 struct regmap *grf_regmap;
292 struct clk *pllref_clk;
294 struct clk *phy_cfg_clk;
296 unsigned int lane_mbps; /* per lane */
302 struct drm_display_mode *mode;
304 const struct dw_mipi_dsi_plat_data *pdata;
307 enum dw_mipi_dsi_mode {
308 DW_MIPI_DSI_CMD_MODE,
309 DW_MIPI_DSI_VID_MODE,
312 struct dphy_pll_testdin_map {
313 unsigned int max_mbps;
317 /* The table is based on 27MHz DPHY pll reference clock. */
318 static const struct dphy_pll_testdin_map dptdin_map[] = {
319 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
320 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
321 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
322 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
323 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
324 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
325 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
326 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
327 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
328 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
331 static int max_mbps_to_testdin(unsigned int max_mbps)
335 for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
336 if (dptdin_map[i].max_mbps > max_mbps)
337 return dptdin_map[i].testdin;
343 * The controller should generate 2 frames before
344 * preparing the peripheral.
346 static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
348 int refresh, two_frames;
350 refresh = drm_mode_vrefresh(dsi->mode);
351 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
355 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
357 return container_of(host, struct dw_mipi_dsi, dsi_host);
360 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
362 return container_of(con, struct dw_mipi_dsi, connector);
365 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
367 return container_of(encoder, struct dw_mipi_dsi, encoder);
369 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
371 writel(val, dsi->base + reg);
374 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
376 return readl(dsi->base + reg);
379 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
383 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
384 * is latched internally as the current test code. Test data is
385 * programmed internally by rising edge on TESTCLK.
387 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
389 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
390 PHY_TESTDIN(test_code));
392 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
394 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
395 PHY_TESTDIN(test_data));
397 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
400 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
402 int ret, testdin, vco, val;
404 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
406 testdin = max_mbps_to_testdin(dsi->lane_mbps);
409 "failed to get testdin for %dmbps lane clock\n",
414 dsi_write(dsi, DSI_PWR_UP, POWERUP);
416 if (!IS_ERR(dsi->phy_cfg_clk)) {
417 ret = clk_prepare_enable(dsi->phy_cfg_clk);
419 dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
424 dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
425 VCO_RANGE_CON_SEL(vco) |
429 dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
430 dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
431 LPF_RESISTORS_20_KOHM);
433 dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
435 dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
436 dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
437 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
439 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
442 dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
443 BIAS_BLOCK_ON | BANDGAP_ON);
445 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
446 SETRD_MAX | TER_RESISTORS_ON);
447 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
448 SETRD_MAX | POWER_MANAGE |
451 dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
452 BIASEXTR_SEL(BIASEXTR_127_7));
453 dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
454 BANDGAP_SEL(BANDGAP_96_10));
456 dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
457 dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
458 dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
460 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
461 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
464 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
465 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
467 dev_err(dsi->dev, "failed to wait for phy lock state\n");
471 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
472 val, val & STOP_STATE_CLK_LANE, 1000,
473 PHY_STATUS_TIMEOUT_US);
476 "failed to wait for phy clk lane stop state\n");
479 if (!IS_ERR(dsi->phy_cfg_clk))
480 clk_disable_unprepare(dsi->phy_cfg_clk);
485 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
488 unsigned long mpclk, pllref, tmp;
489 unsigned int m = 1, n = 1, target_mbps = 1000;
490 unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
493 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
495 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
500 mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
502 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
503 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
507 dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
510 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
513 for (i = 1; i < 6; i++) {
515 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
516 tmp = target_mbps % pre;
518 m = target_mbps / pre;
524 dsi->lane_mbps = pllref / n * m;
526 dsi->feedback_div = m;
531 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
532 struct mipi_dsi_device *device)
534 struct dw_mipi_dsi *dsi = host_to_dsi(host);
536 if (device->lanes > dsi->pdata->max_data_lanes) {
537 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
542 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
543 !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
544 dev_err(dsi->dev, "device mode is unsupported\n");
548 dsi->lanes = device->lanes;
549 dsi->channel = device->channel;
550 dsi->format = device->format;
551 dsi->panel = of_drm_find_panel(device->dev.of_node);
553 DRM_ERROR("failed to find panel\n");
554 return -EPROBE_DEFER;
557 drm_panel_attach(dsi->panel, &dsi->connector);
562 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
563 struct mipi_dsi_device *device)
565 struct dw_mipi_dsi *dsi = host_to_dsi(host);
568 drm_panel_detach(dsi->panel);
573 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
577 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
578 val, !(val & GEN_CMD_FULL), 1000,
579 CMD_PKT_STATUS_TIMEOUT_US);
581 dev_err(dsi->dev, "failed to get available command FIFO\n");
585 dsi_write(dsi, DSI_GEN_HDR, val);
587 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
588 val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
589 1000, CMD_PKT_STATUS_TIMEOUT_US);
591 dev_err(dsi->dev, "failed to write command FIFO\n");
598 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
599 const struct mipi_dsi_msg *msg)
601 const u16 *tx_buf = msg->tx_buf;
602 u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
604 if (msg->tx_len > 2) {
605 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
610 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
613 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
614 const struct mipi_dsi_msg *msg)
616 const u32 *tx_buf = msg->tx_buf;
617 int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
618 u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
621 if (msg->tx_len < 3) {
622 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
627 while (DIV_ROUND_UP(len, pld_data_bytes)) {
628 if (len < pld_data_bytes) {
629 memcpy(&remainder, tx_buf, len);
630 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
633 dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
635 len -= pld_data_bytes;
638 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
639 val, !(val & GEN_PLD_W_FULL), 1000,
640 CMD_PKT_STATUS_TIMEOUT_US);
643 "failed to get available write payload FIFO\n");
648 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
651 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
652 const struct mipi_dsi_msg *msg)
654 struct dw_mipi_dsi *dsi = host_to_dsi(host);
658 case MIPI_DSI_DCS_SHORT_WRITE:
659 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
660 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
661 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
663 case MIPI_DSI_DCS_LONG_WRITE:
664 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
667 dev_err(dsi->dev, "unsupported message type\n");
674 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
675 .attach = dw_mipi_dsi_host_attach,
676 .detach = dw_mipi_dsi_host_detach,
677 .transfer = dw_mipi_dsi_host_transfer,
680 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
684 val = VID_MODE_TYPE_BURST_SYNC_PULSES | ENABLE_LOW_POWER;
686 dsi_write(dsi, DSI_VID_MODE_CFG, val);
689 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
690 enum dw_mipi_dsi_mode mode)
692 if (mode == DW_MIPI_DSI_CMD_MODE) {
693 dsi_write(dsi, DSI_PWR_UP, RESET);
694 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
695 dsi_write(dsi, DSI_PWR_UP, POWERUP);
697 dsi_write(dsi, DSI_PWR_UP, RESET);
698 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
699 dw_mipi_dsi_video_mode_config(dsi);
700 dsi_write(dsi, DSI_PWR_UP, POWERUP);
704 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
706 dsi_write(dsi, DSI_PWR_UP, RESET);
707 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
710 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
712 dsi_write(dsi, DSI_PWR_UP, RESET);
713 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
714 | PHY_RSTZ | PHY_SHUTDOWNZ);
715 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
716 TX_ESC_CLK_DIVIDSION(7));
717 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
720 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
721 struct drm_display_mode *mode)
723 u32 val = 0, color = 0;
725 switch (dsi->format) {
726 case MIPI_DSI_FMT_RGB888:
727 color = DPI_COLOR_CODING_24BIT;
729 case MIPI_DSI_FMT_RGB666:
730 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
732 case MIPI_DSI_FMT_RGB666_PACKED:
733 color = DPI_COLOR_CODING_18BIT_1;
735 case MIPI_DSI_FMT_RGB565:
736 color = DPI_COLOR_CODING_16BIT_1;
740 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
741 val |= VSYNC_ACTIVE_LOW;
742 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
743 val |= HSYNC_ACTIVE_LOW;
745 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
746 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
747 dsi_write(dsi, DSI_DPI_CFG_POL, val);
748 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
749 | INVACT_LPCMD_TIME(4));
752 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
754 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
757 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
758 struct drm_display_mode *mode)
760 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
763 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
765 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
766 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
767 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
768 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
771 /* Get lane byte clock cycles. */
772 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
777 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
779 frac = lbcc % dsi->mode->clock;
780 lbcc = lbcc / dsi->mode->clock;
787 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
789 u32 htotal, hsa, hbp, lbcc;
790 struct drm_display_mode *mode = dsi->mode;
792 htotal = mode->htotal;
793 hsa = mode->hsync_end - mode->hsync_start;
794 hbp = mode->htotal - mode->hsync_end;
796 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
797 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
799 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
800 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
802 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
803 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
806 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
808 u32 vactive, vsa, vfp, vbp;
809 struct drm_display_mode *mode = dsi->mode;
811 vactive = mode->vdisplay;
812 vsa = mode->vsync_end - mode->vsync_start;
813 vfp = mode->vsync_start - mode->vdisplay;
814 vbp = mode->vtotal - mode->vsync_end;
816 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
817 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
818 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
819 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
822 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
824 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
825 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
827 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
828 | PHY_CLKLP2HS_TIME(0x40));
831 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
833 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
834 N_LANES(dsi->lanes));
837 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
839 dsi_read(dsi, DSI_INT_ST0);
840 dsi_read(dsi, DSI_INT_ST1);
841 dsi_write(dsi, DSI_INT_MSK0, 0);
842 dsi_write(dsi, DSI_INT_MSK1, 0);
845 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
846 struct drm_display_mode *mode,
847 struct drm_display_mode *adjusted_mode)
849 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
852 dsi->mode = adjusted_mode;
854 ret = dw_mipi_dsi_get_lane_bps(dsi);
858 if (clk_prepare_enable(dsi->pclk)) {
859 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
863 dw_mipi_dsi_init(dsi);
864 dw_mipi_dsi_dpi_config(dsi, mode);
865 dw_mipi_dsi_packet_handler_config(dsi);
866 dw_mipi_dsi_video_mode_config(dsi);
867 dw_mipi_dsi_video_packet_config(dsi, mode);
868 dw_mipi_dsi_command_mode_config(dsi);
869 dw_mipi_dsi_line_timer_config(dsi);
870 dw_mipi_dsi_vertical_timing_config(dsi);
871 dw_mipi_dsi_dphy_timing_config(dsi);
872 dw_mipi_dsi_dphy_interface_config(dsi);
873 dw_mipi_dsi_clear_err(dsi);
874 if (drm_panel_prepare(dsi->panel))
875 dev_err(dsi->dev, "failed to prepare panel\n");
877 clk_disable_unprepare(dsi->pclk);
880 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
882 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
884 drm_panel_disable(dsi->panel);
886 if (clk_prepare_enable(dsi->pclk)) {
887 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
891 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
892 drm_panel_unprepare(dsi->panel);
893 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
896 * This is necessary to make sure the peripheral will be driven
897 * normally when the display is enabled again later.
901 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
902 dw_mipi_dsi_disable(dsi);
903 clk_disable_unprepare(dsi->pclk);
906 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
907 const struct drm_display_mode *mode,
908 struct drm_display_mode *adjusted_mode)
913 static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
915 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
916 const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
917 int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
920 if (clk_prepare_enable(dsi->pclk)) {
921 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
925 if (pdata->grf_dsi0_mode_reg)
926 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
927 pdata->grf_dsi0_mode);
929 dw_mipi_dsi_phy_init(dsi);
930 dw_mipi_dsi_wait_for_two_frames(dsi);
932 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
933 drm_panel_enable(dsi->panel);
935 clk_disable_unprepare(dsi->pclk);
938 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
940 val = pdata->dsi0_en_bit << 16;
942 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
943 dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
947 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
948 struct drm_crtc_state *crtc_state,
949 struct drm_connector_state *conn_state)
951 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
952 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
954 switch (dsi->format) {
955 case MIPI_DSI_FMT_RGB888:
956 s->output_mode = ROCKCHIP_OUT_MODE_P888;
958 case MIPI_DSI_FMT_RGB666:
959 s->output_mode = ROCKCHIP_OUT_MODE_P666;
961 case MIPI_DSI_FMT_RGB565:
962 s->output_mode = ROCKCHIP_OUT_MODE_P565;
969 s->output_type = DRM_MODE_CONNECTOR_DSI;
974 static struct drm_encoder_helper_funcs
975 dw_mipi_dsi_encoder_helper_funcs = {
976 .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
977 .commit = dw_mipi_dsi_encoder_commit,
978 .mode_set = dw_mipi_dsi_encoder_mode_set,
979 .disable = dw_mipi_dsi_encoder_disable,
980 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
983 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
984 .destroy = drm_encoder_cleanup,
987 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
989 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
991 return drm_panel_get_modes(dsi->panel);
994 static enum drm_mode_status dw_mipi_dsi_mode_valid(
995 struct drm_connector *connector,
996 struct drm_display_mode *mode)
998 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1000 enum drm_mode_status mode_status = MODE_OK;
1002 if (dsi->pdata->mode_valid)
1003 mode_status = dsi->pdata->mode_valid(connector, mode);
1008 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1009 struct drm_connector *connector)
1011 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1013 return &dsi->encoder;
1016 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1017 .get_modes = dw_mipi_dsi_connector_get_modes,
1018 .mode_valid = dw_mipi_dsi_mode_valid,
1019 .best_encoder = dw_mipi_dsi_connector_best_encoder,
1022 static enum drm_connector_status
1023 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1025 return connector_status_connected;
1028 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1030 drm_connector_unregister(connector);
1031 drm_connector_cleanup(connector);
1034 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1035 .dpms = drm_atomic_helper_connector_dpms,
1036 .fill_modes = drm_helper_probe_single_connector_modes,
1037 .detect = dw_mipi_dsi_detect,
1038 .destroy = dw_mipi_dsi_drm_connector_destroy,
1039 .reset = drm_atomic_helper_connector_reset,
1040 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1041 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1044 static int dw_mipi_dsi_register(struct drm_device *drm,
1045 struct dw_mipi_dsi *dsi)
1047 struct drm_encoder *encoder = &dsi->encoder;
1048 struct drm_connector *connector = &dsi->connector;
1049 struct device *dev = dsi->dev;
1052 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1055 * If we failed to find the CRTC(s) which this encoder is
1056 * supposed to be connected to, it's because the CRTC has
1057 * not been registered yet. Defer probing, and hope that
1058 * the required CRTC is added later.
1060 if (encoder->possible_crtcs == 0)
1061 return -EPROBE_DEFER;
1063 drm_encoder_helper_add(&dsi->encoder,
1064 &dw_mipi_dsi_encoder_helper_funcs);
1065 ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1066 DRM_MODE_ENCODER_DSI, NULL);
1068 dev_err(dev, "Failed to initialize encoder with drm\n");
1072 drm_connector_helper_add(connector,
1073 &dw_mipi_dsi_connector_helper_funcs);
1075 drm_connector_init(drm, &dsi->connector,
1076 &dw_mipi_dsi_atomic_connector_funcs,
1077 DRM_MODE_CONNECTOR_DSI);
1079 drm_mode_connector_attach_encoder(connector, encoder);
1084 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1086 struct device_node *np = dsi->dev->of_node;
1088 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1089 if (IS_ERR(dsi->grf_regmap)) {
1090 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1091 return PTR_ERR(dsi->grf_regmap);
1097 static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
1098 struct drm_connector *connector,
1099 struct drm_display_mode *mode)
1102 * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
1103 * register is 11-bit.
1105 if (mode->hdisplay > 0x7ff)
1106 return MODE_BAD_HVALUE;
1109 * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
1110 * register is 11-bit.
1112 if (mode->vdisplay > 0x7ff)
1113 return MODE_BAD_VVALUE;
1118 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1119 .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1120 .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1121 .grf_switch_reg = RK3288_GRF_SOC_CON6,
1122 .max_data_lanes = 4,
1123 .mode_valid = rk3288_mipi_dsi_mode_valid,
1126 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1127 .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1128 .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1129 .grf_switch_reg = RK3399_GRF_SOC_CON19,
1130 .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1131 .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1132 .max_data_lanes = 4,
1133 .mode_valid = rk3288_mipi_dsi_mode_valid,
1136 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1138 .compatible = "rockchip,rk3288-mipi-dsi",
1139 .data = &rk3288_mipi_dsi_drv_data,
1141 .compatible = "rockchip,rk3399-mipi-dsi",
1142 .data = &rk3399_mipi_dsi_drv_data,
1146 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1148 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1151 const struct of_device_id *of_id =
1152 of_match_device(dw_mipi_dsi_dt_ids, dev);
1153 const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1154 struct platform_device *pdev = to_platform_device(dev);
1155 struct drm_device *drm = data;
1156 struct dw_mipi_dsi *dsi;
1157 struct resource *res;
1160 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1167 ret = rockchip_mipi_parse_dt(dsi);
1171 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1175 dsi->base = devm_ioremap_resource(dev, res);
1176 if (IS_ERR(dsi->base))
1177 return PTR_ERR(dsi->base);
1179 dsi->pllref_clk = devm_clk_get(dev, "ref");
1180 if (IS_ERR(dsi->pllref_clk)) {
1181 ret = PTR_ERR(dsi->pllref_clk);
1182 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1186 dsi->pclk = devm_clk_get(dev, "pclk");
1187 if (IS_ERR(dsi->pclk)) {
1188 ret = PTR_ERR(dsi->pclk);
1189 dev_err(dev, "Unable to get pclk: %d\n", ret);
1193 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1194 if (IS_ERR(dsi->phy_cfg_clk))
1195 dev_dbg(dev, "have not phy_cfg_clk\n");
1197 ret = clk_prepare_enable(dsi->pllref_clk);
1199 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1203 ret = dw_mipi_dsi_register(drm, dsi);
1205 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1209 dev_set_drvdata(dev, dsi);
1211 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1212 dsi->dsi_host.dev = dev;
1213 return mipi_dsi_host_register(&dsi->dsi_host);
1216 clk_disable_unprepare(dsi->pllref_clk);
1220 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1223 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1225 mipi_dsi_host_unregister(&dsi->dsi_host);
1226 clk_disable_unprepare(dsi->pllref_clk);
1229 static const struct component_ops dw_mipi_dsi_ops = {
1230 .bind = dw_mipi_dsi_bind,
1231 .unbind = dw_mipi_dsi_unbind,
1234 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1236 return component_add(&pdev->dev, &dw_mipi_dsi_ops);
1239 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1241 component_del(&pdev->dev, &dw_mipi_dsi_ops);
1245 static struct platform_driver dw_mipi_dsi_driver = {
1246 .probe = dw_mipi_dsi_probe,
1247 .remove = dw_mipi_dsi_remove,
1249 .of_match_table = dw_mipi_dsi_dt_ids,
1250 .name = DRIVER_NAME,
1253 module_platform_driver(dw_mipi_dsi_driver);
1255 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1256 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1257 MODULE_LICENSE("GPL");
1258 MODULE_ALIAS("platform:" DRIVER_NAME);