drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3366_GRF_SOC_CON0             0x0400
  40 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  41
  42 #define RK3399_GRF_SOC_CON19            0x6250
  43 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  44 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  45
  46 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  47 #define RK3399_GRF_SOC_CON22            0x6258
  48 #define RK3399_GRF_DSI_MODE             0xffff0000
  49
  50 #define DSI_VERSION                     0x00
  51 #define DSI_PWR_UP                      0x04
  52 #define RESET                           0
  53 #define POWERUP                         BIT(0)
  54
  55 #define DSI_CLKMGR_CFG                  0x08
  56 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  57 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  58
  59 #define DSI_DPI_VCID                    0x0c
  60 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  61
  62 #define DSI_DPI_COLOR_CODING            0x10
  63 #define EN18_LOOSELY                    BIT(8)
  64 #define DPI_COLOR_CODING_16BIT_1        0x0
  65 #define DPI_COLOR_CODING_16BIT_2        0x1
  66 #define DPI_COLOR_CODING_16BIT_3        0x2
  67 #define DPI_COLOR_CODING_18BIT_1        0x3
  68 #define DPI_COLOR_CODING_18BIT_2        0x4
  69 #define DPI_COLOR_CODING_24BIT          0x5
  70
  71 #define DSI_DPI_CFG_POL                 0x14
  72 #define COLORM_ACTIVE_LOW               BIT(4)
  73 #define SHUTD_ACTIVE_LOW                BIT(3)
  74 #define HSYNC_ACTIVE_LOW                BIT(2)
  75 #define VSYNC_ACTIVE_LOW                BIT(1)
  76 #define DATAEN_ACTIVE_LOW               BIT(0)
  77
  78 #define DSI_DPI_LP_CMD_TIM              0x18
  79 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  80 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  81
  82 #define DSI_DBI_CFG                     0x20
  83 #define DSI_DBI_CMDSIZE                 0x28
  84
  85 #define DSI_PCKHDL_CFG                  0x2c
  86 #define EN_CRC_RX                       BIT(4)
  87 #define EN_ECC_RX                       BIT(3)
  88 #define EN_BTA                          BIT(2)
  89 #define EN_EOTP_RX                      BIT(1)
  90 #define EN_EOTP_TX                      BIT(0)
  91
  92 #define DSI_MODE_CFG                    0x34
  93 #define ENABLE_VIDEO_MODE               0
  94 #define ENABLE_CMD_MODE                 BIT(0)
  95
  96 #define DSI_VID_MODE_CFG                0x38
  97 #define VPG_EN                          BIT(16)
  98 #define FRAME_BTA_ACK                   BIT(14)
  99 #define LP_HFP_EN                       BIT(13)
 100 #define LP_HBP_EN                       BIT(12)
 101 #define ENABLE_LOW_POWER                (0xf << 8)
 102 #define ENABLE_LOW_POWER_MASK           (0xf << 8)
 103 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 104 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 105 #define VID_MODE_TYPE_BURST             0x2
 106
 107 #define DSI_VID_PKT_SIZE                0x3c
 108 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 109 #define VID_PKT_MAX_SIZE                0x3fff
 110
 111 #define DSI_VID_NUM_CHUMKS              0x40
 112 #define DSI_VID_NULL_PKT_SIZE           0x44
 113 #define DSI_VID_HSA_TIME                0x48
 114 #define DSI_VID_HBP_TIME                0x4c
 115 #define DSI_VID_HLINE_TIME              0x50
 116 #define DSI_VID_VSA_LINES               0x54
 117 #define DSI_VID_VBP_LINES               0x58
 118 #define DSI_VID_VFP_LINES               0x5c
 119 #define DSI_VID_VACTIVE_LINES           0x60
 120 #define DSI_CMD_MODE_CFG                0x68
 121 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 122 #define DCS_LW_TX_LP                    BIT(19)
 123 #define DCS_SR_0P_TX_LP                 BIT(18)
 124 #define DCS_SW_1P_TX_LP                 BIT(17)
 125 #define DCS_SW_0P_TX_LP                 BIT(16)
 126 #define GEN_LW_TX_LP                    BIT(14)
 127 #define GEN_SR_2P_TX_LP                 BIT(13)
 128 #define GEN_SR_1P_TX_LP                 BIT(12)
 129 #define GEN_SR_0P_TX_LP                 BIT(11)
 130 #define GEN_SW_2P_TX_LP                 BIT(10)
 131 #define GEN_SW_1P_TX_LP                 BIT(9)
 132 #define GEN_SW_0P_TX_LP                 BIT(8)
 133 #define EN_ACK_RQST                     BIT(1)
 134 #define EN_TEAR_FX                      BIT(0)
 135
 136 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 137                                          DCS_LW_TX_LP | \
 138                                          DCS_SR_0P_TX_LP | \
 139                                          DCS_SW_1P_TX_LP | \
 140                                          DCS_SW_0P_TX_LP | \
 141                                          GEN_LW_TX_LP | \
 142                                          GEN_SR_2P_TX_LP | \
 143                                          GEN_SR_1P_TX_LP | \
 144                                          GEN_SR_0P_TX_LP | \
 145                                          GEN_SW_2P_TX_LP | \
 146                                          GEN_SW_1P_TX_LP | \
 147                                          GEN_SW_0P_TX_LP)
 148
 149 #define DSI_GEN_HDR                     0x6c
 150 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 151 #define GEN_HDATA_MASK                  (0xffff << 8)
 152 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 153 #define GEN_HTYPE_MASK                  0xff
 154
 155 #define DSI_GEN_PLD_DATA                0x70
 156
 157 #define DSI_CMD_PKT_STATUS              0x74
 158 #define GEN_CMD_EMPTY                   BIT(0)
 159 #define GEN_CMD_FULL                    BIT(1)
 160 #define GEN_PLD_W_EMPTY                 BIT(2)
 161 #define GEN_PLD_W_FULL                  BIT(3)
 162 #define GEN_PLD_R_EMPTY                 BIT(4)
 163 #define GEN_PLD_R_FULL                  BIT(5)
 164 #define GEN_RD_CMD_BUSY                 BIT(6)
 165
 166 #define DSI_TO_CNT_CFG                  0x78
 167 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 168 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 169
 170 #define DSI_BTA_TO_CNT                  0x8c
 171 #define DSI_LPCLK_CTRL                  0x94
 172 #define AUTO_CLKLANE_CTRL               BIT(1)
 173 #define PHY_TXREQUESTCLKHS              BIT(0)
 174
 175 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 176 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 177 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 178
 179 #define DSI_PHY_TMR_CFG                 0x9c
 180 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 181 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 182 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 183
 184 #define DSI_PHY_RSTZ                    0xa0
 185 #define PHY_DISFORCEPLL                 0
 186 #define PHY_ENFORCEPLL                  BIT(3)
 187 #define PHY_DISABLECLK                  0
 188 #define PHY_ENABLECLK                   BIT(2)
 189 #define PHY_RSTZ                        0
 190 #define PHY_UNRSTZ                      BIT(1)
 191 #define PHY_SHUTDOWNZ                   0
 192 #define PHY_UNSHUTDOWNZ                 BIT(0)
 193
 194 #define DSI_PHY_IF_CFG                  0xa4
 195 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 196 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 197
 198 #define DSI_PHY_STATUS                  0xb0
 199 #define LOCK                            BIT(0)
 200 #define STOP_STATE_CLK_LANE             BIT(2)
 201
 202 #define DSI_PHY_TST_CTRL0               0xb4
 203 #define PHY_TESTCLK                     BIT(1)
 204 #define PHY_UNTESTCLK                   0
 205 #define PHY_TESTCLR                     BIT(0)
 206 #define PHY_UNTESTCLR                   0
 207
 208 #define DSI_PHY_TST_CTRL1               0xb8
 209 #define PHY_TESTEN                      BIT(16)
 210 #define PHY_UNTESTEN                    0
 211 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 212 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 213
 214 #define DSI_INT_ST0                     0xbc
 215 #define DSI_INT_ST1                     0xc0
 216 #define DSI_INT_MSK0                    0xc4
 217 #define DSI_INT_MSK1                    0xc8
 218
 219 #define PHY_STATUS_TIMEOUT_US           10000
 220 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 221
 222 #define BYPASS_VCO_RANGE        BIT(7)
 223 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 224 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 225 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 226 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 227 #define REF_BIAS_CUR_SEL        BIT(0)
 228
 229 #define CP_CURRENT_3MA          BIT(3)
 230 #define CP_PROGRAM_EN           BIT(7)
 231 #define LPF_PROGRAM_EN          BIT(6)
 232 #define LPF_RESISTORS_20_KOHM   0
 233
 234 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 235
 236 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 237 #define LOW_PROGRAM_EN          0
 238 #define HIGH_PROGRAM_EN         BIT(7)
 239 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 240 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 241 #define PLL_LOOP_DIV_EN         BIT(5)
 242 #define PLL_INPUT_DIV_EN        BIT(4)
 243
 244 #define POWER_CONTROL           BIT(6)
 245 #define INTERNAL_REG_CURRENT    BIT(3)
 246 #define BIAS_BLOCK_ON           BIT(2)
 247 #define BANDGAP_ON              BIT(0)
 248
 249 #define TER_RESISTOR_HIGH       BIT(7)
 250 #define TER_RESISTOR_LOW        0
 251 #define LEVEL_SHIFTERS_ON       BIT(6)
 252 #define TER_CAL_DONE            BIT(5)
 253 #define SETRD_MAX               (0x7 << 2)
 254 #define POWER_MANAGE            BIT(1)
 255 #define TER_RESISTORS_ON        BIT(0)
 256
 257 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 258 #define BANDGAP_SEL(val)        ((val) & 0x7)
 259 #define TLP_PROGRAM_EN          BIT(7)
 260 #define THS_PRE_PROGRAM_EN      BIT(7)
 261 #define THS_ZERO_PROGRAM_EN     BIT(6)
 262
 263 enum {
 264         BANDGAP_97_07,
 265         BANDGAP_98_05,
 266         BANDGAP_99_02,
 267         BANDGAP_100_00,
 268         BANDGAP_93_17,
 269         BANDGAP_94_15,
 270         BANDGAP_95_12,
 271         BANDGAP_96_10,
 272 };
 273
 274 enum {
 275         BIASEXTR_87_1,
 276         BIASEXTR_91_5,
 277         BIASEXTR_95_9,
 278         BIASEXTR_100,
 279         BIASEXTR_105_94,
 280         BIASEXTR_111_88,
 281         BIASEXTR_118_8,
 282         BIASEXTR_127_7,
 283 };
 284
 285 struct dw_mipi_dsi_plat_data {
 286         u32 dsi0_en_bit;
 287         u32 dsi1_en_bit;
 288         u32 grf_switch_reg;
 289         u32 grf_dsi0_mode;
 290         u32 grf_dsi0_mode_reg;
 291         unsigned int max_data_lanes;
 292         u32 max_bit_rate_per_lane;
 293         bool has_vop_sel;
 294         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 295                                            struct drm_display_mode *mode);
 296 };
 297
 298 struct dw_mipi_dsi {
 299         struct drm_encoder encoder;
 300         struct drm_connector connector;
 301         struct mipi_dsi_host dsi_host;
 302         struct phy *phy;
 303         struct drm_panel *panel;
 304         struct device *dev;
 305         struct regmap *grf_regmap;
 306         struct reset_control *rst;
 307         void __iomem *base;
 308
 309         struct clk *pllref_clk;
 310         struct clk *pclk;
 311         struct clk *phy_cfg_clk;
 312
 313         unsigned long mode_flags;
 314         unsigned int lane_mbps; /* per lane */
 315         u32 channel;
 316         u32 lanes;
 317         u32 format;
 318         u16 input_div;
 319         u16 feedback_div;
 320         struct drm_display_mode mode;
 321
 322         const struct dw_mipi_dsi_plat_data *pdata;
 323 };
 324
 325 enum dw_mipi_dsi_mode {
 326         DSI_COMMAND_MODE,
 327         DSI_VIDEO_MODE,
 328 };
 329
 330 struct dphy_pll_testdin_map {
 331         unsigned int max_mbps;
 332         u8 testdin;
 333 };
 334
 335 /* The table is based on 27MHz DPHY pll reference clock. */
 336 static const struct dphy_pll_testdin_map dptdin_map[] = {
 337         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 338         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 339         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 340         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 341         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 342         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 343         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 344         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 345         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 346         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 347 };
 348
 349 static int max_mbps_to_testdin(unsigned int max_mbps)
 350 {
 351         int i;
 352
 353         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 354                 if (dptdin_map[i].max_mbps > max_mbps)
 355                         return dptdin_map[i].testdin;
 356
 357         return -EINVAL;
 358 }
 359
 360 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 361 {
 362         return container_of(host, struct dw_mipi_dsi, dsi_host);
 363 }
 364
 365 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 366 {
 367         return container_of(con, struct dw_mipi_dsi, connector);
 368 }
 369
 370 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 371 {
 372         return container_of(encoder, struct dw_mipi_dsi, encoder);
 373 }
 374 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 375 {
 376         writel(val, dsi->base + reg);
 377 }
 378
 379 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 380 {
 381         return readl(dsi->base + reg);
 382 }
 383
 384 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 385 {
 386         u32 sts;
 387         int ret;
 388
 389         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 390                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 391                                  CMD_PKT_STATUS_TIMEOUT_US);
 392         if (ret < 0) {
 393                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 394                 return ret;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 401 {
 402         u32 sts;
 403         int ret;
 404
 405         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 406                                  sts, !(sts & GEN_CMD_FULL), 10,
 407                                  CMD_PKT_STATUS_TIMEOUT_US);
 408         if (ret < 0) {
 409                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 410                 return ret;
 411         }
 412
 413         return 0;
 414 }
 415
 416 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 417 {
 418         u32 sts;
 419         u32 mask;
 420         int ret;
 421
 422         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 423         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 424                                  sts, (sts & mask) == mask, 10,
 425                                  CMD_PKT_STATUS_TIMEOUT_US);
 426         if (ret < 0) {
 427                 dev_err(dsi->dev, "generic write fifo is full\n");
 428                 return ret;
 429         }
 430
 431         return 0;
 432 }
 433
 434 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 435                                  u8 test_data)
 436 {
 437         /*
 438          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 439          * is latched internally as the current test code. Test data is
 440          * programmed internally by rising edge on TESTCLK.
 441          */
 442         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 443
 444         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 445                                           PHY_TESTDIN(test_code));
 446
 447         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 448
 449         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 450                                           PHY_TESTDIN(test_data));
 451
 452         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 453 }
 454
 455 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 456 {
 457         int ret, testdin, vco, val;
 458
 459         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 460
 461         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 462         if (testdin < 0) {
 463                 dev_err(dsi->dev,
 464                         "failed to get testdin for %dmbps lane clock\n",
 465                         dsi->lane_mbps);
 466                 return testdin;
 467         }
 468
 469         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 470
 471         if (!IS_ERR(dsi->phy_cfg_clk)) {
 472                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 473                 if (ret) {
 474                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 475                         return ret;
 476                 }
 477         }
 478
 479         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 480                                          VCO_RANGE_CON_SEL(vco) |
 481                                          VCO_IN_CAP_CON_LOW |
 482                                          REF_BIAS_CUR_SEL);
 483
 484         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 485         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 486                                          LPF_RESISTORS_20_KOHM);
 487
 488         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 489
 490         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 491         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 492         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 493                                          LOW_PROGRAM_EN);
 494         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 495                                          HIGH_PROGRAM_EN);
 496
 497         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 498                                          BIAS_BLOCK_ON | BANDGAP_ON);
 499
 500         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 501                                          SETRD_MAX | TER_RESISTORS_ON);
 502         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 503                                          SETRD_MAX | POWER_MANAGE |
 504                                          TER_RESISTORS_ON);
 505
 506         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 507                                          BIASEXTR_SEL(BIASEXTR_127_7));
 508         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 509                                          BANDGAP_SEL(BANDGAP_96_10));
 510
 511         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 512         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 513         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 514
 515         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 516                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 517
 518
 519         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 520                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 521         if (ret < 0) {
 522                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 523                 goto phy_init_end;
 524         }
 525
 526         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 527                                  val, val & STOP_STATE_CLK_LANE, 1000,
 528                                  PHY_STATUS_TIMEOUT_US);
 529         if (ret < 0)
 530                 dev_err(dsi->dev,
 531                         "failed to wait for phy clk lane stop state\n");
 532
 533 phy_init_end:
 534         if (!IS_ERR(dsi->phy_cfg_clk))
 535                 clk_disable_unprepare(dsi->phy_cfg_clk);
 536
 537         return ret;
 538 }
 539
 540 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 541 {
 542         unsigned int i, pre;
 543         unsigned long mpclk, pllref, tmp;
 544         unsigned int m = 1, n = 1, target_mbps = 1000;
 545         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 546         int bpp;
 547
 548         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 549         if (bpp < 0) {
 550                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 551                         dsi->format);
 552                 return bpp;
 553         }
 554
 555         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 556         if (mpclk) {
 557                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 558                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 559                 if (tmp < max_mbps)
 560                         target_mbps = tmp;
 561                 else
 562                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 563         }
 564
 565         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 566         tmp = pllref;
 567
 568         for (i = 1; i < 6; i++) {
 569                 pre = pllref / i;
 570                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 571                         tmp = target_mbps % pre;
 572                         n = i;
 573                         m = target_mbps / pre;
 574                 }
 575                 if (tmp == 0)
 576                         break;
 577         }
 578
 579         dsi->lane_mbps = pllref / n * m;
 580         dsi->input_div = n;
 581         dsi->feedback_div = m;
 582
 583         return 0;
 584 }
 585
 586 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 587                                    struct mipi_dsi_device *device)
 588 {
 589         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 590
 591         if (device->lanes > dsi->pdata->max_data_lanes) {
 592                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 593                                 device->lanes);
 594                 return -EINVAL;
 595         }
 596
 597         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 598                 dev_err(dsi->dev, "device mode is unsupported\n");
 599                 return -EINVAL;
 600         }
 601
 602         dsi->lanes = device->lanes;
 603         dsi->channel = device->channel;
 604         dsi->format = device->format;
 605         dsi->mode_flags = device->mode_flags;
 606
 607         dsi->panel = of_drm_find_panel(device->dev.of_node);
 608         if (!dsi->panel) {
 609                 DRM_ERROR("failed to find panel\n");
 610                 return -ENODEV;
 611         }
 612
 613         return 0;
 614 }
 615
 616 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 617                                    struct mipi_dsi_device *device)
 618 {
 619         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 620
 621         if (dsi->panel)
 622                 drm_panel_detach(dsi->panel);
 623
 624         dsi->panel = NULL;
 625         return 0;
 626 }
 627
 628 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 629 {
 630         if (flags & MIPI_DSI_MSG_USE_LPM)
 631                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 632         else
 633                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 634 }
 635
 636 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 637                                          const struct mipi_dsi_msg *msg)
 638 {
 639         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 640         struct mipi_dsi_packet packet;
 641         int ret;
 642         int val;
 643         int len = msg->tx_len;
 644
 645         /* create a packet to the DSI protocol */
 646         ret = mipi_dsi_create_packet(&packet, msg);
 647         if (ret) {
 648                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 649                 return ret;
 650         }
 651
 652         rockchip_set_transfer_mode(dsi, msg->flags);
 653
 654         /* Send payload,  */
 655         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 656                 /*
 657                  * Alternatively, you can always keep the FIFO
 658                  * nearly full by monitoring the FIFO state until
 659                  * it is not full, and then writea single word of data.
 660                  * This solution is more resource consuming
 661                  * but it simultaneously avoids FIFO starvation,
 662                  * making it possible to use FIFO sizes smaller than
 663                  * the amount of data of the longest packet to be written.
 664                  */
 665                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 666                 if (ret)
 667                         return ret;
 668
 669                 if (packet.payload_length < 4) {
 670                         /* send residu payload */
 671                         val = 0;
 672                         memcpy(&val, packet.payload, packet.payload_length);
 673                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 674                         packet.payload_length = 0;
 675                 } else {
 676                         val = get_unaligned_le32(packet.payload);
 677                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 678                         packet.payload += 4;
 679                         packet.payload_length -= 4;
 680                 }
 681         }
 682
 683         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 684         if (ret)
 685                 return ret;
 686
 687         /* Send packet header */
 688         val = get_unaligned_le32(packet.header);
 689         dsi_write(dsi, DSI_GEN_HDR, val);
 690
 691         ret = rockchip_wait_write_fifo_empty(dsi);
 692         if (ret)
 693                 return ret;
 694
 695         return len;
 696 }
 697
 698 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 699         .attach = dw_mipi_dsi_host_attach,
 700         .detach = dw_mipi_dsi_host_detach,
 701         .transfer = dw_mipi_dsi_host_transfer,
 702 };
 703
 704 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 705 {
 706         u32 val;
 707
 708         val = LP_HFP_EN | ENABLE_LOW_POWER;
 709
 710         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 711                 val |= VID_MODE_TYPE_BURST;
 712         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 713                 val |= VID_MODE_TYPE_BURST_SYNC_PULSES;
 714         else
 715                 val |= VID_MODE_TYPE_BURST_SYNC_EVENTS;
 716
 717         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 718 }
 719
 720 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 721                                  enum dw_mipi_dsi_mode mode)
 722 {
 723         if (mode == DSI_COMMAND_MODE)
 724                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 725         else
 726                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 727 }
 728
 729 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 730 {
 731         dsi_write(dsi, DSI_PWR_UP, RESET);
 732         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 733                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 734         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 735                   TX_ESC_CLK_DIVIDSION(7));
 736         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 737 }
 738
 739 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 740                                    struct drm_display_mode *mode)
 741 {
 742         u32 val = 0, color = 0;
 743
 744         switch (dsi->format) {
 745         case MIPI_DSI_FMT_RGB888:
 746                 color = DPI_COLOR_CODING_24BIT;
 747                 break;
 748         case MIPI_DSI_FMT_RGB666:
 749                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 750                 break;
 751         case MIPI_DSI_FMT_RGB666_PACKED:
 752                 color = DPI_COLOR_CODING_18BIT_1;
 753                 break;
 754         case MIPI_DSI_FMT_RGB565:
 755                 color = DPI_COLOR_CODING_16BIT_1;
 756                 break;
 757         }
 758
 759         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 760                 val |= VSYNC_ACTIVE_LOW;
 761         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 762                 val |= HSYNC_ACTIVE_LOW;
 763
 764         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 765         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 766         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 767         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 768                   | INVACT_LPCMD_TIME(4));
 769 }
 770
 771 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 772 {
 773         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 774 }
 775
 776 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 777                                             struct drm_display_mode *mode)
 778 {
 779         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 780 }
 781
 782 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 783 {
 784         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 785         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 786 }
 787
 788 /* Get lane byte clock cycles. */
 789 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 790                                            u32 hcomponent)
 791 {
 792         u32 frac, lbcc;
 793
 794         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 795
 796         frac = lbcc % dsi->mode.clock;
 797         lbcc = lbcc / dsi->mode.clock;
 798         if (frac)
 799                 lbcc++;
 800
 801         return lbcc;
 802 }
 803
 804 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 805 {
 806         u32 htotal, hsa, hbp, lbcc;
 807         struct drm_display_mode *mode = &dsi->mode;
 808
 809         htotal = mode->htotal;
 810         hsa = mode->hsync_end - mode->hsync_start;
 811         hbp = mode->htotal - mode->hsync_end;
 812
 813         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 814         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 815
 816         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 817         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 818
 819         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 820         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 821 }
 822
 823 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 824 {
 825         u32 vactive, vsa, vfp, vbp;
 826         struct drm_display_mode *mode = &dsi->mode;
 827
 828         vactive = mode->vdisplay;
 829         vsa = mode->vsync_end - mode->vsync_start;
 830         vfp = mode->vsync_start - mode->vdisplay;
 831         vbp = mode->vtotal - mode->vsync_end;
 832
 833         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 834         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 835         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 836         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 837 }
 838
 839 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 840 {
 841         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 842                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 843
 844         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 845                   | PHY_CLKLP2HS_TIME(0x40));
 846 }
 847
 848 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 849 {
 850         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 851                   N_LANES(dsi->lanes));
 852 }
 853
 854 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 855 {
 856         dsi_read(dsi, DSI_INT_ST0);
 857         dsi_read(dsi, DSI_INT_ST1);
 858         dsi_write(dsi, DSI_INT_MSK0, 0);
 859         dsi_write(dsi, DSI_INT_MSK1, 0);
 860 }
 861
 862 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 863                                         struct drm_display_mode *mode,
 864                                         struct drm_display_mode *adjusted_mode)
 865 {
 866         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 867
 868         drm_mode_copy(&dsi->mode, adjusted_mode);
 869 }
 870
 871 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
 872 {
 873         if (clk_prepare_enable(dsi->pclk)) {
 874                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 875                 return;
 876         }
 877
 878         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 879 }
 880
 881 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
 882 {
 883         /* host */
 884         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 885         dsi_write(dsi, DSI_PWR_UP, RESET);
 886
 887         /* phy */
 888         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 889         if (dsi->phy)
 890                 phy_power_off(dsi->phy);
 891
 892         pm_runtime_put(dsi->dev);
 893         clk_disable_unprepare(dsi->pclk);
 894 }
 895
 896 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 897 {
 898         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 899
 900         if (dsi->panel)
 901                 drm_panel_disable(dsi->panel);
 902
 903         rockchip_dsi_pre_disable(dsi);
 904
 905         if (dsi->panel)
 906                 drm_panel_unprepare(dsi->panel);
 907
 908         rockchip_dsi_disable(dsi);
 909 }
 910
 911 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 912                                         const struct drm_display_mode *mode,
 913                                         struct drm_display_mode *adjusted_mode)
 914 {
 915         return true;
 916 }
 917
 918 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
 919 {
 920         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 921         int val = 0;
 922
 923         if (vop_id)
 924                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 925         else
 926                 val = pdata->dsi0_en_bit << 16;
 927
 928         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 929
 930         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
 931 }
 932
 933 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
 934 {
 935         if (clk_prepare_enable(dsi->pclk)) {
 936                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 937                 return;
 938         }
 939
 940         if (clk_prepare_enable(dsi->pllref_clk)) {
 941                 dev_err(dsi->dev, "Failed to enable pllref_clk\n");
 942                 return;
 943         }
 944
 945         pm_runtime_get_sync(dsi->dev);
 946
 947         if (dsi->rst) {
 948                 /* MIPI DSI APB software reset request. */
 949                 reset_control_assert(dsi->rst);
 950                 udelay(10);
 951                 reset_control_deassert(dsi->rst);
 952                 udelay(10);
 953         }
 954
 955         if (dsi->phy) {
 956                 phy_power_on(dsi->phy);
 957
 958                 /*
 959                  * If using the third party PHY, we get the lane
 960                  * rate information from PHY.
 961                  */
 962                 dsi->lane_mbps = phy_get_bus_width(dsi->phy);
 963         } else {
 964                 dw_mipi_dsi_get_lane_bps(dsi);
 965         }
 966 }
 967
 968 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
 969 {
 970         dw_mipi_dsi_init(dsi);
 971         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 972         dw_mipi_dsi_packet_handler_config(dsi);
 973         dw_mipi_dsi_video_mode_config(dsi);
 974         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 975         dw_mipi_dsi_command_mode_config(dsi);
 976         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 977         dw_mipi_dsi_line_timer_config(dsi);
 978         dw_mipi_dsi_vertical_timing_config(dsi);
 979         dw_mipi_dsi_dphy_timing_config(dsi);
 980         dw_mipi_dsi_dphy_interface_config(dsi);
 981         dw_mipi_dsi_clear_err(dsi);
 982 }
 983
 984 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
 985 {
 986         rockchip_dsi_pre_init(dsi);
 987         rockchip_dsi_host_init(dsi);
 988         dw_mipi_dsi_phy_init(dsi);
 989 }
 990
 991 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
 992 {
 993         dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
 994         clk_disable_unprepare(dsi->pllref_clk);
 995         clk_disable_unprepare(dsi->pclk);
 996 }
 997
 998 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 999 {
1000         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1001         int vop_id;
1002
1003         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
1004
1005         rockchip_dsi_grf_config(dsi, vop_id);
1006         rockchip_dsi_init(dsi);
1007
1008         if (dsi->panel)
1009                 drm_panel_prepare(dsi->panel);
1010
1011         rockchip_dsi_enable(dsi);
1012
1013         if (dsi->panel)
1014                 drm_panel_enable(dsi->panel);
1015 }
1016
1017 static int
1018 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1019                                  struct drm_crtc_state *crtc_state,
1020                                  struct drm_connector_state *conn_state)
1021 {
1022         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1023         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1024         struct drm_connector *connector = conn_state->connector;
1025         struct drm_display_info *info = &connector->display_info;
1026
1027         switch (dsi->format) {
1028         case MIPI_DSI_FMT_RGB888:
1029                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1030                 break;
1031         case MIPI_DSI_FMT_RGB666:
1032                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1033                 break;
1034         case MIPI_DSI_FMT_RGB565:
1035                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1036                 break;
1037         default:
1038                 WARN_ON(1);
1039                 return -EINVAL;
1040         }
1041
1042         s->output_type = DRM_MODE_CONNECTOR_DSI;
1043         if (info->num_bus_formats)
1044                 s->bus_format = info->bus_formats[0];
1045
1046         return 0;
1047 }
1048
1049 static struct drm_encoder_helper_funcs
1050 dw_mipi_dsi_encoder_helper_funcs = {
1051         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1052         .mode_set = dw_mipi_dsi_encoder_mode_set,
1053         .enable = dw_mipi_dsi_encoder_enable,
1054         .disable = dw_mipi_dsi_encoder_disable,
1055         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1056 };
1057
1058 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1059         .destroy = drm_encoder_cleanup,
1060 };
1061
1062 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1063 {
1064         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1065
1066         return drm_panel_get_modes(dsi->panel);
1067 }
1068
1069 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1070                                         struct drm_connector *connector,
1071                                         struct drm_display_mode *mode)
1072 {
1073         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1074
1075         enum drm_mode_status mode_status = MODE_OK;
1076
1077         if (dsi->pdata->mode_valid)
1078                 mode_status = dsi->pdata->mode_valid(connector, mode);
1079
1080         return mode_status;
1081 }
1082
1083 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1084                                         struct drm_connector *connector)
1085 {
1086         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1087
1088         return &dsi->encoder;
1089 }
1090
1091 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1092 {
1093         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1094
1095         if (dsi->panel)
1096                 drm_panel_loader_protect(dsi->panel, on);
1097         if (on)
1098                 pm_runtime_get_sync(dsi->dev);
1099         else
1100                 pm_runtime_put(dsi->dev);
1101
1102         return 0;
1103 }
1104
1105 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1106         .loader_protect = dw_mipi_loader_protect,
1107         .get_modes = dw_mipi_dsi_connector_get_modes,
1108         .mode_valid = dw_mipi_dsi_mode_valid,
1109         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1110 };
1111
1112 static enum drm_connector_status
1113 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1114 {
1115         return connector_status_connected;
1116 }
1117
1118 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1119 {
1120         drm_connector_unregister(connector);
1121         drm_connector_cleanup(connector);
1122 }
1123
1124 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1125         .dpms = drm_atomic_helper_connector_dpms,
1126         .fill_modes = drm_helper_probe_single_connector_modes,
1127         .detect = dw_mipi_dsi_detect,
1128         .destroy = dw_mipi_dsi_drm_connector_destroy,
1129         .reset = drm_atomic_helper_connector_reset,
1130         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1131         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1132 };
1133
1134 static int dw_mipi_dsi_register(struct drm_device *drm,
1135                                       struct dw_mipi_dsi *dsi)
1136 {
1137         struct drm_encoder *encoder = &dsi->encoder;
1138         struct drm_connector *connector = &dsi->connector;
1139         struct device *dev = dsi->dev;
1140         int ret;
1141
1142         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1143                                                              dev->of_node);
1144         /*
1145          * If we failed to find the CRTC(s) which this encoder is
1146          * supposed to be connected to, it's because the CRTC has
1147          * not been registered yet.  Defer probing, and hope that
1148          * the required CRTC is added later.
1149          */
1150         if (encoder->possible_crtcs == 0)
1151                 return -EPROBE_DEFER;
1152
1153         drm_encoder_helper_add(&dsi->encoder,
1154                                &dw_mipi_dsi_encoder_helper_funcs);
1155         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1156                          DRM_MODE_ENCODER_DSI, NULL);
1157         if (ret) {
1158                 dev_err(dev, "Failed to initialize encoder with drm\n");
1159                 return ret;
1160         }
1161
1162         drm_connector_helper_add(connector,
1163                         &dw_mipi_dsi_connector_helper_funcs);
1164
1165         drm_connector_init(drm, &dsi->connector,
1166                            &dw_mipi_dsi_atomic_connector_funcs,
1167                            DRM_MODE_CONNECTOR_DSI);
1168
1169         drm_panel_attach(dsi->panel, &dsi->connector);
1170
1171         dsi->connector.port = dev->of_node;
1172
1173         drm_mode_connector_attach_encoder(connector, encoder);
1174
1175         return 0;
1176 }
1177
1178 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1179         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1180         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1181         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1182         .max_data_lanes = 4,
1183         .max_bit_rate_per_lane = 1500000000,
1184         .has_vop_sel = true,
1185 };
1186
1187 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1188         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1189         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1190         .max_data_lanes = 4,
1191         .max_bit_rate_per_lane = 1000000000,
1192         .has_vop_sel = true,
1193 };
1194
1195 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1196         .max_data_lanes = 4,
1197         .max_bit_rate_per_lane = 1000000000,
1198 };
1199
1200 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1201         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1202         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1203         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1204         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1205         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1206         .max_data_lanes = 4,
1207         .max_bit_rate_per_lane = 1500000000,
1208         .has_vop_sel = true,
1209 };
1210
1211 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1212         {
1213          .compatible = "rockchip,rk3288-mipi-dsi",
1214          .data = &rk3288_mipi_dsi_drv_data,
1215         }, {
1216          .compatible = "rockchip,rk3366-mipi-dsi",
1217          .data = &rk3366_mipi_dsi_drv_data,
1218         }, {
1219          .compatible = "rockchip,rk3368-mipi-dsi",
1220          .data = &rk3368_mipi_dsi_drv_data,
1221         }, {
1222          .compatible = "rockchip,rk3399-mipi-dsi",
1223          .data = &rk3399_mipi_dsi_drv_data,
1224         },
1225         { /* sentinel */ }
1226 };
1227 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1228
1229 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1230                              void *data)
1231 {
1232         struct drm_device *drm = data;
1233         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1234         int ret;
1235
1236         if (!dsi->panel)
1237                 return -EPROBE_DEFER;
1238
1239         ret = dw_mipi_dsi_register(drm, dsi);
1240         if (ret) {
1241                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1242                 return ret;
1243         }
1244
1245         dev_set_drvdata(dev, dsi);
1246
1247         pm_runtime_enable(dev);
1248
1249         return ret;
1250 }
1251
1252 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1253         void *data)
1254 {
1255         pm_runtime_disable(dev);
1256 }
1257
1258 static const struct component_ops dw_mipi_dsi_ops = {
1259         .bind   = dw_mipi_dsi_bind,
1260         .unbind = dw_mipi_dsi_unbind,
1261 };
1262
1263 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
1264 {
1265         struct device *dev = dsi->dev;
1266
1267         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1268         if (IS_ERR(dsi->rst)) {
1269                 dev_info(dev, "no reset control specified\n");
1270                 dsi->rst = NULL;
1271         }
1272
1273         return 0;
1274 }
1275
1276 static int rockchip_dsi_grf_regmap(struct dw_mipi_dsi *dsi)
1277 {
1278         struct device_node *np = dsi->dev->of_node;
1279
1280         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1281         if (IS_ERR(dsi->grf_regmap)) {
1282                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1283                 return PTR_ERR(dsi->grf_regmap);
1284         }
1285
1286         return 0;
1287 }
1288
1289 static int rockchip_dsi_clk_get(struct dw_mipi_dsi *dsi)
1290 {
1291         struct device *dev = dsi->dev;
1292         int ret;
1293
1294         dsi->pclk = devm_clk_get(dev, "pclk");
1295         if (IS_ERR(dsi->pclk)) {
1296                 ret = PTR_ERR(dsi->pclk);
1297                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1298                 return ret;
1299         }
1300
1301         dsi->pllref_clk = devm_clk_get(dev, "ref");
1302         if (IS_ERR(dsi->pllref_clk)) {
1303                 dev_info(dev, "No PHY reference clock specified\n");
1304                 dsi->pllref_clk = NULL;
1305         }
1306
1307         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1308         if (IS_ERR(dsi->phy_cfg_clk)) {
1309                 dev_info(dev, "No PHY APB clock specified\n");
1310                 dsi->phy_cfg_clk = NULL;
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int rockchip_dsi_dphy_parse(struct dw_mipi_dsi *dsi)
1317 {
1318         struct device *dev = dsi->dev;
1319         int ret;
1320
1321         dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
1322         if (IS_ERR(dsi->phy)) {
1323                 ret = PTR_ERR(dsi->phy);
1324                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1325                 return ret;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int rockchip_dsi_ioremap_resource(struct platform_device *pdev,
1332                                          struct dw_mipi_dsi *dsi)
1333 {
1334         struct device *dev = &pdev->dev;
1335         struct resource *res;
1336
1337         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1338         if (!res)
1339                 return -ENODEV;
1340
1341         dsi->base = devm_ioremap_resource(dev, res);
1342         if (IS_ERR(dsi->base))
1343                 return PTR_ERR(dsi->base);
1344
1345         return 0;
1346 }
1347
1348 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1349 {
1350         struct device *dev = &pdev->dev;
1351         const struct of_device_id *of_id =
1352                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1353         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1354         struct dw_mipi_dsi *dsi;
1355         int ret;
1356
1357         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1358         if (!dsi)
1359                 return -ENOMEM;
1360
1361         dsi->dev = dev;
1362         dsi->pdata = pdata;
1363
1364         rockchip_dsi_ioremap_resource(pdev, dsi);
1365         rockchip_dsi_clk_get(dsi);
1366         rockchip_dsi_dphy_parse(dsi);
1367         rockchip_dsi_grf_regmap(dsi);
1368         rockchip_dsi_get_reset_handle(dsi);
1369
1370         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1371         dsi->dsi_host.dev = &pdev->dev;
1372
1373         ret = mipi_dsi_host_register(&dsi->dsi_host);
1374         if (ret)
1375                 return ret;
1376
1377         platform_set_drvdata(pdev, dsi);
1378         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1379         if (ret)
1380                 mipi_dsi_host_unregister(&dsi->dsi_host);
1381
1382         return ret;
1383 }
1384
1385 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1386 {
1387         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1388
1389         if (dsi)
1390                 mipi_dsi_host_unregister(&dsi->dsi_host);
1391         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1392         return 0;
1393 }
1394
1395 static struct platform_driver dw_mipi_dsi_driver = {
1396         .probe          = dw_mipi_dsi_probe,
1397         .remove         = dw_mipi_dsi_remove,
1398         .driver         = {
1399                 .of_match_table = dw_mipi_dsi_dt_ids,
1400                 .name   = DRIVER_NAME,
1401         },
1402 };
1403 module_platform_driver(dw_mipi_dsi_driver);
1404
1405 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1406 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1407 MODULE_LICENSE("GPL");
1408 MODULE_ALIAS("platform:" DRIVER_NAME);