drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drmP.h>
  27 #include <video/mipi_display.h>
  28 #include <asm/unaligned.h>
  29
  30 #include "rockchip_drm_drv.h"
  31 #include "rockchip_drm_vop.h"
  32
  33 #define DRIVER_NAME    "dw-mipi-dsi"
  34
  35 #define RK3288_GRF_SOC_CON6             0x025c
  36 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  37 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  38
  39 #define RK3366_GRF_SOC_CON0             0x0400
  40 #define RK3366_DSI_SEL_VOP_LIT          BIT(2)
  41
  42 #define RK3399_GRF_SOC_CON19            0x6250
  43 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  44 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  45
  46 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  47 #define RK3399_GRF_SOC_CON22            0x6258
  48 #define RK3399_GRF_DSI_MODE             0xffff0000
  49
  50 #define DSI_VERSION                     0x00
  51 #define DSI_PWR_UP                      0x04
  52 #define RESET                           0
  53 #define POWERUP                         BIT(0)
  54
  55 #define DSI_CLKMGR_CFG                  0x08
  56 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  57 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  58
  59 #define DSI_DPI_VCID                    0x0c
  60 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  61
  62 #define DSI_DPI_COLOR_CODING            0x10
  63 #define EN18_LOOSELY                    BIT(8)
  64 #define DPI_COLOR_CODING_16BIT_1        0x0
  65 #define DPI_COLOR_CODING_16BIT_2        0x1
  66 #define DPI_COLOR_CODING_16BIT_3        0x2
  67 #define DPI_COLOR_CODING_18BIT_1        0x3
  68 #define DPI_COLOR_CODING_18BIT_2        0x4
  69 #define DPI_COLOR_CODING_24BIT          0x5
  70
  71 #define DSI_DPI_CFG_POL                 0x14
  72 #define COLORM_ACTIVE_LOW               BIT(4)
  73 #define SHUTD_ACTIVE_LOW                BIT(3)
  74 #define HSYNC_ACTIVE_LOW                BIT(2)
  75 #define VSYNC_ACTIVE_LOW                BIT(1)
  76 #define DATAEN_ACTIVE_LOW               BIT(0)
  77
  78 #define DSI_DPI_LP_CMD_TIM              0x18
  79 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  80 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  81
  82 #define DSI_DBI_CFG                     0x20
  83 #define DSI_DBI_CMDSIZE                 0x28
  84
  85 #define DSI_PCKHDL_CFG                  0x2c
  86 #define EN_CRC_RX                       BIT(4)
  87 #define EN_ECC_RX                       BIT(3)
  88 #define EN_BTA                          BIT(2)
  89 #define EN_EOTP_RX                      BIT(1)
  90 #define EN_EOTP_TX                      BIT(0)
  91
  92 #define DSI_MODE_CFG                    0x34
  93 #define ENABLE_VIDEO_MODE               0
  94 #define ENABLE_CMD_MODE                 BIT(0)
  95
  96 #define DSI_VID_MODE_CFG                0x38
  97 #define FRAME_BTA_ACK                   BIT(14)
  98 #define ENABLE_LOW_POWER                (0x3f << 8)
  99 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
 100 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
 101 #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
 102 #define VID_MODE_TYPE_BURST             0x2
 103
 104 #define DSI_VID_PKT_SIZE                0x3c
 105 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 106 #define VID_PKT_MAX_SIZE                0x3fff
 107
 108 #define DSI_VID_NUM_CHUMKS              0x40
 109 #define DSI_VID_NULL_PKT_SIZE           0x44
 110 #define DSI_VID_HSA_TIME                0x48
 111 #define DSI_VID_HBP_TIME                0x4c
 112 #define DSI_VID_HLINE_TIME              0x50
 113 #define DSI_VID_VSA_LINES               0x54
 114 #define DSI_VID_VBP_LINES               0x58
 115 #define DSI_VID_VFP_LINES               0x5c
 116 #define DSI_VID_VACTIVE_LINES           0x60
 117 #define DSI_CMD_MODE_CFG                0x68
 118 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 119 #define DCS_LW_TX_LP                    BIT(19)
 120 #define DCS_SR_0P_TX_LP                 BIT(18)
 121 #define DCS_SW_1P_TX_LP                 BIT(17)
 122 #define DCS_SW_0P_TX_LP                 BIT(16)
 123 #define GEN_LW_TX_LP                    BIT(14)
 124 #define GEN_SR_2P_TX_LP                 BIT(13)
 125 #define GEN_SR_1P_TX_LP                 BIT(12)
 126 #define GEN_SR_0P_TX_LP                 BIT(11)
 127 #define GEN_SW_2P_TX_LP                 BIT(10)
 128 #define GEN_SW_1P_TX_LP                 BIT(9)
 129 #define GEN_SW_0P_TX_LP                 BIT(8)
 130 #define EN_ACK_RQST                     BIT(1)
 131 #define EN_TEAR_FX                      BIT(0)
 132
 133 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 134                                          DCS_LW_TX_LP | \
 135                                          DCS_SR_0P_TX_LP | \
 136                                          DCS_SW_1P_TX_LP | \
 137                                          DCS_SW_0P_TX_LP | \
 138                                          GEN_LW_TX_LP | \
 139                                          GEN_SR_2P_TX_LP | \
 140                                          GEN_SR_1P_TX_LP | \
 141                                          GEN_SR_0P_TX_LP | \
 142                                          GEN_SW_2P_TX_LP | \
 143                                          GEN_SW_1P_TX_LP | \
 144                                          GEN_SW_0P_TX_LP)
 145
 146 #define DSI_GEN_HDR                     0x6c
 147 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 148 #define GEN_HDATA_MASK                  (0xffff << 8)
 149 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 150 #define GEN_HTYPE_MASK                  0xff
 151
 152 #define DSI_GEN_PLD_DATA                0x70
 153
 154 #define DSI_CMD_PKT_STATUS              0x74
 155 #define GEN_CMD_EMPTY                   BIT(0)
 156 #define GEN_CMD_FULL                    BIT(1)
 157 #define GEN_PLD_W_EMPTY                 BIT(2)
 158 #define GEN_PLD_W_FULL                  BIT(3)
 159 #define GEN_PLD_R_EMPTY                 BIT(4)
 160 #define GEN_PLD_R_FULL                  BIT(5)
 161 #define GEN_RD_CMD_BUSY                 BIT(6)
 162
 163 #define DSI_TO_CNT_CFG                  0x78
 164 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 165 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 166
 167 #define DSI_BTA_TO_CNT                  0x8c
 168 #define DSI_LPCLK_CTRL                  0x94
 169 #define AUTO_CLKLANE_CTRL               BIT(1)
 170 #define PHY_TXREQUESTCLKHS              BIT(0)
 171
 172 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 173 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 174 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 175
 176 #define DSI_PHY_TMR_CFG                 0x9c
 177 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 178 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 179 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 180
 181 #define DSI_PHY_RSTZ                    0xa0
 182 #define PHY_DISFORCEPLL                 0
 183 #define PHY_ENFORCEPLL                  BIT(3)
 184 #define PHY_DISABLECLK                  0
 185 #define PHY_ENABLECLK                   BIT(2)
 186 #define PHY_RSTZ                        0
 187 #define PHY_UNRSTZ                      BIT(1)
 188 #define PHY_SHUTDOWNZ                   0
 189 #define PHY_UNSHUTDOWNZ                 BIT(0)
 190
 191 #define DSI_PHY_IF_CFG                  0xa4
 192 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 193 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 194
 195 #define DSI_PHY_STATUS                  0xb0
 196 #define LOCK                            BIT(0)
 197 #define STOP_STATE_CLK_LANE             BIT(2)
 198
 199 #define DSI_PHY_TST_CTRL0               0xb4
 200 #define PHY_TESTCLK                     BIT(1)
 201 #define PHY_UNTESTCLK                   0
 202 #define PHY_TESTCLR                     BIT(0)
 203 #define PHY_UNTESTCLR                   0
 204
 205 #define DSI_PHY_TST_CTRL1               0xb8
 206 #define PHY_TESTEN                      BIT(16)
 207 #define PHY_UNTESTEN                    0
 208 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 209 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 210
 211 #define DSI_INT_ST0                     0xbc
 212 #define DSI_INT_ST1                     0xc0
 213 #define DSI_INT_MSK0                    0xc4
 214 #define DSI_INT_MSK1                    0xc8
 215
 216 #define PHY_STATUS_TIMEOUT_US           10000
 217 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 218
 219 #define BYPASS_VCO_RANGE        BIT(7)
 220 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 221 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 222 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 223 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 224 #define REF_BIAS_CUR_SEL        BIT(0)
 225
 226 #define CP_CURRENT_3MA          BIT(3)
 227 #define CP_PROGRAM_EN           BIT(7)
 228 #define LPF_PROGRAM_EN          BIT(6)
 229 #define LPF_RESISTORS_20_KOHM   0
 230
 231 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 232
 233 #define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
 234 #define LOW_PROGRAM_EN          0
 235 #define HIGH_PROGRAM_EN         BIT(7)
 236 #define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
 237 #define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0x1f)
 238 #define PLL_LOOP_DIV_EN         BIT(5)
 239 #define PLL_INPUT_DIV_EN        BIT(4)
 240
 241 #define POWER_CONTROL           BIT(6)
 242 #define INTERNAL_REG_CURRENT    BIT(3)
 243 #define BIAS_BLOCK_ON           BIT(2)
 244 #define BANDGAP_ON              BIT(0)
 245
 246 #define TER_RESISTOR_HIGH       BIT(7)
 247 #define TER_RESISTOR_LOW        0
 248 #define LEVEL_SHIFTERS_ON       BIT(6)
 249 #define TER_CAL_DONE            BIT(5)
 250 #define SETRD_MAX               (0x7 << 2)
 251 #define POWER_MANAGE            BIT(1)
 252 #define TER_RESISTORS_ON        BIT(0)
 253
 254 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 255 #define BANDGAP_SEL(val)        ((val) & 0x7)
 256 #define TLP_PROGRAM_EN          BIT(7)
 257 #define THS_PRE_PROGRAM_EN      BIT(7)
 258 #define THS_ZERO_PROGRAM_EN     BIT(6)
 259
 260 enum {
 261         BANDGAP_97_07,
 262         BANDGAP_98_05,
 263         BANDGAP_99_02,
 264         BANDGAP_100_00,
 265         BANDGAP_93_17,
 266         BANDGAP_94_15,
 267         BANDGAP_95_12,
 268         BANDGAP_96_10,
 269 };
 270
 271 enum {
 272         BIASEXTR_87_1,
 273         BIASEXTR_91_5,
 274         BIASEXTR_95_9,
 275         BIASEXTR_100,
 276         BIASEXTR_105_94,
 277         BIASEXTR_111_88,
 278         BIASEXTR_118_8,
 279         BIASEXTR_127_7,
 280 };
 281
 282 struct dw_mipi_dsi_plat_data {
 283         u32 dsi0_en_bit;
 284         u32 dsi1_en_bit;
 285         u32 grf_switch_reg;
 286         u32 grf_dsi0_mode;
 287         u32 grf_dsi0_mode_reg;
 288         unsigned int max_data_lanes;
 289         u32 max_bit_rate_per_lane;
 290         bool has_vop_sel;
 291         enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 292                                            struct drm_display_mode *mode);
 293 };
 294
 295 struct dw_mipi_dsi {
 296         struct drm_encoder encoder;
 297         struct drm_connector connector;
 298         struct mipi_dsi_host dsi_host;
 299         struct phy *phy;
 300         struct drm_panel *panel;
 301         struct device *dev;
 302         struct regmap *grf_regmap;
 303         struct reset_control *rst;
 304         void __iomem *base;
 305
 306         struct clk *pllref_clk;
 307         struct clk *pclk;
 308         struct clk *phy_cfg_clk;
 309
 310         unsigned long mode_flags;
 311         unsigned int lane_mbps; /* per lane */
 312         u32 channel;
 313         u32 lanes;
 314         u32 format;
 315         u16 input_div;
 316         u16 feedback_div;
 317         struct drm_display_mode mode;
 318
 319         const struct dw_mipi_dsi_plat_data *pdata;
 320 };
 321
 322 enum dw_mipi_dsi_mode {
 323         DSI_COMMAND_MODE,
 324         DSI_VIDEO_MODE,
 325 };
 326
 327 struct dphy_pll_testdin_map {
 328         unsigned int max_mbps;
 329         u8 testdin;
 330 };
 331
 332 /* The table is based on 27MHz DPHY pll reference clock. */
 333 static const struct dphy_pll_testdin_map dptdin_map[] = {
 334         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 335         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 336         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 337         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 338         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 339         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 340         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 341         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 342         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 343         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 344 };
 345
 346 static int max_mbps_to_testdin(unsigned int max_mbps)
 347 {
 348         int i;
 349
 350         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 351                 if (dptdin_map[i].max_mbps > max_mbps)
 352                         return dptdin_map[i].testdin;
 353
 354         return -EINVAL;
 355 }
 356
 357 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 358 {
 359         return container_of(host, struct dw_mipi_dsi, dsi_host);
 360 }
 361
 362 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 363 {
 364         return container_of(con, struct dw_mipi_dsi, connector);
 365 }
 366
 367 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 368 {
 369         return container_of(encoder, struct dw_mipi_dsi, encoder);
 370 }
 371 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 372 {
 373         writel(val, dsi->base + reg);
 374 }
 375
 376 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 377 {
 378         return readl(dsi->base + reg);
 379 }
 380
 381 static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
 382 {
 383         u32 sts;
 384         int ret;
 385
 386         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 387                                  sts, !(sts & GEN_PLD_W_FULL), 10,
 388                                  CMD_PKT_STATUS_TIMEOUT_US);
 389         if (ret < 0) {
 390                 dev_err(dsi->dev, "generic write payload fifo is full\n");
 391                 return ret;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
 398 {
 399         u32 sts;
 400         int ret;
 401
 402         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 403                                  sts, !(sts & GEN_CMD_FULL), 10,
 404                                  CMD_PKT_STATUS_TIMEOUT_US);
 405         if (ret < 0) {
 406                 dev_err(dsi->dev, "generic write cmd fifo is full\n");
 407                 return ret;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
 414 {
 415         u32 sts;
 416         u32 mask;
 417         int ret;
 418
 419         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 420         ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 421                                  sts, (sts & mask) == mask, 10,
 422                                  CMD_PKT_STATUS_TIMEOUT_US);
 423         if (ret < 0) {
 424                 dev_err(dsi->dev, "generic write fifo is full\n");
 425                 return ret;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 432                                  u8 test_data)
 433 {
 434         /*
 435          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 436          * is latched internally as the current test code. Test data is
 437          * programmed internally by rising edge on TESTCLK.
 438          */
 439         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 440
 441         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 442                                           PHY_TESTDIN(test_code));
 443
 444         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 445
 446         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 447                                           PHY_TESTDIN(test_data));
 448
 449         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 450 }
 451
 452 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 453 {
 454         int ret, testdin, vco, val;
 455
 456         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 457
 458         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 459         if (testdin < 0) {
 460                 dev_err(dsi->dev,
 461                         "failed to get testdin for %dmbps lane clock\n",
 462                         dsi->lane_mbps);
 463                 return testdin;
 464         }
 465
 466         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 467
 468         if (!IS_ERR(dsi->phy_cfg_clk)) {
 469                 ret = clk_prepare_enable(dsi->phy_cfg_clk);
 470                 if (ret) {
 471                         dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 472                         return ret;
 473                 }
 474         }
 475
 476         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 477                                          VCO_RANGE_CON_SEL(vco) |
 478                                          VCO_IN_CAP_CON_LOW |
 479                                          REF_BIAS_CUR_SEL);
 480
 481         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 482         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 483                                          LPF_RESISTORS_20_KOHM);
 484
 485         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 486
 487         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 488         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 489         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 490                                          LOW_PROGRAM_EN);
 491         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 492                                          HIGH_PROGRAM_EN);
 493
 494         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 495                                          BIAS_BLOCK_ON | BANDGAP_ON);
 496
 497         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 498                                          SETRD_MAX | TER_RESISTORS_ON);
 499         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 500                                          SETRD_MAX | POWER_MANAGE |
 501                                          TER_RESISTORS_ON);
 502
 503         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 504                                          BIASEXTR_SEL(BIASEXTR_127_7));
 505         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 506                                          BANDGAP_SEL(BANDGAP_96_10));
 507
 508         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 509         dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
 510         dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
 511
 512         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 513                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 514
 515
 516         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 517                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 518         if (ret < 0) {
 519                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 520                 goto phy_init_end;
 521         }
 522
 523         ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
 524                                  val, val & STOP_STATE_CLK_LANE, 1000,
 525                                  PHY_STATUS_TIMEOUT_US);
 526         if (ret < 0)
 527                 dev_err(dsi->dev,
 528                         "failed to wait for phy clk lane stop state\n");
 529
 530 phy_init_end:
 531         if (!IS_ERR(dsi->phy_cfg_clk))
 532                 clk_disable_unprepare(dsi->phy_cfg_clk);
 533
 534         return ret;
 535 }
 536
 537 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
 538 {
 539         unsigned int i, pre;
 540         unsigned long mpclk, pllref, tmp;
 541         unsigned int m = 1, n = 1, target_mbps = 1000;
 542         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 543         int bpp;
 544
 545         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 546         if (bpp < 0) {
 547                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 548                         dsi->format);
 549                 return bpp;
 550         }
 551
 552         mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
 553         if (mpclk) {
 554                 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
 555                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
 556                 if (tmp < max_mbps)
 557                         target_mbps = tmp;
 558                 else
 559                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 560         }
 561
 562         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 563         tmp = pllref;
 564
 565         for (i = 1; i < 6; i++) {
 566                 pre = pllref / i;
 567                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 568                         tmp = target_mbps % pre;
 569                         n = i;
 570                         m = target_mbps / pre;
 571                 }
 572                 if (tmp == 0)
 573                         break;
 574         }
 575
 576         dsi->lane_mbps = pllref / n * m;
 577         dsi->input_div = n;
 578         dsi->feedback_div = m;
 579
 580         return 0;
 581 }
 582
 583 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 584                                    struct mipi_dsi_device *device)
 585 {
 586         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 587
 588         if (device->lanes > dsi->pdata->max_data_lanes) {
 589                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 590                                 device->lanes);
 591                 return -EINVAL;
 592         }
 593
 594         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
 595                 dev_err(dsi->dev, "device mode is unsupported\n");
 596                 return -EINVAL;
 597         }
 598
 599         dsi->lanes = device->lanes;
 600         dsi->channel = device->channel;
 601         dsi->format = device->format;
 602         dsi->mode_flags = device->mode_flags;
 603
 604         dsi->panel = of_drm_find_panel(device->dev.of_node);
 605         if (!dsi->panel) {
 606                 DRM_ERROR("failed to find panel\n");
 607                 return -ENODEV;
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 614                                    struct mipi_dsi_device *device)
 615 {
 616         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 617
 618         if (dsi->panel)
 619                 drm_panel_detach(dsi->panel);
 620
 621         dsi->panel = NULL;
 622         return 0;
 623 }
 624
 625 static void rockchip_set_transfer_mode(struct dw_mipi_dsi *dsi, int flags)
 626 {
 627         if (flags & MIPI_DSI_MSG_USE_LPM)
 628                 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
 629         else
 630                 dsi_write(dsi, DSI_CMD_MODE_CFG, 0);
 631 }
 632
 633 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 634                                          const struct mipi_dsi_msg *msg)
 635 {
 636         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 637         struct mipi_dsi_packet packet;
 638         int ret;
 639         int val;
 640         int len = msg->tx_len;
 641
 642         /* create a packet to the DSI protocol */
 643         ret = mipi_dsi_create_packet(&packet, msg);
 644         if (ret) {
 645                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 646                 return ret;
 647         }
 648
 649         rockchip_set_transfer_mode(dsi, msg->flags);
 650
 651         /* Send payload,  */
 652         while (DIV_ROUND_UP(packet.payload_length, 4)) {
 653                 /*
 654                  * Alternatively, you can always keep the FIFO
 655                  * nearly full by monitoring the FIFO state until
 656                  * it is not full, and then writea single word of data.
 657                  * This solution is more resource consuming
 658                  * but it simultaneously avoids FIFO starvation,
 659                  * making it possible to use FIFO sizes smaller than
 660                  * the amount of data of the longest packet to be written.
 661                  */
 662                 ret = rockchip_wait_w_pld_fifo_not_full(dsi);
 663                 if (ret)
 664                         return ret;
 665
 666                 if (packet.payload_length < 4) {
 667                         /* send residu payload */
 668                         val = 0;
 669                         memcpy(&val, packet.payload, packet.payload_length);
 670                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 671                         packet.payload_length = 0;
 672                 } else {
 673                         val = get_unaligned_le32(packet.payload);
 674                         dsi_write(dsi, DSI_GEN_PLD_DATA, val);
 675                         packet.payload += 4;
 676                         packet.payload_length -= 4;
 677                 }
 678         }
 679
 680         ret = rockchip_wait_cmd_fifo_not_full(dsi);
 681         if (ret)
 682                 return ret;
 683
 684         /* Send packet header */
 685         val = get_unaligned_le32(packet.header);
 686         dsi_write(dsi, DSI_GEN_HDR, val);
 687
 688         ret = rockchip_wait_write_fifo_empty(dsi);
 689         if (ret)
 690                 return ret;
 691
 692         return len;
 693 }
 694
 695 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 696         .attach = dw_mipi_dsi_host_attach,
 697         .detach = dw_mipi_dsi_host_detach,
 698         .transfer = dw_mipi_dsi_host_transfer,
 699 };
 700
 701 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 702 {
 703         u32 val;
 704
 705         val = VID_MODE_TYPE_BURST | ENABLE_LOW_POWER;
 706
 707         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 708 }
 709
 710 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 711                                  enum dw_mipi_dsi_mode mode)
 712 {
 713         if (mode == DSI_COMMAND_MODE)
 714                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 715         else
 716                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 717 }
 718
 719 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 720 {
 721         dsi_write(dsi, DSI_PWR_UP, RESET);
 722         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 723                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 724         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 725                   TX_ESC_CLK_DIVIDSION(7));
 726         dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 727 }
 728
 729 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 730                                    struct drm_display_mode *mode)
 731 {
 732         u32 val = 0, color = 0;
 733
 734         switch (dsi->format) {
 735         case MIPI_DSI_FMT_RGB888:
 736                 color = DPI_COLOR_CODING_24BIT;
 737                 break;
 738         case MIPI_DSI_FMT_RGB666:
 739                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 740                 break;
 741         case MIPI_DSI_FMT_RGB666_PACKED:
 742                 color = DPI_COLOR_CODING_18BIT_1;
 743                 break;
 744         case MIPI_DSI_FMT_RGB565:
 745                 color = DPI_COLOR_CODING_16BIT_1;
 746                 break;
 747         }
 748
 749         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 750                 val |= VSYNC_ACTIVE_LOW;
 751         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 752                 val |= HSYNC_ACTIVE_LOW;
 753
 754         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 755         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 756         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 757         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 758                   | INVACT_LPCMD_TIME(4));
 759 }
 760
 761 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 762 {
 763         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 764 }
 765
 766 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 767                                             struct drm_display_mode *mode)
 768 {
 769         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 770 }
 771
 772 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 773 {
 774         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 775         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 776 }
 777
 778 /* Get lane byte clock cycles. */
 779 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 780                                            u32 hcomponent)
 781 {
 782         u32 frac, lbcc;
 783
 784         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 785
 786         frac = lbcc % dsi->mode.clock;
 787         lbcc = lbcc / dsi->mode.clock;
 788         if (frac)
 789                 lbcc++;
 790
 791         return lbcc;
 792 }
 793
 794 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
 795 {
 796         u32 htotal, hsa, hbp, lbcc;
 797         struct drm_display_mode *mode = &dsi->mode;
 798
 799         htotal = mode->htotal;
 800         hsa = mode->hsync_end - mode->hsync_start;
 801         hbp = mode->htotal - mode->hsync_end;
 802
 803         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
 804         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 805
 806         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
 807         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 808
 809         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
 810         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 811 }
 812
 813 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
 814 {
 815         u32 vactive, vsa, vfp, vbp;
 816         struct drm_display_mode *mode = &dsi->mode;
 817
 818         vactive = mode->vdisplay;
 819         vsa = mode->vsync_end - mode->vsync_start;
 820         vfp = mode->vsync_start - mode->vdisplay;
 821         vbp = mode->vtotal - mode->vsync_end;
 822
 823         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 824         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 825         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 826         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 827 }
 828
 829 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 830 {
 831         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
 832                   | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
 833
 834         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 835                   | PHY_CLKLP2HS_TIME(0x40));
 836 }
 837
 838 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 839 {
 840         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 841                   N_LANES(dsi->lanes));
 842 }
 843
 844 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 845 {
 846         dsi_read(dsi, DSI_INT_ST0);
 847         dsi_read(dsi, DSI_INT_ST1);
 848         dsi_write(dsi, DSI_INT_MSK0, 0);
 849         dsi_write(dsi, DSI_INT_MSK1, 0);
 850 }
 851
 852 static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
 853                                         struct drm_display_mode *mode,
 854                                         struct drm_display_mode *adjusted_mode)
 855 {
 856         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 857
 858         drm_mode_copy(&dsi->mode, adjusted_mode);
 859 }
 860
 861 static void rockchip_dsi_pre_disable(struct dw_mipi_dsi *dsi)
 862 {
 863         if (clk_prepare_enable(dsi->pclk)) {
 864                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 865                 return;
 866         }
 867
 868         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 869 }
 870
 871 static void rockchip_dsi_disable(struct dw_mipi_dsi *dsi)
 872 {
 873         /* host */
 874         dsi_write(dsi, DSI_LPCLK_CTRL, 0);
 875         dsi_write(dsi, DSI_PWR_UP, RESET);
 876
 877         /* phy */
 878         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 879         if (dsi->phy)
 880                 phy_power_off(dsi->phy);
 881
 882         pm_runtime_put(dsi->dev);
 883         clk_disable_unprepare(dsi->pclk);
 884 }
 885
 886 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 887 {
 888         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 889
 890         if (dsi->panel)
 891                 drm_panel_disable(dsi->panel);
 892
 893         rockchip_dsi_pre_disable(dsi);
 894
 895         if (dsi->panel)
 896                 drm_panel_unprepare(dsi->panel);
 897
 898         rockchip_dsi_disable(dsi);
 899 }
 900
 901 static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 902                                         const struct drm_display_mode *mode,
 903                                         struct drm_display_mode *adjusted_mode)
 904 {
 905         return true;
 906 }
 907
 908 static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
 909 {
 910         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 911         int val = 0;
 912
 913         if (vop_id)
 914                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 915         else
 916                 val = pdata->dsi0_en_bit << 16;
 917
 918         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 919
 920         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
 921 }
 922
 923 static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
 924 {
 925         if (clk_prepare_enable(dsi->pclk)) {
 926                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 927                 return;
 928         }
 929
 930         pm_runtime_get_sync(dsi->dev);
 931
 932         if (dsi->rst) {
 933                 /* MIPI DSI APB software reset request. */
 934                 reset_control_assert(dsi->rst);
 935                 udelay(10);
 936                 reset_control_deassert(dsi->rst);
 937                 udelay(10);
 938         }
 939
 940         if (dsi->phy) {
 941                 phy_power_on(dsi->phy);
 942
 943                 /*
 944                  * If using the third party PHY, we get the lane
 945                  * rate information from PHY.
 946                  */
 947                 dsi->lane_mbps = phy_get_bus_width(dsi->phy);
 948         } else {
 949                 dw_mipi_dsi_get_lane_bps(dsi);
 950         }
 951 }
 952
 953 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
 954 {
 955         dw_mipi_dsi_init(dsi);
 956         dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
 957         dw_mipi_dsi_packet_handler_config(dsi);
 958         dw_mipi_dsi_video_mode_config(dsi);
 959         dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
 960         dw_mipi_dsi_command_mode_config(dsi);
 961         dw_mipi_dsi_set_mode(dsi, DSI_COMMAND_MODE);
 962         dw_mipi_dsi_line_timer_config(dsi);
 963         dw_mipi_dsi_vertical_timing_config(dsi);
 964         dw_mipi_dsi_dphy_timing_config(dsi);
 965         dw_mipi_dsi_dphy_interface_config(dsi);
 966         dw_mipi_dsi_clear_err(dsi);
 967 }
 968
 969 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
 970 {
 971         rockchip_dsi_pre_init(dsi);
 972         rockchip_dsi_host_init(dsi);
 973         dw_mipi_dsi_phy_init(dsi);
 974 }
 975
 976 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
 977 {
 978         dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
 979         clk_disable_unprepare(dsi->pclk);
 980 }
 981
 982 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 983 {
 984         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 985         int vop_id;
 986
 987         vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 988
 989         rockchip_dsi_grf_config(dsi, vop_id);
 990         rockchip_dsi_init(dsi);
 991
 992         if (dsi->panel)
 993                 drm_panel_prepare(dsi->panel);
 994
 995         rockchip_dsi_enable(dsi);
 996
 997         if (dsi->panel)
 998                 drm_panel_enable(dsi->panel);
 999 }
1000
1001 static int
1002 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1003                                  struct drm_crtc_state *crtc_state,
1004                                  struct drm_connector_state *conn_state)
1005 {
1006         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1007         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1008         struct drm_connector *connector = conn_state->connector;
1009         struct drm_display_info *info = &connector->display_info;
1010
1011         switch (dsi->format) {
1012         case MIPI_DSI_FMT_RGB888:
1013                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1014                 break;
1015         case MIPI_DSI_FMT_RGB666:
1016                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1017                 break;
1018         case MIPI_DSI_FMT_RGB565:
1019                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1020                 break;
1021         default:
1022                 WARN_ON(1);
1023                 return -EINVAL;
1024         }
1025
1026         s->output_type = DRM_MODE_CONNECTOR_DSI;
1027         if (info->num_bus_formats)
1028                 s->bus_format = info->bus_formats[0];
1029
1030         return 0;
1031 }
1032
1033 static struct drm_encoder_helper_funcs
1034 dw_mipi_dsi_encoder_helper_funcs = {
1035         .mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
1036         .mode_set = dw_mipi_dsi_encoder_mode_set,
1037         .enable = dw_mipi_dsi_encoder_enable,
1038         .disable = dw_mipi_dsi_encoder_disable,
1039         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1040 };
1041
1042 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1043         .destroy = drm_encoder_cleanup,
1044 };
1045
1046 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1047 {
1048         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1049
1050         return drm_panel_get_modes(dsi->panel);
1051 }
1052
1053 static enum drm_mode_status dw_mipi_dsi_mode_valid(
1054                                         struct drm_connector *connector,
1055                                         struct drm_display_mode *mode)
1056 {
1057         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1058
1059         enum drm_mode_status mode_status = MODE_OK;
1060
1061         if (dsi->pdata->mode_valid)
1062                 mode_status = dsi->pdata->mode_valid(connector, mode);
1063
1064         return mode_status;
1065 }
1066
1067 static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
1068                                         struct drm_connector *connector)
1069 {
1070         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1071
1072         return &dsi->encoder;
1073 }
1074
1075 static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
1076 {
1077         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1078
1079         if (dsi->panel)
1080                 drm_panel_loader_protect(dsi->panel, on);
1081         if (on)
1082                 pm_runtime_get_sync(dsi->dev);
1083         else
1084                 pm_runtime_put(dsi->dev);
1085
1086         return 0;
1087 }
1088
1089 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1090         .loader_protect = dw_mipi_loader_protect,
1091         .get_modes = dw_mipi_dsi_connector_get_modes,
1092         .mode_valid = dw_mipi_dsi_mode_valid,
1093         .best_encoder = dw_mipi_dsi_connector_best_encoder,
1094 };
1095
1096 static enum drm_connector_status
1097 dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
1098 {
1099         return connector_status_connected;
1100 }
1101
1102 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1103 {
1104         drm_connector_unregister(connector);
1105         drm_connector_cleanup(connector);
1106 }
1107
1108 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1109         .dpms = drm_atomic_helper_connector_dpms,
1110         .fill_modes = drm_helper_probe_single_connector_modes,
1111         .detect = dw_mipi_dsi_detect,
1112         .destroy = dw_mipi_dsi_drm_connector_destroy,
1113         .reset = drm_atomic_helper_connector_reset,
1114         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1115         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1116 };
1117
1118 static int dw_mipi_dsi_register(struct drm_device *drm,
1119                                       struct dw_mipi_dsi *dsi)
1120 {
1121         struct drm_encoder *encoder = &dsi->encoder;
1122         struct drm_connector *connector = &dsi->connector;
1123         struct device *dev = dsi->dev;
1124         int ret;
1125
1126         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1127                                                              dev->of_node);
1128         /*
1129          * If we failed to find the CRTC(s) which this encoder is
1130          * supposed to be connected to, it's because the CRTC has
1131          * not been registered yet.  Defer probing, and hope that
1132          * the required CRTC is added later.
1133          */
1134         if (encoder->possible_crtcs == 0)
1135                 return -EPROBE_DEFER;
1136
1137         drm_encoder_helper_add(&dsi->encoder,
1138                                &dw_mipi_dsi_encoder_helper_funcs);
1139         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1140                          DRM_MODE_ENCODER_DSI, NULL);
1141         if (ret) {
1142                 dev_err(dev, "Failed to initialize encoder with drm\n");
1143                 return ret;
1144         }
1145
1146         drm_connector_helper_add(connector,
1147                         &dw_mipi_dsi_connector_helper_funcs);
1148
1149         drm_connector_init(drm, &dsi->connector,
1150                            &dw_mipi_dsi_atomic_connector_funcs,
1151                            DRM_MODE_CONNECTOR_DSI);
1152
1153         drm_panel_attach(dsi->panel, &dsi->connector);
1154
1155         dsi->connector.port = dev->of_node;
1156
1157         drm_mode_connector_attach_encoder(connector, encoder);
1158
1159         return 0;
1160 }
1161
1162 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1163 {
1164         struct device_node *np = dsi->dev->of_node;
1165
1166         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1167         if (IS_ERR(dsi->grf_regmap)) {
1168                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1169                 return PTR_ERR(dsi->grf_regmap);
1170         }
1171
1172         return 0;
1173 }
1174
1175 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1176         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1177         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1178         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1179         .max_data_lanes = 4,
1180         .max_bit_rate_per_lane = 1500000000,
1181         .has_vop_sel = true,
1182 };
1183
1184 static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
1185         .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
1186         .grf_switch_reg = RK3366_GRF_SOC_CON0,
1187         .max_data_lanes = 4,
1188         .max_bit_rate_per_lane = 1000000000,
1189         .has_vop_sel = true,
1190 };
1191
1192 static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
1193         .max_data_lanes = 4,
1194         .max_bit_rate_per_lane = 1000000000,
1195 };
1196
1197 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1198         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1199         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1200         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1201         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1202         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1203         .max_data_lanes = 4,
1204         .max_bit_rate_per_lane = 1500000000,
1205         .has_vop_sel = true,
1206 };
1207
1208 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1209         {
1210          .compatible = "rockchip,rk3288-mipi-dsi",
1211          .data = &rk3288_mipi_dsi_drv_data,
1212         }, {
1213          .compatible = "rockchip,rk3366-mipi-dsi",
1214          .data = &rk3366_mipi_dsi_drv_data,
1215         }, {
1216          .compatible = "rockchip,rk3368-mipi-dsi",
1217          .data = &rk3368_mipi_dsi_drv_data,
1218         }, {
1219          .compatible = "rockchip,rk3399-mipi-dsi",
1220          .data = &rk3399_mipi_dsi_drv_data,
1221         },
1222         { /* sentinel */ }
1223 };
1224 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1225
1226 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1227                              void *data)
1228 {
1229         struct platform_device *pdev = to_platform_device(dev);
1230         struct drm_device *drm = data;
1231         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1232         struct resource *res;
1233         int ret;
1234
1235         if (!dsi->panel)
1236                 return -EPROBE_DEFER;
1237
1238         ret = rockchip_mipi_parse_dt(dsi);
1239         if (ret)
1240                 return ret;
1241
1242         dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
1243         if (IS_ERR(dsi->phy)) {
1244                 ret = PTR_ERR(dsi->phy);
1245                 dev_err(dev, "failed to get mipi dphy: %d\n", ret);
1246                 return ret;
1247         }
1248
1249         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250         if (!res)
1251                 return -ENODEV;
1252
1253         dsi->base = devm_ioremap_resource(dev, res);
1254         if (IS_ERR(dsi->base))
1255                 return PTR_ERR(dsi->base);
1256
1257         dsi->pclk = devm_clk_get(dev, "pclk");
1258         if (IS_ERR(dsi->pclk)) {
1259                 ret = PTR_ERR(dsi->pclk);
1260                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1261                 return ret;
1262         }
1263
1264         /* optional */
1265         dsi->pllref_clk = devm_clk_get(dev, "ref");
1266         if (IS_ERR(dsi->pllref_clk)) {
1267                 dev_info(dev, "No PHY reference clock specified\n");
1268                 dsi->pllref_clk = NULL;
1269         }
1270
1271         /* optional */
1272         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1273         if (IS_ERR(dsi->phy_cfg_clk)) {
1274                 dev_info(dev, "No PHY APB clock specified\n");
1275                 dsi->phy_cfg_clk = NULL;
1276         }
1277
1278         ret = clk_prepare_enable(dsi->pllref_clk);
1279         if (ret) {
1280                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1281                 return ret;
1282         }
1283
1284         dsi->rst = devm_reset_control_get_optional(dev, "apb");
1285         if (IS_ERR(dsi->rst)) {
1286                 dev_info(dev, "no reset control specified\n");
1287                 dsi->rst = NULL;
1288         }
1289
1290         ret = dw_mipi_dsi_register(drm, dsi);
1291         if (ret) {
1292                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1293                 goto err_pllref;
1294         }
1295
1296         dev_set_drvdata(dev, dsi);
1297
1298         pm_runtime_enable(dev);
1299
1300         return 0;
1301
1302 err_pllref:
1303         clk_disable_unprepare(dsi->pllref_clk);
1304         return ret;
1305 }
1306
1307 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1308         void *data)
1309 {
1310         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1311
1312         pm_runtime_disable(dev);
1313         clk_disable_unprepare(dsi->pllref_clk);
1314 }
1315
1316 static const struct component_ops dw_mipi_dsi_ops = {
1317         .bind   = dw_mipi_dsi_bind,
1318         .unbind = dw_mipi_dsi_unbind,
1319 };
1320
1321 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1322 {
1323         struct device *dev = &pdev->dev;
1324         const struct of_device_id *of_id =
1325                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1326         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1327         struct dw_mipi_dsi *dsi;
1328         int ret;
1329
1330         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1331         if (!dsi)
1332                 return -ENOMEM;
1333
1334         dsi->dev = dev;
1335         dsi->pdata = pdata;
1336         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1337         dsi->dsi_host.dev = &pdev->dev;
1338
1339         ret = mipi_dsi_host_register(&dsi->dsi_host);
1340         if (ret)
1341                 return ret;
1342
1343         platform_set_drvdata(pdev, dsi);
1344         ret = component_add(&pdev->dev, &dw_mipi_dsi_ops);
1345         if (ret)
1346                 mipi_dsi_host_unregister(&dsi->dsi_host);
1347
1348         return ret;
1349 }
1350
1351 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1352 {
1353         struct dw_mipi_dsi *dsi = dev_get_drvdata(&pdev->dev);
1354
1355         if (dsi)
1356                 mipi_dsi_host_unregister(&dsi->dsi_host);
1357         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1358         return 0;
1359 }
1360
1361 static struct platform_driver dw_mipi_dsi_driver = {
1362         .probe          = dw_mipi_dsi_probe,
1363         .remove         = dw_mipi_dsi_remove,
1364         .driver         = {
1365                 .of_match_table = dw_mipi_dsi_dt_ids,
1366                 .name   = DRIVER_NAME,
1367         },
1368 };
1369 module_platform_driver(dw_mipi_dsi_driver);
1370
1371 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1372 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1373 MODULE_LICENSE("GPL");
1374 MODULE_ALIAS("platform:" DRIVER_NAME);