drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <drm/drm_of.h>
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_edid.h>
  20 #include <drm/drm_encoder_slave.h>
  21 #include <drm/bridge/dw_hdmi.h>
  22
  23 #include "rockchip_drm_drv.h"
  24 #include "rockchip_drm_vop.h"
  25
  26 #define RK3288_GRF_SOC_CON6             0x025C
  27 #define RK3288_HDMI_LCDC_SEL            BIT(4)
  28 #define RK3399_GRF_SOC_CON20            0x6250
  29 #define RK3399_HDMI_LCDC_SEL            BIT(6)
  30
  31 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  32
  33 struct rockchip_hdmi {
  34         struct device *dev;
  35         struct regmap *regmap;
  36         struct drm_encoder encoder;
  37         enum dw_hdmi_devtype dev_type;
  38         struct clk *vpll_clk;
  39         struct clk *grf_clk;
  40 };
  41
  42 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  43
  44 #define CLK_SLOP(clk)           ((clk) / 1000)
  45 #define CLK_PLUS_SLOP(clk)      ((clk) + CLK_SLOP(clk))
  46
  47 static const int dw_hdmi_rates[] = {
  48         25176471,       /* for 25.175 MHz, 0.006% off */
  49         25200000,
  50         27000000,
  51         28320000,
  52         30240000,
  53         31500000,
  54         32000000,
  55         33750000,
  56         36000000,
  57         40000000,
  58         49500000,
  59         50000000,
  60         54000000,
  61         57290323,       /* for 57.284 MHz, .011 % off */
  62         65000000,
  63         68250000,
  64         71000000,
  65         72000000,
  66         73250000,
  67         74250000,
  68         74437500,       /* for 74.44 MHz, .003% off */
  69         75000000,
  70         78750000,
  71         78800000,
  72         79500000,
  73         83500000,
  74         85500000,
  75         88750000,
  76         97750000,
  77         101000000,
  78         106500000,
  79         108000000,
  80         115500000,
  81         118666667,      /* for 118.68 MHz, .011% off */
  82         119000000,
  83         121714286,      /* for 121.75 MHz, .029% off */
  84         135000000,
  85         136800000,      /* for 136.75 MHz, .037% off */
  86         146250000,
  87         148500000,
  88         154000000,
  89         162000000,
  90         297000000,
  91         594000000,
  92 };
  93
  94 /*
  95  * There are some rates that would be ranged for better clock jitter at
  96  * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
  97  * to the clock is aglined to KHz in struct drm_display_mode, this would
  98  * bring some inaccurate error if we still run the compute_n math, so
  99  * let's just code an const table for it until we can actually get the
 100  * right clock rate.
 101  */
 102 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
 103         /* 25176471 for 25.175 MHz = 428000000 / 17. */
 104         { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
 105         /* 57290323 for 57.284 MHz */
 106         { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
 107         /* 74437500 for 74.44 MHz = 297750000 / 4 */
 108         { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
 109         /* 118666667 for 118.68 MHz */
 110         { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
 111         /* 121714286 for 121.75 MHz */
 112         { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
 113         /* 136800000 for 136.75 MHz */
 114         { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 115         /* End of table */
 116         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 117 };
 118
 119 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 120         {
 121                 30666000, {
 122                         { 0x00b3, 0x0000 },
 123                         { 0x2153, 0x0000 },
 124                         { 0x40f3, 0x0000 },
 125                 },
 126         },  {
 127                 36800000, {
 128                         { 0x00b3, 0x0000 },
 129                         { 0x2153, 0x0000 },
 130                         { 0x40a2, 0x0001 },
 131                 },
 132         },  {
 133                 46000000, {
 134                         { 0x00b3, 0x0000 },
 135                         { 0x2142, 0x0001 },
 136                         { 0x40a2, 0x0001 },
 137                 },
 138         },  {
 139                 61333000, {
 140                         { 0x0072, 0x0001 },
 141                         { 0x2142, 0x0001 },
 142                         { 0x40a2, 0x0001 },
 143                 },
 144         },  {
 145                 73600000, {
 146                         { 0x0072, 0x0001 },
 147                         { 0x2142, 0x0001 },
 148                         { 0x4061, 0x0002 },
 149                 },
 150         },  {
 151                 92000000, {
 152                         { 0x0072, 0x0001 },
 153                         { 0x2145, 0x0002 },
 154                         { 0x4061, 0x0002 },
 155                 },
 156         },  {
 157                 122666000, {
 158                         { 0x0051, 0x0002 },
 159                         { 0x2145, 0x0002 },
 160                         { 0x4061, 0x0002 },
 161                 },
 162         },  {
 163                 147200000, {
 164                         { 0x0051, 0x0002 },
 165                         { 0x2145, 0x0002 },
 166                         { 0x4064, 0x0003 },
 167                 },
 168         },  {
 169                 184000000, {
 170                         { 0x0051, 0x0002 },
 171                         { 0x214c, 0x0003 },
 172                         { 0x4064, 0x0003 },
 173                 },
 174         },  {
 175                 226666000, {
 176                         { 0x0040, 0x0003 },
 177                         { 0x214c, 0x0003 },
 178                         { 0x4064, 0x0003 },
 179                 },
 180         },  {
 181                 272000000, {
 182                         { 0x0040, 0x0003 },
 183                         { 0x214c, 0x0003 },
 184                         { 0x5a64, 0x0003 },
 185                 },
 186         },  {
 187                 340000000, {
 188                         { 0x0040, 0x0003 },
 189                         { 0x3b4c, 0x0003 },
 190                         { 0x5a64, 0x0003 },
 191                 },
 192         },  {
 193                 600000000, {
 194                         { 0x1a40, 0x0003 },
 195                         { 0x3b4c, 0x0003 },
 196                         { 0x5a64, 0x0003 },
 197                 },
 198         },  {
 199                 ~0UL, {
 200                         { 0x0000, 0x0000 },
 201                         { 0x0000, 0x0000 },
 202                         { 0x0000, 0x0000 },
 203                 },
 204         }
 205 };
 206
 207 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 208         /*      pixelclk    bpp8    bpp10   bpp12 */
 209         {
 210                 600000000, { 0x0000, 0x0000, 0x0000 },
 211         },  {
 212                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 213         }
 214 };
 215
 216 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 217         /*pixelclk   symbol   term   vlev*/
 218         { 74250000,  0x8009, 0x0004, 0x0272},
 219         { 165000000, 0x802b, 0x0004, 0x0209},
 220         { 297000000, 0x8039, 0x0005, 0x028d},
 221         { ~0UL,      0x0000, 0x0000, 0x0000}
 222 };
 223
 224 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 225 {
 226         struct device_node *np = hdmi->dev->of_node;
 227         int ret;
 228
 229         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 230         if (IS_ERR(hdmi->regmap)) {
 231                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 232                 return PTR_ERR(hdmi->regmap);
 233         }
 234
 235         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
 236         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
 237                 hdmi->vpll_clk = NULL;
 238         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
 239                 return -EPROBE_DEFER;
 240         } else if (IS_ERR(hdmi->vpll_clk)) {
 241                 dev_err(hdmi->dev, "failed to get grf clock\n");
 242                 return PTR_ERR(hdmi->vpll_clk);
 243         }
 244
 245         hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
 246         if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
 247                 hdmi->grf_clk = NULL;
 248         } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
 249                 return -EPROBE_DEFER;
 250         } else if (IS_ERR(hdmi->grf_clk)) {
 251                 dev_err(hdmi->dev, "failed to get grf clock\n");
 252                 return PTR_ERR(hdmi->grf_clk);
 253         }
 254
 255         ret = clk_prepare_enable(hdmi->vpll_clk);
 256         if (ret) {
 257                 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
 258                 return ret;
 259         }
 260
 261         return 0;
 262 }
 263
 264 static enum drm_mode_status
 265 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 266                             struct drm_display_mode *mode)
 267 {
 268         int pclk = mode->clock * 1000;
 269         int num_rates = ARRAY_SIZE(dw_hdmi_rates);
 270         int i;
 271
 272         /*
 273          * Pixel clocks we support are always < 2GHz and so fit in an
 274          * int.  We should make sure source rate does too so we don't get
 275          * overflow when we multiply by 1000.
 276          */
 277         if (mode->clock > INT_MAX / 1000)
 278                 return MODE_BAD;
 279
 280         for (i = 0; i < num_rates; i++) {
 281                 int slop = CLK_SLOP(pclk);
 282
 283                 if ((pclk >= dw_hdmi_rates[i] - slop) &&
 284                     (pclk <= dw_hdmi_rates[i] + slop))
 285                         return MODE_OK;
 286         }
 287
 288         return MODE_BAD;
 289 }
 290
 291 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 292         .destroy = drm_encoder_cleanup,
 293 };
 294
 295 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 296 {
 297 }
 298
 299 static bool
 300 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
 301                                     const struct drm_display_mode *mode,
 302                                     struct drm_display_mode *adj_mode)
 303 {
 304         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 305         int pclk = adj_mode->clock * 1000;
 306         int best_diff = INT_MAX;
 307         int best_clock = 0;
 308         int slop;
 309         int i;
 310
 311         /* Pick the best clock */
 312         for (i = 0; i < ARRAY_SIZE(dw_hdmi_rates); i++) {
 313                 int diff = dw_hdmi_rates[i] - pclk;
 314
 315                 if (diff < 0)
 316                         diff = -diff;
 317                 if (diff < best_diff) {
 318                         best_diff = diff;
 319                         best_clock = dw_hdmi_rates[i];
 320
 321                         /* Bail early if we're exact */
 322                         if (best_diff == 0)
 323                                 return true;
 324                 }
 325         }
 326
 327         /* Double check that it's OK */
 328         slop = CLK_SLOP(pclk);
 329         if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) {
 330                 adj_mode->clock = DIV_ROUND_UP(best_clock, 1000);
 331                 return true;
 332         }
 333
 334         /* Shoudn't be here; we should have said rate wasn't valid */
 335         dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock);
 336         return false;
 337 }
 338
 339 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
 340                                               struct drm_display_mode *mode,
 341                                               struct drm_display_mode *adj_mode)
 342 {
 343         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 344
 345         clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
 346 }
 347
 348 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 349 {
 350         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 351         u32 lcdsel_grf_reg, lcdsel_mask;
 352         u32 val;
 353         int mux;
 354         int ret;
 355
 356         switch (hdmi->dev_type) {
 357         case RK3288_HDMI:
 358                 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
 359                 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
 360                 break;
 361         case RK3399_HDMI:
 362                 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
 363                 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
 364                 break;
 365         default:
 366                 return;
 367         };
 368
 369         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 370         if (mux)
 371                 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
 372         else
 373                 val = HIWORD_UPDATE(0, lcdsel_mask);
 374
 375         ret = clk_prepare_enable(hdmi->grf_clk);
 376         if (ret < 0) {
 377                 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
 378                 return;
 379         }
 380
 381         regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
 382         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 383                 (mux) ? "LIT" : "BIG");
 384
 385         clk_disable_unprepare(hdmi->grf_clk);
 386 }
 387
 388 static int
 389 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 390                                       struct drm_crtc_state *crtc_state,
 391                                       struct drm_connector_state *conn_state)
 392 {
 393         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 394
 395         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 396         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 397         s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 398
 399         return 0;
 400 }
 401
 402 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 403         .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
 404         .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
 405         .enable     = dw_hdmi_rockchip_encoder_enable,
 406         .disable    = dw_hdmi_rockchip_encoder_disable,
 407         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 408 };
 409
 410 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
 411         .mode_valid = dw_hdmi_rockchip_mode_valid,
 412         .mpll_cfg   = rockchip_mpll_cfg,
 413         .cur_ctr    = rockchip_cur_ctr,
 414         .phy_config = rockchip_phy_config,
 415         .dev_type   = RK3288_HDMI,
 416         .tmds_n_table = rockchip_werid_tmds_n_table,
 417 };
 418
 419 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 420         .mode_valid = dw_hdmi_rockchip_mode_valid,
 421         .mpll_cfg   = rockchip_mpll_cfg,
 422         .cur_ctr    = rockchip_cur_ctr,
 423         .phy_config = rockchip_phy_config,
 424         .dev_type   = RK3399_HDMI,
 425 };
 426
 427 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 428         { .compatible = "rockchip,rk3288-dw-hdmi",
 429           .data = &rk3288_hdmi_drv_data
 430         },
 431         { .compatible = "rockchip,rk3399-dw-hdmi",
 432           .data = &rk3399_hdmi_drv_data
 433         },
 434         {},
 435 };
 436 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 437
 438 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 439                                  void *data)
 440 {
 441         struct platform_device *pdev = to_platform_device(dev);
 442         const struct dw_hdmi_plat_data *plat_data;
 443         const struct of_device_id *match;
 444         struct drm_device *drm = data;
 445         struct drm_encoder *encoder;
 446         struct rockchip_hdmi *hdmi;
 447         struct resource *iores;
 448         int irq;
 449         int ret;
 450
 451         if (!pdev->dev.of_node)
 452                 return -ENODEV;
 453
 454         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 455         if (!hdmi)
 456                 return -ENOMEM;
 457
 458         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 459         plat_data = match->data;
 460         hdmi->dev = &pdev->dev;
 461         hdmi->dev_type = plat_data->dev_type;
 462         encoder = &hdmi->encoder;
 463
 464         irq = platform_get_irq(pdev, 0);
 465         if (irq < 0)
 466                 return irq;
 467
 468         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 469         if (!iores)
 470                 return -ENXIO;
 471
 472         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 473         /*
 474          * If we failed to find the CRTC(s) which this encoder is
 475          * supposed to be connected to, it's because the CRTC has
 476          * not been registered yet.  Defer probing, and hope that
 477          * the required CRTC is added later.
 478          */
 479         if (encoder->possible_crtcs == 0)
 480                 return -EPROBE_DEFER;
 481
 482         ret = rockchip_hdmi_parse_dt(hdmi);
 483         if (ret) {
 484                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 485                 return ret;
 486         }
 487
 488         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 489         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 490                          DRM_MODE_ENCODER_TMDS, NULL);
 491
 492         ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
 493
 494         /*
 495          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 496          * which would have called the encoder cleanup.  Do it manually.
 497          */
 498         if (ret)
 499                 drm_encoder_cleanup(encoder);
 500
 501         return ret;
 502 }
 503
 504 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 505                                     void *data)
 506 {
 507         return dw_hdmi_unbind(dev, master, data);
 508 }
 509
 510 static const struct component_ops dw_hdmi_rockchip_ops = {
 511         .bind   = dw_hdmi_rockchip_bind,
 512         .unbind = dw_hdmi_rockchip_unbind,
 513 };
 514
 515 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 516 {
 517         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 518 }
 519
 520 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 521 {
 522         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 523
 524         return 0;
 525 }
 526
 527 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 528         .probe  = dw_hdmi_rockchip_probe,
 529         .remove = dw_hdmi_rockchip_remove,
 530         .driver = {
 531                 .name = "dwhdmi-rockchip",
 532                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 533         },
 534 };
 535
 536 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
 537
 538 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
 539 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
 540 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
 541 MODULE_LICENSE("GPL");
 542 MODULE_ALIAS("platform:dwhdmi-rockchip");