2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
16 #include <drm/drm_of.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_encoder_slave.h>
21 #include <drm/bridge/dw_hdmi.h>
23 #include "rockchip_drm_drv.h"
24 #include "rockchip_drm_vop.h"
26 #define RK3288_GRF_SOC_CON6 0x025C
27 #define RK3288_HDMI_LCDC_SEL BIT(4)
28 #define RK3399_GRF_SOC_CON20 0x6250
29 #define RK3399_HDMI_LCDC_SEL BIT(6)
31 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
33 struct rockchip_hdmi {
35 struct regmap *regmap;
36 struct drm_encoder encoder;
37 enum dw_hdmi_devtype dev_type;
41 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
43 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
131 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
132 /* pixelclk bpp8 bpp10 bpp12 */
134 600000000, { 0x0000, 0x0000, 0x0000 },
136 ~0UL, { 0x0000, 0x0000, 0x0000},
140 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
141 /*pixelclk symbol term vlev*/
142 { 74250000, 0x8009, 0x0004, 0x0272},
143 { 165000000, 0x802b, 0x0004, 0x0209},
144 { 297000000, 0x8039, 0x0005, 0x028d},
145 { ~0UL, 0x0000, 0x0000, 0x0000}
148 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
150 struct device_node *np = hdmi->dev->of_node;
153 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
154 if (IS_ERR(hdmi->regmap)) {
155 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
156 return PTR_ERR(hdmi->regmap);
159 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
160 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
161 hdmi->vpll_clk = NULL;
162 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
163 return -EPROBE_DEFER;
164 } else if (IS_ERR(hdmi->vpll_clk)) {
165 dev_err(hdmi->dev, "failed to get grf clock\n");
166 return PTR_ERR(hdmi->vpll_clk);
169 ret = clk_prepare_enable(hdmi->vpll_clk);
171 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
178 static enum drm_mode_status
179 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
180 struct drm_display_mode *mode)
182 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
183 int pclk = mode->clock * 1000;
187 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
188 if (pclk == mpll_cfg[i].mpixelclock) {
194 return (valid) ? MODE_OK : MODE_BAD;
197 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
198 .destroy = drm_encoder_cleanup,
201 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
206 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
207 const struct drm_display_mode *mode,
208 struct drm_display_mode *adj_mode)
213 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
214 struct drm_display_mode *mode,
215 struct drm_display_mode *adj_mode)
217 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
219 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
222 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
224 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
225 u32 lcdsel_grf_reg, lcdsel_mask;
229 switch (hdmi->dev_type) {
231 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
232 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
235 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
236 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
242 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
244 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
246 val = HIWORD_UPDATE(0, lcdsel_mask);
248 regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
249 dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
250 (mux) ? "LIT" : "BIG");
254 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
255 struct drm_crtc_state *crtc_state,
256 struct drm_connector_state *conn_state)
258 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
260 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
261 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
266 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
267 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
268 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
269 .enable = dw_hdmi_rockchip_encoder_enable,
270 .disable = dw_hdmi_rockchip_encoder_disable,
271 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
274 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
275 .mode_valid = dw_hdmi_rockchip_mode_valid,
276 .mpll_cfg = rockchip_mpll_cfg,
277 .cur_ctr = rockchip_cur_ctr,
278 .phy_config = rockchip_phy_config,
279 .dev_type = RK3288_HDMI,
282 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
283 .mode_valid = dw_hdmi_rockchip_mode_valid,
284 .mpll_cfg = rockchip_mpll_cfg,
285 .cur_ctr = rockchip_cur_ctr,
286 .phy_config = rockchip_phy_config,
287 .dev_type = RK3399_HDMI,
290 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
291 { .compatible = "rockchip,rk3288-dw-hdmi",
292 .data = &rk3288_hdmi_drv_data
294 { .compatible = "rockchip,rk3399-dw-hdmi",
295 .data = &rk3399_hdmi_drv_data
299 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
301 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
304 struct platform_device *pdev = to_platform_device(dev);
305 const struct dw_hdmi_plat_data *plat_data;
306 const struct of_device_id *match;
307 struct drm_device *drm = data;
308 struct drm_encoder *encoder;
309 struct rockchip_hdmi *hdmi;
310 struct resource *iores;
314 if (!pdev->dev.of_node)
317 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
321 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
322 plat_data = match->data;
323 hdmi->dev = &pdev->dev;
324 hdmi->dev_type = plat_data->dev_type;
325 encoder = &hdmi->encoder;
327 irq = platform_get_irq(pdev, 0);
331 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
335 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
337 * If we failed to find the CRTC(s) which this encoder is
338 * supposed to be connected to, it's because the CRTC has
339 * not been registered yet. Defer probing, and hope that
340 * the required CRTC is added later.
342 if (encoder->possible_crtcs == 0)
343 return -EPROBE_DEFER;
345 ret = rockchip_hdmi_parse_dt(hdmi);
347 dev_err(hdmi->dev, "Unable to parse OF data\n");
351 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
352 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
353 DRM_MODE_ENCODER_TMDS, NULL);
355 ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
358 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
359 * which would have called the encoder cleanup. Do it manually.
362 drm_encoder_cleanup(encoder);
367 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
370 return dw_hdmi_unbind(dev, master, data);
373 static const struct component_ops dw_hdmi_rockchip_ops = {
374 .bind = dw_hdmi_rockchip_bind,
375 .unbind = dw_hdmi_rockchip_unbind,
378 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
380 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
383 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
385 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
390 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
391 .probe = dw_hdmi_rockchip_probe,
392 .remove = dw_hdmi_rockchip_remove,
394 .name = "dwhdmi-rockchip",
395 .of_match_table = dw_hdmi_rockchip_dt_ids,
399 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
401 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
402 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
403 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
404 MODULE_LICENSE("GPL");
405 MODULE_ALIAS("platform:dwhdmi-rockchip");