drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <drm/drm_of.h>
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_edid.h>
  20 #include <drm/drm_encoder_slave.h>
  21 #include <drm/bridge/dw_hdmi.h>
  22
  23 #include "rockchip_drm_drv.h"
  24 #include "rockchip_drm_vop.h"
  25
  26 #define RK3288_GRF_SOC_CON6             0x025C
  27 #define RK3288_HDMI_LCDC_SEL            BIT(4)
  28 #define RK3399_GRF_SOC_CON20            0x6250
  29 #define RK3399_HDMI_LCDC_SEL            BIT(6)
  30
  31 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  32
  33 struct rockchip_hdmi {
  34         struct device *dev;
  35         struct regmap *regmap;
  36         struct drm_encoder encoder;
  37         enum dw_hdmi_devtype dev_type;
  38         struct clk *vpll_clk;
  39         struct clk *grf_clk;
  40 };
  41
  42 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  43
  44 #define CLK_SLOP(clk)           ((clk) / 1000)
  45 #define CLK_PLUS_SLOP(clk)      ((clk) + CLK_SLOP(clk))
  46
  47 static const int dw_hdmi_rates[] = {
  48         25176471,       /* for 25.175 MHz, 0.006% off */
  49         25200000,
  50         27000000,
  51         28320000,
  52         30240000,
  53         31500000,
  54         32000000,
  55         33750000,
  56         36000000,
  57         40000000,
  58         49500000,
  59         50000000,
  60         54000000,
  61         57290323,       /* for 57.284 MHz, .011 % off */
  62         65000000,
  63         68250000,
  64         71000000,
  65         72000000,
  66         73250000,
  67         74250000,
  68         74437500,       /* for 74.44 MHz, .003% off */
  69         75000000,
  70         78750000,
  71         78800000,
  72         79500000,
  73         83500000,
  74         85500000,
  75         88750000,
  76         97750000,
  77         101000000,
  78         106500000,
  79         108000000,
  80         115500000,
  81         118666667,      /* for 118.68 MHz, .011% off */
  82         119000000,
  83         121714286,      /* for 121.75 MHz, .029% off */
  84         135000000,
  85         136800000,      /* for 136.75 MHz, .037% off */
  86         146250000,
  87         148500000,
  88         154000000,
  89         162000000,
  90         297000000,
  91 };
  92
  93 /*
  94  * There are some rates that would be ranged for better clock jitter at
  95  * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
  96  * to the clock is aglined to KHz in struct drm_display_mode, this would
  97  * bring some inaccurate error if we still run the compute_n math, so
  98  * let's just code an const table for it until we can actually get the
  99  * right clock rate.
 100  */
 101 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
 102         /* 25176471 for 25.175 MHz = 428000000 / 17. */
 103         { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
 104         /* 57290323 for 57.284 MHz */
 105         { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
 106         /* 74437500 for 74.44 MHz = 297750000 / 4 */
 107         { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
 108         /* 118666667 for 118.68 MHz */
 109         { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
 110         /* 121714286 for 121.75 MHz */
 111         { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
 112         /* 136800000 for 136.75 MHz */
 113         { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 114         /* End of table */
 115         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 116 };
 117
 118 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 119         {
 120                 30666000, {
 121                         { 0x00b3, 0x0000 },
 122                         { 0x2153, 0x0000 },
 123                         { 0x40f3, 0x0000 },
 124                 },
 125         },  {
 126                 36800000, {
 127                         { 0x00b3, 0x0000 },
 128                         { 0x2153, 0x0000 },
 129                         { 0x40a2, 0x0001 },
 130                 },
 131         },  {
 132                 46000000, {
 133                         { 0x00b3, 0x0000 },
 134                         { 0x2142, 0x0001 },
 135                         { 0x40a2, 0x0001 },
 136                 },
 137         },  {
 138                 61333000, {
 139                         { 0x0072, 0x0001 },
 140                         { 0x2142, 0x0001 },
 141                         { 0x40a2, 0x0001 },
 142                 },
 143         },  {
 144                 73600000, {
 145                         { 0x0072, 0x0001 },
 146                         { 0x2142, 0x0001 },
 147                         { 0x4061, 0x0002 },
 148                 },
 149         },  {
 150                 92000000, {
 151                         { 0x0072, 0x0001 },
 152                         { 0x2145, 0x0002 },
 153                         { 0x4061, 0x0002 },
 154                 },
 155         },  {
 156                 122666000, {
 157                         { 0x0051, 0x0002 },
 158                         { 0x2145, 0x0002 },
 159                         { 0x4061, 0x0002 },
 160                 },
 161         },  {
 162                 147200000, {
 163                         { 0x0051, 0x0002 },
 164                         { 0x2145, 0x0002 },
 165                         { 0x4064, 0x0003 },
 166                 },
 167         },  {
 168                 184000000, {
 169                         { 0x0051, 0x0002 },
 170                         { 0x214c, 0x0003 },
 171                         { 0x4064, 0x0003 },
 172                 },
 173         },  {
 174                 226666000, {
 175                         { 0x0040, 0x0003 },
 176                         { 0x214c, 0x0003 },
 177                         { 0x4064, 0x0003 },
 178                 },
 179         },  {
 180                 272000000, {
 181                         { 0x0040, 0x0003 },
 182                         { 0x214c, 0x0003 },
 183                         { 0x5a64, 0x0003 },
 184                 },
 185         },  {
 186                 340000000, {
 187                         { 0x0040, 0x0003 },
 188                         { 0x3b4c, 0x0003 },
 189                         { 0x5a64, 0x0003 },
 190                 },
 191         },  {
 192                 600000000, {
 193                         { 0x1a40, 0x0003 },
 194                         { 0x3b4c, 0x0003 },
 195                         { 0x5a64, 0x0003 },
 196                 },
 197         },  {
 198                 ~0UL, {
 199                         { 0x0000, 0x0000 },
 200                         { 0x0000, 0x0000 },
 201                         { 0x0000, 0x0000 },
 202                 },
 203         }
 204 };
 205
 206 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 207         /*      pixelclk    bpp8    bpp10   bpp12 */
 208         {
 209                 600000000, { 0x0000, 0x0000, 0x0000 },
 210         },  {
 211                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 212         }
 213 };
 214
 215 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 216         /*pixelclk   symbol   term   vlev*/
 217         { 74250000,  0x8009, 0x0004, 0x0272},
 218         { 165000000, 0x802b, 0x0004, 0x0209},
 219         { 297000000, 0x8039, 0x0005, 0x028d},
 220         { ~0UL,      0x0000, 0x0000, 0x0000}
 221 };
 222
 223 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 224 {
 225         struct device_node *np = hdmi->dev->of_node;
 226         int ret;
 227
 228         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 229         if (IS_ERR(hdmi->regmap)) {
 230                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 231                 return PTR_ERR(hdmi->regmap);
 232         }
 233
 234         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
 235         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
 236                 hdmi->vpll_clk = NULL;
 237         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
 238                 return -EPROBE_DEFER;
 239         } else if (IS_ERR(hdmi->vpll_clk)) {
 240                 dev_err(hdmi->dev, "failed to get grf clock\n");
 241                 return PTR_ERR(hdmi->vpll_clk);
 242         }
 243
 244         hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
 245         if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
 246                 hdmi->grf_clk = NULL;
 247         } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
 248                 return -EPROBE_DEFER;
 249         } else if (IS_ERR(hdmi->grf_clk)) {
 250                 dev_err(hdmi->dev, "failed to get grf clock\n");
 251                 return PTR_ERR(hdmi->grf_clk);
 252         }
 253
 254         ret = clk_prepare_enable(hdmi->vpll_clk);
 255         if (ret) {
 256                 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
 257                 return ret;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static enum drm_mode_status
 264 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 265                             struct drm_display_mode *mode)
 266 {
 267         int pclk = mode->clock * 1000;
 268         int num_rates = ARRAY_SIZE(dw_hdmi_rates);
 269         int i;
 270
 271         /*
 272          * Pixel clocks we support are always < 2GHz and so fit in an
 273          * int.  We should make sure source rate does too so we don't get
 274          * overflow when we multiply by 1000.
 275          */
 276         if (mode->clock > INT_MAX / 1000)
 277                 return MODE_BAD;
 278
 279         for (i = 0; i < num_rates; i++) {
 280                 int slop = CLK_SLOP(pclk);
 281
 282                 if ((pclk >= dw_hdmi_rates[i] - slop) &&
 283                     (pclk <= dw_hdmi_rates[i] + slop))
 284                         return MODE_OK;
 285         }
 286
 287         return MODE_BAD;
 288 }
 289
 290 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 291         .destroy = drm_encoder_cleanup,
 292 };
 293
 294 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 295 {
 296 }
 297
 298 static bool
 299 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
 300                                     const struct drm_display_mode *mode,
 301                                     struct drm_display_mode *adj_mode)
 302 {
 303         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 304         int pclk = adj_mode->clock * 1000;
 305         int best_diff = INT_MAX;
 306         int best_clock = 0;
 307         int slop;
 308         int i;
 309
 310         /* Pick the best clock */
 311         for (i = 0; i < ARRAY_SIZE(dw_hdmi_rates); i++) {
 312                 int diff = dw_hdmi_rates[i] - pclk;
 313
 314                 if (diff < 0)
 315                         diff = -diff;
 316                 if (diff < best_diff) {
 317                         best_diff = diff;
 318                         best_clock = dw_hdmi_rates[i];
 319
 320                         /* Bail early if we're exact */
 321                         if (best_diff == 0)
 322                                 return true;
 323                 }
 324         }
 325
 326         /* Double check that it's OK */
 327         slop = CLK_SLOP(pclk);
 328         if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) {
 329                 adj_mode->clock = DIV_ROUND_UP(best_clock, 1000);
 330                 return true;
 331         }
 332
 333         /* Shoudn't be here; we should have said rate wasn't valid */
 334         dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock);
 335         return false;
 336 }
 337
 338 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
 339                                               struct drm_display_mode *mode,
 340                                               struct drm_display_mode *adj_mode)
 341 {
 342         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 343
 344         clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
 345 }
 346
 347 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 348 {
 349         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 350         u32 lcdsel_grf_reg, lcdsel_mask;
 351         u32 val;
 352         int mux;
 353         int ret;
 354
 355         switch (hdmi->dev_type) {
 356         case RK3288_HDMI:
 357                 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
 358                 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
 359                 break;
 360         case RK3399_HDMI:
 361                 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
 362                 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
 363                 break;
 364         default:
 365                 return;
 366         };
 367
 368         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 369         if (mux)
 370                 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
 371         else
 372                 val = HIWORD_UPDATE(0, lcdsel_mask);
 373
 374         ret = clk_prepare_enable(hdmi->grf_clk);
 375         if (ret < 0) {
 376                 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
 377                 return;
 378         }
 379
 380         regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
 381         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 382                 (mux) ? "LIT" : "BIG");
 383
 384         clk_disable_unprepare(hdmi->grf_clk);
 385 }
 386
 387 static int
 388 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 389                                       struct drm_crtc_state *crtc_state,
 390                                       struct drm_connector_state *conn_state)
 391 {
 392         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 393
 394         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 395         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 396
 397         return 0;
 398 }
 399
 400 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 401         .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
 402         .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
 403         .enable     = dw_hdmi_rockchip_encoder_enable,
 404         .disable    = dw_hdmi_rockchip_encoder_disable,
 405         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 406 };
 407
 408 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
 409         .mode_valid = dw_hdmi_rockchip_mode_valid,
 410         .mpll_cfg   = rockchip_mpll_cfg,
 411         .cur_ctr    = rockchip_cur_ctr,
 412         .phy_config = rockchip_phy_config,
 413         .dev_type   = RK3288_HDMI,
 414         .tmds_n_table = rockchip_werid_tmds_n_table,
 415 };
 416
 417 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 418         .mode_valid = dw_hdmi_rockchip_mode_valid,
 419         .mpll_cfg   = rockchip_mpll_cfg,
 420         .cur_ctr    = rockchip_cur_ctr,
 421         .phy_config = rockchip_phy_config,
 422         .dev_type   = RK3399_HDMI,
 423 };
 424
 425 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 426         { .compatible = "rockchip,rk3288-dw-hdmi",
 427           .data = &rk3288_hdmi_drv_data
 428         },
 429         { .compatible = "rockchip,rk3399-dw-hdmi",
 430           .data = &rk3399_hdmi_drv_data
 431         },
 432         {},
 433 };
 434 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 435
 436 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 437                                  void *data)
 438 {
 439         struct platform_device *pdev = to_platform_device(dev);
 440         const struct dw_hdmi_plat_data *plat_data;
 441         const struct of_device_id *match;
 442         struct drm_device *drm = data;
 443         struct drm_encoder *encoder;
 444         struct rockchip_hdmi *hdmi;
 445         struct resource *iores;
 446         int irq;
 447         int ret;
 448
 449         if (!pdev->dev.of_node)
 450                 return -ENODEV;
 451
 452         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 453         if (!hdmi)
 454                 return -ENOMEM;
 455
 456         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 457         plat_data = match->data;
 458         hdmi->dev = &pdev->dev;
 459         hdmi->dev_type = plat_data->dev_type;
 460         encoder = &hdmi->encoder;
 461
 462         irq = platform_get_irq(pdev, 0);
 463         if (irq < 0)
 464                 return irq;
 465
 466         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 467         if (!iores)
 468                 return -ENXIO;
 469
 470         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 471         /*
 472          * If we failed to find the CRTC(s) which this encoder is
 473          * supposed to be connected to, it's because the CRTC has
 474          * not been registered yet.  Defer probing, and hope that
 475          * the required CRTC is added later.
 476          */
 477         if (encoder->possible_crtcs == 0)
 478                 return -EPROBE_DEFER;
 479
 480         ret = rockchip_hdmi_parse_dt(hdmi);
 481         if (ret) {
 482                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 483                 return ret;
 484         }
 485
 486         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 487         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 488                          DRM_MODE_ENCODER_TMDS, NULL);
 489
 490         ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
 491
 492         /*
 493          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 494          * which would have called the encoder cleanup.  Do it manually.
 495          */
 496         if (ret)
 497                 drm_encoder_cleanup(encoder);
 498
 499         return ret;
 500 }
 501
 502 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 503                                     void *data)
 504 {
 505         return dw_hdmi_unbind(dev, master, data);
 506 }
 507
 508 static const struct component_ops dw_hdmi_rockchip_ops = {
 509         .bind   = dw_hdmi_rockchip_bind,
 510         .unbind = dw_hdmi_rockchip_unbind,
 511 };
 512
 513 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 514 {
 515         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 516 }
 517
 518 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 519 {
 520         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 521
 522         return 0;
 523 }
 524
 525 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 526         .probe  = dw_hdmi_rockchip_probe,
 527         .remove = dw_hdmi_rockchip_remove,
 528         .driver = {
 529                 .name = "dwhdmi-rockchip",
 530                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 531         },
 532 };
 533
 534 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
 535
 536 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
 537 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
 538 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
 539 MODULE_LICENSE("GPL");
 540 MODULE_ALIAS("platform:dwhdmi-rockchip");