drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15
  16 #include <drm/drm_of.h>
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_edid.h>
  20 #include <drm/drm_encoder_slave.h>
  21 #include <drm/bridge/dw_hdmi.h>
  22
  23 #include "rockchip_drm_drv.h"
  24 #include "rockchip_drm_vop.h"
  25
  26 #define RK3288_GRF_SOC_CON6             0x025C
  27 #define RK3288_HDMI_LCDC_SEL            BIT(4)
  28 #define RK3399_GRF_SOC_CON20            0x6250
  29 #define RK3399_HDMI_LCDC_SEL            BIT(6)
  30
  31 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  32
  33 struct rockchip_hdmi {
  34         struct device *dev;
  35         struct regmap *regmap;
  36         struct drm_encoder encoder;
  37         enum dw_hdmi_devtype dev_type;
  38         struct clk *vpll_clk;
  39         struct clk *grf_clk;
  40 };
  41
  42 #define to_rockchip_hdmi(x)     container_of(x, struct rockchip_hdmi, x)
  43
  44 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  45         {
  46                 30666000, {
  47                         { 0x00b3, 0x0000 },
  48                         { 0x2153, 0x0000 },
  49                         { 0x40f3, 0x0000 },
  50                 },
  51         },  {
  52                 36800000, {
  53                         { 0x00b3, 0x0000 },
  54                         { 0x2153, 0x0000 },
  55                         { 0x40a2, 0x0001 },
  56                 },
  57         },  {
  58                 46000000, {
  59                         { 0x00b3, 0x0000 },
  60                         { 0x2142, 0x0001 },
  61                         { 0x40a2, 0x0001 },
  62                 },
  63         },  {
  64                 61333000, {
  65                         { 0x0072, 0x0001 },
  66                         { 0x2142, 0x0001 },
  67                         { 0x40a2, 0x0001 },
  68                 },
  69         },  {
  70                 73600000, {
  71                         { 0x0072, 0x0001 },
  72                         { 0x2142, 0x0001 },
  73                         { 0x4061, 0x0002 },
  74                 },
  75         },  {
  76                 92000000, {
  77                         { 0x0072, 0x0001 },
  78                         { 0x2145, 0x0002 },
  79                         { 0x4061, 0x0002 },
  80                 },
  81         },  {
  82                 122666000, {
  83                         { 0x0051, 0x0002 },
  84                         { 0x2145, 0x0002 },
  85                         { 0x4061, 0x0002 },
  86                 },
  87         },  {
  88                 147200000, {
  89                         { 0x0051, 0x0002 },
  90                         { 0x2145, 0x0002 },
  91                         { 0x4064, 0x0003 },
  92                 },
  93         },  {
  94                 184000000, {
  95                         { 0x0051, 0x0002 },
  96                         { 0x214c, 0x0003 },
  97                         { 0x4064, 0x0003 },
  98                 },
  99         },  {
 100                 226666000, {
 101                         { 0x0040, 0x0003 },
 102                         { 0x214c, 0x0003 },
 103                         { 0x4064, 0x0003 },
 104                 },
 105         },  {
 106                 272000000, {
 107                         { 0x0040, 0x0003 },
 108                         { 0x214c, 0x0003 },
 109                         { 0x5a64, 0x0003 },
 110                 },
 111         },  {
 112                 340000000, {
 113                         { 0x0040, 0x0003 },
 114                         { 0x3b4c, 0x0003 },
 115                         { 0x5a64, 0x0003 },
 116                 },
 117         },  {
 118                 600000000, {
 119                         { 0x1a40, 0x0003 },
 120                         { 0x3b4c, 0x0003 },
 121                         { 0x5a64, 0x0003 },
 122                 },
 123         },  {
 124                 ~0UL, {
 125                         { 0x0000, 0x0000 },
 126                         { 0x0000, 0x0000 },
 127                         { 0x0000, 0x0000 },
 128                 },
 129         }
 130 };
 131
 132 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 133         /*      pixelclk    bpp8    bpp10   bpp12 */
 134         {
 135                 600000000, { 0x0000, 0x0000, 0x0000 },
 136         },  {
 137                 ~0UL,      { 0x0000, 0x0000, 0x0000},
 138         }
 139 };
 140
 141 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
 142         /*pixelclk   symbol   term   vlev*/
 143         { 74250000,  0x8009, 0x0004, 0x0272},
 144         { 165000000, 0x802b, 0x0004, 0x0209},
 145         { 297000000, 0x8039, 0x0005, 0x028d},
 146         { ~0UL,      0x0000, 0x0000, 0x0000}
 147 };
 148
 149 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 150 {
 151         struct device_node *np = hdmi->dev->of_node;
 152         int ret;
 153
 154         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 155         if (IS_ERR(hdmi->regmap)) {
 156                 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
 157                 return PTR_ERR(hdmi->regmap);
 158         }
 159
 160         hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
 161         if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
 162                 hdmi->vpll_clk = NULL;
 163         } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
 164                 return -EPROBE_DEFER;
 165         } else if (IS_ERR(hdmi->vpll_clk)) {
 166                 dev_err(hdmi->dev, "failed to get grf clock\n");
 167                 return PTR_ERR(hdmi->vpll_clk);
 168         }
 169
 170         hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
 171         if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
 172                 hdmi->grf_clk = NULL;
 173         } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
 174                 return -EPROBE_DEFER;
 175         } else if (IS_ERR(hdmi->grf_clk)) {
 176                 dev_err(hdmi->dev, "failed to get grf clock\n");
 177                 return PTR_ERR(hdmi->grf_clk);
 178         }
 179
 180         ret = clk_prepare_enable(hdmi->vpll_clk);
 181         if (ret) {
 182                 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
 183                 return ret;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static enum drm_mode_status
 190 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
 191                             struct drm_display_mode *mode)
 192 {
 193         const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
 194         int pclk = mode->clock * 1000;
 195         bool valid = false;
 196         int i;
 197
 198         for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
 199                 if (pclk == mpll_cfg[i].mpixelclock) {
 200                         valid = true;
 201                         break;
 202                 }
 203         }
 204
 205         return (valid) ? MODE_OK : MODE_BAD;
 206 }
 207
 208 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
 209         .destroy = drm_encoder_cleanup,
 210 };
 211
 212 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 213 {
 214 }
 215
 216 static bool
 217 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
 218                                     const struct drm_display_mode *mode,
 219                                     struct drm_display_mode *adj_mode)
 220 {
 221         return true;
 222 }
 223
 224 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
 225                                               struct drm_display_mode *mode,
 226                                               struct drm_display_mode *adj_mode)
 227 {
 228         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 229
 230         clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
 231 }
 232
 233 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
 234 {
 235         struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 236         u32 lcdsel_grf_reg, lcdsel_mask;
 237         u32 val;
 238         int mux;
 239         int ret;
 240
 241         switch (hdmi->dev_type) {
 242         case RK3288_HDMI:
 243                 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
 244                 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
 245                 break;
 246         case RK3399_HDMI:
 247                 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
 248                 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
 249                 break;
 250         default:
 251                 return;
 252         };
 253
 254         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 255         if (mux)
 256                 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
 257         else
 258                 val = HIWORD_UPDATE(0, lcdsel_mask);
 259
 260         ret = clk_prepare_enable(hdmi->grf_clk);
 261         if (ret < 0) {
 262                 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
 263                 return;
 264         }
 265
 266         regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
 267         dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
 268                 (mux) ? "LIT" : "BIG");
 269
 270         clk_disable_unprepare(hdmi->grf_clk);
 271 }
 272
 273 static int
 274 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
 275                                       struct drm_crtc_state *crtc_state,
 276                                       struct drm_connector_state *conn_state)
 277 {
 278         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 279
 280         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 281         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 282
 283         return 0;
 284 }
 285
 286 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
 287         .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
 288         .mode_set   = dw_hdmi_rockchip_encoder_mode_set,
 289         .enable     = dw_hdmi_rockchip_encoder_enable,
 290         .disable    = dw_hdmi_rockchip_encoder_disable,
 291         .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
 292 };
 293
 294 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
 295         .mode_valid = dw_hdmi_rockchip_mode_valid,
 296         .mpll_cfg   = rockchip_mpll_cfg,
 297         .cur_ctr    = rockchip_cur_ctr,
 298         .phy_config = rockchip_phy_config,
 299         .dev_type   = RK3288_HDMI,
 300 };
 301
 302 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 303         .mode_valid = dw_hdmi_rockchip_mode_valid,
 304         .mpll_cfg   = rockchip_mpll_cfg,
 305         .cur_ctr    = rockchip_cur_ctr,
 306         .phy_config = rockchip_phy_config,
 307         .dev_type   = RK3399_HDMI,
 308 };
 309
 310 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 311         { .compatible = "rockchip,rk3288-dw-hdmi",
 312           .data = &rk3288_hdmi_drv_data
 313         },
 314         { .compatible = "rockchip,rk3399-dw-hdmi",
 315           .data = &rk3399_hdmi_drv_data
 316         },
 317         {},
 318 };
 319 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
 320
 321 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 322                                  void *data)
 323 {
 324         struct platform_device *pdev = to_platform_device(dev);
 325         const struct dw_hdmi_plat_data *plat_data;
 326         const struct of_device_id *match;
 327         struct drm_device *drm = data;
 328         struct drm_encoder *encoder;
 329         struct rockchip_hdmi *hdmi;
 330         struct resource *iores;
 331         int irq;
 332         int ret;
 333
 334         if (!pdev->dev.of_node)
 335                 return -ENODEV;
 336
 337         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 338         if (!hdmi)
 339                 return -ENOMEM;
 340
 341         match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
 342         plat_data = match->data;
 343         hdmi->dev = &pdev->dev;
 344         hdmi->dev_type = plat_data->dev_type;
 345         encoder = &hdmi->encoder;
 346
 347         irq = platform_get_irq(pdev, 0);
 348         if (irq < 0)
 349                 return irq;
 350
 351         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 352         if (!iores)
 353                 return -ENXIO;
 354
 355         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 356         /*
 357          * If we failed to find the CRTC(s) which this encoder is
 358          * supposed to be connected to, it's because the CRTC has
 359          * not been registered yet.  Defer probing, and hope that
 360          * the required CRTC is added later.
 361          */
 362         if (encoder->possible_crtcs == 0)
 363                 return -EPROBE_DEFER;
 364
 365         ret = rockchip_hdmi_parse_dt(hdmi);
 366         if (ret) {
 367                 dev_err(hdmi->dev, "Unable to parse OF data\n");
 368                 return ret;
 369         }
 370
 371         drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 372         drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
 373                          DRM_MODE_ENCODER_TMDS, NULL);
 374
 375         ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
 376
 377         /*
 378          * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 379          * which would have called the encoder cleanup.  Do it manually.
 380          */
 381         if (ret)
 382                 drm_encoder_cleanup(encoder);
 383
 384         return ret;
 385 }
 386
 387 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 388                                     void *data)
 389 {
 390         return dw_hdmi_unbind(dev, master, data);
 391 }
 392
 393 static const struct component_ops dw_hdmi_rockchip_ops = {
 394         .bind   = dw_hdmi_rockchip_bind,
 395         .unbind = dw_hdmi_rockchip_unbind,
 396 };
 397
 398 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
 399 {
 400         return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
 401 }
 402
 403 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
 404 {
 405         component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
 406
 407         return 0;
 408 }
 409
 410 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
 411         .probe  = dw_hdmi_rockchip_probe,
 412         .remove = dw_hdmi_rockchip_remove,
 413         .driver = {
 414                 .name = "dwhdmi-rockchip",
 415                 .of_match_table = dw_hdmi_rockchip_dt_ids,
 416         },
 417 };
 418
 419 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
 420
 421 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
 422 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
 423 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
 424 MODULE_LICENSE("GPL");
 425 MODULE_ALIAS("platform:dwhdmi-rockchip");