2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
16 #include <drm/drm_of.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_encoder_slave.h>
21 #include <drm/bridge/dw_hdmi.h>
23 #include "rockchip_drm_drv.h"
24 #include "rockchip_drm_vop.h"
26 #define RK3288_GRF_SOC_CON6 0x025C
27 #define RK3288_HDMI_LCDC_SEL BIT(4)
28 #define RK3399_GRF_SOC_CON20 0x6250
29 #define RK3399_HDMI_LCDC_SEL BIT(6)
31 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
33 struct rockchip_hdmi {
35 struct regmap *regmap;
36 struct drm_encoder encoder;
37 enum dw_hdmi_devtype dev_type;
42 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
44 #define CLK_SLOP(clk) ((clk) / 1000)
45 #define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk))
47 static const int dw_hdmi_rates[] = {
48 25176471, /* for 25.175 MHz, 0.006% off */
61 57290323, /* for 57.284 MHz, .011 % off */
68 74437500, /* for 74.44 MHz, .003% off */
81 118666667, /* for 118.68 MHz, .011% off */
83 121714286, /* for 121.75 MHz, .029% off */
85 136800000, /* for 136.75 MHz, .037% off */
95 * There are some rates that would be ranged for better clock jitter at
96 * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
97 * to the clock is aglined to KHz in struct drm_display_mode, this would
98 * bring some inaccurate error if we still run the compute_n math, so
99 * let's just code an const table for it until we can actually get the
102 static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
103 /* 25176471 for 25.175 MHz = 428000000 / 17. */
104 { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
105 /* 57290323 for 57.284 MHz */
106 { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
107 /* 74437500 for 74.44 MHz = 297750000 / 4 */
108 { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
109 /* 118666667 for 118.68 MHz */
110 { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
111 /* 121714286 for 121.75 MHz */
112 { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
113 /* 136800000 for 136.75 MHz */
114 { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
116 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
119 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
207 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
208 /* pixelclk bpp8 bpp10 bpp12 */
210 600000000, { 0x0000, 0x0000, 0x0000 },
212 ~0UL, { 0x0000, 0x0000, 0x0000},
216 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
217 /*pixelclk symbol term vlev*/
218 { 74250000, 0x8009, 0x0004, 0x0272},
219 { 165000000, 0x802b, 0x0004, 0x0209},
220 { 297000000, 0x8039, 0x0005, 0x028d},
221 { ~0UL, 0x0000, 0x0000, 0x0000}
224 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
226 struct device_node *np = hdmi->dev->of_node;
229 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
230 if (IS_ERR(hdmi->regmap)) {
231 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
232 return PTR_ERR(hdmi->regmap);
235 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
236 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
237 hdmi->vpll_clk = NULL;
238 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
239 return -EPROBE_DEFER;
240 } else if (IS_ERR(hdmi->vpll_clk)) {
241 dev_err(hdmi->dev, "failed to get grf clock\n");
242 return PTR_ERR(hdmi->vpll_clk);
245 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
246 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
247 hdmi->grf_clk = NULL;
248 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
249 return -EPROBE_DEFER;
250 } else if (IS_ERR(hdmi->grf_clk)) {
251 dev_err(hdmi->dev, "failed to get grf clock\n");
252 return PTR_ERR(hdmi->grf_clk);
255 ret = clk_prepare_enable(hdmi->vpll_clk);
257 dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
264 static enum drm_mode_status
265 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
266 struct drm_display_mode *mode)
268 int pclk = mode->clock * 1000;
269 int num_rates = ARRAY_SIZE(dw_hdmi_rates);
273 * Pixel clocks we support are always < 2GHz and so fit in an
274 * int. We should make sure source rate does too so we don't get
275 * overflow when we multiply by 1000.
277 if (mode->clock > INT_MAX / 1000)
280 for (i = 0; i < num_rates; i++) {
281 int slop = CLK_SLOP(pclk);
283 if ((pclk >= dw_hdmi_rates[i] - slop) &&
284 (pclk <= dw_hdmi_rates[i] + slop))
291 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
292 .destroy = drm_encoder_cleanup,
295 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
300 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
301 const struct drm_display_mode *mode,
302 struct drm_display_mode *adj_mode)
304 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
305 int pclk = adj_mode->clock * 1000;
306 int best_diff = INT_MAX;
311 /* Pick the best clock */
312 for (i = 0; i < ARRAY_SIZE(dw_hdmi_rates); i++) {
313 int diff = dw_hdmi_rates[i] - pclk;
317 if (diff < best_diff) {
319 best_clock = dw_hdmi_rates[i];
321 /* Bail early if we're exact */
327 /* Double check that it's OK */
328 slop = CLK_SLOP(pclk);
329 if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) {
330 adj_mode->clock = DIV_ROUND_UP(best_clock, 1000);
334 /* Shoudn't be here; we should have said rate wasn't valid */
335 dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock);
339 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
340 struct drm_display_mode *mode,
341 struct drm_display_mode *adj_mode)
343 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
345 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
348 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
350 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
351 u32 lcdsel_grf_reg, lcdsel_mask;
356 switch (hdmi->dev_type) {
358 lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
359 lcdsel_mask = RK3288_HDMI_LCDC_SEL;
362 lcdsel_grf_reg = RK3399_GRF_SOC_CON20;
363 lcdsel_mask = RK3399_HDMI_LCDC_SEL;
369 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
371 val = HIWORD_UPDATE(lcdsel_mask, lcdsel_mask);
373 val = HIWORD_UPDATE(0, lcdsel_mask);
375 ret = clk_prepare_enable(hdmi->grf_clk);
377 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
381 regmap_write(hdmi->regmap, lcdsel_grf_reg, val);
382 dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
383 (mux) ? "LIT" : "BIG");
385 clk_disable_unprepare(hdmi->grf_clk);
389 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
390 struct drm_crtc_state *crtc_state,
391 struct drm_connector_state *conn_state)
393 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
395 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
396 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
397 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
402 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
403 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
404 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
405 .enable = dw_hdmi_rockchip_encoder_enable,
406 .disable = dw_hdmi_rockchip_encoder_disable,
407 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
410 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
411 .mode_valid = dw_hdmi_rockchip_mode_valid,
412 .mpll_cfg = rockchip_mpll_cfg,
413 .cur_ctr = rockchip_cur_ctr,
414 .phy_config = rockchip_phy_config,
415 .dev_type = RK3288_HDMI,
416 .tmds_n_table = rockchip_werid_tmds_n_table,
419 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
420 .mode_valid = dw_hdmi_rockchip_mode_valid,
421 .mpll_cfg = rockchip_mpll_cfg,
422 .cur_ctr = rockchip_cur_ctr,
423 .phy_config = rockchip_phy_config,
424 .dev_type = RK3399_HDMI,
427 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
428 { .compatible = "rockchip,rk3288-dw-hdmi",
429 .data = &rk3288_hdmi_drv_data
431 { .compatible = "rockchip,rk3399-dw-hdmi",
432 .data = &rk3399_hdmi_drv_data
436 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
438 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
441 struct platform_device *pdev = to_platform_device(dev);
442 const struct dw_hdmi_plat_data *plat_data;
443 const struct of_device_id *match;
444 struct drm_device *drm = data;
445 struct drm_encoder *encoder;
446 struct rockchip_hdmi *hdmi;
447 struct resource *iores;
451 if (!pdev->dev.of_node)
454 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
458 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
459 plat_data = match->data;
460 hdmi->dev = &pdev->dev;
461 hdmi->dev_type = plat_data->dev_type;
462 encoder = &hdmi->encoder;
464 irq = platform_get_irq(pdev, 0);
468 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
472 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
474 * If we failed to find the CRTC(s) which this encoder is
475 * supposed to be connected to, it's because the CRTC has
476 * not been registered yet. Defer probing, and hope that
477 * the required CRTC is added later.
479 if (encoder->possible_crtcs == 0)
480 return -EPROBE_DEFER;
482 ret = rockchip_hdmi_parse_dt(hdmi);
484 dev_err(hdmi->dev, "Unable to parse OF data\n");
488 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
489 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
490 DRM_MODE_ENCODER_TMDS, NULL);
492 ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
495 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
496 * which would have called the encoder cleanup. Do it manually.
499 drm_encoder_cleanup(encoder);
504 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
507 return dw_hdmi_unbind(dev, master, data);
510 static const struct component_ops dw_hdmi_rockchip_ops = {
511 .bind = dw_hdmi_rockchip_bind,
512 .unbind = dw_hdmi_rockchip_unbind,
515 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
517 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
520 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
522 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
527 static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
528 .probe = dw_hdmi_rockchip_probe,
529 .remove = dw_hdmi_rockchip_remove,
531 .name = "dwhdmi-rockchip",
532 .of_match_table = dw_hdmi_rockchip_dt_ids,
536 module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
538 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
539 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
540 MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
541 MODULE_LICENSE("GPL");
542 MODULE_ALIAS("platform:dwhdmi-rockchip");