drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/devfreq.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/component.h>
  32
  33 #include <linux/reset.h>
  34 #include <linux/delay.h>
  35 #include <linux/sort.h>
  36 #include <uapi/drm/rockchip_drm.h>
  37
  38 #include "rockchip_drm_drv.h"
  39 #include "rockchip_drm_gem.h"
  40 #include "rockchip_drm_fb.h"
  41 #include "rockchip_drm_vop.h"
  42
  43 #define VOP_REG_SUPPORT(vop, reg) \
  44                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  45                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  46                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  47                 reg.mask))
  48
  49 #define VOP_WIN_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, win->phy->name)
  51
  52 #define VOP_CTRL_SUPPORT(vop, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  54
  55 #define VOP_INTR_SUPPORT(vop, name) \
  56                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  57
  58 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  59                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  60
  61 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  62         do { \
  63                 if (VOP_REG_SUPPORT(vop, reg)) \
  64                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  65                                   v, reg.write_mask, relaxed); \
  66                 else \
  67                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  68         } while(0)
  69
  70 #define REG_SET(x, name, off, reg, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  72 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  73                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  74
  75 #define VOP_WIN_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  77 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  78                 REG_SET(x, name, 0, win->ext->name, v, true)
  79 #define VOP_SCL_SET(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  81 #define VOP_SCL_SET_EXT(x, win, name, v) \
  82                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  83
  84 #define VOP_CTRL_SET(x, name, v) \
  85                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  86
  87 #define VOP_INTR_GET(vop, name) \
  88                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  89
  90 #define VOP_INTR_SET(vop, name, v) \
  91                 REG_SET(vop, name, 0, vop->data->intr->name, \
  92                         v, false)
  93 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  94                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  95                              mask, v, false)
  96
  97 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  98         do { \
  99                 int i, reg = 0, mask = 0; \
 100                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 101                         if (vop->data->intr->intrs[i] & type) { \
 102                                 reg |= (v) << i; \
 103                                 mask |= 1 << i; \
 104                         } \
 105                 } \
 106                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 107         } while (0)
 108 #define VOP_INTR_GET_TYPE(vop, name, type) \
 109                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 110
 111 #define VOP_CTRL_GET(x, name) \
 112                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 113
 114 #define VOP_WIN_GET(x, win, name) \
 115                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 116
 117 #define VOP_WIN_NAME(win, name) \
 118                 (vop_get_win_phy(win, &win->phy->name)->name)
 119
 120 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 121                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 122
 123 #define to_vop(x) container_of(x, struct vop, crtc)
 124 #define to_vop_win(x) container_of(x, struct vop_win, base)
 125 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 126
 127 struct vop_zpos {
 128         int win_id;
 129         int zpos;
 130 };
 131
 132 struct vop_plane_state {
 133         struct drm_plane_state base;
 134         int format;
 135         int zpos;
 136         struct drm_rect src;
 137         struct drm_rect dest;
 138         dma_addr_t yrgb_mst;
 139         dma_addr_t uv_mst;
 140         const uint32_t *y2r_table;
 141         const uint32_t *r2r_table;
 142         const uint32_t *r2y_table;
 143         bool enable;
 144 };
 145
 146 struct vop_win {
 147         struct vop_win *parent;
 148         struct drm_plane base;
 149
 150         int win_id;
 151         int area_id;
 152         uint32_t offset;
 153         enum drm_plane_type type;
 154         const struct vop_win_phy *phy;
 155         const struct vop_csc *csc;
 156         const uint32_t *data_formats;
 157         uint32_t nformats;
 158         struct vop *vop;
 159
 160         struct drm_property *rotation_prop;
 161         struct vop_plane_state state;
 162 };
 163
 164 struct vop {
 165         struct drm_crtc crtc;
 166         struct device *dev;
 167         struct drm_device *drm_dev;
 168         struct drm_property *plane_zpos_prop;
 169         struct drm_property *plane_feature_prop;
 170         struct drm_property *feature_prop;
 171         bool is_iommu_enabled;
 172         bool is_iommu_needed;
 173         bool is_enabled;
 174
 175         /* mutex vsync_ work */
 176         struct mutex vsync_mutex;
 177         bool vsync_work_pending;
 178         bool loader_protect;
 179         struct completion dsp_hold_completion;
 180         struct completion wait_update_complete;
 181         struct drm_pending_vblank_event *event;
 182
 183         struct completion line_flag_completion;
 184
 185         const struct vop_data *data;
 186         int num_wins;
 187
 188         uint32_t *regsbak;
 189         void __iomem *regs;
 190
 191         /* physical map length of vop register */
 192         uint32_t len;
 193
 194         void __iomem *lut_regs;
 195         u32 *lut;
 196         u32 lut_len;
 197         bool lut_active;
 198
 199         /* one time only one process allowed to config the register */
 200         spinlock_t reg_lock;
 201         /* lock vop irq reg */
 202         spinlock_t irq_lock;
 203         /* mutex vop enable and disable */
 204         struct mutex vop_lock;
 205
 206         unsigned int irq;
 207
 208         /* vop AHP clk */
 209         struct clk *hclk;
 210         /* vop dclk */
 211         struct clk *dclk;
 212         /* vop share memory frequency */
 213         struct clk *aclk;
 214
 215         /* vop dclk reset */
 216         struct reset_control *dclk_rst;
 217
 218         struct devfreq *devfreq;
 219         struct notifier_block dmc_nb;
 220
 221         struct vop_win win[];
 222 };
 223
 224 struct vop *dmc_vop;
 225
 226 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 227 {
 228         writel(v, vop->regs + offset);
 229         vop->regsbak[offset >> 2] = v;
 230 }
 231
 232 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 233 {
 234         return readl(vop->regs + offset);
 235 }
 236
 237 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 238                                     const struct vop_reg *reg)
 239 {
 240         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 241 }
 242
 243 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 244                                   uint32_t mask, uint32_t shift, uint32_t v,
 245                                   bool write_mask, bool relaxed)
 246 {
 247         if (!mask)
 248                 return;
 249
 250         if (write_mask) {
 251                 v = ((v & mask) << shift) | (mask << (shift + 16));
 252         } else {
 253                 uint32_t cached_val = vop->regsbak[offset >> 2];
 254
 255                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 256                 vop->regsbak[offset >> 2] = v;
 257         }
 258
 259         if (relaxed)
 260                 writel_relaxed(v, vop->regs + offset);
 261         else
 262                 writel(v, vop->regs + offset);
 263 }
 264
 265 static inline const struct vop_win_phy *
 266 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 267 {
 268         if (!reg->mask && win->parent)
 269                 return win->parent->phy;
 270
 271         return win->phy;
 272 }
 273
 274 static inline uint32_t vop_get_intr_type(struct vop *vop,
 275                                          const struct vop_reg *reg, int type)
 276 {
 277         uint32_t i, ret = 0;
 278         uint32_t regs = vop_read_reg(vop, 0, reg);
 279
 280         for (i = 0; i < vop->data->intr->nintrs; i++) {
 281                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 282                         ret |= vop->data->intr->intrs[i];
 283         }
 284
 285         return ret;
 286 }
 287
 288 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 289 {
 290         int i;
 291
 292         if (!table)
 293                 return;
 294
 295         for (i = 0; i < 8; i++)
 296                 vop_writel(vop, offset + i * 4, table[i]);
 297 }
 298
 299 static inline void vop_cfg_done(struct vop *vop)
 300 {
 301         VOP_CTRL_SET(vop, cfg_done, 1);
 302 }
 303
 304 static bool vop_is_allwin_disabled(struct vop *vop)
 305 {
 306         int i;
 307
 308         for (i = 0; i < vop->num_wins; i++) {
 309                 struct vop_win *win = &vop->win[i];
 310
 311                 if (VOP_WIN_GET(vop, win, enable) != 0)
 312                         return false;
 313         }
 314
 315         return true;
 316 }
 317
 318 static bool vop_is_cfg_done_complete(struct vop *vop)
 319 {
 320         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 321 }
 322
 323 static bool vop_fs_irq_is_active(struct vop *vop)
 324 {
 325         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 326 }
 327
 328 static bool vop_line_flag_is_active(struct vop *vop)
 329 {
 330         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 331 }
 332
 333 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 334 {
 335         writel(v, vop->lut_regs + offset);
 336 }
 337
 338 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 339 {
 340         return readl(vop->lut_regs + offset);
 341 }
 342
 343 static bool has_rb_swapped(uint32_t format)
 344 {
 345         switch (format) {
 346         case DRM_FORMAT_XBGR8888:
 347         case DRM_FORMAT_ABGR8888:
 348         case DRM_FORMAT_BGR888:
 349         case DRM_FORMAT_BGR565:
 350                 return true;
 351         default:
 352                 return false;
 353         }
 354 }
 355
 356 static enum vop_data_format vop_convert_format(uint32_t format)
 357 {
 358         switch (format) {
 359         case DRM_FORMAT_XRGB8888:
 360         case DRM_FORMAT_ARGB8888:
 361         case DRM_FORMAT_XBGR8888:
 362         case DRM_FORMAT_ABGR8888:
 363                 return VOP_FMT_ARGB8888;
 364         case DRM_FORMAT_RGB888:
 365         case DRM_FORMAT_BGR888:
 366                 return VOP_FMT_RGB888;
 367         case DRM_FORMAT_RGB565:
 368         case DRM_FORMAT_BGR565:
 369                 return VOP_FMT_RGB565;
 370         case DRM_FORMAT_NV12:
 371         case DRM_FORMAT_NV12_10:
 372                 return VOP_FMT_YUV420SP;
 373         case DRM_FORMAT_NV16:
 374         case DRM_FORMAT_NV16_10:
 375                 return VOP_FMT_YUV422SP;
 376         case DRM_FORMAT_NV24:
 377         case DRM_FORMAT_NV24_10:
 378                 return VOP_FMT_YUV444SP;
 379         default:
 380                 DRM_ERROR("unsupport format[%08x]\n", format);
 381                 return -EINVAL;
 382         }
 383 }
 384
 385 static bool is_yuv_output(uint32_t bus_format)
 386 {
 387         switch (bus_format) {
 388         case MEDIA_BUS_FMT_YUV8_1X24:
 389         case MEDIA_BUS_FMT_YUV10_1X30:
 390                 return true;
 391         default:
 392                 return false;
 393         }
 394 }
 395
 396 static bool is_yuv_support(uint32_t format)
 397 {
 398         switch (format) {
 399         case DRM_FORMAT_NV12:
 400         case DRM_FORMAT_NV12_10:
 401         case DRM_FORMAT_NV16:
 402         case DRM_FORMAT_NV16_10:
 403         case DRM_FORMAT_NV24:
 404         case DRM_FORMAT_NV24_10:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410
 411 static bool is_yuv_10bit(uint32_t format)
 412 {
 413         switch (format) {
 414         case DRM_FORMAT_NV12_10:
 415         case DRM_FORMAT_NV16_10:
 416         case DRM_FORMAT_NV24_10:
 417                 return true;
 418         default:
 419                 return false;
 420         }
 421 }
 422
 423 static bool is_alpha_support(uint32_t format)
 424 {
 425         switch (format) {
 426         case DRM_FORMAT_ARGB8888:
 427         case DRM_FORMAT_ABGR8888:
 428                 return true;
 429         default:
 430                 return false;
 431         }
 432 }
 433
 434 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 435                                   uint32_t dst, bool is_horizontal,
 436                                   int vsu_mode, int *vskiplines)
 437 {
 438         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 439
 440         if (is_horizontal) {
 441                 if (mode == SCALE_UP)
 442                         val = GET_SCL_FT_BIC(src, dst);
 443                 else if (mode == SCALE_DOWN)
 444                         val = GET_SCL_FT_BILI_DN(src, dst);
 445         } else {
 446                 if (mode == SCALE_UP) {
 447                         if (vsu_mode == SCALE_UP_BIL)
 448                                 val = GET_SCL_FT_BILI_UP(src, dst);
 449                         else
 450                                 val = GET_SCL_FT_BIC(src, dst);
 451                 } else if (mode == SCALE_DOWN) {
 452                         if (vskiplines) {
 453                                 *vskiplines = scl_get_vskiplines(src, dst);
 454                                 val = scl_get_bili_dn_vskip(src, dst,
 455                                                             *vskiplines);
 456                         } else {
 457                                 val = GET_SCL_FT_BILI_DN(src, dst);
 458                         }
 459                 }
 460         }
 461
 462         return val;
 463 }
 464
 465 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 466                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 467                                 uint32_t dst_h, uint32_t pixel_format)
 468 {
 469         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 470         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 471         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 472         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 473         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 474         bool is_yuv = is_yuv_support(pixel_format);
 475         uint16_t cbcr_src_w = src_w / hsub;
 476         uint16_t cbcr_src_h = src_h / vsub;
 477         uint16_t vsu_mode;
 478         uint16_t lb_mode;
 479         uint32_t val;
 480         int vskiplines = 0;
 481
 482         if (!win->phy->scl)
 483                 return;
 484
 485         if (!win->phy->scl->ext) {
 486                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 487                             scl_cal_scale2(src_w, dst_w));
 488                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 489                             scl_cal_scale2(src_h, dst_h));
 490                 if (is_yuv) {
 491                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 492                                     scl_cal_scale2(cbcr_src_w, dst_w));
 493                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 494                                     scl_cal_scale2(cbcr_src_h, dst_h));
 495                 }
 496                 return;
 497         }
 498
 499         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 500         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 501
 502         if (is_yuv) {
 503                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 504                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 505                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 506                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 507                 else
 508                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 509         } else {
 510                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 511                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 512                 else
 513                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 514         }
 515
 516         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 517         if (lb_mode == LB_RGB_3840X2) {
 518                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 519                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 520                         return;
 521                 }
 522                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 523                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 524                         return;
 525                 }
 526                 vsu_mode = SCALE_UP_BIL;
 527         } else if (lb_mode == LB_RGB_2560X4) {
 528                 vsu_mode = SCALE_UP_BIL;
 529         } else {
 530                 vsu_mode = SCALE_UP_BIC;
 531         }
 532
 533         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 534                                 true, 0, NULL);
 535         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 536         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 537                                 false, vsu_mode, &vskiplines);
 538         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 539
 540         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 541         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 542
 543         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 544         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 545         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 546         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 547         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 548         if (is_yuv) {
 549                 vskiplines = 0;
 550
 551                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 552                                         dst_w, true, 0, NULL);
 553                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 554                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 555                                         dst_h, false, vsu_mode, &vskiplines);
 556                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 557
 558                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 559                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 560                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 561                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 562                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 563                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 564                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 565         }
 566 }
 567
 568 /*
 569  * rk3399 colorspace path:
 570  *      Input        Win csc                     Output
 571  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 572  *    RGB        --> R2Y                  __/
 573  *
 574  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 575  *    RGB        --> 709To2020->R2Y       __/
 576  *
 577  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 578  *    RGB        --> R2Y                  __/
 579  *
 580  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 581  *    RGB        --> 709To2020->R2Y       __/
 582  *
 583  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 584  *    RGB        --> R2Y                  __/
 585  *
 586  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 587  *    RGB        --> R2Y(601)             __/
 588  *
 589  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 590  *    RGB        --> bypass               __/
 591  *
 592  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 593  *
 594  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 595  *
 596  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 597  *
 598  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 599  */
 600 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 601                          bool is_input_yuv, bool is_output_yuv,
 602                          int input_csc, int output_csc,
 603                          const uint32_t **y2r_table,
 604                          const uint32_t **r2r_table,
 605                          const uint32_t **r2y_table)
 606 {
 607         *y2r_table = NULL;
 608         *r2r_table = NULL;
 609         *r2y_table = NULL;
 610
 611         if (is_output_yuv) {
 612                 if (output_csc == CSC_BT2020) {
 613                         if (is_input_yuv) {
 614                                 if (input_csc == CSC_BT2020)
 615                                         return 0;
 616                                 *y2r_table = csc_table->y2r_bt709;
 617                         }
 618                         if (input_csc != CSC_BT2020)
 619                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 620                         *r2y_table = csc_table->r2y_bt2020;
 621                 } else {
 622                         if (is_input_yuv && input_csc == CSC_BT2020)
 623                                 *y2r_table = csc_table->y2r_bt2020;
 624                         if (input_csc == CSC_BT2020)
 625                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 626                         if (!is_input_yuv || *y2r_table) {
 627                                 if (output_csc == CSC_BT709)
 628                                         *r2y_table = csc_table->r2y_bt709;
 629                                 else
 630                                         *r2y_table = csc_table->r2y_bt601;
 631                         }
 632                 }
 633         } else {
 634                 if (!is_input_yuv)
 635                         return 0;
 636
 637                 /*
 638                  * is possible use bt2020 on rgb mode?
 639                  */
 640                 if (WARN_ON(output_csc == CSC_BT2020))
 641                         return -EINVAL;
 642
 643                 if (input_csc == CSC_BT2020)
 644                         *y2r_table = csc_table->y2r_bt2020;
 645                 else if (input_csc == CSC_BT709)
 646                         *y2r_table = csc_table->y2r_bt709;
 647                 else
 648                         *y2r_table = csc_table->y2r_bt601;
 649
 650                 if (input_csc == CSC_BT2020)
 651                         /*
 652                          * We don't have bt601 to bt709 table, force use bt709.
 653                          */
 654                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 661                                 struct drm_crtc_state *crtc_state)
 662 {
 663         struct vop *vop = to_vop(crtc);
 664         struct drm_atomic_state *state = crtc_state->state;
 665         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 666         const struct vop_csc_table *csc_table = vop->data->csc_table;
 667         struct drm_plane_state *pstate;
 668         struct drm_plane *plane;
 669         bool is_input_yuv, is_output_yuv;
 670         int ret;
 671
 672         if (!csc_table)
 673                 return 0;
 674
 675         is_output_yuv = is_yuv_output(s->bus_format);
 676
 677         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 678                 struct vop_plane_state *vop_plane_state;
 679
 680                 pstate = drm_atomic_get_plane_state(state, plane);
 681                 if (IS_ERR(pstate))
 682                         return PTR_ERR(pstate);
 683                 vop_plane_state = to_vop_plane_state(pstate);
 684
 685                 if (!pstate->fb)
 686                         continue;
 687                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 688
 689                 /*
 690                  * TODO: force set input and output csc mode.
 691                  */
 692                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 693                                     CSC_BT709, CSC_BT709,
 694                                     &vop_plane_state->y2r_table,
 695                                     &vop_plane_state->r2r_table,
 696                                     &vop_plane_state->r2y_table);
 697                 if (ret)
 698                         return ret;
 699         }
 700
 701         return 0;
 702 }
 703
 704 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 705 {
 706         unsigned long flags;
 707
 708         spin_lock_irqsave(&vop->irq_lock, flags);
 709
 710         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 711         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 712
 713         spin_unlock_irqrestore(&vop->irq_lock, flags);
 714 }
 715
 716 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 717 {
 718         unsigned long flags;
 719
 720         spin_lock_irqsave(&vop->irq_lock, flags);
 721
 722         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 723
 724         spin_unlock_irqrestore(&vop->irq_lock, flags);
 725 }
 726
 727 /*
 728  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 729  *     the "FRAME_SYNC" interrupt.
 730  * (2) the active data region of each frame ends at dsp_vact_end
 731  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 732  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 733  *
 734  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 735  * Interrupts
 736  * LINE_FLAG -------------------------------+
 737  * FRAME_SYNC ----+                         |
 738  *                |                         |
 739  *                v                         v
 740  *                | Vsync | Vbp |  Vactive  | Vfp |
 741  *                        ^     ^           ^     ^
 742  *                        |     |           |     |
 743  *                        |     |           |     |
 744  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 745  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 746  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 747  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 748  */
 749 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 750 {
 751         uint32_t line_flag_irq;
 752         unsigned long flags;
 753
 754         spin_lock_irqsave(&vop->irq_lock, flags);
 755
 756         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 757
 758         spin_unlock_irqrestore(&vop->irq_lock, flags);
 759
 760         return !!line_flag_irq;
 761 }
 762
 763 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 764 {
 765         unsigned long flags;
 766
 767         if (WARN_ON(!vop->is_enabled))
 768                 return;
 769
 770         spin_lock_irqsave(&vop->irq_lock, flags);
 771
 772         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 773         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 774         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 775
 776         spin_unlock_irqrestore(&vop->irq_lock, flags);
 777 }
 778
 779 static void vop_line_flag_irq_disable(struct vop *vop)
 780 {
 781         unsigned long flags;
 782
 783         if (WARN_ON(!vop->is_enabled))
 784                 return;
 785
 786         spin_lock_irqsave(&vop->irq_lock, flags);
 787
 788         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 789
 790         spin_unlock_irqrestore(&vop->irq_lock, flags);
 791 }
 792
 793 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 794 {
 795         struct vop *vop = to_vop(crtc);
 796         int i, dle, lut_idx;
 797
 798         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 799                 return;
 800
 801         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 802                 return;
 803
 804         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 805                 spin_lock(&vop->reg_lock);
 806                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 807                 vop_cfg_done(vop);
 808                 spin_unlock(&vop->reg_lock);
 809
 810 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 811                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 812                                 dle, !dle, 5, 33333);
 813         } else {
 814                 lut_idx = CTRL_GET(lut_buffer_index);
 815         }
 816
 817         for (i = 0; i < vop->lut_len; i++)
 818                 vop_write_lut(vop, i << 2, vop->lut[i]);
 819
 820         spin_lock(&vop->reg_lock);
 821
 822         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 823         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 824         vop_cfg_done(vop);
 825         vop->lut_active = true;
 826
 827         spin_unlock(&vop->reg_lock);
 828
 829         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 830                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 831                                    dle, dle != lut_idx, 5, 33333);
 832                 /* FIXME:
 833                  * update_gamma value auto clean to 0 by HW, should not
 834                  * bakeup it.
 835                  */
 836                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 837         }
 838 #undef CTRL_GET
 839 }
 840
 841 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 842                                     u16 blue, int regno)
 843 {
 844         struct vop *vop = to_vop(crtc);
 845         u32 lut_len = vop->lut_len;
 846         u32 r, g, b;
 847
 848         if (regno >= lut_len || !vop->lut)
 849                 return;
 850
 851         r = red * (lut_len - 1) / 0xffff;
 852         g = green * (lut_len - 1) / 0xffff;
 853         b = blue * (lut_len - 1) / 0xffff;
 854         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 855 }
 856
 857 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 858                                     u16 *blue, int regno)
 859 {
 860         struct vop *vop = to_vop(crtc);
 861         u32 lut_len = vop->lut_len;
 862         u32 r, g, b;
 863
 864         if (regno >= lut_len || !vop->lut)
 865                 return;
 866
 867         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 868         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 869         b = vop->lut[regno] & (lut_len - 1);
 870         *red = r * 0xffff / (lut_len - 1);
 871         *green = g * 0xffff / (lut_len - 1);
 872         *blue = b * 0xffff / (lut_len - 1);
 873 }
 874
 875 static void vop_power_enable(struct drm_crtc *crtc)
 876 {
 877         struct vop *vop = to_vop(crtc);
 878         int ret;
 879
 880         ret = clk_prepare_enable(vop->hclk);
 881         if (ret < 0) {
 882                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 883                 return;
 884         }
 885
 886         ret = clk_prepare_enable(vop->dclk);
 887         if (ret < 0) {
 888                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 889                 goto err_disable_hclk;
 890         }
 891
 892         ret = clk_prepare_enable(vop->aclk);
 893         if (ret < 0) {
 894                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 895                 goto err_disable_dclk;
 896         }
 897
 898         ret = pm_runtime_get_sync(vop->dev);
 899         if (ret < 0) {
 900                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 901                 return;
 902         }
 903
 904         memcpy(vop->regsbak, vop->regs, vop->len);
 905
 906         vop->is_enabled = true;
 907
 908         return;
 909
 910 err_disable_dclk:
 911         clk_disable_unprepare(vop->dclk);
 912 err_disable_hclk:
 913         clk_disable_unprepare(vop->hclk);
 914 }
 915
 916 static void vop_initial(struct drm_crtc *crtc)
 917 {
 918         struct vop *vop = to_vop(crtc);
 919         int i;
 920
 921         vop_power_enable(crtc);
 922
 923         VOP_CTRL_SET(vop, global_regdone_en, 1);
 924         VOP_CTRL_SET(vop, dsp_blank, 0);
 925
 926         /*
 927          * restore the lut table.
 928          */
 929         if (vop->lut_active)
 930                 vop_crtc_load_lut(crtc);
 931
 932         /*
 933          * We need to make sure that all windows are disabled before resume
 934          * the crtc. Otherwise we might try to scan from a destroyed
 935          * buffer later.
 936          */
 937         for (i = 0; i < vop->num_wins; i++) {
 938                 struct vop_win *win = &vop->win[i];
 939                 int channel = i * 2 + 1;
 940
 941                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 942                 if (win->phy->scl && win->phy->scl->ext) {
 943                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 944                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 945                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 946                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 947                 }
 948                 VOP_WIN_SET(vop, win, enable, 0);
 949                 VOP_WIN_SET(vop, win, gate, 1);
 950         }
 951         VOP_CTRL_SET(vop, afbdc_en, 0);
 952 }
 953
 954 static void vop_crtc_disable(struct drm_crtc *crtc)
 955 {
 956         struct vop *vop = to_vop(crtc);
 957
 958         mutex_lock(&vop->vop_lock);
 959         drm_crtc_vblank_off(crtc);
 960
 961         /*
 962          * Vop standby will take effect at end of current frame,
 963          * if dsp hold valid irq happen, it means standby complete.
 964          *
 965          * we must wait standby complete when we want to disable aclk,
 966          * if not, memory bus maybe dead.
 967          */
 968         reinit_completion(&vop->dsp_hold_completion);
 969         vop_dsp_hold_valid_irq_enable(vop);
 970
 971         spin_lock(&vop->reg_lock);
 972
 973         VOP_CTRL_SET(vop, standby, 1);
 974
 975         spin_unlock(&vop->reg_lock);
 976
 977         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 978                                              msecs_to_jiffies(50)));
 979
 980         vop_dsp_hold_valid_irq_disable(vop);
 981
 982         disable_irq(vop->irq);
 983
 984         vop->is_enabled = false;
 985         if (vop->is_iommu_enabled) {
 986                 /*
 987                  * vop standby complete, so iommu detach is safe.
 988                  */
 989                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 990                 vop->is_iommu_enabled = false;
 991         }
 992
 993         pm_runtime_put(vop->dev);
 994         clk_disable_unprepare(vop->dclk);
 995         clk_disable_unprepare(vop->aclk);
 996         clk_disable_unprepare(vop->hclk);
 997         mutex_unlock(&vop->vop_lock);
 998 }
 999
1000 static void vop_plane_destroy(struct drm_plane *plane)
1001 {
1002         drm_plane_cleanup(plane);
1003 }
1004
1005 static int vop_plane_prepare_fb(struct drm_plane *plane,
1006                                 const struct drm_plane_state *new_state)
1007 {
1008         if (plane->state->fb)
1009                 drm_framebuffer_reference(plane->state->fb);
1010
1011         return 0;
1012 }
1013
1014 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1015                                  const struct drm_plane_state *old_state)
1016 {
1017         if (old_state->fb)
1018                 drm_framebuffer_unreference(old_state->fb);
1019 }
1020
1021 static int vop_plane_atomic_check(struct drm_plane *plane,
1022                            struct drm_plane_state *state)
1023 {
1024         struct drm_crtc *crtc = state->crtc;
1025         struct drm_framebuffer *fb = state->fb;
1026         struct vop_win *win = to_vop_win(plane);
1027         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1028         struct drm_crtc_state *crtc_state;
1029         const struct vop_data *vop_data;
1030         struct vop *vop;
1031         bool visible;
1032         int ret;
1033         struct drm_rect *dest = &vop_plane_state->dest;
1034         struct drm_rect *src = &vop_plane_state->src;
1035         struct drm_rect clip;
1036         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1037                                         DRM_PLANE_HELPER_NO_SCALING;
1038         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1039                                         DRM_PLANE_HELPER_NO_SCALING;
1040         unsigned long offset;
1041         dma_addr_t dma_addr;
1042         u16 vdisplay;
1043
1044         crtc = crtc ? crtc : plane->state->crtc;
1045         /*
1046          * Both crtc or plane->state->crtc can be null.
1047          */
1048         if (!crtc || !fb)
1049                 goto out_disable;
1050
1051         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1052         if (IS_ERR(crtc_state))
1053                 return PTR_ERR(crtc_state);
1054
1055         src->x1 = state->src_x;
1056         src->y1 = state->src_y;
1057         src->x2 = state->src_x + state->src_w;
1058         src->y2 = state->src_y + state->src_h;
1059         dest->x1 = state->crtc_x;
1060         dest->y1 = state->crtc_y;
1061         dest->x2 = state->crtc_x + state->crtc_w;
1062         dest->y2 = state->crtc_y + state->crtc_h;
1063
1064         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1065         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1066                 vdisplay *= 2;
1067
1068         clip.x1 = 0;
1069         clip.y1 = 0;
1070         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1071         clip.y2 = vdisplay;
1072
1073         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1074                                             src, dest, &clip,
1075                                             min_scale,
1076                                             max_scale,
1077                                             true, true, &visible);
1078         if (ret)
1079                 return ret;
1080
1081         if (!visible)
1082                 goto out_disable;
1083
1084         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1085         if (vop_plane_state->format < 0)
1086                 return vop_plane_state->format;
1087
1088         vop = to_vop(crtc);
1089         vop_data = vop->data;
1090
1091         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1092             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1093                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1094                           drm_rect_width(src) >> 16,
1095                           drm_rect_height(src) >> 16,
1096                           vop_data->max_input.width,
1097                           vop_data->max_input.height);
1098                 return -EINVAL;
1099         }
1100
1101         /*
1102          * Src.x1 can be odd when do clip, but yuv plane start point
1103          * need align with 2 pixel.
1104          */
1105         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1106                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1107                 return -EINVAL;
1108         }
1109
1110         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1111         if (state->rotation & BIT(DRM_REFLECT_Y))
1112                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1113         else
1114                 offset += (src->y1 >> 16) * fb->pitches[0];
1115
1116         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1117         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1118         if (is_yuv_support(fb->pixel_format)) {
1119                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1120                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1121                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1122
1123                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1124                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1125
1126                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1127                 dma_addr += offset + fb->offsets[1];
1128                 vop_plane_state->uv_mst = dma_addr;
1129         }
1130
1131         vop_plane_state->enable = true;
1132
1133         return 0;
1134
1135 out_disable:
1136         vop_plane_state->enable = false;
1137         return 0;
1138 }
1139
1140 static void vop_plane_atomic_disable(struct drm_plane *plane,
1141                                      struct drm_plane_state *old_state)
1142 {
1143         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1144         struct vop_win *win = to_vop_win(plane);
1145         struct vop *vop = to_vop(old_state->crtc);
1146
1147         if (!old_state->crtc)
1148                 return;
1149
1150         spin_lock(&vop->reg_lock);
1151
1152         /*
1153          * FIXUP: some of the vop scale would be abnormal after windows power
1154          * on/off so deinit scale to scale_none mode.
1155          */
1156         if (win->phy->scl && win->phy->scl->ext) {
1157                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1158                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1159                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1160                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1161         }
1162         VOP_WIN_SET(vop, win, enable, 0);
1163
1164         spin_unlock(&vop->reg_lock);
1165
1166         vop_plane_state->enable = false;
1167 }
1168
1169 static void vop_plane_atomic_update(struct drm_plane *plane,
1170                 struct drm_plane_state *old_state)
1171 {
1172         struct drm_plane_state *state = plane->state;
1173         struct drm_crtc *crtc = state->crtc;
1174         struct vop_win *win = to_vop_win(plane);
1175         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1176         struct rockchip_crtc_state *s;
1177         struct vop *vop;
1178         struct drm_framebuffer *fb = state->fb;
1179         unsigned int actual_w, actual_h;
1180         unsigned int dsp_stx, dsp_sty;
1181         uint32_t act_info, dsp_info, dsp_st;
1182         struct drm_rect *src = &vop_plane_state->src;
1183         struct drm_rect *dest = &vop_plane_state->dest;
1184         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1185         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1186         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1187         int ymirror, xmirror;
1188         uint32_t val;
1189         bool rb_swap;
1190
1191         /*
1192          * can't update plane when vop is disabled.
1193          */
1194         if (!crtc)
1195                 return;
1196
1197         if (!vop_plane_state->enable) {
1198                 vop_plane_atomic_disable(plane, old_state);
1199                 return;
1200         }
1201
1202         actual_w = drm_rect_width(src) >> 16;
1203         actual_h = drm_rect_height(src) >> 16;
1204         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1205
1206         dsp_info = (drm_rect_height(dest) - 1) << 16;
1207         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1208
1209         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1210         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1211         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1212
1213         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1214         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1215
1216         vop = to_vop(state->crtc);
1217         s = to_rockchip_crtc_state(crtc->state);
1218
1219         spin_lock(&vop->reg_lock);
1220
1221         VOP_WIN_SET(vop, win, xmirror, xmirror);
1222         VOP_WIN_SET(vop, win, ymirror, ymirror);
1223         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1224         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1225         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1226         if (is_yuv_support(fb->pixel_format)) {
1227                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1228                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1229         }
1230         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1231
1232         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1233                             drm_rect_width(dest), drm_rect_height(dest),
1234                             fb->pixel_format);
1235
1236         VOP_WIN_SET(vop, win, act_info, act_info);
1237         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1238         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1239
1240         rb_swap = has_rb_swapped(fb->pixel_format);
1241         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1242
1243         if (is_alpha_support(fb->pixel_format) &&
1244             (s->dsp_layer_sel & 0x3) != win->win_id) {
1245                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1246                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1247                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1248                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1249                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1250                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1251                         SRC_FACTOR_M0(ALPHA_ONE);
1252                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1253                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1254                 VOP_WIN_SET(vop, win, alpha_en, 1);
1255         } else {
1256                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1257                 VOP_WIN_SET(vop, win, alpha_en, 0);
1258         }
1259
1260         if (win->csc) {
1261                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1262                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1263                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1264                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1265                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1266                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1267         }
1268         VOP_WIN_SET(vop, win, enable, 1);
1269         spin_unlock(&vop->reg_lock);
1270         vop->is_iommu_needed = true;
1271 }
1272
1273 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1274         .prepare_fb = vop_plane_prepare_fb,
1275         .cleanup_fb = vop_plane_cleanup_fb,
1276         .atomic_check = vop_plane_atomic_check,
1277         .atomic_update = vop_plane_atomic_update,
1278         .atomic_disable = vop_plane_atomic_disable,
1279 };
1280
1281 void vop_atomic_plane_reset(struct drm_plane *plane)
1282 {
1283         struct vop_win *win = to_vop_win(plane);
1284         struct vop_plane_state *vop_plane_state =
1285                                         to_vop_plane_state(plane->state);
1286
1287         if (plane->state && plane->state->fb)
1288                 drm_framebuffer_unreference(plane->state->fb);
1289
1290         kfree(vop_plane_state);
1291         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1292         if (!vop_plane_state)
1293                 return;
1294
1295         vop_plane_state->zpos = win->win_id;
1296         plane->state = &vop_plane_state->base;
1297         plane->state->plane = plane;
1298 }
1299
1300 struct drm_plane_state *
1301 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1302 {
1303         struct vop_plane_state *old_vop_plane_state;
1304         struct vop_plane_state *vop_plane_state;
1305
1306         if (WARN_ON(!plane->state))
1307                 return NULL;
1308
1309         old_vop_plane_state = to_vop_plane_state(plane->state);
1310         vop_plane_state = kmemdup(old_vop_plane_state,
1311                                   sizeof(*vop_plane_state), GFP_KERNEL);
1312         if (!vop_plane_state)
1313                 return NULL;
1314
1315         __drm_atomic_helper_plane_duplicate_state(plane,
1316                                                   &vop_plane_state->base);
1317
1318         return &vop_plane_state->base;
1319 }
1320
1321 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1322                                            struct drm_plane_state *state)
1323 {
1324         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1325
1326         __drm_atomic_helper_plane_destroy_state(plane, state);
1327
1328         kfree(vop_state);
1329 }
1330
1331 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1332                                          struct drm_plane_state *state,
1333                                          struct drm_property *property,
1334                                          uint64_t val)
1335 {
1336         struct vop_win *win = to_vop_win(plane);
1337         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1338
1339         if (property == win->vop->plane_zpos_prop) {
1340                 plane_state->zpos = val;
1341                 return 0;
1342         }
1343
1344         if (property == win->rotation_prop) {
1345                 state->rotation = val;
1346                 return 0;
1347         }
1348
1349         DRM_ERROR("failed to set vop plane property\n");
1350         return -EINVAL;
1351 }
1352
1353 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1354                                          const struct drm_plane_state *state,
1355                                          struct drm_property *property,
1356                                          uint64_t *val)
1357 {
1358         struct vop_win *win = to_vop_win(plane);
1359         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1360
1361         if (property == win->vop->plane_zpos_prop) {
1362                 *val = plane_state->zpos;
1363                 return 0;
1364         }
1365
1366         if (property == win->rotation_prop) {
1367                 *val = state->rotation;
1368                 return 0;
1369         }
1370
1371         DRM_ERROR("failed to get vop plane property\n");
1372         return -EINVAL;
1373 }
1374
1375 static const struct drm_plane_funcs vop_plane_funcs = {
1376         .update_plane   = drm_atomic_helper_update_plane,
1377         .disable_plane  = drm_atomic_helper_disable_plane,
1378         .destroy = vop_plane_destroy,
1379         .reset = vop_atomic_plane_reset,
1380         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1381         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1382         .atomic_set_property = vop_atomic_plane_set_property,
1383         .atomic_get_property = vop_atomic_plane_get_property,
1384 };
1385
1386 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1387 {
1388         struct vop *vop = to_vop(crtc);
1389         unsigned long flags;
1390
1391         if (!vop->is_enabled)
1392                 return -EPERM;
1393
1394         spin_lock_irqsave(&vop->irq_lock, flags);
1395
1396         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1397         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1398
1399         spin_unlock_irqrestore(&vop->irq_lock, flags);
1400
1401         return 0;
1402 }
1403
1404 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1405 {
1406         struct vop *vop = to_vop(crtc);
1407         unsigned long flags;
1408
1409         if (!vop->is_enabled)
1410                 return;
1411
1412         spin_lock_irqsave(&vop->irq_lock, flags);
1413
1414         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1415
1416         spin_unlock_irqrestore(&vop->irq_lock, flags);
1417 }
1418
1419 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1420 {
1421         struct vop *vop = to_vop(crtc);
1422
1423         reinit_completion(&vop->wait_update_complete);
1424         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete,
1425                                              msecs_to_jiffies(1000)));
1426 }
1427
1428 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1429                                            struct drm_file *file_priv)
1430 {
1431         struct drm_device *drm = crtc->dev;
1432         struct vop *vop = to_vop(crtc);
1433         struct drm_pending_vblank_event *e;
1434         unsigned long flags;
1435
1436         spin_lock_irqsave(&drm->event_lock, flags);
1437         e = vop->event;
1438         if (e && e->base.file_priv == file_priv) {
1439                 vop->event = NULL;
1440
1441                 e->base.destroy(&e->base);
1442                 file_priv->event_space += sizeof(e->event);
1443         }
1444         spin_unlock_irqrestore(&drm->event_lock, flags);
1445 }
1446
1447 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1448 {
1449         struct vop *vop = to_vop(crtc);
1450
1451         if (on == vop->loader_protect)
1452                 return 0;
1453
1454         if (on) {
1455                 vop_power_enable(crtc);
1456                 enable_irq(vop->irq);
1457                 drm_crtc_vblank_on(crtc);
1458                 vop->loader_protect = true;
1459         } else {
1460                 vop_crtc_disable(crtc);
1461
1462                 vop->loader_protect = false;
1463         }
1464
1465         return 0;
1466 }
1467
1468 #define DEBUG_PRINT(args...) \
1469                 do { \
1470                         if (s) \
1471                                 seq_printf(s, args); \
1472                         else \
1473                                 printk(args); \
1474                 } while (0)
1475
1476 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1477 {
1478         struct vop_win *win = to_vop_win(plane);
1479         struct drm_plane_state *state = plane->state;
1480         struct vop_plane_state *pstate = to_vop_plane_state(state);
1481         struct drm_rect *src, *dest;
1482         struct drm_framebuffer *fb = state->fb;
1483         int i;
1484
1485         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1486                     pstate->enable ? "ACTIVE" : "DISABLED");
1487         if (!fb)
1488                 return 0;
1489
1490         src = &pstate->src;
1491         dest = &pstate->dest;
1492
1493         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1494                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1495         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1496         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1497                     src->y1 >> 16, drm_rect_width(src) >> 16,
1498                     drm_rect_height(src) >> 16);
1499         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1500                     drm_rect_width(dest), drm_rect_height(dest));
1501
1502         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1503                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1504                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1505                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1506         }
1507
1508         return 0;
1509 }
1510
1511 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1512 {
1513         struct vop *vop = to_vop(crtc);
1514         struct drm_crtc_state *crtc_state = crtc->state;
1515         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1516         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1517         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1518         struct drm_plane *plane;
1519         int i;
1520
1521         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1522                     crtc_state->active ? "ACTIVE" : "DISABLED");
1523
1524         if (!crtc_state->active)
1525                 return 0;
1526
1527         DEBUG_PRINT("    Connector: %s\n",
1528                     drm_get_connector_name(state->output_type));
1529         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1530                     state->bus_format, state->output_mode);
1531         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1532                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1533                     drm_mode_vrefresh(mode));
1534         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1535                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1536         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1537                     mode->hsync_end, mode->htotal);
1538         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1539                     mode->vsync_end, mode->vtotal);
1540
1541         for (i = 0; i < vop->num_wins; i++) {
1542                 plane = &vop->win[i].base;
1543                 vop_plane_info_dump(s, plane);
1544         }
1545
1546         return 0;
1547 }
1548
1549 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1550 {
1551         struct vop *vop = to_vop(crtc);
1552         struct drm_crtc_state *crtc_state = crtc->state;
1553         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1554         int i;
1555
1556         if (!crtc_state->active)
1557                 return;
1558
1559         for (i = 0; i < dump_len; i += 4) {
1560                 if (i % 16 == 0)
1561                         DEBUG_PRINT("\n0x%08x: ", i);
1562                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1563         }
1564 }
1565
1566 #undef DEBUG_PRINT
1567
1568 static enum drm_mode_status
1569 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1570                     int output_type)
1571 {
1572         struct vop *vop = to_vop(crtc);
1573         const struct vop_data *vop_data = vop->data;
1574         int request_clock = mode->clock;
1575         int clock;
1576
1577         if (mode->hdisplay > vop_data->max_output.width)
1578                 return MODE_BAD_HVALUE;
1579         if (mode->vdisplay > vop_data->max_output.height)
1580                 return MODE_BAD_VVALUE;
1581
1582         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1583                 request_clock *= 2;
1584         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1585
1586         /*
1587          * Hdmi or DisplayPort request a Accurate clock.
1588          */
1589         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1590             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1591                 if (clock != request_clock)
1592                         return MODE_CLOCK_RANGE;
1593
1594         return MODE_OK;
1595 }
1596
1597 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1598         .loader_protect = vop_crtc_loader_protect,
1599         .enable_vblank = vop_crtc_enable_vblank,
1600         .disable_vblank = vop_crtc_disable_vblank,
1601         .wait_for_update = vop_crtc_wait_for_update,
1602         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1603         .debugfs_dump = vop_crtc_debugfs_dump,
1604         .regs_dump = vop_crtc_regs_dump,
1605         .mode_valid = vop_crtc_mode_valid,
1606 };
1607
1608 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1609                                 const struct drm_display_mode *mode,
1610                                 struct drm_display_mode *adj_mode)
1611 {
1612         struct vop *vop = to_vop(crtc);
1613         const struct vop_data *vop_data = vop->data;
1614
1615         if (mode->hdisplay > vop_data->max_output.width ||
1616             mode->vdisplay > vop_data->max_output.height)
1617                 return false;
1618
1619         drm_mode_set_crtcinfo(adj_mode,
1620                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1621
1622         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1623                 adj_mode->crtc_clock *= 2;
1624
1625         adj_mode->crtc_clock =
1626                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1627
1628         return true;
1629 }
1630
1631 static void vop_crtc_enable(struct drm_crtc *crtc)
1632 {
1633         struct vop *vop = to_vop(crtc);
1634         const struct vop_data *vop_data = vop->data;
1635         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1636         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1637         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1638         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1639         u16 htotal = adjusted_mode->crtc_htotal;
1640         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1641         u16 hact_end = hact_st + hdisplay;
1642         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1643         u16 vtotal = adjusted_mode->crtc_vtotal;
1644         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1645         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1646         u16 vact_end = vact_st + vdisplay;
1647         uint32_t val;
1648
1649         mutex_lock(&vop->vop_lock);
1650         vop_initial(crtc);
1651
1652         val = BIT(DCLK_INVERT);
1653         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1654                    0 : BIT(HSYNC_POSITIVE);
1655         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1656                    0 : BIT(VSYNC_POSITIVE);
1657         VOP_CTRL_SET(vop, pin_pol, val);
1658         switch (s->output_type) {
1659         case DRM_MODE_CONNECTOR_LVDS:
1660                 VOP_CTRL_SET(vop, rgb_en, 1);
1661                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1662                 break;
1663         case DRM_MODE_CONNECTOR_eDP:
1664                 VOP_CTRL_SET(vop, edp_en, 1);
1665                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1666                 break;
1667         case DRM_MODE_CONNECTOR_HDMIA:
1668                 VOP_CTRL_SET(vop, hdmi_en, 1);
1669                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1670                 break;
1671         case DRM_MODE_CONNECTOR_DSI:
1672                 VOP_CTRL_SET(vop, mipi_en, 1);
1673                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1674                 break;
1675         case DRM_MODE_CONNECTOR_DisplayPort:
1676                 val &= ~BIT(DCLK_INVERT);
1677                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1678                 VOP_CTRL_SET(vop, dp_en, 1);
1679                 break;
1680         default:
1681                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1682         }
1683
1684         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1685             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1686                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1687
1688         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1689         switch (s->bus_format) {
1690         case MEDIA_BUS_FMT_RGB565_1X16:
1691                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1692                 break;
1693         case MEDIA_BUS_FMT_RGB666_1X18:
1694         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1695                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1696                 break;
1697         case MEDIA_BUS_FMT_YUV8_1X24:
1698                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1699                 break;
1700         case MEDIA_BUS_FMT_YUV10_1X30:
1701                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1702                 break;
1703         case MEDIA_BUS_FMT_RGB888_1X24:
1704         default:
1705                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1706                 break;
1707         }
1708
1709         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1710                 val |= PRE_DITHER_DOWN_EN(0);
1711         else
1712                 val |= PRE_DITHER_DOWN_EN(1);
1713         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1714         VOP_CTRL_SET(vop, dither_down, val);
1715         VOP_CTRL_SET(vop, dclk_ddr,
1716                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1717         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1718         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1719         VOP_CTRL_SET(vop, dsp_background,
1720                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1721
1722         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1723         val = hact_st << 16;
1724         val |= hact_end;
1725         VOP_CTRL_SET(vop, hact_st_end, val);
1726         VOP_CTRL_SET(vop, hpost_st_end, val);
1727
1728         val = vact_st << 16;
1729         val |= vact_end;
1730         VOP_CTRL_SET(vop, vact_st_end, val);
1731         VOP_CTRL_SET(vop, vpost_st_end, val);
1732
1733         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1734         VOP_INTR_SET(vop, line_flag_num[1],
1735                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1736         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1737                 u16 vact_st_f1 = vtotal + vact_st + 1;
1738                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1739
1740                 val = vact_st_f1 << 16 | vact_end_f1;
1741                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1742                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1743
1744                 val = vtotal << 16 | (vtotal + vsync_len);
1745                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1746                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1747                 VOP_CTRL_SET(vop, p2i_en, 1);
1748                 vtotal += vtotal + 1;
1749         } else {
1750                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1751                 VOP_CTRL_SET(vop, p2i_en, 0);
1752         }
1753         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1754
1755         VOP_CTRL_SET(vop, core_dclk_div,
1756                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1757
1758         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1759
1760         vop_cfg_done(vop);
1761         /*
1762          * enable vop, all the register would take effect when vop exit standby
1763          */
1764         VOP_CTRL_SET(vop, standby, 0);
1765
1766         enable_irq(vop->irq);
1767         drm_crtc_vblank_on(crtc);
1768         mutex_unlock(&vop->vop_lock);
1769 }
1770
1771 static int vop_zpos_cmp(const void *a, const void *b)
1772 {
1773         struct vop_zpos *pa = (struct vop_zpos *)a;
1774         struct vop_zpos *pb = (struct vop_zpos *)b;
1775
1776         return pa->zpos - pb->zpos;
1777 }
1778
1779 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1780                                   struct drm_crtc_state *crtc_state)
1781 {
1782         struct vop *vop = to_vop(crtc);
1783         const struct vop_data *vop_data = vop->data;
1784         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1785         struct drm_atomic_state *state = crtc_state->state;
1786         struct drm_plane *plane;
1787         struct drm_plane_state *pstate;
1788         struct vop_plane_state *plane_state;
1789         struct vop_win *win;
1790         int afbdc_format;
1791         int i;
1792
1793         s->afbdc_en = 0;
1794
1795         for_each_plane_in_state(state, plane, pstate, i) {
1796                 struct drm_framebuffer *fb = pstate->fb;
1797                 struct drm_rect *src;
1798
1799                 win = to_vop_win(plane);
1800                 plane_state = to_vop_plane_state(pstate);
1801
1802                 if (pstate->crtc != crtc || !fb)
1803                         continue;
1804
1805                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1806                         continue;
1807
1808                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1809                         DRM_ERROR("not support afbdc\n");
1810                         return -EINVAL;
1811                 }
1812
1813                 switch (plane_state->format) {
1814                 case VOP_FMT_ARGB8888:
1815                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1816                         break;
1817                 case VOP_FMT_RGB888:
1818                         afbdc_format = AFBDC_FMT_U8U8U8;
1819                         break;
1820                 case VOP_FMT_RGB565:
1821                         afbdc_format = AFBDC_FMT_RGB565;
1822                         break;
1823                 default:
1824                         return -EINVAL;
1825                 }
1826
1827                 if (s->afbdc_en) {
1828                         DRM_ERROR("vop only support one afbc layer\n");
1829                         return -EINVAL;
1830                 }
1831
1832                 src = &plane_state->src;
1833                 if (src->x1 || src->y1 || fb->offsets[0]) {
1834                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1835                                   win->win_id);
1836                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1837                                   src->x1, src->y1, fb->offsets[0]);
1838                         return -EINVAL;
1839                 }
1840                 s->afbdc_win_format = afbdc_format;
1841                 s->afbdc_win_width = pstate->fb->width - 1;
1842                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1843                 s->afbdc_win_id = win->win_id;
1844                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1845                 s->afbdc_en = 1;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1852                                  struct drm_crtc_state *crtc_state)
1853 {
1854         struct drm_atomic_state *state = crtc_state->state;
1855         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1856         struct vop *vop = to_vop(crtc);
1857         const struct vop_data *vop_data = vop->data;
1858         struct drm_plane *plane;
1859         struct drm_plane_state *pstate;
1860         struct vop_plane_state *plane_state;
1861         struct vop_zpos *pzpos;
1862         int dsp_layer_sel = 0;
1863         int i, j, cnt = 0, ret = 0;
1864
1865         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1866         if (ret)
1867                 return ret;
1868
1869         ret = vop_csc_atomic_check(crtc, crtc_state);
1870         if (ret)
1871                 return ret;
1872
1873         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1874         if (!pzpos)
1875                 return -ENOMEM;
1876
1877         for (i = 0; i < vop_data->win_size; i++) {
1878                 const struct vop_win_data *win_data = &vop_data->win[i];
1879                 struct vop_win *win;
1880
1881                 if (!win_data->phy)
1882                         continue;
1883
1884                 for (j = 0; j < vop->num_wins; j++) {
1885                         win = &vop->win[j];
1886
1887                         if (win->win_id == i && !win->area_id)
1888                                 break;
1889                 }
1890                 if (WARN_ON(j >= vop->num_wins)) {
1891                         ret = -EINVAL;
1892                         goto err_free_pzpos;
1893                 }
1894
1895                 plane = &win->base;
1896                 pstate = state->plane_states[drm_plane_index(plane)];
1897                 /*
1898                  * plane might not have changed, in which case take
1899                  * current state:
1900                  */
1901                 if (!pstate)
1902                         pstate = plane->state;
1903                 plane_state = to_vop_plane_state(pstate);
1904                 pzpos[cnt].zpos = plane_state->zpos;
1905                 pzpos[cnt++].win_id = win->win_id;
1906         }
1907
1908         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1909
1910         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1911                 const struct vop_win_data *win_data = &vop_data->win[i];
1912                 int shift = i * 2;
1913
1914                 if (win_data->phy) {
1915                         struct vop_zpos *zpos = &pzpos[cnt++];
1916
1917                         dsp_layer_sel |= zpos->win_id << shift;
1918                 } else {
1919                         dsp_layer_sel |= i << shift;
1920                 }
1921         }
1922
1923         s->dsp_layer_sel = dsp_layer_sel;
1924
1925 err_free_pzpos:
1926         kfree(pzpos);
1927         return ret;
1928 }
1929
1930 static void vop_post_config(struct drm_crtc *crtc)
1931 {
1932         struct vop *vop = to_vop(crtc);
1933         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1934         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1935         u16 vtotal = mode->crtc_vtotal;
1936         u16 hdisplay = mode->crtc_hdisplay;
1937         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1938         u16 vdisplay = mode->crtc_vdisplay;
1939         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1940         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1941         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1942         u16 hact_end, vact_end;
1943         u32 val;
1944
1945         hact_st += hdisplay * (100 - s->left_margin) / 200;
1946         hact_end = hact_st + hsize;
1947         val = hact_st << 16;
1948         val |= hact_end;
1949         VOP_CTRL_SET(vop, hpost_st_end, val);
1950         vact_st += vdisplay * (100 - s->top_margin) / 200;
1951         vact_end = vact_st + vsize;
1952         val = vact_st << 16;
1953         val |= vact_end;
1954         VOP_CTRL_SET(vop, vpost_st_end, val);
1955         val = scl_cal_scale2(vdisplay, vsize) << 16;
1956         val |= scl_cal_scale2(hdisplay, hsize);
1957         VOP_CTRL_SET(vop, post_scl_factor, val);
1958         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1959         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1960                 u16 vact_st_f1 = vtotal + vact_st + 1;
1961                 u16 vact_end_f1 = vact_st_f1 + vsize;
1962
1963                 val = vact_st_f1 << 16 | vact_end_f1;
1964                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1965         }
1966 }
1967
1968 static void vop_cfg_update(struct drm_crtc *crtc,
1969                            struct drm_crtc_state *old_crtc_state)
1970 {
1971         struct rockchip_crtc_state *s =
1972                         to_rockchip_crtc_state(crtc->state);
1973         struct vop *vop = to_vop(crtc);
1974
1975         spin_lock(&vop->reg_lock);
1976
1977         if (s->afbdc_en) {
1978                 uint32_t pic_size;
1979
1980                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1981                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1982                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1983                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1984                 pic_size = (s->afbdc_win_width & 0xffff);
1985                 pic_size |= s->afbdc_win_height << 16;
1986                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1987         }
1988
1989         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1990         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1991         vop_post_config(crtc);
1992
1993         spin_unlock(&vop->reg_lock);
1994 }
1995
1996 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1997                                   struct drm_crtc_state *old_crtc_state)
1998 {
1999         struct vop *vop = to_vop(crtc);
2000
2001         vop_cfg_update(crtc, old_crtc_state);
2002
2003         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2004                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2005                 int ret;
2006
2007                 if (need_wait_vblank) {
2008                         bool active;
2009
2010                         disable_irq(vop->irq);
2011                         drm_crtc_vblank_get(crtc);
2012                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2013
2014                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2015                                                         vop, active, active,
2016                                                         0, 50 * 1000);
2017                         if (ret)
2018                                 dev_err(vop->dev, "wait fs irq timeout\n");
2019
2020                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2021                         vop_cfg_done(vop);
2022
2023                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2024                                                         vop, active, active,
2025                                                         0, 50 * 1000);
2026                         if (ret)
2027                                 dev_err(vop->dev, "wait line flag timeout\n");
2028
2029                         enable_irq(vop->irq);
2030                 }
2031                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2032                 if (ret)
2033                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2034                                 ret);
2035
2036                 if (need_wait_vblank) {
2037                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2038                         drm_crtc_vblank_put(crtc);
2039                 }
2040
2041                 vop->is_iommu_enabled = true;
2042         }
2043
2044         vop_cfg_done(vop);
2045 }
2046
2047 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2048                                   struct drm_crtc_state *old_crtc_state)
2049 {
2050         struct vop *vop = to_vop(crtc);
2051
2052         if (crtc->state->event) {
2053                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2054
2055                 vop->event = crtc->state->event;
2056                 crtc->state->event = NULL;
2057         }
2058 }
2059
2060 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2061         .load_lut = vop_crtc_load_lut,
2062         .enable = vop_crtc_enable,
2063         .disable = vop_crtc_disable,
2064         .mode_fixup = vop_crtc_mode_fixup,
2065         .atomic_check = vop_crtc_atomic_check,
2066         .atomic_flush = vop_crtc_atomic_flush,
2067         .atomic_begin = vop_crtc_atomic_begin,
2068 };
2069
2070 static void vop_crtc_destroy(struct drm_crtc *crtc)
2071 {
2072         drm_crtc_cleanup(crtc);
2073 }
2074
2075 static void vop_crtc_reset(struct drm_crtc *crtc)
2076 {
2077         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2078
2079         if (crtc->state) {
2080                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2081                 kfree(s);
2082         }
2083
2084         s = kzalloc(sizeof(*s), GFP_KERNEL);
2085         if (!s)
2086                 return;
2087         crtc->state = &s->base;
2088         crtc->state->crtc = crtc;
2089         s->left_margin = 100;
2090         s->right_margin = 100;
2091         s->top_margin = 100;
2092         s->bottom_margin = 100;
2093 }
2094
2095 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2096 {
2097         struct rockchip_crtc_state *rockchip_state, *old_state;
2098
2099         old_state = to_rockchip_crtc_state(crtc->state);
2100         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2101         if (!rockchip_state)
2102                 return NULL;
2103
2104         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2105         return &rockchip_state->base;
2106 }
2107
2108 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2109                                    struct drm_crtc_state *state)
2110 {
2111         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2112
2113         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2114         kfree(s);
2115 }
2116
2117 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2118                                         const struct drm_crtc_state *state,
2119                                         struct drm_property *property,
2120                                         uint64_t *val)
2121 {
2122         struct drm_device *drm_dev = crtc->dev;
2123         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2124         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2125
2126         if (property == mode_config->tv_left_margin_property) {
2127                 *val = s->left_margin;
2128                 return 0;
2129         }
2130
2131         if (property == mode_config->tv_right_margin_property) {
2132                 *val = s->right_margin;
2133                 return 0;
2134         }
2135
2136         if (property == mode_config->tv_top_margin_property) {
2137                 *val = s->top_margin;
2138                 return 0;
2139         }
2140
2141         if (property == mode_config->tv_bottom_margin_property) {
2142                 *val = s->bottom_margin;
2143                 return 0;
2144         }
2145
2146         DRM_ERROR("failed to get vop crtc property\n");
2147         return -EINVAL;
2148 }
2149
2150 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2151                                         struct drm_crtc_state *state,
2152                                         struct drm_property *property,
2153                                         uint64_t val)
2154 {
2155         struct drm_device *drm_dev = crtc->dev;
2156         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2157         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2158
2159         if (property == mode_config->tv_left_margin_property) {
2160                 s->left_margin = val;
2161                 return 0;
2162         }
2163
2164         if (property == mode_config->tv_right_margin_property) {
2165                 s->right_margin = val;
2166                 return 0;
2167         }
2168
2169         if (property == mode_config->tv_top_margin_property) {
2170                 s->top_margin = val;
2171                 return 0;
2172         }
2173
2174         if (property == mode_config->tv_bottom_margin_property) {
2175                 s->bottom_margin = val;
2176                 return 0;
2177         }
2178
2179         DRM_ERROR("failed to set vop crtc property\n");
2180         return -EINVAL;
2181 }
2182
2183 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2184                                u16 *blue, uint32_t start, uint32_t size)
2185 {
2186         struct vop *vop = to_vop(crtc);
2187         int end = min_t(u32, start + size, vop->lut_len);
2188         int i;
2189
2190         if (!vop->lut)
2191                 return;
2192
2193         for (i = start; i < end; i++)
2194                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2195                                                blue[i], i);
2196
2197         vop_crtc_load_lut(crtc);
2198 }
2199
2200 static const struct drm_crtc_funcs vop_crtc_funcs = {
2201         .gamma_set = vop_crtc_gamma_set,
2202         .set_config = drm_atomic_helper_set_config,
2203         .page_flip = drm_atomic_helper_page_flip,
2204         .destroy = vop_crtc_destroy,
2205         .reset = vop_crtc_reset,
2206         .atomic_get_property = vop_crtc_atomic_get_property,
2207         .atomic_set_property = vop_crtc_atomic_set_property,
2208         .atomic_duplicate_state = vop_crtc_duplicate_state,
2209         .atomic_destroy_state = vop_crtc_destroy_state,
2210 };
2211
2212 static void vop_handle_vblank(struct vop *vop)
2213 {
2214         struct drm_device *drm = vop->drm_dev;
2215         struct drm_crtc *crtc = &vop->crtc;
2216         unsigned long flags;
2217
2218         if (!vop_is_cfg_done_complete(vop))
2219                 return;
2220
2221         if (vop->event) {
2222                 spin_lock_irqsave(&drm->event_lock, flags);
2223
2224                 drm_crtc_send_vblank_event(crtc, vop->event);
2225                 drm_crtc_vblank_put(crtc);
2226                 vop->event = NULL;
2227
2228                 spin_unlock_irqrestore(&drm->event_lock, flags);
2229         }
2230         if (!completion_done(&vop->wait_update_complete))
2231                 complete(&vop->wait_update_complete);
2232 }
2233
2234 static irqreturn_t vop_isr(int irq, void *data)
2235 {
2236         struct vop *vop = data;
2237         struct drm_crtc *crtc = &vop->crtc;
2238         uint32_t active_irqs;
2239         unsigned long flags;
2240         int ret = IRQ_NONE;
2241
2242         /*
2243          * interrupt register has interrupt status, enable and clear bits, we
2244          * must hold irq_lock to avoid a race with enable/disable_vblank().
2245         */
2246         spin_lock_irqsave(&vop->irq_lock, flags);
2247
2248         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2249         /* Clear all active interrupt sources */
2250         if (active_irqs)
2251                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2252
2253         spin_unlock_irqrestore(&vop->irq_lock, flags);
2254
2255         /* This is expected for vop iommu irqs, since the irq is shared */
2256         if (!active_irqs)
2257                 return IRQ_NONE;
2258
2259         if (active_irqs & DSP_HOLD_VALID_INTR) {
2260                 complete(&vop->dsp_hold_completion);
2261                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2262                 ret = IRQ_HANDLED;
2263         }
2264
2265         if (active_irqs & LINE_FLAG_INTR) {
2266                 complete(&vop->line_flag_completion);
2267                 active_irqs &= ~LINE_FLAG_INTR;
2268                 ret = IRQ_HANDLED;
2269         }
2270
2271         if (active_irqs & FS_INTR) {
2272                 drm_crtc_handle_vblank(crtc);
2273                 vop_handle_vblank(vop);
2274                 active_irqs &= ~FS_INTR;
2275                 ret = IRQ_HANDLED;
2276         }
2277
2278         /* Unhandled irqs are spurious. */
2279         if (active_irqs)
2280                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2281
2282         return ret;
2283 }
2284
2285 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2286                           unsigned long possible_crtcs)
2287 {
2288         struct drm_plane *share = NULL;
2289         unsigned int rotations = 0;
2290         struct drm_property *prop;
2291         uint64_t feature = 0;
2292         int ret;
2293
2294         if (win->parent)
2295                 share = &win->parent->base;
2296
2297         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2298                                    possible_crtcs, &vop_plane_funcs,
2299                                    win->data_formats, win->nformats, win->type);
2300         if (ret) {
2301                 DRM_ERROR("failed to initialize plane\n");
2302                 return ret;
2303         }
2304         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2305         drm_object_attach_property(&win->base.base,
2306                                    vop->plane_zpos_prop, win->win_id);
2307
2308         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2309                 rotations |= BIT(DRM_REFLECT_X);
2310
2311         if (VOP_WIN_SUPPORT(vop, win, ymirror))
2312                 rotations |= BIT(DRM_REFLECT_Y);
2313
2314         if (rotations) {
2315                 rotations |= BIT(DRM_ROTATE_0);
2316                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2317                                                          rotations);
2318                 if (!prop) {
2319                         DRM_ERROR("failed to create zpos property\n");
2320                         return -EINVAL;
2321                 }
2322                 drm_object_attach_property(&win->base.base, prop,
2323                                            BIT(DRM_ROTATE_0));
2324                 win->rotation_prop = prop;
2325         }
2326         if (win->phy->scl)
2327                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2328         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2329             VOP_WIN_SUPPORT(vop, win, alpha_en))
2330                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2331
2332         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2333                                    feature);
2334
2335         return 0;
2336 }
2337
2338 static int vop_create_crtc(struct vop *vop)
2339 {
2340         struct device *dev = vop->dev;
2341         const struct vop_data *vop_data = vop->data;
2342         struct drm_device *drm_dev = vop->drm_dev;
2343         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2344         struct drm_crtc *crtc = &vop->crtc;
2345         struct device_node *port;
2346         uint64_t feature = 0;
2347         int ret;
2348         int i;
2349
2350         /*
2351          * Create drm_plane for primary and cursor planes first, since we need
2352          * to pass them to drm_crtc_init_with_planes, which sets the
2353          * "possible_crtcs" to the newly initialized crtc.
2354          */
2355         for (i = 0; i < vop->num_wins; i++) {
2356                 struct vop_win *win = &vop->win[i];
2357
2358                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2359                     win->type != DRM_PLANE_TYPE_CURSOR)
2360                         continue;
2361
2362                 ret = vop_plane_init(vop, win, 0);
2363                 if (ret)
2364                         goto err_cleanup_planes;
2365
2366                 plane = &win->base;
2367                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2368                         primary = plane;
2369                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2370                         cursor = plane;
2371
2372         }
2373
2374         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2375                                         &vop_crtc_funcs, NULL);
2376         if (ret)
2377                 goto err_cleanup_planes;
2378
2379         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2380
2381         /*
2382          * Create drm_planes for overlay windows with possible_crtcs restricted
2383          * to the newly created crtc.
2384          */
2385         for (i = 0; i < vop->num_wins; i++) {
2386                 struct vop_win *win = &vop->win[i];
2387                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2388
2389                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2390                         continue;
2391
2392                 ret = vop_plane_init(vop, win, possible_crtcs);
2393                 if (ret)
2394                         goto err_cleanup_crtc;
2395         }
2396
2397         port = of_get_child_by_name(dev->of_node, "port");
2398         if (!port) {
2399                 DRM_ERROR("no port node found in %s\n",
2400                           dev->of_node->full_name);
2401                 ret = -ENOENT;
2402                 goto err_cleanup_crtc;
2403         }
2404
2405         init_completion(&vop->dsp_hold_completion);
2406         init_completion(&vop->wait_update_complete);
2407         init_completion(&vop->line_flag_completion);
2408         crtc->port = port;
2409         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2410
2411         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2412         if (ret)
2413                 goto err_unregister_crtc_funcs;
2414 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2415         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2416
2417         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2418         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2419         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2420         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2421 #undef VOP_ATTACH_MODE_CONFIG_PROP
2422
2423         if (vop_data->feature & VOP_FEATURE_AFBDC)
2424                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2425         drm_object_attach_property(&crtc->base, vop->feature_prop,
2426                                    feature);
2427         if (vop->lut_regs) {
2428                 u16 *r_base, *g_base, *b_base;
2429                 u32 lut_len = vop->lut_len;
2430
2431                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2432                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2433                                               GFP_KERNEL);
2434                 if (!vop->lut)
2435                         return -ENOMEM;
2436
2437                 r_base = crtc->gamma_store;
2438                 g_base = r_base + crtc->gamma_size;
2439                 b_base = g_base + crtc->gamma_size;
2440
2441                 for (i = 0; i < lut_len; i++) {
2442                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2443                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2444                                                        &g_base[i], &b_base[i],
2445                                                        i);
2446                 }
2447         }
2448
2449         return 0;
2450
2451 err_unregister_crtc_funcs:
2452         rockchip_unregister_crtc_funcs(crtc);
2453 err_cleanup_crtc:
2454         drm_crtc_cleanup(crtc);
2455 err_cleanup_planes:
2456         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2457                                  head)
2458                 drm_plane_cleanup(plane);
2459         return ret;
2460 }
2461
2462 static void vop_destroy_crtc(struct vop *vop)
2463 {
2464         struct drm_crtc *crtc = &vop->crtc;
2465         struct drm_device *drm_dev = vop->drm_dev;
2466         struct drm_plane *plane, *tmp;
2467
2468         rockchip_unregister_crtc_funcs(crtc);
2469         of_node_put(crtc->port);
2470
2471         /*
2472          * We need to cleanup the planes now.  Why?
2473          *
2474          * The planes are "&vop->win[i].base".  That means the memory is
2475          * all part of the big "struct vop" chunk of memory.  That memory
2476          * was devm allocated and associated with this component.  We need to
2477          * free it ourselves before vop_unbind() finishes.
2478          */
2479         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2480                                  head)
2481                 vop_plane_destroy(plane);
2482
2483         /*
2484          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2485          * references the CRTC.
2486          */
2487         drm_crtc_cleanup(crtc);
2488 }
2489
2490 /*
2491  * Initialize the vop->win array elements.
2492  */
2493 static int vop_win_init(struct vop *vop)
2494 {
2495         const struct vop_data *vop_data = vop->data;
2496         unsigned int i, j;
2497         unsigned int num_wins = 0;
2498         struct drm_property *prop;
2499         static const struct drm_prop_enum_list props[] = {
2500                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2501                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2502         };
2503         static const struct drm_prop_enum_list crtc_props[] = {
2504                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2505         };
2506
2507         for (i = 0; i < vop_data->win_size; i++) {
2508                 struct vop_win *vop_win = &vop->win[num_wins];
2509                 const struct vop_win_data *win_data = &vop_data->win[i];
2510
2511                 if (!win_data->phy)
2512                         continue;
2513
2514                 vop_win->phy = win_data->phy;
2515                 vop_win->csc = win_data->csc;
2516                 vop_win->offset = win_data->base;
2517                 vop_win->type = win_data->type;
2518                 vop_win->data_formats = win_data->phy->data_formats;
2519                 vop_win->nformats = win_data->phy->nformats;
2520                 vop_win->vop = vop;
2521                 vop_win->win_id = i;
2522                 vop_win->area_id = 0;
2523                 num_wins++;
2524
2525                 for (j = 0; j < win_data->area_size; j++) {
2526                         struct vop_win *vop_area = &vop->win[num_wins];
2527                         const struct vop_win_phy *area = win_data->area[j];
2528
2529                         vop_area->parent = vop_win;
2530                         vop_area->offset = vop_win->offset;
2531                         vop_area->phy = area;
2532                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2533                         vop_area->data_formats = vop_win->data_formats;
2534                         vop_area->nformats = vop_win->nformats;
2535                         vop_area->vop = vop;
2536                         vop_area->win_id = i;
2537                         vop_area->area_id = j;
2538                         num_wins++;
2539                 }
2540         }
2541
2542         vop->num_wins = num_wins;
2543
2544         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2545                                          "ZPOS", 0, vop->data->win_size);
2546         if (!prop) {
2547                 DRM_ERROR("failed to create zpos property\n");
2548                 return -EINVAL;
2549         }
2550         vop->plane_zpos_prop = prop;
2551
2552         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2553                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2554                                 props, ARRAY_SIZE(props),
2555                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2556                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2557         if (!vop->plane_feature_prop) {
2558                 DRM_ERROR("failed to create feature property\n");
2559                 return -EINVAL;
2560         }
2561
2562         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2563                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2564                                 crtc_props, ARRAY_SIZE(crtc_props),
2565                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2566         if (!vop->feature_prop) {
2567                 DRM_ERROR("failed to create vop feature property\n");
2568                 return -EINVAL;
2569         }
2570
2571         return 0;
2572 }
2573
2574 /**
2575  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2576  * @crtc: CRTC to enable line flag
2577  * @line_num: interested line number
2578  * @mstimeout: millisecond for timeout
2579  *
2580  * Driver would hold here until the interested line flag interrupt have
2581  * happened or timeout to wait.
2582  *
2583  * Returns:
2584  * Zero on success, negative errno on failure.
2585  */
2586 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2587                                 unsigned int mstimeout)
2588 {
2589         struct vop *vop = to_vop(crtc);
2590         unsigned long jiffies_left;
2591         int ret = 0;
2592
2593         if (!crtc || !vop->is_enabled)
2594                 return -ENODEV;
2595
2596         mutex_lock(&vop->vop_lock);
2597
2598         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2599                 ret = -EINVAL;
2600                 goto out;
2601         }
2602
2603         if (vop_line_flag_irq_is_enabled(vop)) {
2604                 ret = -EBUSY;
2605                 goto out;
2606         }
2607
2608         reinit_completion(&vop->line_flag_completion);
2609         vop_line_flag_irq_enable(vop, line_num);
2610
2611         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2612                                                    msecs_to_jiffies(mstimeout));
2613         vop_line_flag_irq_disable(vop);
2614
2615         if (jiffies_left == 0) {
2616                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2617                 ret = -ETIMEDOUT;
2618                 goto out;
2619         }
2620
2621 out:
2622         mutex_unlock(&vop->vop_lock);
2623
2624         return ret;
2625 }
2626 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2627
2628 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
2629                              void *data)
2630 {
2631         if (event == DEVFREQ_PRECHANGE)
2632                 mutex_lock(&dmc_vop->vop_lock);
2633         else if (event == DEVFREQ_POSTCHANGE)
2634                 mutex_unlock(&dmc_vop->vop_lock);
2635
2636         return NOTIFY_OK;
2637 }
2638
2639 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
2640 {
2641         if (!dmc_vop)
2642                 return -ENOMEM;
2643
2644         dmc_vop->devfreq = devfreq;
2645         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
2646         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
2647                                   DEVFREQ_TRANSITION_NOTIFIER);
2648         return 0;
2649 }
2650 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
2651
2652 static int vop_bind(struct device *dev, struct device *master, void *data)
2653 {
2654         struct platform_device *pdev = to_platform_device(dev);
2655         const struct vop_data *vop_data;
2656         struct drm_device *drm_dev = data;
2657         struct vop *vop;
2658         struct resource *res;
2659         size_t alloc_size;
2660         int ret, irq, i;
2661         int num_wins = 0;
2662
2663         vop_data = of_device_get_match_data(dev);
2664         if (!vop_data)
2665                 return -ENODEV;
2666
2667         for (i = 0; i < vop_data->win_size; i++) {
2668                 const struct vop_win_data *win_data = &vop_data->win[i];
2669
2670                 num_wins += win_data->area_size + 1;
2671         }
2672
2673         /* Allocate vop struct and its vop_win array */
2674         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2675         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2676         if (!vop)
2677                 return -ENOMEM;
2678
2679         vop->dev = dev;
2680         vop->data = vop_data;
2681         vop->drm_dev = drm_dev;
2682         vop->num_wins = num_wins;
2683         dev_set_drvdata(dev, vop);
2684
2685         ret = vop_win_init(vop);
2686         if (ret)
2687                 return ret;
2688
2689         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2690         vop->len = resource_size(res);
2691         vop->regs = devm_ioremap_resource(dev, res);
2692         if (IS_ERR(vop->regs))
2693                 return PTR_ERR(vop->regs);
2694
2695         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2696         if (!vop->regsbak)
2697                 return -ENOMEM;
2698
2699         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2700         vop->lut_regs = devm_ioremap_resource(dev, res);
2701         if (IS_ERR(vop->lut_regs)) {
2702                 dev_warn(vop->dev, "failed to get vop lut registers\n");
2703                 vop->lut_regs = NULL;
2704         }
2705         if (vop->lut_regs) {
2706                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
2707                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
2708                         dev_err(vop->dev, "unsupport lut sizes %d\n",
2709                                 vop->lut_len);
2710                         return -EINVAL;
2711                 }
2712         }
2713
2714         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2715         if (IS_ERR(vop->hclk)) {
2716                 dev_err(vop->dev, "failed to get hclk source\n");
2717                 return PTR_ERR(vop->hclk);
2718         }
2719         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2720         if (IS_ERR(vop->aclk)) {
2721                 dev_err(vop->dev, "failed to get aclk source\n");
2722                 return PTR_ERR(vop->aclk);
2723         }
2724         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2725         if (IS_ERR(vop->dclk)) {
2726                 dev_err(vop->dev, "failed to get dclk source\n");
2727                 return PTR_ERR(vop->dclk);
2728         }
2729
2730         irq = platform_get_irq(pdev, 0);
2731         if (irq < 0) {
2732                 dev_err(dev, "cannot find irq for vop\n");
2733                 return irq;
2734         }
2735         vop->irq = (unsigned int)irq;
2736
2737         spin_lock_init(&vop->reg_lock);
2738         spin_lock_init(&vop->irq_lock);
2739         mutex_init(&vop->vop_lock);
2740
2741         mutex_init(&vop->vsync_mutex);
2742
2743         ret = devm_request_irq(dev, vop->irq, vop_isr,
2744                                IRQF_SHARED, dev_name(dev), vop);
2745         if (ret)
2746                 return ret;
2747
2748         /* IRQ is initially disabled; it gets enabled in power_on */
2749         disable_irq(vop->irq);
2750
2751         ret = vop_create_crtc(vop);
2752         if (ret)
2753                 return ret;
2754
2755         pm_runtime_enable(&pdev->dev);
2756
2757         dmc_vop = vop;
2758
2759         return 0;
2760 }
2761
2762 static void vop_unbind(struct device *dev, struct device *master, void *data)
2763 {
2764         struct vop *vop = dev_get_drvdata(dev);
2765
2766         pm_runtime_disable(dev);
2767         vop_destroy_crtc(vop);
2768 }
2769
2770 const struct component_ops vop_component_ops = {
2771         .bind = vop_bind,
2772         .unbind = vop_unbind,
2773 };
2774 EXPORT_SYMBOL_GPL(vop_component_ops);