drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22
  23 #include <linux/devfreq.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/iopoll.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/component.h>
  34
  35 #include <linux/reset.h>
  36 #include <linux/delay.h>
  37 #include <linux/sort.h>
  38 #include <uapi/drm/rockchip_drm.h>
  39
  40 #include "rockchip_drm_drv.h"
  41 #include "rockchip_drm_gem.h"
  42 #include "rockchip_drm_fb.h"
  43 #include "rockchip_drm_vop.h"
  44 #include "rockchip_drm_backlight.h"
  45
  46 #define VOP_REG_SUPPORT(vop, reg) \
  47                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  48                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  49                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  50                 reg.mask))
  51
  52 #define VOP_WIN_SUPPORT(vop, win, name) \
  53                 VOP_REG_SUPPORT(vop, win->phy->name)
  54
  55 #define VOP_CTRL_SUPPORT(vop, name) \
  56                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  57
  58 #define VOP_INTR_SUPPORT(vop, name) \
  59                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  60
  61 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  62                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  63
  64 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  65         do { \
  66                 if (VOP_REG_SUPPORT(vop, reg)) \
  67                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  68                                   v, reg.write_mask, relaxed); \
  69                 else \
  70                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  71         } while(0)
  72
  73 #define REG_SET(x, name, off, reg, v, relaxed) \
  74                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  75 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  76                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  77
  78 #define VOP_WIN_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  80 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  81                 REG_SET(x, name, 0, win->ext->name, v, true)
  82 #define VOP_SCL_SET(x, win, name, v) \
  83                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  84 #define VOP_SCL_SET_EXT(x, win, name, v) \
  85                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  86
  87 #define VOP_CTRL_SET(x, name, v) \
  88                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  89
  90 #define VOP_INTR_GET(vop, name) \
  91                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  92
  93 #define VOP_INTR_SET(vop, name, v) \
  94                 REG_SET(vop, name, 0, vop->data->intr->name, \
  95                         v, false)
  96 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  97                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  98                              mask, v, false)
  99
 100 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
 101         do { \
 102                 int i, reg = 0, mask = 0; \
 103                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 104                         if (vop->data->intr->intrs[i] & type) { \
 105                                 reg |= (v) << i; \
 106                                 mask |= 1 << i; \
 107                         } \
 108                 } \
 109                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 110         } while (0)
 111 #define VOP_INTR_GET_TYPE(vop, name, type) \
 112                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 113
 114 #define VOP_CTRL_GET(x, name) \
 115                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 116
 117 #define VOP_WIN_GET(x, win, name) \
 118                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 119
 120 #define VOP_WIN_NAME(win, name) \
 121                 (vop_get_win_phy(win, &win->phy->name)->name)
 122
 123 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 124                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 125
 126 #define to_vop(x) container_of(x, struct vop, crtc)
 127 #define to_vop_win(x) container_of(x, struct vop_win, base)
 128 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 129
 130 struct vop_zpos {
 131         int win_id;
 132         int zpos;
 133 };
 134
 135 enum vop_pending {
 136         VOP_PENDING_FB_UNREF,
 137 };
 138
 139 struct vop_plane_state {
 140         struct drm_plane_state base;
 141         int format;
 142         int zpos;
 143         unsigned int logo_ymirror;
 144         struct drm_rect src;
 145         struct drm_rect dest;
 146         dma_addr_t yrgb_mst;
 147         dma_addr_t uv_mst;
 148         const uint32_t *y2r_table;
 149         const uint32_t *r2r_table;
 150         const uint32_t *r2y_table;
 151         bool enable;
 152 };
 153
 154 struct vop_win {
 155         struct vop_win *parent;
 156         struct drm_plane base;
 157
 158         int win_id;
 159         int area_id;
 160         uint32_t offset;
 161         enum drm_plane_type type;
 162         const struct vop_win_phy *phy;
 163         const struct vop_csc *csc;
 164         const uint32_t *data_formats;
 165         uint32_t nformats;
 166         struct vop *vop;
 167
 168         struct drm_property *rotation_prop;
 169         struct vop_plane_state state;
 170 };
 171
 172 struct vop {
 173         struct drm_crtc crtc;
 174         struct device *dev;
 175         struct drm_device *drm_dev;
 176         struct drm_property *plane_zpos_prop;
 177         struct drm_property *plane_feature_prop;
 178         struct drm_property *feature_prop;
 179         bool is_iommu_enabled;
 180         bool is_iommu_needed;
 181         bool is_enabled;
 182
 183         /* mutex vsync_ work */
 184         struct mutex vsync_mutex;
 185         bool vsync_work_pending;
 186         bool loader_protect;
 187         struct completion dsp_hold_completion;
 188
 189         /* protected by dev->event_lock */
 190         struct drm_pending_vblank_event *event;
 191
 192         struct drm_flip_work fb_unref_work;
 193         unsigned long pending;
 194
 195         struct completion line_flag_completion;
 196
 197         const struct vop_data *data;
 198         int num_wins;
 199
 200         uint32_t *regsbak;
 201         void __iomem *regs;
 202
 203         /* physical map length of vop register */
 204         uint32_t len;
 205
 206         void __iomem *lut_regs;
 207         u32 *lut;
 208         u32 lut_len;
 209         bool lut_active;
 210         void __iomem *cabc_lut_regs;
 211         u32 cabc_lut_len;
 212
 213         /* one time only one process allowed to config the register */
 214         spinlock_t reg_lock;
 215         /* lock vop irq reg */
 216         spinlock_t irq_lock;
 217         /* mutex vop enable and disable */
 218         struct mutex vop_lock;
 219
 220         unsigned int irq;
 221
 222         /* vop AHP clk */
 223         struct clk *hclk;
 224         /* vop dclk */
 225         struct clk *dclk;
 226         /* vop share memory frequency */
 227         struct clk *aclk;
 228         /* vop source handling, optional */
 229         struct clk *dclk_source;
 230
 231         /* vop dclk reset */
 232         struct reset_control *dclk_rst;
 233
 234         struct devfreq *devfreq;
 235         struct notifier_block dmc_nb;
 236
 237         struct rockchip_dclk_pll *pll;
 238
 239         struct vop_win win[];
 240 };
 241
 242 struct vop *dmc_vop;
 243
 244 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 245 {
 246         writel(v, vop->regs + offset);
 247         vop->regsbak[offset >> 2] = v;
 248 }
 249
 250 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 251 {
 252         return readl(vop->regs + offset);
 253 }
 254
 255 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 256                                     const struct vop_reg *reg)
 257 {
 258         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 259 }
 260
 261 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 262                                   uint32_t mask, uint32_t shift, uint32_t v,
 263                                   bool write_mask, bool relaxed)
 264 {
 265         if (!mask)
 266                 return;
 267
 268         if (write_mask) {
 269                 v = ((v & mask) << shift) | (mask << (shift + 16));
 270         } else {
 271                 uint32_t cached_val = vop->regsbak[offset >> 2];
 272
 273                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 274                 vop->regsbak[offset >> 2] = v;
 275         }
 276
 277         if (relaxed)
 278                 writel_relaxed(v, vop->regs + offset);
 279         else
 280                 writel(v, vop->regs + offset);
 281 }
 282
 283 static inline const struct vop_win_phy *
 284 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 285 {
 286         if (!reg->mask && win->parent)
 287                 return win->parent->phy;
 288
 289         return win->phy;
 290 }
 291
 292 static inline uint32_t vop_get_intr_type(struct vop *vop,
 293                                          const struct vop_reg *reg, int type)
 294 {
 295         uint32_t i, ret = 0;
 296         uint32_t regs = vop_read_reg(vop, 0, reg);
 297
 298         for (i = 0; i < vop->data->intr->nintrs; i++) {
 299                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 300                         ret |= vop->data->intr->intrs[i];
 301         }
 302
 303         return ret;
 304 }
 305
 306 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 307 {
 308         int i;
 309
 310         if (!table)
 311                 return;
 312
 313         for (i = 0; i < 8; i++)
 314                 vop_writel(vop, offset + i * 4, table[i]);
 315 }
 316
 317 static inline void vop_cfg_done(struct vop *vop)
 318 {
 319         VOP_CTRL_SET(vop, cfg_done, 1);
 320 }
 321
 322 static bool vop_is_allwin_disabled(struct vop *vop)
 323 {
 324         int i;
 325
 326         for (i = 0; i < vop->num_wins; i++) {
 327                 struct vop_win *win = &vop->win[i];
 328
 329                 if (VOP_WIN_GET(vop, win, enable) != 0)
 330                         return false;
 331         }
 332
 333         return true;
 334 }
 335
 336 static bool vop_fs_irq_is_active(struct vop *vop)
 337 {
 338         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 339 }
 340
 341 static bool vop_line_flag_is_active(struct vop *vop)
 342 {
 343         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 344 }
 345
 346 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 347 {
 348         writel(v, vop->lut_regs + offset);
 349 }
 350
 351 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 352 {
 353         return readl(vop->lut_regs + offset);
 354 }
 355
 356 static inline void vop_write_cabc_lut(struct vop *vop, uint32_t offset, uint32_t v)
 357 {
 358         writel(v, vop->cabc_lut_regs + offset);
 359 }
 360
 361 static bool has_rb_swapped(uint32_t format)
 362 {
 363         switch (format) {
 364         case DRM_FORMAT_XBGR8888:
 365         case DRM_FORMAT_ABGR8888:
 366         case DRM_FORMAT_BGR888:
 367         case DRM_FORMAT_BGR565:
 368                 return true;
 369         default:
 370                 return false;
 371         }
 372 }
 373
 374 static enum vop_data_format vop_convert_format(uint32_t format)
 375 {
 376         switch (format) {
 377         case DRM_FORMAT_XRGB8888:
 378         case DRM_FORMAT_ARGB8888:
 379         case DRM_FORMAT_XBGR8888:
 380         case DRM_FORMAT_ABGR8888:
 381                 return VOP_FMT_ARGB8888;
 382         case DRM_FORMAT_RGB888:
 383         case DRM_FORMAT_BGR888:
 384                 return VOP_FMT_RGB888;
 385         case DRM_FORMAT_RGB565:
 386         case DRM_FORMAT_BGR565:
 387                 return VOP_FMT_RGB565;
 388         case DRM_FORMAT_NV12:
 389         case DRM_FORMAT_NV12_10:
 390                 return VOP_FMT_YUV420SP;
 391         case DRM_FORMAT_NV16:
 392         case DRM_FORMAT_NV16_10:
 393                 return VOP_FMT_YUV422SP;
 394         case DRM_FORMAT_NV24:
 395         case DRM_FORMAT_NV24_10:
 396                 return VOP_FMT_YUV444SP;
 397         default:
 398                 DRM_ERROR("unsupport format[%08x]\n", format);
 399                 return -EINVAL;
 400         }
 401 }
 402
 403 static bool is_yuv_output(uint32_t bus_format)
 404 {
 405         switch (bus_format) {
 406         case MEDIA_BUS_FMT_YUV8_1X24:
 407         case MEDIA_BUS_FMT_YUV10_1X30:
 408         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 409         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 410                 return true;
 411         default:
 412                 return false;
 413         }
 414 }
 415
 416 static bool is_yuv_support(uint32_t format)
 417 {
 418         switch (format) {
 419         case DRM_FORMAT_NV12:
 420         case DRM_FORMAT_NV12_10:
 421         case DRM_FORMAT_NV16:
 422         case DRM_FORMAT_NV16_10:
 423         case DRM_FORMAT_NV24:
 424         case DRM_FORMAT_NV24_10:
 425                 return true;
 426         default:
 427                 return false;
 428         }
 429 }
 430
 431 static bool is_yuv_10bit(uint32_t format)
 432 {
 433         switch (format) {
 434         case DRM_FORMAT_NV12_10:
 435         case DRM_FORMAT_NV16_10:
 436         case DRM_FORMAT_NV24_10:
 437                 return true;
 438         default:
 439                 return false;
 440         }
 441 }
 442
 443 static bool is_alpha_support(uint32_t format)
 444 {
 445         switch (format) {
 446         case DRM_FORMAT_ARGB8888:
 447         case DRM_FORMAT_ABGR8888:
 448                 return true;
 449         default:
 450                 return false;
 451         }
 452 }
 453
 454 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 455                                   uint32_t dst, bool is_horizontal,
 456                                   int vsu_mode, int *vskiplines)
 457 {
 458         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 459
 460         if (is_horizontal) {
 461                 if (mode == SCALE_UP)
 462                         val = GET_SCL_FT_BIC(src, dst);
 463                 else if (mode == SCALE_DOWN)
 464                         val = GET_SCL_FT_BILI_DN(src, dst);
 465         } else {
 466                 if (mode == SCALE_UP) {
 467                         if (vsu_mode == SCALE_UP_BIL)
 468                                 val = GET_SCL_FT_BILI_UP(src, dst);
 469                         else
 470                                 val = GET_SCL_FT_BIC(src, dst);
 471                 } else if (mode == SCALE_DOWN) {
 472                         if (vskiplines) {
 473                                 *vskiplines = scl_get_vskiplines(src, dst);
 474                                 val = scl_get_bili_dn_vskip(src, dst,
 475                                                             *vskiplines);
 476                         } else {
 477                                 val = GET_SCL_FT_BILI_DN(src, dst);
 478                         }
 479                 }
 480         }
 481
 482         return val;
 483 }
 484
 485 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 486                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 487                                 uint32_t dst_h, uint32_t pixel_format)
 488 {
 489         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 490         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 491         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 492         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 493         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 494         bool is_yuv = is_yuv_support(pixel_format);
 495         uint16_t cbcr_src_w = src_w / hsub;
 496         uint16_t cbcr_src_h = src_h / vsub;
 497         uint16_t vsu_mode;
 498         uint16_t lb_mode;
 499         uint32_t val;
 500         int vskiplines = 0;
 501
 502         if (!win->phy->scl)
 503                 return;
 504
 505         if (!win->phy->scl->ext) {
 506                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 507                             scl_cal_scale2(src_w, dst_w));
 508                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 509                             scl_cal_scale2(src_h, dst_h));
 510                 if (is_yuv) {
 511                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 512                                     scl_cal_scale2(cbcr_src_w, dst_w));
 513                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 514                                     scl_cal_scale2(cbcr_src_h, dst_h));
 515                 }
 516                 return;
 517         }
 518
 519         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 520         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 521
 522         if (is_yuv) {
 523                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 524                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 525                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 526                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 527                 else
 528                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 529         } else {
 530                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 531                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 532                 else
 533                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 534         }
 535
 536         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 537         if (lb_mode == LB_RGB_3840X2) {
 538                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 539                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 540                         return;
 541                 }
 542                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 543                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 544                         return;
 545                 }
 546                 vsu_mode = SCALE_UP_BIL;
 547         } else if (lb_mode == LB_RGB_2560X4) {
 548                 vsu_mode = SCALE_UP_BIL;
 549         } else {
 550                 vsu_mode = SCALE_UP_BIC;
 551         }
 552
 553         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 554                                 true, 0, NULL);
 555         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 556         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 557                                 false, vsu_mode, &vskiplines);
 558         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 559
 560         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 561         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 562
 563         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 564         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 565         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 566         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 567         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 568         if (is_yuv) {
 569                 vskiplines = 0;
 570
 571                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 572                                         dst_w, true, 0, NULL);
 573                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 574                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 575                                         dst_h, false, vsu_mode, &vskiplines);
 576                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 577
 578                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 579                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 580                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 581                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 582                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 583                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 584                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 585         }
 586 }
 587
 588 /*
 589  * rk3399 colorspace path:
 590  *      Input        Win csc                     Output
 591  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 592  *    RGB        --> R2Y                  __/
 593  *
 594  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 595  *    RGB        --> 709To2020->R2Y       __/
 596  *
 597  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 598  *    RGB        --> R2Y                  __/
 599  *
 600  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 601  *    RGB        --> 709To2020->R2Y       __/
 602  *
 603  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 604  *    RGB        --> R2Y                  __/
 605  *
 606  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 607  *    RGB        --> R2Y(601)             __/
 608  *
 609  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 610  *    RGB        --> bypass               __/
 611  *
 612  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 613  *
 614  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 615  *
 616  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 617  *
 618  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 619  */
 620 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 621                          bool is_input_yuv, bool is_output_yuv,
 622                          int input_csc, int output_csc,
 623                          const uint32_t **y2r_table,
 624                          const uint32_t **r2r_table,
 625                          const uint32_t **r2y_table)
 626 {
 627         *y2r_table = NULL;
 628         *r2r_table = NULL;
 629         *r2y_table = NULL;
 630
 631         if (is_output_yuv) {
 632                 if (output_csc == CSC_BT2020) {
 633                         if (is_input_yuv) {
 634                                 if (input_csc == CSC_BT2020)
 635                                         return 0;
 636                                 *y2r_table = csc_table->y2r_bt709;
 637                         }
 638                         if (input_csc != CSC_BT2020)
 639                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 640                         *r2y_table = csc_table->r2y_bt2020;
 641                 } else {
 642                         if (is_input_yuv && input_csc == CSC_BT2020)
 643                                 *y2r_table = csc_table->y2r_bt2020;
 644                         if (input_csc == CSC_BT2020)
 645                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 646                         if (!is_input_yuv || *y2r_table) {
 647                                 if (output_csc == CSC_BT709)
 648                                         *r2y_table = csc_table->r2y_bt709;
 649                                 else
 650                                         *r2y_table = csc_table->r2y_bt601;
 651                         }
 652                 }
 653         } else {
 654                 if (!is_input_yuv)
 655                         return 0;
 656
 657                 /*
 658                  * is possible use bt2020 on rgb mode?
 659                  */
 660                 if (WARN_ON(output_csc == CSC_BT2020))
 661                         return -EINVAL;
 662
 663                 if (input_csc == CSC_BT2020)
 664                         *y2r_table = csc_table->y2r_bt2020;
 665                 else if (input_csc == CSC_BT709)
 666                         *y2r_table = csc_table->y2r_bt709;
 667                 else
 668                         *y2r_table = csc_table->y2r_bt601;
 669
 670                 if (input_csc == CSC_BT2020)
 671                         /*
 672                          * We don't have bt601 to bt709 table, force use bt709.
 673                          */
 674                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 681                                 struct drm_crtc_state *crtc_state)
 682 {
 683         struct vop *vop = to_vop(crtc);
 684         struct drm_atomic_state *state = crtc_state->state;
 685         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 686         const struct vop_csc_table *csc_table = vop->data->csc_table;
 687         struct drm_plane_state *pstate;
 688         struct drm_plane *plane;
 689         bool is_input_yuv, is_output_yuv;
 690         int ret;
 691
 692         if (!csc_table)
 693                 return 0;
 694
 695         is_output_yuv = is_yuv_output(s->bus_format);
 696
 697         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 698                 struct vop_plane_state *vop_plane_state;
 699
 700                 pstate = drm_atomic_get_plane_state(state, plane);
 701                 if (IS_ERR(pstate))
 702                         return PTR_ERR(pstate);
 703                 vop_plane_state = to_vop_plane_state(pstate);
 704
 705                 if (!pstate->fb)
 706                         continue;
 707                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 708
 709                 /*
 710                  * TODO: force set input and output csc mode.
 711                  */
 712                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 713                                     CSC_BT709, CSC_BT709,
 714                                     &vop_plane_state->y2r_table,
 715                                     &vop_plane_state->r2r_table,
 716                                     &vop_plane_state->r2y_table);
 717                 if (ret)
 718                         return ret;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 725 {
 726         unsigned long flags;
 727
 728         spin_lock_irqsave(&vop->irq_lock, flags);
 729
 730         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 731         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 732
 733         spin_unlock_irqrestore(&vop->irq_lock, flags);
 734 }
 735
 736 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 737 {
 738         unsigned long flags;
 739
 740         spin_lock_irqsave(&vop->irq_lock, flags);
 741
 742         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 743
 744         spin_unlock_irqrestore(&vop->irq_lock, flags);
 745 }
 746
 747 /*
 748  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 749  *     the "FRAME_SYNC" interrupt.
 750  * (2) the active data region of each frame ends at dsp_vact_end
 751  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 752  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 753  *
 754  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 755  * Interrupts
 756  * LINE_FLAG -------------------------------+
 757  * FRAME_SYNC ----+                         |
 758  *                |                         |
 759  *                v                         v
 760  *                | Vsync | Vbp |  Vactive  | Vfp |
 761  *                        ^     ^           ^     ^
 762  *                        |     |           |     |
 763  *                        |     |           |     |
 764  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 765  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 766  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 767  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 768  */
 769 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 770 {
 771         uint32_t line_flag_irq;
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&vop->irq_lock, flags);
 775
 776         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 777
 778         spin_unlock_irqrestore(&vop->irq_lock, flags);
 779
 780         return !!line_flag_irq;
 781 }
 782
 783 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 784 {
 785         unsigned long flags;
 786
 787         if (WARN_ON(!vop->is_enabled))
 788                 return;
 789
 790         spin_lock_irqsave(&vop->irq_lock, flags);
 791
 792         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 793         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 794         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 795
 796         spin_unlock_irqrestore(&vop->irq_lock, flags);
 797 }
 798
 799 static void vop_line_flag_irq_disable(struct vop *vop)
 800 {
 801         unsigned long flags;
 802
 803         if (WARN_ON(!vop->is_enabled))
 804                 return;
 805
 806         spin_lock_irqsave(&vop->irq_lock, flags);
 807
 808         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 809
 810         spin_unlock_irqrestore(&vop->irq_lock, flags);
 811 }
 812
 813 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 814 {
 815         struct vop *vop = to_vop(crtc);
 816         int i, dle, lut_idx;
 817
 818         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 819                 return;
 820
 821         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 822                 return;
 823
 824         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 825                 spin_lock(&vop->reg_lock);
 826                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 827                 vop_cfg_done(vop);
 828                 spin_unlock(&vop->reg_lock);
 829
 830 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 831                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 832                                 dle, !dle, 5, 33333);
 833         } else {
 834                 lut_idx = CTRL_GET(lut_buffer_index);
 835         }
 836
 837         for (i = 0; i < vop->lut_len; i++)
 838                 vop_write_lut(vop, i << 2, vop->lut[i]);
 839
 840         spin_lock(&vop->reg_lock);
 841
 842         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 843         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 844         vop_cfg_done(vop);
 845         vop->lut_active = true;
 846
 847         spin_unlock(&vop->reg_lock);
 848
 849         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 850                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 851                                    dle, dle != lut_idx, 5, 33333);
 852                 /* FIXME:
 853                  * update_gamma value auto clean to 0 by HW, should not
 854                  * bakeup it.
 855                  */
 856                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 857         }
 858 #undef CTRL_GET
 859 }
 860
 861 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 862                                     u16 blue, int regno)
 863 {
 864         struct vop *vop = to_vop(crtc);
 865         u32 lut_len = vop->lut_len;
 866         u32 r, g, b;
 867
 868         if (regno >= lut_len || !vop->lut)
 869                 return;
 870
 871         r = red * (lut_len - 1) / 0xffff;
 872         g = green * (lut_len - 1) / 0xffff;
 873         b = blue * (lut_len - 1) / 0xffff;
 874         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 875 }
 876
 877 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 878                                     u16 *blue, int regno)
 879 {
 880         struct vop *vop = to_vop(crtc);
 881         u32 lut_len = vop->lut_len;
 882         u32 r, g, b;
 883
 884         if (regno >= lut_len || !vop->lut)
 885                 return;
 886
 887         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 888         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 889         b = vop->lut[regno] & (lut_len - 1);
 890         *red = r * 0xffff / (lut_len - 1);
 891         *green = g * 0xffff / (lut_len - 1);
 892         *blue = b * 0xffff / (lut_len - 1);
 893 }
 894
 895 static void vop_power_enable(struct drm_crtc *crtc)
 896 {
 897         struct vop *vop = to_vop(crtc);
 898         int ret;
 899
 900         ret = clk_prepare_enable(vop->hclk);
 901         if (ret < 0) {
 902                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 903                 return;
 904         }
 905
 906         ret = clk_prepare_enable(vop->dclk);
 907         if (ret < 0) {
 908                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 909                 goto err_disable_hclk;
 910         }
 911
 912         ret = clk_prepare_enable(vop->aclk);
 913         if (ret < 0) {
 914                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 915                 goto err_disable_dclk;
 916         }
 917
 918         ret = pm_runtime_get_sync(vop->dev);
 919         if (ret < 0) {
 920                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 921                 return;
 922         }
 923
 924         memcpy(vop->regsbak, vop->regs, vop->len);
 925
 926         vop->is_enabled = true;
 927
 928         return;
 929
 930 err_disable_dclk:
 931         clk_disable_unprepare(vop->dclk);
 932 err_disable_hclk:
 933         clk_disable_unprepare(vop->hclk);
 934 }
 935
 936 static void vop_initial(struct drm_crtc *crtc)
 937 {
 938         struct vop *vop = to_vop(crtc);
 939         uint32_t irqs;
 940         int i;
 941
 942         vop_power_enable(crtc);
 943
 944         VOP_CTRL_SET(vop, global_regdone_en, 1);
 945         VOP_CTRL_SET(vop, dsp_blank, 0);
 946
 947         /*
 948          * restore the lut table.
 949          */
 950         if (vop->lut_active)
 951                 vop_crtc_load_lut(crtc);
 952
 953         /*
 954          * We need to make sure that all windows are disabled before resume
 955          * the crtc. Otherwise we might try to scan from a destroyed
 956          * buffer later.
 957          */
 958         for (i = 0; i < vop->num_wins; i++) {
 959                 struct vop_win *win = &vop->win[i];
 960                 int channel = i * 2 + 1;
 961
 962                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 963                 if (win->phy->scl && win->phy->scl->ext) {
 964                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 965                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 966                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 967                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 968                 }
 969                 VOP_WIN_SET(vop, win, enable, 0);
 970                 VOP_WIN_SET(vop, win, gate, 1);
 971         }
 972         VOP_CTRL_SET(vop, afbdc_en, 0);
 973
 974         irqs = BUS_ERROR_INTR | WIN0_EMPTY_INTR | WIN1_EMPTY_INTR |
 975                 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | HWC_EMPTY_INTR |
 976                 POST_BUF_EMPTY_INTR;
 977         VOP_INTR_SET_TYPE(vop, clear, irqs, 1);
 978         VOP_INTR_SET_TYPE(vop, enable, irqs, 1);
 979 }
 980
 981 static void vop_crtc_disable(struct drm_crtc *crtc)
 982 {
 983         struct vop *vop = to_vop(crtc);
 984
 985         mutex_lock(&vop->vop_lock);
 986         drm_crtc_vblank_off(crtc);
 987
 988         /*
 989          * Vop standby will take effect at end of current frame,
 990          * if dsp hold valid irq happen, it means standby complete.
 991          *
 992          * we must wait standby complete when we want to disable aclk,
 993          * if not, memory bus maybe dead.
 994          */
 995         reinit_completion(&vop->dsp_hold_completion);
 996         vop_dsp_hold_valid_irq_enable(vop);
 997
 998         spin_lock(&vop->reg_lock);
 999
1000         VOP_CTRL_SET(vop, standby, 1);
1001
1002         spin_unlock(&vop->reg_lock);
1003
1004         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
1005                                              msecs_to_jiffies(50)));
1006
1007         vop_dsp_hold_valid_irq_disable(vop);
1008
1009         disable_irq(vop->irq);
1010
1011         vop->is_enabled = false;
1012         if (vop->is_iommu_enabled) {
1013                 /*
1014                  * vop standby complete, so iommu detach is safe.
1015                  */
1016                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
1017                 vop->is_iommu_enabled = false;
1018         }
1019
1020         pm_runtime_put(vop->dev);
1021         clk_disable_unprepare(vop->dclk);
1022         clk_disable_unprepare(vop->aclk);
1023         clk_disable_unprepare(vop->hclk);
1024         mutex_unlock(&vop->vop_lock);
1025 }
1026
1027 static void vop_plane_destroy(struct drm_plane *plane)
1028 {
1029         drm_plane_cleanup(plane);
1030 }
1031
1032 static int vop_plane_prepare_fb(struct drm_plane *plane,
1033                                 const struct drm_plane_state *new_state)
1034 {
1035         if (plane->state->fb)
1036                 drm_framebuffer_reference(plane->state->fb);
1037
1038         return 0;
1039 }
1040
1041 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1042                                  const struct drm_plane_state *old_state)
1043 {
1044         if (old_state->fb)
1045                 drm_framebuffer_unreference(old_state->fb);
1046 }
1047
1048 static int vop_plane_atomic_check(struct drm_plane *plane,
1049                            struct drm_plane_state *state)
1050 {
1051         struct drm_crtc *crtc = state->crtc;
1052         struct drm_framebuffer *fb = state->fb;
1053         struct vop_win *win = to_vop_win(plane);
1054         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1055         struct drm_crtc_state *crtc_state;
1056         const struct vop_data *vop_data;
1057         struct vop *vop;
1058         bool visible;
1059         int ret;
1060         struct drm_rect *dest = &vop_plane_state->dest;
1061         struct drm_rect *src = &vop_plane_state->src;
1062         struct drm_rect clip;
1063         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1064                                         DRM_PLANE_HELPER_NO_SCALING;
1065         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1066                                         DRM_PLANE_HELPER_NO_SCALING;
1067         unsigned long offset;
1068         dma_addr_t dma_addr;
1069         u16 vdisplay;
1070
1071         crtc = crtc ? crtc : plane->state->crtc;
1072         /*
1073          * Both crtc or plane->state->crtc can be null.
1074          */
1075         if (!crtc || !fb)
1076                 goto out_disable;
1077
1078         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1079         if (IS_ERR(crtc_state))
1080                 return PTR_ERR(crtc_state);
1081
1082         src->x1 = state->src_x;
1083         src->y1 = state->src_y;
1084         src->x2 = state->src_x + state->src_w;
1085         src->y2 = state->src_y + state->src_h;
1086         dest->x1 = state->crtc_x;
1087         dest->y1 = state->crtc_y;
1088         dest->x2 = state->crtc_x + state->crtc_w;
1089         dest->y2 = state->crtc_y + state->crtc_h;
1090
1091         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1092         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1093                 vdisplay *= 2;
1094
1095         clip.x1 = 0;
1096         clip.y1 = 0;
1097         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1098         clip.y2 = vdisplay;
1099
1100         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1101                                             src, dest, &clip,
1102                                             min_scale,
1103                                             max_scale,
1104                                             true, true, &visible);
1105         if (ret)
1106                 return ret;
1107
1108         if (!visible)
1109                 goto out_disable;
1110
1111         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1112         if (vop_plane_state->format < 0)
1113                 return vop_plane_state->format;
1114
1115         vop = to_vop(crtc);
1116         vop_data = vop->data;
1117
1118         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1119             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1120                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1121                           drm_rect_width(src) >> 16,
1122                           drm_rect_height(src) >> 16,
1123                           vop_data->max_input.width,
1124                           vop_data->max_input.height);
1125                 return -EINVAL;
1126         }
1127
1128         /*
1129          * Src.x1 can be odd when do clip, but yuv plane start point
1130          * need align with 2 pixel.
1131          */
1132         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1133                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1134                 return -EINVAL;
1135         }
1136
1137         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1138         if (state->rotation & BIT(DRM_REFLECT_Y) ||
1139             (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1140                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1141         else
1142                 offset += (src->y1 >> 16) * fb->pitches[0];
1143
1144         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1145         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1146         if (is_yuv_support(fb->pixel_format)) {
1147                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1148                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1149                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1150
1151                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1152                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1153
1154                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1155                 dma_addr += offset + fb->offsets[1];
1156                 vop_plane_state->uv_mst = dma_addr;
1157         }
1158
1159         vop_plane_state->enable = true;
1160
1161         return 0;
1162
1163 out_disable:
1164         vop_plane_state->enable = false;
1165         return 0;
1166 }
1167
1168 static void vop_plane_atomic_disable(struct drm_plane *plane,
1169                                      struct drm_plane_state *old_state)
1170 {
1171         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1172         struct vop_win *win = to_vop_win(plane);
1173         struct vop *vop = to_vop(old_state->crtc);
1174
1175         if (!old_state->crtc)
1176                 return;
1177
1178         spin_lock(&vop->reg_lock);
1179
1180         /*
1181          * FIXUP: some of the vop scale would be abnormal after windows power
1182          * on/off so deinit scale to scale_none mode.
1183          */
1184         if (win->phy->scl && win->phy->scl->ext) {
1185                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1186                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1187                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1188                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1189         }
1190         VOP_WIN_SET(vop, win, enable, 0);
1191
1192         spin_unlock(&vop->reg_lock);
1193
1194         vop_plane_state->enable = false;
1195 }
1196
1197 static void vop_plane_atomic_update(struct drm_plane *plane,
1198                 struct drm_plane_state *old_state)
1199 {
1200         struct drm_plane_state *state = plane->state;
1201         struct drm_crtc *crtc = state->crtc;
1202         struct vop_win *win = to_vop_win(plane);
1203         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1204         struct rockchip_crtc_state *s;
1205         struct vop *vop;
1206         struct drm_framebuffer *fb = state->fb;
1207         unsigned int actual_w, actual_h;
1208         unsigned int dsp_stx, dsp_sty;
1209         uint32_t act_info, dsp_info, dsp_st;
1210         struct drm_rect *src = &vop_plane_state->src;
1211         struct drm_rect *dest = &vop_plane_state->dest;
1212         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1213         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1214         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1215         int ymirror, xmirror;
1216         uint32_t val;
1217         bool rb_swap;
1218
1219         /*
1220          * can't update plane when vop is disabled.
1221          */
1222         if (!crtc)
1223                 return;
1224
1225         if (!vop_plane_state->enable) {
1226                 vop_plane_atomic_disable(plane, old_state);
1227                 return;
1228         }
1229
1230         actual_w = drm_rect_width(src) >> 16;
1231         actual_h = drm_rect_height(src) >> 16;
1232         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1233
1234         dsp_info = (drm_rect_height(dest) - 1) << 16;
1235         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1236
1237         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1238         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1239         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1240
1241         ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1242                   (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1243         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1244
1245         vop = to_vop(state->crtc);
1246         s = to_rockchip_crtc_state(crtc->state);
1247
1248         spin_lock(&vop->reg_lock);
1249
1250         VOP_WIN_SET(vop, win, xmirror, xmirror);
1251         VOP_WIN_SET(vop, win, ymirror, ymirror);
1252         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1253         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1254         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1255         if (is_yuv_support(fb->pixel_format)) {
1256                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1257                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1258         }
1259         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1260
1261         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1262                             drm_rect_width(dest), drm_rect_height(dest),
1263                             fb->pixel_format);
1264
1265         VOP_WIN_SET(vop, win, act_info, act_info);
1266         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1267         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1268
1269         rb_swap = has_rb_swapped(fb->pixel_format);
1270         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1271
1272         if (is_alpha_support(fb->pixel_format) &&
1273             (s->dsp_layer_sel & 0x3) != win->win_id) {
1274                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1275                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1276                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1277                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1278                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1279                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1280                         SRC_FACTOR_M0(ALPHA_ONE);
1281                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1282                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1283                 VOP_WIN_SET(vop, win, alpha_en, 1);
1284         } else {
1285                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1286                 VOP_WIN_SET(vop, win, alpha_en, 0);
1287         }
1288
1289         if (win->csc) {
1290                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1291                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1292                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1293                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1294                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1295                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1296         }
1297         VOP_WIN_SET(vop, win, enable, 1);
1298         spin_unlock(&vop->reg_lock);
1299         vop->is_iommu_needed = true;
1300 }
1301
1302 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1303         .prepare_fb = vop_plane_prepare_fb,
1304         .cleanup_fb = vop_plane_cleanup_fb,
1305         .atomic_check = vop_plane_atomic_check,
1306         .atomic_update = vop_plane_atomic_update,
1307         .atomic_disable = vop_plane_atomic_disable,
1308 };
1309
1310 void vop_atomic_plane_reset(struct drm_plane *plane)
1311 {
1312         struct vop_win *win = to_vop_win(plane);
1313         struct vop_plane_state *vop_plane_state =
1314                                         to_vop_plane_state(plane->state);
1315
1316         if (plane->state && plane->state->fb)
1317                 drm_framebuffer_unreference(plane->state->fb);
1318
1319         kfree(vop_plane_state);
1320         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1321         if (!vop_plane_state)
1322                 return;
1323
1324         vop_plane_state->zpos = win->win_id;
1325         plane->state = &vop_plane_state->base;
1326         plane->state->plane = plane;
1327 }
1328
1329 struct drm_plane_state *
1330 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1331 {
1332         struct vop_plane_state *old_vop_plane_state;
1333         struct vop_plane_state *vop_plane_state;
1334
1335         if (WARN_ON(!plane->state))
1336                 return NULL;
1337
1338         old_vop_plane_state = to_vop_plane_state(plane->state);
1339         vop_plane_state = kmemdup(old_vop_plane_state,
1340                                   sizeof(*vop_plane_state), GFP_KERNEL);
1341         if (!vop_plane_state)
1342                 return NULL;
1343
1344         __drm_atomic_helper_plane_duplicate_state(plane,
1345                                                   &vop_plane_state->base);
1346
1347         return &vop_plane_state->base;
1348 }
1349
1350 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1351                                            struct drm_plane_state *state)
1352 {
1353         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1354
1355         __drm_atomic_helper_plane_destroy_state(plane, state);
1356
1357         kfree(vop_state);
1358 }
1359
1360 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1361                                          struct drm_plane_state *state,
1362                                          struct drm_property *property,
1363                                          uint64_t val)
1364 {
1365         struct rockchip_drm_private *private = plane->dev->dev_private;
1366         struct vop_win *win = to_vop_win(plane);
1367         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1368
1369         if (property == win->vop->plane_zpos_prop) {
1370                 plane_state->zpos = val;
1371                 return 0;
1372         }
1373
1374         if (property == win->rotation_prop) {
1375                 state->rotation = val;
1376                 return 0;
1377         }
1378
1379         if (property == private->logo_ymirror_prop) {
1380                 WARN_ON(!rockchip_fb_is_logo(state->fb));
1381                 plane_state->logo_ymirror = val;
1382                 return 0;
1383         }
1384
1385         DRM_ERROR("failed to set vop plane property\n");
1386         return -EINVAL;
1387 }
1388
1389 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1390                                          const struct drm_plane_state *state,
1391                                          struct drm_property *property,
1392                                          uint64_t *val)
1393 {
1394         struct vop_win *win = to_vop_win(plane);
1395         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1396
1397         if (property == win->vop->plane_zpos_prop) {
1398                 *val = plane_state->zpos;
1399                 return 0;
1400         }
1401
1402         if (property == win->rotation_prop) {
1403                 *val = state->rotation;
1404                 return 0;
1405         }
1406
1407         DRM_ERROR("failed to get vop plane property\n");
1408         return -EINVAL;
1409 }
1410
1411 static const struct drm_plane_funcs vop_plane_funcs = {
1412         .update_plane   = drm_atomic_helper_update_plane,
1413         .disable_plane  = drm_atomic_helper_disable_plane,
1414         .destroy = vop_plane_destroy,
1415         .reset = vop_atomic_plane_reset,
1416         .set_property = drm_atomic_helper_plane_set_property,
1417         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1418         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1419         .atomic_set_property = vop_atomic_plane_set_property,
1420         .atomic_get_property = vop_atomic_plane_get_property,
1421 };
1422
1423 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1424 {
1425         struct vop *vop = to_vop(crtc);
1426         unsigned long flags;
1427
1428         if (!vop->is_enabled)
1429                 return -EPERM;
1430
1431         spin_lock_irqsave(&vop->irq_lock, flags);
1432
1433         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1434         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1435
1436         spin_unlock_irqrestore(&vop->irq_lock, flags);
1437
1438         return 0;
1439 }
1440
1441 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1442 {
1443         struct vop *vop = to_vop(crtc);
1444         unsigned long flags;
1445
1446         if (!vop->is_enabled)
1447                 return;
1448
1449         spin_lock_irqsave(&vop->irq_lock, flags);
1450
1451         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1452
1453         spin_unlock_irqrestore(&vop->irq_lock, flags);
1454 }
1455
1456 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1457                                            struct drm_file *file_priv)
1458 {
1459         struct drm_device *drm = crtc->dev;
1460         struct vop *vop = to_vop(crtc);
1461         struct drm_pending_vblank_event *e;
1462         unsigned long flags;
1463
1464         spin_lock_irqsave(&drm->event_lock, flags);
1465         e = vop->event;
1466         if (e && e->base.file_priv == file_priv) {
1467                 vop->event = NULL;
1468
1469                 e->base.destroy(&e->base);
1470                 file_priv->event_space += sizeof(e->event);
1471         }
1472         spin_unlock_irqrestore(&drm->event_lock, flags);
1473 }
1474
1475 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1476 {
1477         struct rockchip_drm_private *private = crtc->dev->dev_private;
1478         struct vop *vop = to_vop(crtc);
1479
1480         if (on == vop->loader_protect)
1481                 return 0;
1482
1483         if (on) {
1484                 if (vop->dclk_source) {
1485                         struct clk *parent;
1486
1487                         parent = clk_get_parent(vop->dclk_source);
1488                         if (parent) {
1489                                 if (clk_is_match(private->default_pll.pll, parent))
1490                                         vop->pll = &private->default_pll;
1491                                 else if (clk_is_match(private->hdmi_pll.pll, parent))
1492                                         vop->pll = &private->hdmi_pll;
1493                                 if (vop->pll)
1494                                         vop->pll->use_count++;
1495                         }
1496                 }
1497
1498                 vop_power_enable(crtc);
1499                 enable_irq(vop->irq);
1500                 drm_crtc_vblank_on(crtc);
1501                 vop->loader_protect = true;
1502         } else {
1503                 vop_crtc_disable(crtc);
1504
1505                 if (vop->dclk_source && vop->pll) {
1506                         vop->pll->use_count--;
1507                         vop->pll = NULL;
1508                 }
1509                 vop->loader_protect = false;
1510         }
1511
1512         return 0;
1513 }
1514
1515 #define DEBUG_PRINT(args...) \
1516                 do { \
1517                         if (s) \
1518                                 seq_printf(s, args); \
1519                         else \
1520                                 printk(args); \
1521                 } while (0)
1522
1523 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1524 {
1525         struct vop_win *win = to_vop_win(plane);
1526         struct drm_plane_state *state = plane->state;
1527         struct vop_plane_state *pstate = to_vop_plane_state(state);
1528         struct drm_rect *src, *dest;
1529         struct drm_framebuffer *fb = state->fb;
1530         int i;
1531
1532         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1533                     pstate->enable ? "ACTIVE" : "DISABLED");
1534         if (!fb)
1535                 return 0;
1536
1537         src = &pstate->src;
1538         dest = &pstate->dest;
1539
1540         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1541                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1542         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1543         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1544                     src->y1 >> 16, drm_rect_width(src) >> 16,
1545                     drm_rect_height(src) >> 16);
1546         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1547                     drm_rect_width(dest), drm_rect_height(dest));
1548
1549         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1550                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1551                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1552                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1559 {
1560         struct vop *vop = to_vop(crtc);
1561         struct drm_crtc_state *crtc_state = crtc->state;
1562         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1563         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1564         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1565         struct drm_plane *plane;
1566         int i;
1567
1568         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1569                     crtc_state->active ? "ACTIVE" : "DISABLED");
1570
1571         if (!crtc_state->active)
1572                 return 0;
1573
1574         DEBUG_PRINT("    Connector: %s\n",
1575                     drm_get_connector_name(state->output_type));
1576         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1577                     state->bus_format, state->output_mode);
1578         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1579                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1580                     drm_mode_vrefresh(mode));
1581         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1582                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1583         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1584                     mode->hsync_end, mode->htotal);
1585         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1586                     mode->vsync_end, mode->vtotal);
1587
1588         for (i = 0; i < vop->num_wins; i++) {
1589                 plane = &vop->win[i].base;
1590                 vop_plane_info_dump(s, plane);
1591         }
1592
1593         return 0;
1594 }
1595
1596 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1597 {
1598         struct vop *vop = to_vop(crtc);
1599         struct drm_crtc_state *crtc_state = crtc->state;
1600         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1601         int i;
1602
1603         if (!crtc_state->active)
1604                 return;
1605
1606         for (i = 0; i < dump_len; i += 4) {
1607                 if (i % 16 == 0)
1608                         DEBUG_PRINT("\n0x%08x: ", i);
1609                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1610         }
1611 }
1612
1613 #undef DEBUG_PRINT
1614
1615 static enum drm_mode_status
1616 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1617                     int output_type)
1618 {
1619         struct vop *vop = to_vop(crtc);
1620         const struct vop_data *vop_data = vop->data;
1621         int request_clock = mode->clock;
1622         int clock;
1623
1624         if (mode->hdisplay > vop_data->max_output.width)
1625                 return MODE_BAD_HVALUE;
1626
1627         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
1628             VOP_MAJOR(vop->data->version) == 3 &&
1629             VOP_MINOR(vop->data->version) <= 2)
1630                 return MODE_BAD;
1631
1632         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1633                 request_clock *= 2;
1634         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1635
1636         /*
1637          * Hdmi or DisplayPort request a Accurate clock.
1638          */
1639         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1640             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1641                 if (clock != request_clock)
1642                         return MODE_CLOCK_RANGE;
1643
1644         return MODE_OK;
1645 }
1646
1647 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1648         .loader_protect = vop_crtc_loader_protect,
1649         .enable_vblank = vop_crtc_enable_vblank,
1650         .disable_vblank = vop_crtc_disable_vblank,
1651         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1652         .debugfs_dump = vop_crtc_debugfs_dump,
1653         .regs_dump = vop_crtc_regs_dump,
1654         .mode_valid = vop_crtc_mode_valid,
1655 };
1656
1657 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1658                                 const struct drm_display_mode *mode,
1659                                 struct drm_display_mode *adj_mode)
1660 {
1661         struct vop *vop = to_vop(crtc);
1662         const struct vop_data *vop_data = vop->data;
1663
1664         if (mode->hdisplay > vop_data->max_output.width)
1665                 return false;
1666
1667         drm_mode_set_crtcinfo(adj_mode,
1668                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1669
1670         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1671                 adj_mode->crtc_clock *= 2;
1672
1673         adj_mode->crtc_clock =
1674                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1675
1676         return true;
1677 }
1678
1679 static void vop_crtc_enable(struct drm_crtc *crtc)
1680 {
1681         struct vop *vop = to_vop(crtc);
1682         const struct vop_data *vop_data = vop->data;
1683         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1684         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1685         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1686         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1687         u16 htotal = adjusted_mode->crtc_htotal;
1688         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1689         u16 hact_end = hact_st + hdisplay;
1690         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1691         u16 vtotal = adjusted_mode->crtc_vtotal;
1692         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1693         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1694         u16 vact_end = vact_st + vdisplay;
1695         uint32_t val;
1696
1697         mutex_lock(&vop->vop_lock);
1698         vop_initial(crtc);
1699
1700         VOP_CTRL_SET(vop, dclk_pol, 1);
1701         val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1702                    0 : BIT(HSYNC_POSITIVE);
1703         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1704                    0 : BIT(VSYNC_POSITIVE);
1705         VOP_CTRL_SET(vop, pin_pol, val);
1706
1707         if (vop->dclk_source && vop->pll && vop->pll->pll) {
1708                 if (clk_set_parent(vop->dclk_source, vop->pll->pll))
1709                         DRM_DEV_ERROR(vop->dev,
1710                                       "failed to set dclk's parents\n");
1711         }
1712
1713         switch (s->output_type) {
1714         case DRM_MODE_CONNECTOR_LVDS:
1715                 VOP_CTRL_SET(vop, rgb_en, 1);
1716                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1717                 VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
1718                 VOP_CTRL_SET(vop, lvds_en, 1);
1719                 VOP_CTRL_SET(vop, lvds_pin_pol, val);
1720                 VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
1721                 break;
1722         case DRM_MODE_CONNECTOR_eDP:
1723                 VOP_CTRL_SET(vop, edp_en, 1);
1724                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1725                 VOP_CTRL_SET(vop, edp_dclk_pol, 1);
1726                 break;
1727         case DRM_MODE_CONNECTOR_HDMIA:
1728                 VOP_CTRL_SET(vop, hdmi_en, 1);
1729                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1730                 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
1731                 break;
1732         case DRM_MODE_CONNECTOR_DSI:
1733                 VOP_CTRL_SET(vop, mipi_en, 1);
1734                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1735                 VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
1736                 if (s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)
1737                         VOP_CTRL_SET(vop, mipi_dual_channel_en, 1);
1738                 else
1739                         VOP_CTRL_SET(vop, mipi_dual_channel_en, 0);
1740                 break;
1741         case DRM_MODE_CONNECTOR_DisplayPort:
1742                 VOP_CTRL_SET(vop, dp_dclk_pol, 0);
1743                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1744                 VOP_CTRL_SET(vop, dp_en, 1);
1745                 break;
1746         case DRM_MODE_CONNECTOR_TV:
1747                 if (vdisplay == CVBS_PAL_VDISPLAY)
1748                         VOP_CTRL_SET(vop, tve_sw_mode, 1);
1749                 else
1750                         VOP_CTRL_SET(vop, tve_sw_mode, 0);
1751
1752                 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
1753                 VOP_CTRL_SET(vop, tve_dclk_en, 1);
1754                 /* use the same pol reg with hdmi */
1755                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1756                 VOP_CTRL_SET(vop, sw_genlock, 1);
1757                 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
1758                 VOP_CTRL_SET(vop, dither_up, 1);
1759                 break;
1760         default:
1761                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1762         }
1763
1764         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1765             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1766                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1767
1768         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1769         switch (s->bus_format) {
1770         case MEDIA_BUS_FMT_RGB565_1X16:
1771                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1772                 break;
1773         case MEDIA_BUS_FMT_RGB666_1X18:
1774         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1775                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1776                 break;
1777         case MEDIA_BUS_FMT_YUV8_1X24:
1778         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1779                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1780                 break;
1781         case MEDIA_BUS_FMT_YUV10_1X30:
1782         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1783                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1784                 break;
1785         case MEDIA_BUS_FMT_RGB888_1X24:
1786         default:
1787                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1788                 break;
1789         }
1790
1791         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1792                 val |= PRE_DITHER_DOWN_EN(0);
1793         else
1794                 val |= PRE_DITHER_DOWN_EN(1);
1795         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1796         VOP_CTRL_SET(vop, dither_down, val);
1797         VOP_CTRL_SET(vop, dclk_ddr,
1798                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1799         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1800         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1801
1802         /*
1803          * Background color is 10bit depth if vop version >= 3.5
1804          */
1805         if (!is_yuv_output(s->bus_format))
1806                 val = 0;
1807         else if (VOP_MAJOR(vop->data->version) == 3 &&
1808                  VOP_MINOR(vop->data->version) >= 5)
1809                 val = 0x20010200;
1810         else
1811                 val = 0x801080;
1812         VOP_CTRL_SET(vop, dsp_background, val);
1813         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1814         val = hact_st << 16;
1815         val |= hact_end;
1816         VOP_CTRL_SET(vop, hact_st_end, val);
1817         VOP_CTRL_SET(vop, hpost_st_end, val);
1818
1819         val = vact_st << 16;
1820         val |= vact_end;
1821         VOP_CTRL_SET(vop, vact_st_end, val);
1822         VOP_CTRL_SET(vop, vpost_st_end, val);
1823
1824         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1825         VOP_INTR_SET(vop, line_flag_num[1],
1826                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1827         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1828                 u16 vact_st_f1 = vtotal + vact_st + 1;
1829                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1830
1831                 val = vact_st_f1 << 16 | vact_end_f1;
1832                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1833                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1834
1835                 val = vtotal << 16 | (vtotal + vsync_len);
1836                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1837                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1838                 VOP_CTRL_SET(vop, p2i_en, 1);
1839                 vtotal += vtotal + 1;
1840         } else {
1841                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1842                 VOP_CTRL_SET(vop, p2i_en, 0);
1843         }
1844         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1845
1846         VOP_CTRL_SET(vop, core_dclk_div,
1847                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1848
1849         VOP_CTRL_SET(vop, cabc_total_num, hdisplay * vdisplay);
1850         VOP_CTRL_SET(vop, cabc_config_mode, STAGE_BY_STAGE);
1851         VOP_CTRL_SET(vop, cabc_stage_up_mode, MUL_MODE);
1852         VOP_CTRL_SET(vop, cabc_scale_cfg_value, 1);
1853         VOP_CTRL_SET(vop, cabc_scale_cfg_enable, 0);
1854         VOP_CTRL_SET(vop, cabc_global_dn_limit_en, 1);
1855
1856         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1857
1858         vop_cfg_done(vop);
1859         /*
1860          * enable vop, all the register would take effect when vop exit standby
1861          */
1862         VOP_CTRL_SET(vop, standby, 0);
1863
1864         enable_irq(vop->irq);
1865         drm_crtc_vblank_on(crtc);
1866         mutex_unlock(&vop->vop_lock);
1867 }
1868
1869 static int vop_zpos_cmp(const void *a, const void *b)
1870 {
1871         struct vop_zpos *pa = (struct vop_zpos *)a;
1872         struct vop_zpos *pb = (struct vop_zpos *)b;
1873
1874         return pa->zpos - pb->zpos;
1875 }
1876
1877 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1878                                   struct drm_crtc_state *crtc_state)
1879 {
1880         struct vop *vop = to_vop(crtc);
1881         const struct vop_data *vop_data = vop->data;
1882         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1883         struct drm_atomic_state *state = crtc_state->state;
1884         struct drm_plane *plane;
1885         struct drm_plane_state *pstate;
1886         struct vop_plane_state *plane_state;
1887         struct vop_win *win;
1888         int afbdc_format;
1889         int i;
1890
1891         s->afbdc_en = 0;
1892
1893         for_each_plane_in_state(state, plane, pstate, i) {
1894                 struct drm_framebuffer *fb = pstate->fb;
1895                 struct drm_rect *src;
1896
1897                 win = to_vop_win(plane);
1898                 plane_state = to_vop_plane_state(pstate);
1899
1900                 if (pstate->crtc != crtc || !fb)
1901                         continue;
1902
1903                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1904                         continue;
1905
1906                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1907                         DRM_ERROR("not support afbdc\n");
1908                         return -EINVAL;
1909                 }
1910
1911                 switch (plane_state->format) {
1912                 case VOP_FMT_ARGB8888:
1913                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1914                         break;
1915                 case VOP_FMT_RGB888:
1916                         afbdc_format = AFBDC_FMT_U8U8U8;
1917                         break;
1918                 case VOP_FMT_RGB565:
1919                         afbdc_format = AFBDC_FMT_RGB565;
1920                         break;
1921                 default:
1922                         return -EINVAL;
1923                 }
1924
1925                 if (s->afbdc_en) {
1926                         DRM_ERROR("vop only support one afbc layer\n");
1927                         return -EINVAL;
1928                 }
1929
1930                 src = &plane_state->src;
1931                 if (src->x1 || src->y1 || fb->offsets[0]) {
1932                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1933                                   win->win_id);
1934                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1935                                   src->x1, src->y1, fb->offsets[0]);
1936                         return -EINVAL;
1937                 }
1938                 s->afbdc_win_format = afbdc_format;
1939                 s->afbdc_win_width = pstate->fb->width - 1;
1940                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1941                 s->afbdc_win_id = win->win_id;
1942                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1943                 s->afbdc_en = 1;
1944         }
1945
1946         return 0;
1947 }
1948
1949 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1950                                      struct drm_crtc_state *crtc_state)
1951 {
1952         struct rockchip_drm_private *private = crtc->dev->dev_private;
1953         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1954         struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1955         struct vop *vop = to_vop(crtc);
1956         struct rockchip_dclk_pll *old_pll = vop->pll;
1957
1958         if (!vop->dclk_source)
1959                 return;
1960
1961         if (crtc_state->active) {
1962                 WARN_ON(vop->pll && !vop->pll->use_count);
1963                 if (!vop->pll || vop->pll->use_count > 1 ||
1964                     s->output_type != old_s->output_type) {
1965                         if (vop->pll)
1966                                 vop->pll->use_count--;
1967
1968                         if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1969                             !private->default_pll.use_count)
1970                                 vop->pll = &private->default_pll;
1971                         else
1972                                 vop->pll = &private->hdmi_pll;
1973
1974                         vop->pll->use_count++;
1975                 }
1976         } else if (vop->pll) {
1977                 vop->pll->use_count--;
1978                 vop->pll = NULL;
1979         }
1980         if (vop->pll != old_pll)
1981                 crtc_state->mode_changed = true;
1982 }
1983
1984 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1985                                  struct drm_crtc_state *crtc_state)
1986 {
1987         struct drm_atomic_state *state = crtc_state->state;
1988         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1989         struct vop *vop = to_vop(crtc);
1990         const struct vop_data *vop_data = vop->data;
1991         struct drm_plane *plane;
1992         struct drm_plane_state *pstate;
1993         struct vop_plane_state *plane_state;
1994         struct vop_zpos *pzpos;
1995         int dsp_layer_sel = 0;
1996         int i, j, cnt = 0, ret = 0;
1997
1998         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1999         if (ret)
2000                 return ret;
2001
2002         ret = vop_csc_atomic_check(crtc, crtc_state);
2003         if (ret)
2004                 return ret;
2005
2006         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
2007         if (!pzpos)
2008                 return -ENOMEM;
2009
2010         for (i = 0; i < vop_data->win_size; i++) {
2011                 const struct vop_win_data *win_data = &vop_data->win[i];
2012                 struct vop_win *win;
2013
2014                 if (!win_data->phy)
2015                         continue;
2016
2017                 for (j = 0; j < vop->num_wins; j++) {
2018                         win = &vop->win[j];
2019
2020                         if (win->win_id == i && !win->area_id)
2021                                 break;
2022                 }
2023                 if (WARN_ON(j >= vop->num_wins)) {
2024                         ret = -EINVAL;
2025                         goto err_free_pzpos;
2026                 }
2027
2028                 plane = &win->base;
2029                 pstate = state->plane_states[drm_plane_index(plane)];
2030                 /*
2031                  * plane might not have changed, in which case take
2032                  * current state:
2033                  */
2034                 if (!pstate)
2035                         pstate = plane->state;
2036                 plane_state = to_vop_plane_state(pstate);
2037                 pzpos[cnt].zpos = plane_state->zpos;
2038                 pzpos[cnt++].win_id = win->win_id;
2039         }
2040
2041         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
2042
2043         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
2044                 const struct vop_win_data *win_data = &vop_data->win[i];
2045                 int shift = i * 2;
2046
2047                 if (win_data->phy) {
2048                         struct vop_zpos *zpos = &pzpos[cnt++];
2049
2050                         dsp_layer_sel |= zpos->win_id << shift;
2051                 } else {
2052                         dsp_layer_sel |= i << shift;
2053                 }
2054         }
2055
2056         s->dsp_layer_sel = dsp_layer_sel;
2057
2058         vop_dclk_source_generate(crtc, crtc_state);
2059
2060 err_free_pzpos:
2061         kfree(pzpos);
2062         return ret;
2063 }
2064
2065 static void vop_post_config(struct drm_crtc *crtc)
2066 {
2067         struct vop *vop = to_vop(crtc);
2068         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2069         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2070         u16 vtotal = mode->crtc_vtotal;
2071         u16 hdisplay = mode->crtc_hdisplay;
2072         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2073         u16 vdisplay = mode->crtc_vdisplay;
2074         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2075         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
2076         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
2077         u16 hact_end, vact_end;
2078         u32 val;
2079
2080         hact_st += hdisplay * (100 - s->left_margin) / 200;
2081         hact_end = hact_st + hsize;
2082         val = hact_st << 16;
2083         val |= hact_end;
2084         VOP_CTRL_SET(vop, hpost_st_end, val);
2085         vact_st += vdisplay * (100 - s->top_margin) / 200;
2086         vact_end = vact_st + vsize;
2087         val = vact_st << 16;
2088         val |= vact_end;
2089         VOP_CTRL_SET(vop, vpost_st_end, val);
2090         val = scl_cal_scale2(vdisplay, vsize) << 16;
2091         val |= scl_cal_scale2(hdisplay, hsize);
2092         VOP_CTRL_SET(vop, post_scl_factor, val);
2093
2094 #define POST_HORIZONTAL_SCALEDOWN_EN(x)         ((x) << 0)
2095 #define POST_VERTICAL_SCALEDOWN_EN(x)           ((x) << 1)
2096         VOP_CTRL_SET(vop, post_scl_ctrl,
2097                      POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) ||
2098                      POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
2099         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2100                 u16 vact_st_f1 = vtotal + vact_st + 1;
2101                 u16 vact_end_f1 = vact_st_f1 + vsize;
2102
2103                 val = vact_st_f1 << 16 | vact_end_f1;
2104                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2105         }
2106 }
2107
2108 static void vop_update_cabc_lut(struct drm_crtc *crtc,
2109                             struct drm_crtc_state *old_crtc_state)
2110 {
2111         struct rockchip_crtc_state *s =
2112                         to_rockchip_crtc_state(crtc->state);
2113         struct rockchip_crtc_state *old_s =
2114                         to_rockchip_crtc_state(old_crtc_state);
2115         struct drm_property_blob *cabc_lut = s->cabc_lut;
2116         struct drm_property_blob *old_cabc_lut = old_s->cabc_lut;
2117         struct vop *vop = to_vop(crtc);
2118         int lut_size;
2119         u32 *lut;
2120         u32 lut_len = vop->cabc_lut_len;
2121         int i, dle;
2122
2123         if (!cabc_lut && old_cabc_lut) {
2124                 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2125                 return;
2126         }
2127         if (!cabc_lut)
2128                 return;
2129
2130         if (old_cabc_lut && old_cabc_lut->base.id == cabc_lut->base.id)
2131                 return;
2132
2133         lut = (u32 *)cabc_lut->data;
2134         lut_size = cabc_lut->length / sizeof(u32);
2135         if (WARN(lut_size != lut_len, "Unexpect cabc lut size not match\n"))
2136                 return;
2137
2138 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
2139         if (CTRL_GET(cabc_lut_en)) {
2140                 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2141                 vop_cfg_done(vop);
2142                 readx_poll_timeout(CTRL_GET, cabc_lut_en, dle, !dle, 5, 33333);
2143         }
2144
2145         for (i = 0; i < lut_len; i++)
2146                 vop_write_cabc_lut(vop, (i << 2), lut[i]);
2147 #undef CTRL_GET
2148         VOP_CTRL_SET(vop, cabc_lut_en, 1);
2149 }
2150
2151 static void vop_update_cabc(struct drm_crtc *crtc,
2152                             struct drm_crtc_state *old_crtc_state)
2153 {
2154         struct rockchip_crtc_state *s =
2155                         to_rockchip_crtc_state(crtc->state);
2156         struct vop *vop = to_vop(crtc);
2157         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2158         int pixel_total = mode->hdisplay * mode->vdisplay;
2159
2160         if (!vop->cabc_lut_regs)
2161                 return;
2162
2163         vop_update_cabc_lut(crtc, old_crtc_state);
2164
2165         if (s->cabc_mode != ROCKCHIP_DRM_CABC_MODE_DISABLE) {
2166                 VOP_CTRL_SET(vop, cabc_en, 1);
2167                 VOP_CTRL_SET(vop, cabc_handle_en, 1);
2168                 VOP_CTRL_SET(vop, cabc_stage_up, s->cabc_stage_up);
2169                 VOP_CTRL_SET(vop, cabc_stage_down, s->cabc_stage_down);
2170                 VOP_CTRL_SET(vop, cabc_global_dn, s->cabc_global_dn);
2171                 VOP_CTRL_SET(vop, cabc_calc_pixel_num,
2172                              s->cabc_calc_pixel_num * pixel_total / 1000);
2173         } else {
2174                 /*
2175                  * There are some hardware issues on cabc disabling:
2176                  *   1: if cabc auto gating enable, cabc disabling will cause
2177                  *      vop die
2178                  *   2: cabc disabling always would make timing several
2179                  *      pixel cycle abnormal, cause some panel abnormal.
2180                  *
2181                  * So just keep cabc enable, and make it no work with max
2182                  * cabc_calc_pixel_num, it only has little power consume.
2183                  */
2184                 VOP_CTRL_SET(vop, cabc_calc_pixel_num, pixel_total);
2185         }
2186 }
2187
2188 static void vop_cfg_update(struct drm_crtc *crtc,
2189                            struct drm_crtc_state *old_crtc_state)
2190 {
2191         struct rockchip_crtc_state *s =
2192                         to_rockchip_crtc_state(crtc->state);
2193         struct vop *vop = to_vop(crtc);
2194
2195         spin_lock(&vop->reg_lock);
2196
2197         if (s->afbdc_en) {
2198                 uint32_t pic_size;
2199
2200                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2201                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2202                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2203                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2204                 pic_size = (s->afbdc_win_width & 0xffff);
2205                 pic_size |= s->afbdc_win_height << 16;
2206                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2207         }
2208
2209         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2210         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2211         vop_post_config(crtc);
2212
2213         spin_unlock(&vop->reg_lock);
2214 }
2215
2216 static bool vop_fs_irq_is_pending(struct vop *vop)
2217 {
2218         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
2219 }
2220
2221 static void vop_wait_for_irq_handler(struct vop *vop)
2222 {
2223         bool pending;
2224         int ret;
2225
2226         /*
2227          * Spin until frame start interrupt status bit goes low, which means
2228          * that interrupt handler was invoked and cleared it. The timeout of
2229          * 10 msecs is really too long, but it is just a safety measure if
2230          * something goes really wrong. The wait will only happen in the very
2231          * unlikely case of a vblank happening exactly at the same time and
2232          * shouldn't exceed microseconds range.
2233          */
2234         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
2235                                         !pending, 0, 10 * 1000);
2236         if (ret)
2237                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
2238
2239         synchronize_irq(vop->irq);
2240 }
2241
2242 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2243                                   struct drm_crtc_state *old_crtc_state)
2244 {
2245         struct drm_atomic_state *old_state = old_crtc_state->state;
2246         struct drm_plane_state *old_plane_state;
2247         struct vop *vop = to_vop(crtc);
2248         struct drm_plane *plane;
2249         int i;
2250
2251         vop_cfg_update(crtc, old_crtc_state);
2252
2253         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2254                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2255                 int ret;
2256
2257                 if (need_wait_vblank) {
2258                         bool active;
2259
2260                         disable_irq(vop->irq);
2261                         drm_crtc_vblank_get(crtc);
2262                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2263
2264                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2265                                                         vop, active, active,
2266                                                         0, 50 * 1000);
2267                         if (ret)
2268                                 dev_err(vop->dev, "wait fs irq timeout\n");
2269
2270                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2271                         vop_cfg_done(vop);
2272
2273                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2274                                                         vop, active, active,
2275                                                         0, 50 * 1000);
2276                         if (ret)
2277                                 dev_err(vop->dev, "wait line flag timeout\n");
2278
2279                         enable_irq(vop->irq);
2280                 }
2281                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2282                 if (ret)
2283                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2284                                 ret);
2285
2286                 if (need_wait_vblank) {
2287                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2288                         drm_crtc_vblank_put(crtc);
2289                 }
2290
2291                 vop->is_iommu_enabled = true;
2292         }
2293
2294         vop_update_cabc(crtc, old_crtc_state);
2295
2296         vop_cfg_done(vop);
2297
2298         /*
2299          * There is a (rather unlikely) possiblity that a vblank interrupt
2300          * fired before we set the cfg_done bit. To avoid spuriously
2301          * signalling flip completion we need to wait for it to finish.
2302          */
2303         vop_wait_for_irq_handler(vop);
2304
2305         spin_lock_irq(&crtc->dev->event_lock);
2306         if (crtc->state->event) {
2307                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2308                 WARN_ON(vop->event);
2309
2310                 vop->event = crtc->state->event;
2311                 crtc->state->event = NULL;
2312         }
2313         spin_unlock_irq(&crtc->dev->event_lock);
2314
2315         for_each_plane_in_state(old_state, plane, old_plane_state, i) {
2316                 if (!old_plane_state->fb)
2317                         continue;
2318
2319                 if (old_plane_state->fb == plane->state->fb)
2320                         continue;
2321
2322                 drm_framebuffer_reference(old_plane_state->fb);
2323                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
2324                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
2325                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2326         }
2327 }
2328
2329 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2330                                   struct drm_crtc_state *old_crtc_state)
2331 {
2332 }
2333
2334 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2335         .load_lut = vop_crtc_load_lut,
2336         .enable = vop_crtc_enable,
2337         .disable = vop_crtc_disable,
2338         .mode_fixup = vop_crtc_mode_fixup,
2339         .atomic_check = vop_crtc_atomic_check,
2340         .atomic_flush = vop_crtc_atomic_flush,
2341         .atomic_begin = vop_crtc_atomic_begin,
2342 };
2343
2344 static void vop_crtc_destroy(struct drm_crtc *crtc)
2345 {
2346         drm_crtc_cleanup(crtc);
2347 }
2348
2349 static void vop_crtc_reset(struct drm_crtc *crtc)
2350 {
2351         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2352
2353         if (crtc->state) {
2354                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2355                 kfree(s);
2356         }
2357
2358         s = kzalloc(sizeof(*s), GFP_KERNEL);
2359         if (!s)
2360                 return;
2361         crtc->state = &s->base;
2362         crtc->state->crtc = crtc;
2363
2364         s->left_margin = 100;
2365         s->right_margin = 100;
2366         s->top_margin = 100;
2367         s->bottom_margin = 100;
2368 }
2369
2370 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2371 {
2372         struct rockchip_crtc_state *rockchip_state, *old_state;
2373
2374         old_state = to_rockchip_crtc_state(crtc->state);
2375         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2376         if (!rockchip_state)
2377                 return NULL;
2378
2379         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2380         return &rockchip_state->base;
2381 }
2382
2383 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2384                                    struct drm_crtc_state *state)
2385 {
2386         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2387
2388         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2389         kfree(s);
2390 }
2391
2392 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2393                                         const struct drm_crtc_state *state,
2394                                         struct drm_property *property,
2395                                         uint64_t *val)
2396 {
2397         struct drm_device *drm_dev = crtc->dev;
2398         struct rockchip_drm_private *private = drm_dev->dev_private;
2399         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2400         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2401
2402         if (property == mode_config->tv_left_margin_property) {
2403                 *val = s->left_margin;
2404                 return 0;
2405         }
2406
2407         if (property == mode_config->tv_right_margin_property) {
2408                 *val = s->right_margin;
2409                 return 0;
2410         }
2411
2412         if (property == mode_config->tv_top_margin_property) {
2413                 *val = s->top_margin;
2414                 return 0;
2415         }
2416
2417         if (property == mode_config->tv_bottom_margin_property) {
2418                 *val = s->bottom_margin;
2419                 return 0;
2420         }
2421
2422         if (property == private->cabc_mode_property) {
2423                 *val = s->cabc_mode;
2424                 return 0;
2425         }
2426
2427         if (property == private->cabc_stage_up_property) {
2428                 *val = s->cabc_stage_up;
2429                 return 0;
2430         }
2431
2432         if (property == private->cabc_stage_down_property) {
2433                 *val = s->cabc_stage_down;
2434                 return 0;
2435         }
2436
2437         if (property == private->cabc_global_dn_property) {
2438                 *val = s->cabc_global_dn;
2439                 return 0;
2440         }
2441
2442         if (property == private->cabc_calc_pixel_num_property) {
2443                 *val = s->cabc_calc_pixel_num;
2444                 return 0;
2445         }
2446
2447         if (property == private->cabc_lut_property) {
2448                 *val = s->cabc_lut ? s->cabc_lut->base.id : 0;
2449                 return 0;
2450         }
2451
2452         DRM_ERROR("failed to get vop crtc property\n");
2453         return -EINVAL;
2454 }
2455
2456 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2457                                         struct drm_crtc_state *state,
2458                                         struct drm_property *property,
2459                                         uint64_t val)
2460 {
2461         struct drm_device *drm_dev = crtc->dev;
2462         struct rockchip_drm_private *private = drm_dev->dev_private;
2463         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2464         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2465         struct vop *vop = to_vop(crtc);
2466
2467         if (property == mode_config->tv_left_margin_property) {
2468                 s->left_margin = val;
2469                 return 0;
2470         }
2471
2472         if (property == mode_config->tv_right_margin_property) {
2473                 s->right_margin = val;
2474                 return 0;
2475         }
2476
2477         if (property == mode_config->tv_top_margin_property) {
2478                 s->top_margin = val;
2479                 return 0;
2480         }
2481
2482         if (property == mode_config->tv_bottom_margin_property) {
2483                 s->bottom_margin = val;
2484                 return 0;
2485         }
2486
2487         if (property == private->cabc_mode_property) {
2488                 s->cabc_mode = val;
2489                 /*
2490                  * Pre-define lowpower and normal mode to make cabc
2491                  * easier to use.
2492                  */
2493                 if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_NORMAL) {
2494                         s->cabc_stage_up = 257;
2495                         s->cabc_stage_down = 255;
2496                         s->cabc_global_dn = 192;
2497                         s->cabc_calc_pixel_num = 995;
2498                 } else if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_LOWPOWER) {
2499                         s->cabc_stage_up = 260;
2500                         s->cabc_stage_down = 252;
2501                         s->cabc_global_dn = 180;
2502                         s->cabc_calc_pixel_num = 992;
2503                 }
2504                 return 0;
2505         }
2506
2507         if (property == private->cabc_stage_up_property) {
2508                 s->cabc_stage_up = val;
2509                 return 0;
2510         }
2511
2512         if (property == private->cabc_stage_down_property) {
2513                 s->cabc_stage_down = val;
2514                 return 0;
2515         }
2516
2517         if (property == private->cabc_calc_pixel_num_property) {
2518                 s->cabc_calc_pixel_num = val;
2519                 return 0;
2520         }
2521
2522         if (property == private->cabc_global_dn_property) {
2523                 s->cabc_global_dn = val;
2524                 return 0;
2525         }
2526
2527         if (property == private->cabc_lut_property) {
2528                 bool replaced;
2529                 ssize_t size = vop->cabc_lut_len * 4;
2530
2531                 return drm_atomic_replace_property_blob_from_id(crtc,
2532                                                                 &s->cabc_lut,
2533                                                                 val,
2534                                                                 size,
2535                                                                 &replaced);
2536         }
2537
2538         DRM_ERROR("failed to set vop crtc property\n");
2539         return -EINVAL;
2540 }
2541
2542 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2543                                u16 *blue, uint32_t start, uint32_t size)
2544 {
2545         struct vop *vop = to_vop(crtc);
2546         int end = min_t(u32, start + size, vop->lut_len);
2547         int i;
2548
2549         if (!vop->lut)
2550                 return;
2551
2552         for (i = start; i < end; i++)
2553                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2554                                                blue[i], i);
2555
2556         vop_crtc_load_lut(crtc);
2557 }
2558
2559 static const struct drm_crtc_funcs vop_crtc_funcs = {
2560         .gamma_set = vop_crtc_gamma_set,
2561         .set_config = drm_atomic_helper_set_config,
2562         .page_flip = drm_atomic_helper_page_flip,
2563         .destroy = vop_crtc_destroy,
2564         .reset = vop_crtc_reset,
2565         .set_property = drm_atomic_helper_crtc_set_property,
2566         .atomic_get_property = vop_crtc_atomic_get_property,
2567         .atomic_set_property = vop_crtc_atomic_set_property,
2568         .atomic_duplicate_state = vop_crtc_duplicate_state,
2569         .atomic_destroy_state = vop_crtc_destroy_state,
2570 };
2571
2572 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
2573 {
2574         struct vop *vop = container_of(work, struct vop, fb_unref_work);
2575         struct drm_framebuffer *fb = val;
2576
2577         drm_crtc_vblank_put(&vop->crtc);
2578         drm_framebuffer_unreference(fb);
2579 }
2580
2581 static void vop_handle_vblank(struct vop *vop)
2582 {
2583         struct drm_device *drm = vop->drm_dev;
2584         struct drm_crtc *crtc = &vop->crtc;
2585         unsigned long flags;
2586
2587         if (vop->event) {
2588                 spin_lock_irqsave(&drm->event_lock, flags);
2589
2590                 drm_crtc_send_vblank_event(crtc, vop->event);
2591                 drm_crtc_vblank_put(crtc);
2592                 vop->event = NULL;
2593
2594                 spin_unlock_irqrestore(&drm->event_lock, flags);
2595         }
2596
2597         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
2598                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2599 }
2600
2601 static irqreturn_t vop_isr(int irq, void *data)
2602 {
2603         struct vop *vop = data;
2604         struct drm_crtc *crtc = &vop->crtc;
2605         uint32_t active_irqs;
2606         unsigned long flags;
2607         int ret = IRQ_NONE;
2608
2609         /*
2610          * interrupt register has interrupt status, enable and clear bits, we
2611          * must hold irq_lock to avoid a race with enable/disable_vblank().
2612         */
2613         spin_lock_irqsave(&vop->irq_lock, flags);
2614
2615         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2616         /* Clear all active interrupt sources */
2617         if (active_irqs)
2618                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2619
2620         spin_unlock_irqrestore(&vop->irq_lock, flags);
2621
2622         /* This is expected for vop iommu irqs, since the irq is shared */
2623         if (!active_irqs)
2624                 return IRQ_NONE;
2625
2626         if (active_irqs & DSP_HOLD_VALID_INTR) {
2627                 complete(&vop->dsp_hold_completion);
2628                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2629                 ret = IRQ_HANDLED;
2630         }
2631
2632         if (active_irqs & LINE_FLAG_INTR) {
2633                 complete(&vop->line_flag_completion);
2634                 active_irqs &= ~LINE_FLAG_INTR;
2635                 ret = IRQ_HANDLED;
2636         }
2637
2638         if (active_irqs & FS_INTR) {
2639                 drm_crtc_handle_vblank(crtc);
2640                 vop_handle_vblank(vop);
2641                 active_irqs &= ~FS_INTR;
2642                 ret = IRQ_HANDLED;
2643         }
2644
2645 #define ERROR_HANDLER(x) \
2646         do { \
2647                 if (active_irqs & x##_INTR) {\
2648                         DRM_DEV_ERROR_RATELIMITED(vop->dev, #x " irq err\n"); \
2649                         active_irqs &= ~x##_INTR; \
2650                         ret = IRQ_HANDLED; \
2651                 } \
2652         } while (0)
2653
2654         ERROR_HANDLER(BUS_ERROR);
2655         ERROR_HANDLER(WIN0_EMPTY);
2656         ERROR_HANDLER(WIN1_EMPTY);
2657         ERROR_HANDLER(WIN2_EMPTY);
2658         ERROR_HANDLER(WIN3_EMPTY);
2659         ERROR_HANDLER(HWC_EMPTY);
2660         ERROR_HANDLER(POST_BUF_EMPTY);
2661
2662         /* Unhandled irqs are spurious. */
2663         if (active_irqs)
2664                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2665
2666         return ret;
2667 }
2668
2669 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2670                           unsigned long possible_crtcs)
2671 {
2672         struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2673         struct drm_plane *share = NULL;
2674         unsigned int rotations = 0;
2675         struct drm_property *prop;
2676         uint64_t feature = 0;
2677         int ret;
2678
2679         if (win->parent)
2680                 share = &win->parent->base;
2681
2682         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2683                                    possible_crtcs, &vop_plane_funcs,
2684                                    win->data_formats, win->nformats, win->type);
2685         if (ret) {
2686                 DRM_ERROR("failed to initialize plane\n");
2687                 return ret;
2688         }
2689         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2690         drm_object_attach_property(&win->base.base,
2691                                    vop->plane_zpos_prop, win->win_id);
2692
2693         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2694                 rotations |= BIT(DRM_REFLECT_X);
2695
2696         if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2697                 rotations |= BIT(DRM_REFLECT_Y);
2698
2699                 prop = drm_property_create_bool(vop->drm_dev,
2700                                                 DRM_MODE_PROP_ATOMIC,
2701                                                 "LOGO_YMIRROR");
2702                 if (!prop)
2703                         return -ENOMEM;
2704                 private->logo_ymirror_prop = prop;
2705         }
2706
2707         if (rotations) {
2708                 rotations |= BIT(DRM_ROTATE_0);
2709                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2710                                                          rotations);
2711                 if (!prop) {
2712                         DRM_ERROR("failed to create zpos property\n");
2713                         return -EINVAL;
2714                 }
2715                 drm_object_attach_property(&win->base.base, prop,
2716                                            BIT(DRM_ROTATE_0));
2717                 win->rotation_prop = prop;
2718         }
2719         if (win->phy->scl)
2720                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2721         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2722             VOP_WIN_SUPPORT(vop, win, alpha_en))
2723                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2724
2725         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2726                                    feature);
2727
2728         return 0;
2729 }
2730
2731 static int vop_create_crtc(struct vop *vop)
2732 {
2733         struct device *dev = vop->dev;
2734         const struct vop_data *vop_data = vop->data;
2735         struct drm_device *drm_dev = vop->drm_dev;
2736         struct rockchip_drm_private *private = drm_dev->dev_private;
2737         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2738         struct drm_crtc *crtc = &vop->crtc;
2739         struct device_node *port;
2740         uint64_t feature = 0;
2741         int ret;
2742         int i;
2743
2744         /*
2745          * Create drm_plane for primary and cursor planes first, since we need
2746          * to pass them to drm_crtc_init_with_planes, which sets the
2747          * "possible_crtcs" to the newly initialized crtc.
2748          */
2749         for (i = 0; i < vop->num_wins; i++) {
2750                 struct vop_win *win = &vop->win[i];
2751
2752                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2753                     win->type != DRM_PLANE_TYPE_CURSOR)
2754                         continue;
2755
2756                 ret = vop_plane_init(vop, win, 0);
2757                 if (ret)
2758                         goto err_cleanup_planes;
2759
2760                 plane = &win->base;
2761                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2762                         primary = plane;
2763                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2764                         cursor = plane;
2765
2766         }
2767
2768         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2769                                         &vop_crtc_funcs, NULL);
2770         if (ret)
2771                 goto err_cleanup_planes;
2772
2773         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2774
2775         /*
2776          * Create drm_planes for overlay windows with possible_crtcs restricted
2777          * to the newly created crtc.
2778          */
2779         for (i = 0; i < vop->num_wins; i++) {
2780                 struct vop_win *win = &vop->win[i];
2781                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2782
2783                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2784                         continue;
2785
2786                 ret = vop_plane_init(vop, win, possible_crtcs);
2787                 if (ret)
2788                         goto err_cleanup_crtc;
2789         }
2790
2791         port = of_get_child_by_name(dev->of_node, "port");
2792         if (!port) {
2793                 DRM_ERROR("no port node found in %s\n",
2794                           dev->of_node->full_name);
2795                 ret = -ENOENT;
2796                 goto err_cleanup_crtc;
2797         }
2798
2799         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
2800                            vop_fb_unref_worker);
2801
2802         init_completion(&vop->dsp_hold_completion);
2803         init_completion(&vop->line_flag_completion);
2804         crtc->port = port;
2805         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2806
2807         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2808         if (ret)
2809                 goto err_unregister_crtc_funcs;
2810 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2811         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2812
2813         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2814         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2815         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2816         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2817
2818 #undef VOP_ATTACH_MODE_CONFIG_PROP
2819
2820         drm_object_attach_property(&crtc->base, private->cabc_lut_property, 0);
2821         drm_object_attach_property(&crtc->base, private->cabc_mode_property, 0);
2822         drm_object_attach_property(&crtc->base, private->cabc_stage_up_property, 0);
2823         drm_object_attach_property(&crtc->base, private->cabc_stage_down_property, 0);
2824         drm_object_attach_property(&crtc->base, private->cabc_global_dn_property, 0);
2825         drm_object_attach_property(&crtc->base, private->cabc_calc_pixel_num_property, 0);
2826
2827         if (vop_data->feature & VOP_FEATURE_AFBDC)
2828                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2829         drm_object_attach_property(&crtc->base, vop->feature_prop,
2830                                    feature);
2831         if (vop->lut_regs) {
2832                 u16 *r_base, *g_base, *b_base;
2833                 u32 lut_len = vop->lut_len;
2834
2835                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2836                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2837                                               GFP_KERNEL);
2838                 if (!vop->lut)
2839                         return -ENOMEM;
2840
2841                 r_base = crtc->gamma_store;
2842                 g_base = r_base + crtc->gamma_size;
2843                 b_base = g_base + crtc->gamma_size;
2844
2845                 for (i = 0; i < lut_len; i++) {
2846                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2847                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2848                                                        &g_base[i], &b_base[i],
2849                                                        i);
2850                 }
2851         }
2852
2853         return 0;
2854
2855 err_unregister_crtc_funcs:
2856         rockchip_unregister_crtc_funcs(crtc);
2857 err_cleanup_crtc:
2858         drm_crtc_cleanup(crtc);
2859 err_cleanup_planes:
2860         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2861                                  head)
2862                 drm_plane_cleanup(plane);
2863         return ret;
2864 }
2865
2866 static void vop_destroy_crtc(struct vop *vop)
2867 {
2868         struct drm_crtc *crtc = &vop->crtc;
2869         struct drm_device *drm_dev = vop->drm_dev;
2870         struct drm_plane *plane, *tmp;
2871
2872         rockchip_unregister_crtc_funcs(crtc);
2873         of_node_put(crtc->port);
2874
2875         /*
2876          * We need to cleanup the planes now.  Why?
2877          *
2878          * The planes are "&vop->win[i].base".  That means the memory is
2879          * all part of the big "struct vop" chunk of memory.  That memory
2880          * was devm allocated and associated with this component.  We need to
2881          * free it ourselves before vop_unbind() finishes.
2882          */
2883         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2884                                  head)
2885                 vop_plane_destroy(plane);
2886
2887         /*
2888          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2889          * references the CRTC.
2890          */
2891         drm_crtc_cleanup(crtc);
2892         drm_flip_work_cleanup(&vop->fb_unref_work);
2893 }
2894
2895 /*
2896  * Initialize the vop->win array elements.
2897  */
2898 static int vop_win_init(struct vop *vop)
2899 {
2900         const struct vop_data *vop_data = vop->data;
2901         unsigned int i, j;
2902         unsigned int num_wins = 0;
2903         struct drm_property *prop;
2904         static const struct drm_prop_enum_list props[] = {
2905                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2906                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2907         };
2908         static const struct drm_prop_enum_list crtc_props[] = {
2909                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2910         };
2911
2912         for (i = 0; i < vop_data->win_size; i++) {
2913                 struct vop_win *vop_win = &vop->win[num_wins];
2914                 const struct vop_win_data *win_data = &vop_data->win[i];
2915
2916                 if (!win_data->phy)
2917                         continue;
2918
2919                 vop_win->phy = win_data->phy;
2920                 vop_win->csc = win_data->csc;
2921                 vop_win->offset = win_data->base;
2922                 vop_win->type = win_data->type;
2923                 vop_win->data_formats = win_data->phy->data_formats;
2924                 vop_win->nformats = win_data->phy->nformats;
2925                 vop_win->vop = vop;
2926                 vop_win->win_id = i;
2927                 vop_win->area_id = 0;
2928                 num_wins++;
2929
2930                 for (j = 0; j < win_data->area_size; j++) {
2931                         struct vop_win *vop_area = &vop->win[num_wins];
2932                         const struct vop_win_phy *area = win_data->area[j];
2933
2934                         vop_area->parent = vop_win;
2935                         vop_area->offset = vop_win->offset;
2936                         vop_area->phy = area;
2937                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2938                         vop_area->data_formats = vop_win->data_formats;
2939                         vop_area->nformats = vop_win->nformats;
2940                         vop_area->vop = vop;
2941                         vop_area->win_id = i;
2942                         vop_area->area_id = j;
2943                         num_wins++;
2944                 }
2945         }
2946
2947         vop->num_wins = num_wins;
2948
2949         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2950                                          "ZPOS", 0, vop->data->win_size);
2951         if (!prop) {
2952                 DRM_ERROR("failed to create zpos property\n");
2953                 return -EINVAL;
2954         }
2955         vop->plane_zpos_prop = prop;
2956
2957         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2958                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2959                                 props, ARRAY_SIZE(props),
2960                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2961                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2962         if (!vop->plane_feature_prop) {
2963                 DRM_ERROR("failed to create feature property\n");
2964                 return -EINVAL;
2965         }
2966
2967         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2968                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2969                                 crtc_props, ARRAY_SIZE(crtc_props),
2970                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2971         if (!vop->feature_prop) {
2972                 DRM_ERROR("failed to create vop feature property\n");
2973                 return -EINVAL;
2974         }
2975
2976         return 0;
2977 }
2978
2979 /**
2980  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2981  * @crtc: CRTC to enable line flag
2982  * @line_num: interested line number
2983  * @mstimeout: millisecond for timeout
2984  *
2985  * Driver would hold here until the interested line flag interrupt have
2986  * happened or timeout to wait.
2987  *
2988  * Returns:
2989  * Zero on success, negative errno on failure.
2990  */
2991 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2992                                 unsigned int mstimeout)
2993 {
2994         struct vop *vop = to_vop(crtc);
2995         unsigned long jiffies_left;
2996         int ret = 0;
2997
2998         if (!crtc || !vop->is_enabled)
2999                 return -ENODEV;
3000
3001         mutex_lock(&vop->vop_lock);
3002
3003         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
3004                 ret = -EINVAL;
3005                 goto out;
3006         }
3007
3008         if (vop_line_flag_irq_is_enabled(vop)) {
3009                 ret = -EBUSY;
3010                 goto out;
3011         }
3012
3013         reinit_completion(&vop->line_flag_completion);
3014         vop_line_flag_irq_enable(vop, line_num);
3015
3016         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
3017                                                    msecs_to_jiffies(mstimeout));
3018         vop_line_flag_irq_disable(vop);
3019
3020         if (jiffies_left == 0) {
3021                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
3022                 ret = -ETIMEDOUT;
3023                 goto out;
3024         }
3025
3026 out:
3027         mutex_unlock(&vop->vop_lock);
3028
3029         return ret;
3030 }
3031 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
3032
3033 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
3034                              void *data)
3035 {
3036         if (event == DEVFREQ_PRECHANGE)
3037                 mutex_lock(&dmc_vop->vop_lock);
3038         else if (event == DEVFREQ_POSTCHANGE)
3039                 mutex_unlock(&dmc_vop->vop_lock);
3040
3041         return NOTIFY_OK;
3042 }
3043
3044 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
3045 {
3046         if (!dmc_vop)
3047                 return -ENOMEM;
3048
3049         dmc_vop->devfreq = devfreq;
3050         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
3051         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
3052                                   DEVFREQ_TRANSITION_NOTIFIER);
3053         return 0;
3054 }
3055 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
3056
3057 static void vop_backlight_config_done(struct device *dev, bool async)
3058 {
3059         struct vop *vop = dev_get_drvdata(dev);
3060
3061         if (vop && vop->is_enabled) {
3062                 int dle;
3063
3064                 vop_cfg_done(vop);
3065                 if (!async) {
3066                         #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
3067                         readx_poll_timeout(CTRL_GET, cfg_done,
3068                                            dle, !dle, 5, 33333);
3069                         #undef CTRL_GET
3070                 }
3071         }
3072 }
3073
3074 static const struct rockchip_sub_backlight_ops rockchip_sub_backlight_ops = {
3075         .config_done = vop_backlight_config_done,
3076 };
3077
3078 static int vop_bind(struct device *dev, struct device *master, void *data)
3079 {
3080         struct platform_device *pdev = to_platform_device(dev);
3081         const struct vop_data *vop_data;
3082         struct drm_device *drm_dev = data;
3083         struct vop *vop;
3084         struct resource *res;
3085         size_t alloc_size;
3086         int ret, irq, i;
3087         int num_wins = 0;
3088
3089         vop_data = of_device_get_match_data(dev);
3090         if (!vop_data)
3091                 return -ENODEV;
3092
3093         for (i = 0; i < vop_data->win_size; i++) {
3094                 const struct vop_win_data *win_data = &vop_data->win[i];
3095
3096                 num_wins += win_data->area_size + 1;
3097         }
3098
3099         /* Allocate vop struct and its vop_win array */
3100         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
3101         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3102         if (!vop)
3103                 return -ENOMEM;
3104
3105         vop->dev = dev;
3106         vop->data = vop_data;
3107         vop->drm_dev = drm_dev;
3108         vop->num_wins = num_wins;
3109         dev_set_drvdata(dev, vop);
3110
3111         ret = vop_win_init(vop);
3112         if (ret)
3113                 return ret;
3114
3115         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3116         if (!res) {
3117                 dev_warn(vop->dev, "failed to get vop register byname\n");
3118                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3119         }
3120         vop->regs = devm_ioremap_resource(dev, res);
3121         if (IS_ERR(vop->regs))
3122                 return PTR_ERR(vop->regs);
3123         vop->len = resource_size(res);
3124
3125         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
3126         if (!vop->regsbak)
3127                 return -ENOMEM;
3128
3129         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
3130         vop->lut_regs = devm_ioremap_resource(dev, res);
3131         if (IS_ERR(vop->lut_regs)) {
3132                 dev_warn(vop->dev, "failed to get vop lut registers\n");
3133                 vop->lut_regs = NULL;
3134         }
3135         if (vop->lut_regs) {
3136                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
3137                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
3138                         dev_err(vop->dev, "unsupport lut sizes %d\n",
3139                                 vop->lut_len);
3140                         return -EINVAL;
3141                 }
3142         }
3143
3144         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cabc_lut");
3145         vop->cabc_lut_regs = devm_ioremap_resource(dev, res);
3146         if (IS_ERR(vop->cabc_lut_regs)) {
3147                 dev_warn(vop->dev, "failed to get vop cabc lut registers\n");
3148                 vop->cabc_lut_regs = NULL;
3149         }
3150
3151         if (vop->cabc_lut_regs) {
3152                 vop->cabc_lut_len = resource_size(res) >> 2;
3153                 if (vop->cabc_lut_len != 128) {
3154                         dev_err(vop->dev, "unsupport cabc lut sizes %d\n",
3155                                 vop->cabc_lut_len);
3156                         return -EINVAL;
3157                 }
3158         }
3159
3160         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
3161         if (IS_ERR(vop->hclk)) {
3162                 dev_err(vop->dev, "failed to get hclk source\n");
3163                 return PTR_ERR(vop->hclk);
3164         }
3165         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
3166         if (IS_ERR(vop->aclk)) {
3167                 dev_err(vop->dev, "failed to get aclk source\n");
3168                 return PTR_ERR(vop->aclk);
3169         }
3170         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
3171         if (IS_ERR(vop->dclk)) {
3172                 dev_err(vop->dev, "failed to get dclk source\n");
3173                 return PTR_ERR(vop->dclk);
3174         }
3175
3176         vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
3177         if (PTR_ERR(vop->dclk_source) == -ENOENT) {
3178                 vop->dclk_source = NULL;
3179         } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
3180                 return -EPROBE_DEFER;
3181         } else if (IS_ERR(vop->dclk_source)) {
3182                 dev_err(vop->dev, "failed to get dclk source parent\n");
3183                 return PTR_ERR(vop->dclk_source);
3184         }
3185
3186         irq = platform_get_irq(pdev, 0);
3187         if (irq < 0) {
3188                 dev_err(dev, "cannot find irq for vop\n");
3189                 return irq;
3190         }
3191         vop->irq = (unsigned int)irq;
3192
3193         spin_lock_init(&vop->reg_lock);
3194         spin_lock_init(&vop->irq_lock);
3195         mutex_init(&vop->vop_lock);
3196
3197         mutex_init(&vop->vsync_mutex);
3198
3199         ret = devm_request_irq(dev, vop->irq, vop_isr,
3200                                IRQF_SHARED, dev_name(dev), vop);
3201         if (ret)
3202                 return ret;
3203
3204         /* IRQ is initially disabled; it gets enabled in power_on */
3205         disable_irq(vop->irq);
3206
3207         ret = vop_create_crtc(vop);
3208         if (ret)
3209                 return ret;
3210
3211         pm_runtime_enable(&pdev->dev);
3212
3213         of_rockchip_drm_sub_backlight_register(dev, &vop->crtc,
3214                                                &rockchip_sub_backlight_ops);
3215
3216         dmc_vop = vop;
3217
3218         return 0;
3219 }
3220
3221 static void vop_unbind(struct device *dev, struct device *master, void *data)
3222 {
3223         struct vop *vop = dev_get_drvdata(dev);
3224
3225         pm_runtime_disable(dev);
3226         vop_destroy_crtc(vop);
3227 }
3228
3229 const struct component_ops vop_component_ops = {
3230         .bind = vop_bind,
3231         .unbind = vop_unbind,
3232 };
3233 EXPORT_SYMBOL_GPL(vop_component_ops);