drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22
  23 #include <linux/devfreq.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/iopoll.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/component.h>
  34
  35 #include <linux/reset.h>
  36 #include <linux/delay.h>
  37 #include <linux/sort.h>
  38 #include <uapi/drm/rockchip_drm.h>
  39
  40 #include "rockchip_drm_drv.h"
  41 #include "rockchip_drm_gem.h"
  42 #include "rockchip_drm_fb.h"
  43 #include "rockchip_drm_vop.h"
  44
  45 #define VOP_REG_SUPPORT(vop, reg) \
  46                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  47                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  48                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  49                 reg.mask))
  50
  51 #define VOP_WIN_SUPPORT(vop, win, name) \
  52                 VOP_REG_SUPPORT(vop, win->phy->name)
  53
  54 #define VOP_CTRL_SUPPORT(vop, name) \
  55                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  56
  57 #define VOP_INTR_SUPPORT(vop, name) \
  58                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  59
  60 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  61                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  62
  63 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  64         do { \
  65                 if (VOP_REG_SUPPORT(vop, reg)) \
  66                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  67                                   v, reg.write_mask, relaxed); \
  68                 else \
  69                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  70         } while(0)
  71
  72 #define REG_SET(x, name, off, reg, v, relaxed) \
  73                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  74 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  75                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  76
  77 #define VOP_WIN_SET(x, win, name, v) \
  78                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  79 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  80                 REG_SET(x, name, 0, win->ext->name, v, true)
  81 #define VOP_SCL_SET(x, win, name, v) \
  82                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  83 #define VOP_SCL_SET_EXT(x, win, name, v) \
  84                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  85
  86 #define VOP_CTRL_SET(x, name, v) \
  87                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  88
  89 #define VOP_INTR_GET(vop, name) \
  90                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  91
  92 #define VOP_INTR_SET(vop, name, v) \
  93                 REG_SET(vop, name, 0, vop->data->intr->name, \
  94                         v, false)
  95 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  96                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  97                              mask, v, false)
  98
  99 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
 100         do { \
 101                 int i, reg = 0, mask = 0; \
 102                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 103                         if (vop->data->intr->intrs[i] & type) { \
 104                                 reg |= (v) << i; \
 105                                 mask |= 1 << i; \
 106                         } \
 107                 } \
 108                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 109         } while (0)
 110 #define VOP_INTR_GET_TYPE(vop, name, type) \
 111                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 112
 113 #define VOP_CTRL_GET(x, name) \
 114                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 115
 116 #define VOP_WIN_GET(x, win, name) \
 117                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 118
 119 #define VOP_WIN_NAME(win, name) \
 120                 (vop_get_win_phy(win, &win->phy->name)->name)
 121
 122 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 123                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 124
 125 #define to_vop(x) container_of(x, struct vop, crtc)
 126 #define to_vop_win(x) container_of(x, struct vop_win, base)
 127 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 128
 129 struct vop_zpos {
 130         int win_id;
 131         int zpos;
 132 };
 133
 134 enum vop_pending {
 135         VOP_PENDING_FB_UNREF,
 136 };
 137
 138 struct vop_plane_state {
 139         struct drm_plane_state base;
 140         int format;
 141         int zpos;
 142         unsigned int logo_ymirror;
 143         struct drm_rect src;
 144         struct drm_rect dest;
 145         dma_addr_t yrgb_mst;
 146         dma_addr_t uv_mst;
 147         const uint32_t *y2r_table;
 148         const uint32_t *r2r_table;
 149         const uint32_t *r2y_table;
 150         bool enable;
 151 };
 152
 153 struct vop_win {
 154         struct vop_win *parent;
 155         struct drm_plane base;
 156
 157         int win_id;
 158         int area_id;
 159         uint32_t offset;
 160         enum drm_plane_type type;
 161         const struct vop_win_phy *phy;
 162         const struct vop_csc *csc;
 163         const uint32_t *data_formats;
 164         uint32_t nformats;
 165         struct vop *vop;
 166
 167         struct drm_property *rotation_prop;
 168         struct vop_plane_state state;
 169 };
 170
 171 struct vop {
 172         struct drm_crtc crtc;
 173         struct device *dev;
 174         struct drm_device *drm_dev;
 175         struct drm_property *plane_zpos_prop;
 176         struct drm_property *plane_feature_prop;
 177         struct drm_property *feature_prop;
 178         bool is_iommu_enabled;
 179         bool is_iommu_needed;
 180         bool is_enabled;
 181
 182         /* mutex vsync_ work */
 183         struct mutex vsync_mutex;
 184         bool vsync_work_pending;
 185         bool loader_protect;
 186         struct completion dsp_hold_completion;
 187
 188         /* protected by dev->event_lock */
 189         struct drm_pending_vblank_event *event;
 190
 191         struct drm_flip_work fb_unref_work;
 192         unsigned long pending;
 193
 194         struct completion line_flag_completion;
 195
 196         const struct vop_data *data;
 197         int num_wins;
 198
 199         uint32_t *regsbak;
 200         void __iomem *regs;
 201
 202         /* physical map length of vop register */
 203         uint32_t len;
 204
 205         void __iomem *lut_regs;
 206         u32 *lut;
 207         u32 lut_len;
 208         bool lut_active;
 209
 210         /* one time only one process allowed to config the register */
 211         spinlock_t reg_lock;
 212         /* lock vop irq reg */
 213         spinlock_t irq_lock;
 214         /* mutex vop enable and disable */
 215         struct mutex vop_lock;
 216
 217         unsigned int irq;
 218
 219         /* vop AHP clk */
 220         struct clk *hclk;
 221         /* vop dclk */
 222         struct clk *dclk;
 223         /* vop share memory frequency */
 224         struct clk *aclk;
 225         /* vop source handling, optional */
 226         struct clk *dclk_source;
 227
 228         /* vop dclk reset */
 229         struct reset_control *dclk_rst;
 230
 231         struct devfreq *devfreq;
 232         struct notifier_block dmc_nb;
 233
 234         struct vop_win win[];
 235 };
 236
 237 struct vop *dmc_vop;
 238
 239 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 240 {
 241         writel(v, vop->regs + offset);
 242         vop->regsbak[offset >> 2] = v;
 243 }
 244
 245 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 246 {
 247         return readl(vop->regs + offset);
 248 }
 249
 250 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 251                                     const struct vop_reg *reg)
 252 {
 253         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 254 }
 255
 256 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 257                                   uint32_t mask, uint32_t shift, uint32_t v,
 258                                   bool write_mask, bool relaxed)
 259 {
 260         if (!mask)
 261                 return;
 262
 263         if (write_mask) {
 264                 v = ((v & mask) << shift) | (mask << (shift + 16));
 265         } else {
 266                 uint32_t cached_val = vop->regsbak[offset >> 2];
 267
 268                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 269                 vop->regsbak[offset >> 2] = v;
 270         }
 271
 272         if (relaxed)
 273                 writel_relaxed(v, vop->regs + offset);
 274         else
 275                 writel(v, vop->regs + offset);
 276 }
 277
 278 static inline const struct vop_win_phy *
 279 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 280 {
 281         if (!reg->mask && win->parent)
 282                 return win->parent->phy;
 283
 284         return win->phy;
 285 }
 286
 287 static inline uint32_t vop_get_intr_type(struct vop *vop,
 288                                          const struct vop_reg *reg, int type)
 289 {
 290         uint32_t i, ret = 0;
 291         uint32_t regs = vop_read_reg(vop, 0, reg);
 292
 293         for (i = 0; i < vop->data->intr->nintrs; i++) {
 294                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 295                         ret |= vop->data->intr->intrs[i];
 296         }
 297
 298         return ret;
 299 }
 300
 301 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 302 {
 303         int i;
 304
 305         if (!table)
 306                 return;
 307
 308         for (i = 0; i < 8; i++)
 309                 vop_writel(vop, offset + i * 4, table[i]);
 310 }
 311
 312 static inline void vop_cfg_done(struct vop *vop)
 313 {
 314         VOP_CTRL_SET(vop, cfg_done, 1);
 315 }
 316
 317 static bool vop_is_allwin_disabled(struct vop *vop)
 318 {
 319         int i;
 320
 321         for (i = 0; i < vop->num_wins; i++) {
 322                 struct vop_win *win = &vop->win[i];
 323
 324                 if (VOP_WIN_GET(vop, win, enable) != 0)
 325                         return false;
 326         }
 327
 328         return true;
 329 }
 330
 331 static bool vop_is_cfg_done_complete(struct vop *vop)
 332 {
 333         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 334 }
 335
 336 static bool vop_fs_irq_is_active(struct vop *vop)
 337 {
 338         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 339 }
 340
 341 static bool vop_line_flag_is_active(struct vop *vop)
 342 {
 343         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 344 }
 345
 346 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 347 {
 348         writel(v, vop->lut_regs + offset);
 349 }
 350
 351 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 352 {
 353         return readl(vop->lut_regs + offset);
 354 }
 355
 356 static bool has_rb_swapped(uint32_t format)
 357 {
 358         switch (format) {
 359         case DRM_FORMAT_XBGR8888:
 360         case DRM_FORMAT_ABGR8888:
 361         case DRM_FORMAT_BGR888:
 362         case DRM_FORMAT_BGR565:
 363                 return true;
 364         default:
 365                 return false;
 366         }
 367 }
 368
 369 static enum vop_data_format vop_convert_format(uint32_t format)
 370 {
 371         switch (format) {
 372         case DRM_FORMAT_XRGB8888:
 373         case DRM_FORMAT_ARGB8888:
 374         case DRM_FORMAT_XBGR8888:
 375         case DRM_FORMAT_ABGR8888:
 376                 return VOP_FMT_ARGB8888;
 377         case DRM_FORMAT_RGB888:
 378         case DRM_FORMAT_BGR888:
 379                 return VOP_FMT_RGB888;
 380         case DRM_FORMAT_RGB565:
 381         case DRM_FORMAT_BGR565:
 382                 return VOP_FMT_RGB565;
 383         case DRM_FORMAT_NV12:
 384         case DRM_FORMAT_NV12_10:
 385                 return VOP_FMT_YUV420SP;
 386         case DRM_FORMAT_NV16:
 387         case DRM_FORMAT_NV16_10:
 388                 return VOP_FMT_YUV422SP;
 389         case DRM_FORMAT_NV24:
 390         case DRM_FORMAT_NV24_10:
 391                 return VOP_FMT_YUV444SP;
 392         default:
 393                 DRM_ERROR("unsupport format[%08x]\n", format);
 394                 return -EINVAL;
 395         }
 396 }
 397
 398 static bool is_yuv_output(uint32_t bus_format)
 399 {
 400         switch (bus_format) {
 401         case MEDIA_BUS_FMT_YUV8_1X24:
 402         case MEDIA_BUS_FMT_YUV10_1X30:
 403         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 404         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410
 411 static bool is_yuv_support(uint32_t format)
 412 {
 413         switch (format) {
 414         case DRM_FORMAT_NV12:
 415         case DRM_FORMAT_NV12_10:
 416         case DRM_FORMAT_NV16:
 417         case DRM_FORMAT_NV16_10:
 418         case DRM_FORMAT_NV24:
 419         case DRM_FORMAT_NV24_10:
 420                 return true;
 421         default:
 422                 return false;
 423         }
 424 }
 425
 426 static bool is_yuv_10bit(uint32_t format)
 427 {
 428         switch (format) {
 429         case DRM_FORMAT_NV12_10:
 430         case DRM_FORMAT_NV16_10:
 431         case DRM_FORMAT_NV24_10:
 432                 return true;
 433         default:
 434                 return false;
 435         }
 436 }
 437
 438 static bool is_alpha_support(uint32_t format)
 439 {
 440         switch (format) {
 441         case DRM_FORMAT_ARGB8888:
 442         case DRM_FORMAT_ABGR8888:
 443                 return true;
 444         default:
 445                 return false;
 446         }
 447 }
 448
 449 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 450                                   uint32_t dst, bool is_horizontal,
 451                                   int vsu_mode, int *vskiplines)
 452 {
 453         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 454
 455         if (is_horizontal) {
 456                 if (mode == SCALE_UP)
 457                         val = GET_SCL_FT_BIC(src, dst);
 458                 else if (mode == SCALE_DOWN)
 459                         val = GET_SCL_FT_BILI_DN(src, dst);
 460         } else {
 461                 if (mode == SCALE_UP) {
 462                         if (vsu_mode == SCALE_UP_BIL)
 463                                 val = GET_SCL_FT_BILI_UP(src, dst);
 464                         else
 465                                 val = GET_SCL_FT_BIC(src, dst);
 466                 } else if (mode == SCALE_DOWN) {
 467                         if (vskiplines) {
 468                                 *vskiplines = scl_get_vskiplines(src, dst);
 469                                 val = scl_get_bili_dn_vskip(src, dst,
 470                                                             *vskiplines);
 471                         } else {
 472                                 val = GET_SCL_FT_BILI_DN(src, dst);
 473                         }
 474                 }
 475         }
 476
 477         return val;
 478 }
 479
 480 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 481                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 482                                 uint32_t dst_h, uint32_t pixel_format)
 483 {
 484         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 485         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 486         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 487         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 488         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 489         bool is_yuv = is_yuv_support(pixel_format);
 490         uint16_t cbcr_src_w = src_w / hsub;
 491         uint16_t cbcr_src_h = src_h / vsub;
 492         uint16_t vsu_mode;
 493         uint16_t lb_mode;
 494         uint32_t val;
 495         int vskiplines = 0;
 496
 497         if (!win->phy->scl)
 498                 return;
 499
 500         if (!win->phy->scl->ext) {
 501                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 502                             scl_cal_scale2(src_w, dst_w));
 503                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 504                             scl_cal_scale2(src_h, dst_h));
 505                 if (is_yuv) {
 506                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 507                                     scl_cal_scale2(cbcr_src_w, dst_w));
 508                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 509                                     scl_cal_scale2(cbcr_src_h, dst_h));
 510                 }
 511                 return;
 512         }
 513
 514         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 515         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 516
 517         if (is_yuv) {
 518                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 519                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 520                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 521                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 522                 else
 523                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 524         } else {
 525                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 526                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 527                 else
 528                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 529         }
 530
 531         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 532         if (lb_mode == LB_RGB_3840X2) {
 533                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 534                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 535                         return;
 536                 }
 537                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 538                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 539                         return;
 540                 }
 541                 vsu_mode = SCALE_UP_BIL;
 542         } else if (lb_mode == LB_RGB_2560X4) {
 543                 vsu_mode = SCALE_UP_BIL;
 544         } else {
 545                 vsu_mode = SCALE_UP_BIC;
 546         }
 547
 548         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 549                                 true, 0, NULL);
 550         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 551         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 552                                 false, vsu_mode, &vskiplines);
 553         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 554
 555         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 556         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 557
 558         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 559         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 560         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 561         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 562         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 563         if (is_yuv) {
 564                 vskiplines = 0;
 565
 566                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 567                                         dst_w, true, 0, NULL);
 568                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 569                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 570                                         dst_h, false, vsu_mode, &vskiplines);
 571                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 572
 573                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 574                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 575                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 576                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 577                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 578                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 579                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 580         }
 581 }
 582
 583 /*
 584  * rk3399 colorspace path:
 585  *      Input        Win csc                     Output
 586  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 587  *    RGB        --> R2Y                  __/
 588  *
 589  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 590  *    RGB        --> 709To2020->R2Y       __/
 591  *
 592  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 593  *    RGB        --> R2Y                  __/
 594  *
 595  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 596  *    RGB        --> 709To2020->R2Y       __/
 597  *
 598  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 599  *    RGB        --> R2Y                  __/
 600  *
 601  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 602  *    RGB        --> R2Y(601)             __/
 603  *
 604  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 605  *    RGB        --> bypass               __/
 606  *
 607  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 608  *
 609  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 610  *
 611  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 612  *
 613  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 614  */
 615 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 616                          bool is_input_yuv, bool is_output_yuv,
 617                          int input_csc, int output_csc,
 618                          const uint32_t **y2r_table,
 619                          const uint32_t **r2r_table,
 620                          const uint32_t **r2y_table)
 621 {
 622         *y2r_table = NULL;
 623         *r2r_table = NULL;
 624         *r2y_table = NULL;
 625
 626         if (is_output_yuv) {
 627                 if (output_csc == CSC_BT2020) {
 628                         if (is_input_yuv) {
 629                                 if (input_csc == CSC_BT2020)
 630                                         return 0;
 631                                 *y2r_table = csc_table->y2r_bt709;
 632                         }
 633                         if (input_csc != CSC_BT2020)
 634                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 635                         *r2y_table = csc_table->r2y_bt2020;
 636                 } else {
 637                         if (is_input_yuv && input_csc == CSC_BT2020)
 638                                 *y2r_table = csc_table->y2r_bt2020;
 639                         if (input_csc == CSC_BT2020)
 640                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 641                         if (!is_input_yuv || *y2r_table) {
 642                                 if (output_csc == CSC_BT709)
 643                                         *r2y_table = csc_table->r2y_bt709;
 644                                 else
 645                                         *r2y_table = csc_table->r2y_bt601;
 646                         }
 647                 }
 648         } else {
 649                 if (!is_input_yuv)
 650                         return 0;
 651
 652                 /*
 653                  * is possible use bt2020 on rgb mode?
 654                  */
 655                 if (WARN_ON(output_csc == CSC_BT2020))
 656                         return -EINVAL;
 657
 658                 if (input_csc == CSC_BT2020)
 659                         *y2r_table = csc_table->y2r_bt2020;
 660                 else if (input_csc == CSC_BT709)
 661                         *y2r_table = csc_table->y2r_bt709;
 662                 else
 663                         *y2r_table = csc_table->y2r_bt601;
 664
 665                 if (input_csc == CSC_BT2020)
 666                         /*
 667                          * We don't have bt601 to bt709 table, force use bt709.
 668                          */
 669                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 670         }
 671
 672         return 0;
 673 }
 674
 675 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 676                                 struct drm_crtc_state *crtc_state)
 677 {
 678         struct vop *vop = to_vop(crtc);
 679         struct drm_atomic_state *state = crtc_state->state;
 680         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 681         const struct vop_csc_table *csc_table = vop->data->csc_table;
 682         struct drm_plane_state *pstate;
 683         struct drm_plane *plane;
 684         bool is_input_yuv, is_output_yuv;
 685         int ret;
 686
 687         if (!csc_table)
 688                 return 0;
 689
 690         is_output_yuv = is_yuv_output(s->bus_format);
 691
 692         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 693                 struct vop_plane_state *vop_plane_state;
 694
 695                 pstate = drm_atomic_get_plane_state(state, plane);
 696                 if (IS_ERR(pstate))
 697                         return PTR_ERR(pstate);
 698                 vop_plane_state = to_vop_plane_state(pstate);
 699
 700                 if (!pstate->fb)
 701                         continue;
 702                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 703
 704                 /*
 705                  * TODO: force set input and output csc mode.
 706                  */
 707                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 708                                     CSC_BT709, CSC_BT709,
 709                                     &vop_plane_state->y2r_table,
 710                                     &vop_plane_state->r2r_table,
 711                                     &vop_plane_state->r2y_table);
 712                 if (ret)
 713                         return ret;
 714         }
 715
 716         return 0;
 717 }
 718
 719 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 720 {
 721         unsigned long flags;
 722
 723         spin_lock_irqsave(&vop->irq_lock, flags);
 724
 725         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 726         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 727
 728         spin_unlock_irqrestore(&vop->irq_lock, flags);
 729 }
 730
 731 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 732 {
 733         unsigned long flags;
 734
 735         spin_lock_irqsave(&vop->irq_lock, flags);
 736
 737         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 738
 739         spin_unlock_irqrestore(&vop->irq_lock, flags);
 740 }
 741
 742 /*
 743  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 744  *     the "FRAME_SYNC" interrupt.
 745  * (2) the active data region of each frame ends at dsp_vact_end
 746  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 747  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 748  *
 749  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 750  * Interrupts
 751  * LINE_FLAG -------------------------------+
 752  * FRAME_SYNC ----+                         |
 753  *                |                         |
 754  *                v                         v
 755  *                | Vsync | Vbp |  Vactive  | Vfp |
 756  *                        ^     ^           ^     ^
 757  *                        |     |           |     |
 758  *                        |     |           |     |
 759  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 760  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 761  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 762  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 763  */
 764 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 765 {
 766         uint32_t line_flag_irq;
 767         unsigned long flags;
 768
 769         spin_lock_irqsave(&vop->irq_lock, flags);
 770
 771         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 772
 773         spin_unlock_irqrestore(&vop->irq_lock, flags);
 774
 775         return !!line_flag_irq;
 776 }
 777
 778 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 779 {
 780         unsigned long flags;
 781
 782         if (WARN_ON(!vop->is_enabled))
 783                 return;
 784
 785         spin_lock_irqsave(&vop->irq_lock, flags);
 786
 787         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 788         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 789         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 790
 791         spin_unlock_irqrestore(&vop->irq_lock, flags);
 792 }
 793
 794 static void vop_line_flag_irq_disable(struct vop *vop)
 795 {
 796         unsigned long flags;
 797
 798         if (WARN_ON(!vop->is_enabled))
 799                 return;
 800
 801         spin_lock_irqsave(&vop->irq_lock, flags);
 802
 803         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 804
 805         spin_unlock_irqrestore(&vop->irq_lock, flags);
 806 }
 807
 808 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 809 {
 810         struct vop *vop = to_vop(crtc);
 811         int i, dle, lut_idx;
 812
 813         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 814                 return;
 815
 816         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 817                 return;
 818
 819         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 820                 spin_lock(&vop->reg_lock);
 821                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 822                 vop_cfg_done(vop);
 823                 spin_unlock(&vop->reg_lock);
 824
 825 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 826                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 827                                 dle, !dle, 5, 33333);
 828         } else {
 829                 lut_idx = CTRL_GET(lut_buffer_index);
 830         }
 831
 832         for (i = 0; i < vop->lut_len; i++)
 833                 vop_write_lut(vop, i << 2, vop->lut[i]);
 834
 835         spin_lock(&vop->reg_lock);
 836
 837         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 838         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 839         vop_cfg_done(vop);
 840         vop->lut_active = true;
 841
 842         spin_unlock(&vop->reg_lock);
 843
 844         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 845                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 846                                    dle, dle != lut_idx, 5, 33333);
 847                 /* FIXME:
 848                  * update_gamma value auto clean to 0 by HW, should not
 849                  * bakeup it.
 850                  */
 851                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 852         }
 853 #undef CTRL_GET
 854 }
 855
 856 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 857                                     u16 blue, int regno)
 858 {
 859         struct vop *vop = to_vop(crtc);
 860         u32 lut_len = vop->lut_len;
 861         u32 r, g, b;
 862
 863         if (regno >= lut_len || !vop->lut)
 864                 return;
 865
 866         r = red * (lut_len - 1) / 0xffff;
 867         g = green * (lut_len - 1) / 0xffff;
 868         b = blue * (lut_len - 1) / 0xffff;
 869         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 870 }
 871
 872 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 873                                     u16 *blue, int regno)
 874 {
 875         struct vop *vop = to_vop(crtc);
 876         u32 lut_len = vop->lut_len;
 877         u32 r, g, b;
 878
 879         if (regno >= lut_len || !vop->lut)
 880                 return;
 881
 882         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 883         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 884         b = vop->lut[regno] & (lut_len - 1);
 885         *red = r * 0xffff / (lut_len - 1);
 886         *green = g * 0xffff / (lut_len - 1);
 887         *blue = b * 0xffff / (lut_len - 1);
 888 }
 889
 890 static void vop_power_enable(struct drm_crtc *crtc)
 891 {
 892         struct vop *vop = to_vop(crtc);
 893         int ret;
 894
 895         ret = clk_prepare_enable(vop->hclk);
 896         if (ret < 0) {
 897                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 898                 return;
 899         }
 900
 901         ret = clk_prepare_enable(vop->dclk);
 902         if (ret < 0) {
 903                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 904                 goto err_disable_hclk;
 905         }
 906
 907         ret = clk_prepare_enable(vop->aclk);
 908         if (ret < 0) {
 909                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 910                 goto err_disable_dclk;
 911         }
 912
 913         ret = pm_runtime_get_sync(vop->dev);
 914         if (ret < 0) {
 915                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 916                 return;
 917         }
 918
 919         memcpy(vop->regsbak, vop->regs, vop->len);
 920
 921         vop->is_enabled = true;
 922
 923         return;
 924
 925 err_disable_dclk:
 926         clk_disable_unprepare(vop->dclk);
 927 err_disable_hclk:
 928         clk_disable_unprepare(vop->hclk);
 929 }
 930
 931 static void vop_initial(struct drm_crtc *crtc)
 932 {
 933         struct vop *vop = to_vop(crtc);
 934         int i;
 935
 936         vop_power_enable(crtc);
 937
 938         VOP_CTRL_SET(vop, global_regdone_en, 1);
 939         VOP_CTRL_SET(vop, dsp_blank, 0);
 940
 941         /*
 942          * restore the lut table.
 943          */
 944         if (vop->lut_active)
 945                 vop_crtc_load_lut(crtc);
 946
 947         /*
 948          * We need to make sure that all windows are disabled before resume
 949          * the crtc. Otherwise we might try to scan from a destroyed
 950          * buffer later.
 951          */
 952         for (i = 0; i < vop->num_wins; i++) {
 953                 struct vop_win *win = &vop->win[i];
 954                 int channel = i * 2 + 1;
 955
 956                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 957                 if (win->phy->scl && win->phy->scl->ext) {
 958                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 959                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 960                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 961                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 962                 }
 963                 VOP_WIN_SET(vop, win, enable, 0);
 964                 VOP_WIN_SET(vop, win, gate, 1);
 965         }
 966         VOP_CTRL_SET(vop, afbdc_en, 0);
 967 }
 968
 969 static void vop_crtc_disable(struct drm_crtc *crtc)
 970 {
 971         struct vop *vop = to_vop(crtc);
 972
 973         mutex_lock(&vop->vop_lock);
 974         drm_crtc_vblank_off(crtc);
 975
 976         /*
 977          * Vop standby will take effect at end of current frame,
 978          * if dsp hold valid irq happen, it means standby complete.
 979          *
 980          * we must wait standby complete when we want to disable aclk,
 981          * if not, memory bus maybe dead.
 982          */
 983         reinit_completion(&vop->dsp_hold_completion);
 984         vop_dsp_hold_valid_irq_enable(vop);
 985
 986         spin_lock(&vop->reg_lock);
 987
 988         VOP_CTRL_SET(vop, standby, 1);
 989
 990         spin_unlock(&vop->reg_lock);
 991
 992         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 993                                              msecs_to_jiffies(50)));
 994
 995         vop_dsp_hold_valid_irq_disable(vop);
 996
 997         disable_irq(vop->irq);
 998
 999         vop->is_enabled = false;
1000         if (vop->is_iommu_enabled) {
1001                 /*
1002                  * vop standby complete, so iommu detach is safe.
1003                  */
1004                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
1005                 vop->is_iommu_enabled = false;
1006         }
1007
1008         pm_runtime_put(vop->dev);
1009         clk_disable_unprepare(vop->dclk);
1010         clk_disable_unprepare(vop->aclk);
1011         clk_disable_unprepare(vop->hclk);
1012         mutex_unlock(&vop->vop_lock);
1013 }
1014
1015 static void vop_plane_destroy(struct drm_plane *plane)
1016 {
1017         drm_plane_cleanup(plane);
1018 }
1019
1020 static int vop_plane_prepare_fb(struct drm_plane *plane,
1021                                 const struct drm_plane_state *new_state)
1022 {
1023         if (plane->state->fb)
1024                 drm_framebuffer_reference(plane->state->fb);
1025
1026         return 0;
1027 }
1028
1029 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1030                                  const struct drm_plane_state *old_state)
1031 {
1032         if (old_state->fb)
1033                 drm_framebuffer_unreference(old_state->fb);
1034 }
1035
1036 static int vop_plane_atomic_check(struct drm_plane *plane,
1037                            struct drm_plane_state *state)
1038 {
1039         struct drm_crtc *crtc = state->crtc;
1040         struct drm_framebuffer *fb = state->fb;
1041         struct vop_win *win = to_vop_win(plane);
1042         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1043         struct drm_crtc_state *crtc_state;
1044         const struct vop_data *vop_data;
1045         struct vop *vop;
1046         bool visible;
1047         int ret;
1048         struct drm_rect *dest = &vop_plane_state->dest;
1049         struct drm_rect *src = &vop_plane_state->src;
1050         struct drm_rect clip;
1051         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1052                                         DRM_PLANE_HELPER_NO_SCALING;
1053         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1054                                         DRM_PLANE_HELPER_NO_SCALING;
1055         unsigned long offset;
1056         dma_addr_t dma_addr;
1057         u16 vdisplay;
1058
1059         crtc = crtc ? crtc : plane->state->crtc;
1060         /*
1061          * Both crtc or plane->state->crtc can be null.
1062          */
1063         if (!crtc || !fb)
1064                 goto out_disable;
1065
1066         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1067         if (IS_ERR(crtc_state))
1068                 return PTR_ERR(crtc_state);
1069
1070         src->x1 = state->src_x;
1071         src->y1 = state->src_y;
1072         src->x2 = state->src_x + state->src_w;
1073         src->y2 = state->src_y + state->src_h;
1074         dest->x1 = state->crtc_x;
1075         dest->y1 = state->crtc_y;
1076         dest->x2 = state->crtc_x + state->crtc_w;
1077         dest->y2 = state->crtc_y + state->crtc_h;
1078
1079         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1080         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1081                 vdisplay *= 2;
1082
1083         clip.x1 = 0;
1084         clip.y1 = 0;
1085         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1086         clip.y2 = vdisplay;
1087
1088         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1089                                             src, dest, &clip,
1090                                             min_scale,
1091                                             max_scale,
1092                                             true, true, &visible);
1093         if (ret)
1094                 return ret;
1095
1096         if (!visible)
1097                 goto out_disable;
1098
1099         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1100         if (vop_plane_state->format < 0)
1101                 return vop_plane_state->format;
1102
1103         vop = to_vop(crtc);
1104         vop_data = vop->data;
1105
1106         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1107             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1108                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1109                           drm_rect_width(src) >> 16,
1110                           drm_rect_height(src) >> 16,
1111                           vop_data->max_input.width,
1112                           vop_data->max_input.height);
1113                 return -EINVAL;
1114         }
1115
1116         /*
1117          * Src.x1 can be odd when do clip, but yuv plane start point
1118          * need align with 2 pixel.
1119          */
1120         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1121                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1122                 return -EINVAL;
1123         }
1124
1125         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1126         if (state->rotation & BIT(DRM_REFLECT_Y) ||
1127             (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1128                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1129         else
1130                 offset += (src->y1 >> 16) * fb->pitches[0];
1131
1132         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1133         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1134         if (is_yuv_support(fb->pixel_format)) {
1135                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1136                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1137                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1138
1139                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1140                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1141
1142                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1143                 dma_addr += offset + fb->offsets[1];
1144                 vop_plane_state->uv_mst = dma_addr;
1145         }
1146
1147         vop_plane_state->enable = true;
1148
1149         return 0;
1150
1151 out_disable:
1152         vop_plane_state->enable = false;
1153         return 0;
1154 }
1155
1156 static void vop_plane_atomic_disable(struct drm_plane *plane,
1157                                      struct drm_plane_state *old_state)
1158 {
1159         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1160         struct vop_win *win = to_vop_win(plane);
1161         struct vop *vop = to_vop(old_state->crtc);
1162
1163         if (!old_state->crtc)
1164                 return;
1165
1166         spin_lock(&vop->reg_lock);
1167
1168         /*
1169          * FIXUP: some of the vop scale would be abnormal after windows power
1170          * on/off so deinit scale to scale_none mode.
1171          */
1172         if (win->phy->scl && win->phy->scl->ext) {
1173                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1174                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1175                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1176                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1177         }
1178         VOP_WIN_SET(vop, win, enable, 0);
1179
1180         spin_unlock(&vop->reg_lock);
1181
1182         vop_plane_state->enable = false;
1183 }
1184
1185 static void vop_plane_atomic_update(struct drm_plane *plane,
1186                 struct drm_plane_state *old_state)
1187 {
1188         struct drm_plane_state *state = plane->state;
1189         struct drm_crtc *crtc = state->crtc;
1190         struct vop_win *win = to_vop_win(plane);
1191         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1192         struct rockchip_crtc_state *s;
1193         struct vop *vop;
1194         struct drm_framebuffer *fb = state->fb;
1195         unsigned int actual_w, actual_h;
1196         unsigned int dsp_stx, dsp_sty;
1197         uint32_t act_info, dsp_info, dsp_st;
1198         struct drm_rect *src = &vop_plane_state->src;
1199         struct drm_rect *dest = &vop_plane_state->dest;
1200         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1201         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1202         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1203         int ymirror, xmirror;
1204         uint32_t val;
1205         bool rb_swap;
1206
1207         /*
1208          * can't update plane when vop is disabled.
1209          */
1210         if (!crtc)
1211                 return;
1212
1213         if (!vop_plane_state->enable) {
1214                 vop_plane_atomic_disable(plane, old_state);
1215                 return;
1216         }
1217
1218         actual_w = drm_rect_width(src) >> 16;
1219         actual_h = drm_rect_height(src) >> 16;
1220         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1221
1222         dsp_info = (drm_rect_height(dest) - 1) << 16;
1223         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1224
1225         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1226         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1227         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1228
1229         ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1230                   (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1231         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1232
1233         vop = to_vop(state->crtc);
1234         s = to_rockchip_crtc_state(crtc->state);
1235
1236         spin_lock(&vop->reg_lock);
1237
1238         VOP_WIN_SET(vop, win, xmirror, xmirror);
1239         VOP_WIN_SET(vop, win, ymirror, ymirror);
1240         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1241         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1242         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1243         if (is_yuv_support(fb->pixel_format)) {
1244                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1245                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1246         }
1247         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1248
1249         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1250                             drm_rect_width(dest), drm_rect_height(dest),
1251                             fb->pixel_format);
1252
1253         VOP_WIN_SET(vop, win, act_info, act_info);
1254         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1255         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1256
1257         rb_swap = has_rb_swapped(fb->pixel_format);
1258         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1259
1260         if (is_alpha_support(fb->pixel_format) &&
1261             (s->dsp_layer_sel & 0x3) != win->win_id) {
1262                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1263                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1264                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1265                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1266                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1267                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1268                         SRC_FACTOR_M0(ALPHA_ONE);
1269                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1270                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1271                 VOP_WIN_SET(vop, win, alpha_en, 1);
1272         } else {
1273                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1274                 VOP_WIN_SET(vop, win, alpha_en, 0);
1275         }
1276
1277         if (win->csc) {
1278                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1279                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1280                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1281                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1282                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1283                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1284         }
1285         VOP_WIN_SET(vop, win, enable, 1);
1286         spin_unlock(&vop->reg_lock);
1287         vop->is_iommu_needed = true;
1288 }
1289
1290 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1291         .prepare_fb = vop_plane_prepare_fb,
1292         .cleanup_fb = vop_plane_cleanup_fb,
1293         .atomic_check = vop_plane_atomic_check,
1294         .atomic_update = vop_plane_atomic_update,
1295         .atomic_disable = vop_plane_atomic_disable,
1296 };
1297
1298 void vop_atomic_plane_reset(struct drm_plane *plane)
1299 {
1300         struct vop_win *win = to_vop_win(plane);
1301         struct vop_plane_state *vop_plane_state =
1302                                         to_vop_plane_state(plane->state);
1303
1304         if (plane->state && plane->state->fb)
1305                 drm_framebuffer_unreference(plane->state->fb);
1306
1307         kfree(vop_plane_state);
1308         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1309         if (!vop_plane_state)
1310                 return;
1311
1312         vop_plane_state->zpos = win->win_id;
1313         plane->state = &vop_plane_state->base;
1314         plane->state->plane = plane;
1315 }
1316
1317 struct drm_plane_state *
1318 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1319 {
1320         struct vop_plane_state *old_vop_plane_state;
1321         struct vop_plane_state *vop_plane_state;
1322
1323         if (WARN_ON(!plane->state))
1324                 return NULL;
1325
1326         old_vop_plane_state = to_vop_plane_state(plane->state);
1327         vop_plane_state = kmemdup(old_vop_plane_state,
1328                                   sizeof(*vop_plane_state), GFP_KERNEL);
1329         if (!vop_plane_state)
1330                 return NULL;
1331
1332         __drm_atomic_helper_plane_duplicate_state(plane,
1333                                                   &vop_plane_state->base);
1334
1335         return &vop_plane_state->base;
1336 }
1337
1338 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1339                                            struct drm_plane_state *state)
1340 {
1341         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1342
1343         __drm_atomic_helper_plane_destroy_state(plane, state);
1344
1345         kfree(vop_state);
1346 }
1347
1348 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1349                                          struct drm_plane_state *state,
1350                                          struct drm_property *property,
1351                                          uint64_t val)
1352 {
1353         struct rockchip_drm_private *private = plane->dev->dev_private;
1354         struct vop_win *win = to_vop_win(plane);
1355         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1356
1357         if (property == win->vop->plane_zpos_prop) {
1358                 plane_state->zpos = val;
1359                 return 0;
1360         }
1361
1362         if (property == win->rotation_prop) {
1363                 state->rotation = val;
1364                 return 0;
1365         }
1366
1367         if (property == private->logo_ymirror_prop) {
1368                 WARN_ON(!rockchip_fb_is_logo(state->fb));
1369                 plane_state->logo_ymirror = val;
1370                 return 0;
1371         }
1372
1373         DRM_ERROR("failed to set vop plane property\n");
1374         return -EINVAL;
1375 }
1376
1377 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1378                                          const struct drm_plane_state *state,
1379                                          struct drm_property *property,
1380                                          uint64_t *val)
1381 {
1382         struct vop_win *win = to_vop_win(plane);
1383         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1384
1385         if (property == win->vop->plane_zpos_prop) {
1386                 *val = plane_state->zpos;
1387                 return 0;
1388         }
1389
1390         if (property == win->rotation_prop) {
1391                 *val = state->rotation;
1392                 return 0;
1393         }
1394
1395         DRM_ERROR("failed to get vop plane property\n");
1396         return -EINVAL;
1397 }
1398
1399 static const struct drm_plane_funcs vop_plane_funcs = {
1400         .update_plane   = drm_atomic_helper_update_plane,
1401         .disable_plane  = drm_atomic_helper_disable_plane,
1402         .destroy = vop_plane_destroy,
1403         .reset = vop_atomic_plane_reset,
1404         .set_property = drm_atomic_helper_plane_set_property,
1405         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1406         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1407         .atomic_set_property = vop_atomic_plane_set_property,
1408         .atomic_get_property = vop_atomic_plane_get_property,
1409 };
1410
1411 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1412 {
1413         struct vop *vop = to_vop(crtc);
1414         unsigned long flags;
1415
1416         if (!vop->is_enabled)
1417                 return -EPERM;
1418
1419         spin_lock_irqsave(&vop->irq_lock, flags);
1420
1421         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1422         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1423
1424         spin_unlock_irqrestore(&vop->irq_lock, flags);
1425
1426         return 0;
1427 }
1428
1429 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1430 {
1431         struct vop *vop = to_vop(crtc);
1432         unsigned long flags;
1433
1434         if (!vop->is_enabled)
1435                 return;
1436
1437         spin_lock_irqsave(&vop->irq_lock, flags);
1438
1439         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1440
1441         spin_unlock_irqrestore(&vop->irq_lock, flags);
1442 }
1443
1444 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1445                                            struct drm_file *file_priv)
1446 {
1447         struct drm_device *drm = crtc->dev;
1448         struct vop *vop = to_vop(crtc);
1449         struct drm_pending_vblank_event *e;
1450         unsigned long flags;
1451
1452         spin_lock_irqsave(&drm->event_lock, flags);
1453         e = vop->event;
1454         if (e && e->base.file_priv == file_priv) {
1455                 vop->event = NULL;
1456
1457                 e->base.destroy(&e->base);
1458                 file_priv->event_space += sizeof(e->event);
1459         }
1460         spin_unlock_irqrestore(&drm->event_lock, flags);
1461 }
1462
1463 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1464 {
1465         struct vop *vop = to_vop(crtc);
1466
1467         if (on == vop->loader_protect)
1468                 return 0;
1469
1470         if (on) {
1471                 vop_power_enable(crtc);
1472                 enable_irq(vop->irq);
1473                 drm_crtc_vblank_on(crtc);
1474                 vop->loader_protect = true;
1475         } else {
1476                 vop_crtc_disable(crtc);
1477
1478                 vop->loader_protect = false;
1479         }
1480
1481         return 0;
1482 }
1483
1484 #define DEBUG_PRINT(args...) \
1485                 do { \
1486                         if (s) \
1487                                 seq_printf(s, args); \
1488                         else \
1489                                 printk(args); \
1490                 } while (0)
1491
1492 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1493 {
1494         struct vop_win *win = to_vop_win(plane);
1495         struct drm_plane_state *state = plane->state;
1496         struct vop_plane_state *pstate = to_vop_plane_state(state);
1497         struct drm_rect *src, *dest;
1498         struct drm_framebuffer *fb = state->fb;
1499         int i;
1500
1501         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1502                     pstate->enable ? "ACTIVE" : "DISABLED");
1503         if (!fb)
1504                 return 0;
1505
1506         src = &pstate->src;
1507         dest = &pstate->dest;
1508
1509         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1510                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1511         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1512         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1513                     src->y1 >> 16, drm_rect_width(src) >> 16,
1514                     drm_rect_height(src) >> 16);
1515         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1516                     drm_rect_width(dest), drm_rect_height(dest));
1517
1518         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1519                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1520                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1521                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1528 {
1529         struct vop *vop = to_vop(crtc);
1530         struct drm_crtc_state *crtc_state = crtc->state;
1531         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1532         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1533         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1534         struct drm_plane *plane;
1535         int i;
1536
1537         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1538                     crtc_state->active ? "ACTIVE" : "DISABLED");
1539
1540         if (!crtc_state->active)
1541                 return 0;
1542
1543         DEBUG_PRINT("    Connector: %s\n",
1544                     drm_get_connector_name(state->output_type));
1545         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1546                     state->bus_format, state->output_mode);
1547         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1548                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1549                     drm_mode_vrefresh(mode));
1550         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1551                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1552         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1553                     mode->hsync_end, mode->htotal);
1554         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1555                     mode->vsync_end, mode->vtotal);
1556
1557         for (i = 0; i < vop->num_wins; i++) {
1558                 plane = &vop->win[i].base;
1559                 vop_plane_info_dump(s, plane);
1560         }
1561
1562         return 0;
1563 }
1564
1565 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1566 {
1567         struct vop *vop = to_vop(crtc);
1568         struct drm_crtc_state *crtc_state = crtc->state;
1569         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1570         int i;
1571
1572         if (!crtc_state->active)
1573                 return;
1574
1575         for (i = 0; i < dump_len; i += 4) {
1576                 if (i % 16 == 0)
1577                         DEBUG_PRINT("\n0x%08x: ", i);
1578                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1579         }
1580 }
1581
1582 #undef DEBUG_PRINT
1583
1584 static enum drm_mode_status
1585 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1586                     int output_type)
1587 {
1588         struct vop *vop = to_vop(crtc);
1589         const struct vop_data *vop_data = vop->data;
1590         int request_clock = mode->clock;
1591         int clock;
1592
1593         if (mode->hdisplay > vop_data->max_output.width)
1594                 return MODE_BAD_HVALUE;
1595
1596         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
1597             VOP_MAJOR(vop->data->version) == 3 &&
1598             VOP_MINOR(vop->data->version) <= 2)
1599                 return MODE_BAD;
1600
1601         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1602                 request_clock *= 2;
1603         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1604
1605         /*
1606          * Hdmi or DisplayPort request a Accurate clock.
1607          */
1608         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1609             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1610                 if (clock != request_clock)
1611                         return MODE_CLOCK_RANGE;
1612
1613         return MODE_OK;
1614 }
1615
1616 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1617         .loader_protect = vop_crtc_loader_protect,
1618         .enable_vblank = vop_crtc_enable_vblank,
1619         .disable_vblank = vop_crtc_disable_vblank,
1620         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1621         .debugfs_dump = vop_crtc_debugfs_dump,
1622         .regs_dump = vop_crtc_regs_dump,
1623         .mode_valid = vop_crtc_mode_valid,
1624 };
1625
1626 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1627                                 const struct drm_display_mode *mode,
1628                                 struct drm_display_mode *adj_mode)
1629 {
1630         struct vop *vop = to_vop(crtc);
1631         const struct vop_data *vop_data = vop->data;
1632
1633         if (mode->hdisplay > vop_data->max_output.width)
1634                 return false;
1635
1636         drm_mode_set_crtcinfo(adj_mode,
1637                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1638
1639         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1640                 adj_mode->crtc_clock *= 2;
1641
1642         adj_mode->crtc_clock =
1643                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1644
1645         return true;
1646 }
1647
1648 static void vop_crtc_enable(struct drm_crtc *crtc)
1649 {
1650         struct vop *vop = to_vop(crtc);
1651         const struct vop_data *vop_data = vop->data;
1652         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1653         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1654         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1655         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1656         u16 htotal = adjusted_mode->crtc_htotal;
1657         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1658         u16 hact_end = hact_st + hdisplay;
1659         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1660         u16 vtotal = adjusted_mode->crtc_vtotal;
1661         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1662         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1663         u16 vact_end = vact_st + vdisplay;
1664         uint32_t val;
1665
1666         mutex_lock(&vop->vop_lock);
1667         vop_initial(crtc);
1668
1669         val = BIT(DCLK_INVERT);
1670         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1671                    0 : BIT(HSYNC_POSITIVE);
1672         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1673                    0 : BIT(VSYNC_POSITIVE);
1674         VOP_CTRL_SET(vop, pin_pol, val);
1675
1676         if (vop->dclk_source && s->pll && s->pll->pll) {
1677                 if (clk_set_parent(vop->dclk_source, s->pll->pll))
1678                         DRM_DEV_ERROR(vop->dev,
1679                                       "failed to set dclk's parents\n");
1680         }
1681
1682         switch (s->output_type) {
1683         case DRM_MODE_CONNECTOR_LVDS:
1684                 VOP_CTRL_SET(vop, rgb_en, 1);
1685                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1686                 break;
1687         case DRM_MODE_CONNECTOR_eDP:
1688                 VOP_CTRL_SET(vop, edp_en, 1);
1689                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1690                 break;
1691         case DRM_MODE_CONNECTOR_HDMIA:
1692                 VOP_CTRL_SET(vop, hdmi_en, 1);
1693                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1694                 break;
1695         case DRM_MODE_CONNECTOR_DSI:
1696                 VOP_CTRL_SET(vop, mipi_en, 1);
1697                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1698                 break;
1699         case DRM_MODE_CONNECTOR_DisplayPort:
1700                 val &= ~BIT(DCLK_INVERT);
1701                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1702                 VOP_CTRL_SET(vop, dp_en, 1);
1703                 break;
1704         case DRM_MODE_CONNECTOR_TV:
1705                 if (vdisplay == CVBS_PAL_VDISPLAY)
1706                         VOP_CTRL_SET(vop, tve_sw_mode, 1);
1707                 else
1708                         VOP_CTRL_SET(vop, tve_sw_mode, 0);
1709
1710                 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
1711                 VOP_CTRL_SET(vop, tve_dclk_en, 1);
1712                 /* use the same pol reg with hdmi */
1713                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1714                 VOP_CTRL_SET(vop, sw_genlock, 1);
1715                 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
1716                 VOP_CTRL_SET(vop, dither_up, 1);
1717                 break;
1718         default:
1719                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1720         }
1721
1722         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1723             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1724                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1725
1726         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1727         switch (s->bus_format) {
1728         case MEDIA_BUS_FMT_RGB565_1X16:
1729                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1730                 break;
1731         case MEDIA_BUS_FMT_RGB666_1X18:
1732         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1733                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1734                 break;
1735         case MEDIA_BUS_FMT_YUV8_1X24:
1736         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1737                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1738                 break;
1739         case MEDIA_BUS_FMT_YUV10_1X30:
1740         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1741                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1742                 break;
1743         case MEDIA_BUS_FMT_RGB888_1X24:
1744         default:
1745                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1746                 break;
1747         }
1748
1749         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1750                 val |= PRE_DITHER_DOWN_EN(0);
1751         else
1752                 val |= PRE_DITHER_DOWN_EN(1);
1753         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1754         VOP_CTRL_SET(vop, dither_down, val);
1755         VOP_CTRL_SET(vop, dclk_ddr,
1756                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1757         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1758         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1759         VOP_CTRL_SET(vop, dsp_background,
1760                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1761
1762         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1763         val = hact_st << 16;
1764         val |= hact_end;
1765         VOP_CTRL_SET(vop, hact_st_end, val);
1766         VOP_CTRL_SET(vop, hpost_st_end, val);
1767
1768         val = vact_st << 16;
1769         val |= vact_end;
1770         VOP_CTRL_SET(vop, vact_st_end, val);
1771         VOP_CTRL_SET(vop, vpost_st_end, val);
1772
1773         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1774         VOP_INTR_SET(vop, line_flag_num[1],
1775                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1776         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1777                 u16 vact_st_f1 = vtotal + vact_st + 1;
1778                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1779
1780                 val = vact_st_f1 << 16 | vact_end_f1;
1781                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1782                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1783
1784                 val = vtotal << 16 | (vtotal + vsync_len);
1785                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1786                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1787                 VOP_CTRL_SET(vop, p2i_en, 1);
1788                 vtotal += vtotal + 1;
1789         } else {
1790                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1791                 VOP_CTRL_SET(vop, p2i_en, 0);
1792         }
1793         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1794
1795         VOP_CTRL_SET(vop, core_dclk_div,
1796                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1797
1798         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1799
1800         vop_cfg_done(vop);
1801         /*
1802          * enable vop, all the register would take effect when vop exit standby
1803          */
1804         VOP_CTRL_SET(vop, standby, 0);
1805
1806         enable_irq(vop->irq);
1807         drm_crtc_vblank_on(crtc);
1808         mutex_unlock(&vop->vop_lock);
1809 }
1810
1811 static int vop_zpos_cmp(const void *a, const void *b)
1812 {
1813         struct vop_zpos *pa = (struct vop_zpos *)a;
1814         struct vop_zpos *pb = (struct vop_zpos *)b;
1815
1816         return pa->zpos - pb->zpos;
1817 }
1818
1819 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1820                                   struct drm_crtc_state *crtc_state)
1821 {
1822         struct vop *vop = to_vop(crtc);
1823         const struct vop_data *vop_data = vop->data;
1824         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1825         struct drm_atomic_state *state = crtc_state->state;
1826         struct drm_plane *plane;
1827         struct drm_plane_state *pstate;
1828         struct vop_plane_state *plane_state;
1829         struct vop_win *win;
1830         int afbdc_format;
1831         int i;
1832
1833         s->afbdc_en = 0;
1834
1835         for_each_plane_in_state(state, plane, pstate, i) {
1836                 struct drm_framebuffer *fb = pstate->fb;
1837                 struct drm_rect *src;
1838
1839                 win = to_vop_win(plane);
1840                 plane_state = to_vop_plane_state(pstate);
1841
1842                 if (pstate->crtc != crtc || !fb)
1843                         continue;
1844
1845                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1846                         continue;
1847
1848                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1849                         DRM_ERROR("not support afbdc\n");
1850                         return -EINVAL;
1851                 }
1852
1853                 switch (plane_state->format) {
1854                 case VOP_FMT_ARGB8888:
1855                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1856                         break;
1857                 case VOP_FMT_RGB888:
1858                         afbdc_format = AFBDC_FMT_U8U8U8;
1859                         break;
1860                 case VOP_FMT_RGB565:
1861                         afbdc_format = AFBDC_FMT_RGB565;
1862                         break;
1863                 default:
1864                         return -EINVAL;
1865                 }
1866
1867                 if (s->afbdc_en) {
1868                         DRM_ERROR("vop only support one afbc layer\n");
1869                         return -EINVAL;
1870                 }
1871
1872                 src = &plane_state->src;
1873                 if (src->x1 || src->y1 || fb->offsets[0]) {
1874                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1875                                   win->win_id);
1876                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1877                                   src->x1, src->y1, fb->offsets[0]);
1878                         return -EINVAL;
1879                 }
1880                 s->afbdc_win_format = afbdc_format;
1881                 s->afbdc_win_width = pstate->fb->width - 1;
1882                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1883                 s->afbdc_win_id = win->win_id;
1884                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1885                 s->afbdc_en = 1;
1886         }
1887
1888         return 0;
1889 }
1890
1891 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1892                                      struct drm_crtc_state *crtc_state)
1893 {
1894         struct rockchip_drm_private *private = crtc->dev->dev_private;
1895         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1896         struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1897         struct vop *vop = to_vop(crtc);
1898
1899         if (!vop->dclk_source)
1900                 return;
1901
1902         if (crtc_state->active) {
1903                 WARN_ON(s->pll && !s->pll->use_count);
1904                 if (!s->pll || s->pll->use_count > 1 ||
1905                     s->output_type != old_s->output_type) {
1906                         if (s->pll)
1907                                 s->pll->use_count--;
1908
1909                         if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1910                             !private->default_pll.use_count)
1911                                 s->pll = &private->default_pll;
1912                         else
1913                                 s->pll = &private->hdmi_pll;
1914
1915                         s->pll->use_count++;
1916                 }
1917         } else if (s->pll) {
1918                 s->pll->use_count--;
1919                 s->pll = NULL;
1920         }
1921         if (s->pll && s->pll != old_s->pll)
1922                 crtc_state->mode_changed = true;
1923 }
1924
1925 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1926                                  struct drm_crtc_state *crtc_state)
1927 {
1928         struct drm_atomic_state *state = crtc_state->state;
1929         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1930         struct vop *vop = to_vop(crtc);
1931         const struct vop_data *vop_data = vop->data;
1932         struct drm_plane *plane;
1933         struct drm_plane_state *pstate;
1934         struct vop_plane_state *plane_state;
1935         struct vop_zpos *pzpos;
1936         int dsp_layer_sel = 0;
1937         int i, j, cnt = 0, ret = 0;
1938
1939         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1940         if (ret)
1941                 return ret;
1942
1943         ret = vop_csc_atomic_check(crtc, crtc_state);
1944         if (ret)
1945                 return ret;
1946
1947         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1948         if (!pzpos)
1949                 return -ENOMEM;
1950
1951         for (i = 0; i < vop_data->win_size; i++) {
1952                 const struct vop_win_data *win_data = &vop_data->win[i];
1953                 struct vop_win *win;
1954
1955                 if (!win_data->phy)
1956                         continue;
1957
1958                 for (j = 0; j < vop->num_wins; j++) {
1959                         win = &vop->win[j];
1960
1961                         if (win->win_id == i && !win->area_id)
1962                                 break;
1963                 }
1964                 if (WARN_ON(j >= vop->num_wins)) {
1965                         ret = -EINVAL;
1966                         goto err_free_pzpos;
1967                 }
1968
1969                 plane = &win->base;
1970                 pstate = state->plane_states[drm_plane_index(plane)];
1971                 /*
1972                  * plane might not have changed, in which case take
1973                  * current state:
1974                  */
1975                 if (!pstate)
1976                         pstate = plane->state;
1977                 plane_state = to_vop_plane_state(pstate);
1978                 pzpos[cnt].zpos = plane_state->zpos;
1979                 pzpos[cnt++].win_id = win->win_id;
1980         }
1981
1982         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1983
1984         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1985                 const struct vop_win_data *win_data = &vop_data->win[i];
1986                 int shift = i * 2;
1987
1988                 if (win_data->phy) {
1989                         struct vop_zpos *zpos = &pzpos[cnt++];
1990
1991                         dsp_layer_sel |= zpos->win_id << shift;
1992                 } else {
1993                         dsp_layer_sel |= i << shift;
1994                 }
1995         }
1996
1997         s->dsp_layer_sel = dsp_layer_sel;
1998
1999         vop_dclk_source_generate(crtc, crtc_state);
2000
2001 err_free_pzpos:
2002         kfree(pzpos);
2003         return ret;
2004 }
2005
2006 static void vop_post_config(struct drm_crtc *crtc)
2007 {
2008         struct vop *vop = to_vop(crtc);
2009         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2010         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2011         u16 vtotal = mode->crtc_vtotal;
2012         u16 hdisplay = mode->crtc_hdisplay;
2013         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2014         u16 vdisplay = mode->crtc_vdisplay;
2015         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2016         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
2017         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
2018         u16 hact_end, vact_end;
2019         u32 val;
2020
2021         hact_st += hdisplay * (100 - s->left_margin) / 200;
2022         hact_end = hact_st + hsize;
2023         val = hact_st << 16;
2024         val |= hact_end;
2025         VOP_CTRL_SET(vop, hpost_st_end, val);
2026         vact_st += vdisplay * (100 - s->top_margin) / 200;
2027         vact_end = vact_st + vsize;
2028         val = vact_st << 16;
2029         val |= vact_end;
2030         VOP_CTRL_SET(vop, vpost_st_end, val);
2031         val = scl_cal_scale2(vdisplay, vsize) << 16;
2032         val |= scl_cal_scale2(hdisplay, hsize);
2033         VOP_CTRL_SET(vop, post_scl_factor, val);
2034         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
2035         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2036                 u16 vact_st_f1 = vtotal + vact_st + 1;
2037                 u16 vact_end_f1 = vact_st_f1 + vsize;
2038
2039                 val = vact_st_f1 << 16 | vact_end_f1;
2040                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2041         }
2042 }
2043
2044 static void vop_cfg_update(struct drm_crtc *crtc,
2045                            struct drm_crtc_state *old_crtc_state)
2046 {
2047         struct rockchip_crtc_state *s =
2048                         to_rockchip_crtc_state(crtc->state);
2049         struct vop *vop = to_vop(crtc);
2050
2051         spin_lock(&vop->reg_lock);
2052
2053         if (s->afbdc_en) {
2054                 uint32_t pic_size;
2055
2056                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2057                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2058                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2059                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2060                 pic_size = (s->afbdc_win_width & 0xffff);
2061                 pic_size |= s->afbdc_win_height << 16;
2062                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2063         }
2064
2065         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2066         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2067         vop_post_config(crtc);
2068
2069         spin_unlock(&vop->reg_lock);
2070 }
2071
2072 static bool vop_fs_irq_is_pending(struct vop *vop)
2073 {
2074         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
2075 }
2076
2077 static void vop_wait_for_irq_handler(struct vop *vop)
2078 {
2079         bool pending;
2080         int ret;
2081
2082         /*
2083          * Spin until frame start interrupt status bit goes low, which means
2084          * that interrupt handler was invoked and cleared it. The timeout of
2085          * 10 msecs is really too long, but it is just a safety measure if
2086          * something goes really wrong. The wait will only happen in the very
2087          * unlikely case of a vblank happening exactly at the same time and
2088          * shouldn't exceed microseconds range.
2089          */
2090         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
2091                                         !pending, 0, 10 * 1000);
2092         if (ret)
2093                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
2094
2095         synchronize_irq(vop->irq);
2096 }
2097
2098 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2099                                   struct drm_crtc_state *old_crtc_state)
2100 {
2101         struct drm_atomic_state *old_state = old_crtc_state->state;
2102         struct drm_plane_state *old_plane_state;
2103         struct vop *vop = to_vop(crtc);
2104         struct drm_plane *plane;
2105         int i;
2106
2107         vop_cfg_update(crtc, old_crtc_state);
2108
2109         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2110                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2111                 int ret;
2112
2113                 if (need_wait_vblank) {
2114                         bool active;
2115
2116                         disable_irq(vop->irq);
2117                         drm_crtc_vblank_get(crtc);
2118                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2119
2120                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2121                                                         vop, active, active,
2122                                                         0, 50 * 1000);
2123                         if (ret)
2124                                 dev_err(vop->dev, "wait fs irq timeout\n");
2125
2126                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2127                         vop_cfg_done(vop);
2128
2129                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2130                                                         vop, active, active,
2131                                                         0, 50 * 1000);
2132                         if (ret)
2133                                 dev_err(vop->dev, "wait line flag timeout\n");
2134
2135                         enable_irq(vop->irq);
2136                 }
2137                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2138                 if (ret)
2139                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2140                                 ret);
2141
2142                 if (need_wait_vblank) {
2143                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2144                         drm_crtc_vblank_put(crtc);
2145                 }
2146
2147                 vop->is_iommu_enabled = true;
2148         }
2149
2150         vop_cfg_done(vop);
2151
2152         /*
2153          * There is a (rather unlikely) possiblity that a vblank interrupt
2154          * fired before we set the cfg_done bit. To avoid spuriously
2155          * signalling flip completion we need to wait for it to finish.
2156          */
2157         vop_wait_for_irq_handler(vop);
2158
2159         for_each_plane_in_state(old_state, plane, old_plane_state, i) {
2160                 if (!old_plane_state->fb)
2161                         continue;
2162
2163                 if (old_plane_state->fb == plane->state->fb)
2164                         continue;
2165
2166                 drm_framebuffer_reference(old_plane_state->fb);
2167                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
2168                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
2169                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2170         }
2171 }
2172
2173 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2174                                   struct drm_crtc_state *old_crtc_state)
2175 {
2176         struct vop *vop = to_vop(crtc);
2177
2178         if (crtc->state->event) {
2179                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2180
2181                 vop->event = crtc->state->event;
2182                 crtc->state->event = NULL;
2183         }
2184 }
2185
2186 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2187         .load_lut = vop_crtc_load_lut,
2188         .enable = vop_crtc_enable,
2189         .disable = vop_crtc_disable,
2190         .mode_fixup = vop_crtc_mode_fixup,
2191         .atomic_check = vop_crtc_atomic_check,
2192         .atomic_flush = vop_crtc_atomic_flush,
2193         .atomic_begin = vop_crtc_atomic_begin,
2194 };
2195
2196 static void vop_crtc_destroy(struct drm_crtc *crtc)
2197 {
2198         drm_crtc_cleanup(crtc);
2199 }
2200
2201 static void vop_crtc_reset(struct drm_crtc *crtc)
2202 {
2203         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2204         struct rockchip_drm_private *private = crtc->dev->dev_private;
2205         struct vop *vop = to_vop(crtc);
2206
2207         if (crtc->state) {
2208                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2209                 kfree(s);
2210         }
2211
2212         s = kzalloc(sizeof(*s), GFP_KERNEL);
2213         if (!s)
2214                 return;
2215         crtc->state = &s->base;
2216         crtc->state->crtc = crtc;
2217
2218         if (vop->dclk_source) {
2219                 struct clk *parent;
2220
2221                 parent = clk_get_parent(vop->dclk_source);
2222                 if (parent) {
2223                         if (clk_is_match(private->default_pll.pll, parent))
2224                                 s->pll = &private->default_pll;
2225                         else if (clk_is_match(private->hdmi_pll.pll, parent))
2226                                 s->pll = &private->hdmi_pll;
2227                         if (s->pll)
2228                                 s->pll->use_count++;
2229                 }
2230         }
2231         s->left_margin = 100;
2232         s->right_margin = 100;
2233         s->top_margin = 100;
2234         s->bottom_margin = 100;
2235 }
2236
2237 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2238 {
2239         struct rockchip_crtc_state *rockchip_state, *old_state;
2240
2241         old_state = to_rockchip_crtc_state(crtc->state);
2242         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2243         if (!rockchip_state)
2244                 return NULL;
2245
2246         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2247         return &rockchip_state->base;
2248 }
2249
2250 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2251                                    struct drm_crtc_state *state)
2252 {
2253         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2254
2255         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2256         kfree(s);
2257 }
2258
2259 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2260                                         const struct drm_crtc_state *state,
2261                                         struct drm_property *property,
2262                                         uint64_t *val)
2263 {
2264         struct drm_device *drm_dev = crtc->dev;
2265         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2266         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2267
2268         if (property == mode_config->tv_left_margin_property) {
2269                 *val = s->left_margin;
2270                 return 0;
2271         }
2272
2273         if (property == mode_config->tv_right_margin_property) {
2274                 *val = s->right_margin;
2275                 return 0;
2276         }
2277
2278         if (property == mode_config->tv_top_margin_property) {
2279                 *val = s->top_margin;
2280                 return 0;
2281         }
2282
2283         if (property == mode_config->tv_bottom_margin_property) {
2284                 *val = s->bottom_margin;
2285                 return 0;
2286         }
2287
2288         DRM_ERROR("failed to get vop crtc property\n");
2289         return -EINVAL;
2290 }
2291
2292 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2293                                         struct drm_crtc_state *state,
2294                                         struct drm_property *property,
2295                                         uint64_t val)
2296 {
2297         struct drm_device *drm_dev = crtc->dev;
2298         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2299         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2300
2301         if (property == mode_config->tv_left_margin_property) {
2302                 s->left_margin = val;
2303                 return 0;
2304         }
2305
2306         if (property == mode_config->tv_right_margin_property) {
2307                 s->right_margin = val;
2308                 return 0;
2309         }
2310
2311         if (property == mode_config->tv_top_margin_property) {
2312                 s->top_margin = val;
2313                 return 0;
2314         }
2315
2316         if (property == mode_config->tv_bottom_margin_property) {
2317                 s->bottom_margin = val;
2318                 return 0;
2319         }
2320
2321         DRM_ERROR("failed to set vop crtc property\n");
2322         return -EINVAL;
2323 }
2324
2325 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2326                                u16 *blue, uint32_t start, uint32_t size)
2327 {
2328         struct vop *vop = to_vop(crtc);
2329         int end = min_t(u32, start + size, vop->lut_len);
2330         int i;
2331
2332         if (!vop->lut)
2333                 return;
2334
2335         for (i = start; i < end; i++)
2336                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2337                                                blue[i], i);
2338
2339         vop_crtc_load_lut(crtc);
2340 }
2341
2342 static const struct drm_crtc_funcs vop_crtc_funcs = {
2343         .gamma_set = vop_crtc_gamma_set,
2344         .set_config = drm_atomic_helper_set_config,
2345         .page_flip = drm_atomic_helper_page_flip,
2346         .destroy = vop_crtc_destroy,
2347         .reset = vop_crtc_reset,
2348         .set_property = drm_atomic_helper_crtc_set_property,
2349         .atomic_get_property = vop_crtc_atomic_get_property,
2350         .atomic_set_property = vop_crtc_atomic_set_property,
2351         .atomic_duplicate_state = vop_crtc_duplicate_state,
2352         .atomic_destroy_state = vop_crtc_destroy_state,
2353 };
2354
2355 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
2356 {
2357         struct vop *vop = container_of(work, struct vop, fb_unref_work);
2358         struct drm_framebuffer *fb = val;
2359
2360         drm_crtc_vblank_put(&vop->crtc);
2361         drm_framebuffer_unreference(fb);
2362 }
2363
2364 static void vop_handle_vblank(struct vop *vop)
2365 {
2366         struct drm_device *drm = vop->drm_dev;
2367         struct drm_crtc *crtc = &vop->crtc;
2368         unsigned long flags;
2369
2370         if (!vop_is_cfg_done_complete(vop))
2371                 return;
2372
2373         if (vop->event) {
2374                 spin_lock_irqsave(&drm->event_lock, flags);
2375
2376                 drm_crtc_send_vblank_event(crtc, vop->event);
2377                 drm_crtc_vblank_put(crtc);
2378                 vop->event = NULL;
2379
2380                 spin_unlock_irqrestore(&drm->event_lock, flags);
2381         }
2382
2383         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
2384                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2385 }
2386
2387 static irqreturn_t vop_isr(int irq, void *data)
2388 {
2389         struct vop *vop = data;
2390         struct drm_crtc *crtc = &vop->crtc;
2391         uint32_t active_irqs;
2392         unsigned long flags;
2393         int ret = IRQ_NONE;
2394
2395         /*
2396          * interrupt register has interrupt status, enable and clear bits, we
2397          * must hold irq_lock to avoid a race with enable/disable_vblank().
2398         */
2399         spin_lock_irqsave(&vop->irq_lock, flags);
2400
2401         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2402         /* Clear all active interrupt sources */
2403         if (active_irqs)
2404                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2405
2406         spin_unlock_irqrestore(&vop->irq_lock, flags);
2407
2408         /* This is expected for vop iommu irqs, since the irq is shared */
2409         if (!active_irqs)
2410                 return IRQ_NONE;
2411
2412         if (active_irqs & DSP_HOLD_VALID_INTR) {
2413                 complete(&vop->dsp_hold_completion);
2414                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2415                 ret = IRQ_HANDLED;
2416         }
2417
2418         if (active_irqs & LINE_FLAG_INTR) {
2419                 complete(&vop->line_flag_completion);
2420                 active_irqs &= ~LINE_FLAG_INTR;
2421                 ret = IRQ_HANDLED;
2422         }
2423
2424         if (active_irqs & FS_INTR) {
2425                 drm_crtc_handle_vblank(crtc);
2426                 vop_handle_vblank(vop);
2427                 active_irqs &= ~FS_INTR;
2428                 ret = IRQ_HANDLED;
2429         }
2430
2431         /* Unhandled irqs are spurious. */
2432         if (active_irqs)
2433                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2434
2435         return ret;
2436 }
2437
2438 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2439                           unsigned long possible_crtcs)
2440 {
2441         struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2442         struct drm_plane *share = NULL;
2443         unsigned int rotations = 0;
2444         struct drm_property *prop;
2445         uint64_t feature = 0;
2446         int ret;
2447
2448         if (win->parent)
2449                 share = &win->parent->base;
2450
2451         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2452                                    possible_crtcs, &vop_plane_funcs,
2453                                    win->data_formats, win->nformats, win->type);
2454         if (ret) {
2455                 DRM_ERROR("failed to initialize plane\n");
2456                 return ret;
2457         }
2458         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2459         drm_object_attach_property(&win->base.base,
2460                                    vop->plane_zpos_prop, win->win_id);
2461
2462         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2463                 rotations |= BIT(DRM_REFLECT_X);
2464
2465         if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2466                 rotations |= BIT(DRM_REFLECT_Y);
2467
2468                 prop = drm_property_create_bool(vop->drm_dev,
2469                                                 DRM_MODE_PROP_ATOMIC,
2470                                                 "LOGO_YMIRROR");
2471                 if (!prop)
2472                         return -ENOMEM;
2473                 private->logo_ymirror_prop = prop;
2474         }
2475
2476         if (rotations) {
2477                 rotations |= BIT(DRM_ROTATE_0);
2478                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2479                                                          rotations);
2480                 if (!prop) {
2481                         DRM_ERROR("failed to create zpos property\n");
2482                         return -EINVAL;
2483                 }
2484                 drm_object_attach_property(&win->base.base, prop,
2485                                            BIT(DRM_ROTATE_0));
2486                 win->rotation_prop = prop;
2487         }
2488         if (win->phy->scl)
2489                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2490         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2491             VOP_WIN_SUPPORT(vop, win, alpha_en))
2492                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2493
2494         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2495                                    feature);
2496
2497         return 0;
2498 }
2499
2500 static int vop_create_crtc(struct vop *vop)
2501 {
2502         struct device *dev = vop->dev;
2503         const struct vop_data *vop_data = vop->data;
2504         struct drm_device *drm_dev = vop->drm_dev;
2505         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2506         struct drm_crtc *crtc = &vop->crtc;
2507         struct device_node *port;
2508         uint64_t feature = 0;
2509         int ret;
2510         int i;
2511
2512         /*
2513          * Create drm_plane for primary and cursor planes first, since we need
2514          * to pass them to drm_crtc_init_with_planes, which sets the
2515          * "possible_crtcs" to the newly initialized crtc.
2516          */
2517         for (i = 0; i < vop->num_wins; i++) {
2518                 struct vop_win *win = &vop->win[i];
2519
2520                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2521                     win->type != DRM_PLANE_TYPE_CURSOR)
2522                         continue;
2523
2524                 ret = vop_plane_init(vop, win, 0);
2525                 if (ret)
2526                         goto err_cleanup_planes;
2527
2528                 plane = &win->base;
2529                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2530                         primary = plane;
2531                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2532                         cursor = plane;
2533
2534         }
2535
2536         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2537                                         &vop_crtc_funcs, NULL);
2538         if (ret)
2539                 goto err_cleanup_planes;
2540
2541         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2542
2543         /*
2544          * Create drm_planes for overlay windows with possible_crtcs restricted
2545          * to the newly created crtc.
2546          */
2547         for (i = 0; i < vop->num_wins; i++) {
2548                 struct vop_win *win = &vop->win[i];
2549                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2550
2551                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2552                         continue;
2553
2554                 ret = vop_plane_init(vop, win, possible_crtcs);
2555                 if (ret)
2556                         goto err_cleanup_crtc;
2557         }
2558
2559         port = of_get_child_by_name(dev->of_node, "port");
2560         if (!port) {
2561                 DRM_ERROR("no port node found in %s\n",
2562                           dev->of_node->full_name);
2563                 ret = -ENOENT;
2564                 goto err_cleanup_crtc;
2565         }
2566
2567         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
2568                            vop_fb_unref_worker);
2569
2570         init_completion(&vop->dsp_hold_completion);
2571         init_completion(&vop->line_flag_completion);
2572         crtc->port = port;
2573         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2574
2575         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2576         if (ret)
2577                 goto err_unregister_crtc_funcs;
2578 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2579         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2580
2581         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2582         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2583         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2584         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2585 #undef VOP_ATTACH_MODE_CONFIG_PROP
2586
2587         if (vop_data->feature & VOP_FEATURE_AFBDC)
2588                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2589         drm_object_attach_property(&crtc->base, vop->feature_prop,
2590                                    feature);
2591         if (vop->lut_regs) {
2592                 u16 *r_base, *g_base, *b_base;
2593                 u32 lut_len = vop->lut_len;
2594
2595                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2596                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2597                                               GFP_KERNEL);
2598                 if (!vop->lut)
2599                         return -ENOMEM;
2600
2601                 r_base = crtc->gamma_store;
2602                 g_base = r_base + crtc->gamma_size;
2603                 b_base = g_base + crtc->gamma_size;
2604
2605                 for (i = 0; i < lut_len; i++) {
2606                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2607                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2608                                                        &g_base[i], &b_base[i],
2609                                                        i);
2610                 }
2611         }
2612
2613         return 0;
2614
2615 err_unregister_crtc_funcs:
2616         rockchip_unregister_crtc_funcs(crtc);
2617 err_cleanup_crtc:
2618         drm_crtc_cleanup(crtc);
2619 err_cleanup_planes:
2620         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2621                                  head)
2622                 drm_plane_cleanup(plane);
2623         return ret;
2624 }
2625
2626 static void vop_destroy_crtc(struct vop *vop)
2627 {
2628         struct drm_crtc *crtc = &vop->crtc;
2629         struct drm_device *drm_dev = vop->drm_dev;
2630         struct drm_plane *plane, *tmp;
2631
2632         rockchip_unregister_crtc_funcs(crtc);
2633         of_node_put(crtc->port);
2634
2635         /*
2636          * We need to cleanup the planes now.  Why?
2637          *
2638          * The planes are "&vop->win[i].base".  That means the memory is
2639          * all part of the big "struct vop" chunk of memory.  That memory
2640          * was devm allocated and associated with this component.  We need to
2641          * free it ourselves before vop_unbind() finishes.
2642          */
2643         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2644                                  head)
2645                 vop_plane_destroy(plane);
2646
2647         /*
2648          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2649          * references the CRTC.
2650          */
2651         drm_crtc_cleanup(crtc);
2652         drm_flip_work_cleanup(&vop->fb_unref_work);
2653 }
2654
2655 /*
2656  * Initialize the vop->win array elements.
2657  */
2658 static int vop_win_init(struct vop *vop)
2659 {
2660         const struct vop_data *vop_data = vop->data;
2661         unsigned int i, j;
2662         unsigned int num_wins = 0;
2663         struct drm_property *prop;
2664         static const struct drm_prop_enum_list props[] = {
2665                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2666                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2667         };
2668         static const struct drm_prop_enum_list crtc_props[] = {
2669                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2670         };
2671
2672         for (i = 0; i < vop_data->win_size; i++) {
2673                 struct vop_win *vop_win = &vop->win[num_wins];
2674                 const struct vop_win_data *win_data = &vop_data->win[i];
2675
2676                 if (!win_data->phy)
2677                         continue;
2678
2679                 vop_win->phy = win_data->phy;
2680                 vop_win->csc = win_data->csc;
2681                 vop_win->offset = win_data->base;
2682                 vop_win->type = win_data->type;
2683                 vop_win->data_formats = win_data->phy->data_formats;
2684                 vop_win->nformats = win_data->phy->nformats;
2685                 vop_win->vop = vop;
2686                 vop_win->win_id = i;
2687                 vop_win->area_id = 0;
2688                 num_wins++;
2689
2690                 for (j = 0; j < win_data->area_size; j++) {
2691                         struct vop_win *vop_area = &vop->win[num_wins];
2692                         const struct vop_win_phy *area = win_data->area[j];
2693
2694                         vop_area->parent = vop_win;
2695                         vop_area->offset = vop_win->offset;
2696                         vop_area->phy = area;
2697                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2698                         vop_area->data_formats = vop_win->data_formats;
2699                         vop_area->nformats = vop_win->nformats;
2700                         vop_area->vop = vop;
2701                         vop_area->win_id = i;
2702                         vop_area->area_id = j;
2703                         num_wins++;
2704                 }
2705         }
2706
2707         vop->num_wins = num_wins;
2708
2709         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2710                                          "ZPOS", 0, vop->data->win_size);
2711         if (!prop) {
2712                 DRM_ERROR("failed to create zpos property\n");
2713                 return -EINVAL;
2714         }
2715         vop->plane_zpos_prop = prop;
2716
2717         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2718                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2719                                 props, ARRAY_SIZE(props),
2720                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2721                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2722         if (!vop->plane_feature_prop) {
2723                 DRM_ERROR("failed to create feature property\n");
2724                 return -EINVAL;
2725         }
2726
2727         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2728                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2729                                 crtc_props, ARRAY_SIZE(crtc_props),
2730                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2731         if (!vop->feature_prop) {
2732                 DRM_ERROR("failed to create vop feature property\n");
2733                 return -EINVAL;
2734         }
2735
2736         return 0;
2737 }
2738
2739 /**
2740  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2741  * @crtc: CRTC to enable line flag
2742  * @line_num: interested line number
2743  * @mstimeout: millisecond for timeout
2744  *
2745  * Driver would hold here until the interested line flag interrupt have
2746  * happened or timeout to wait.
2747  *
2748  * Returns:
2749  * Zero on success, negative errno on failure.
2750  */
2751 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2752                                 unsigned int mstimeout)
2753 {
2754         struct vop *vop = to_vop(crtc);
2755         unsigned long jiffies_left;
2756         int ret = 0;
2757
2758         if (!crtc || !vop->is_enabled)
2759                 return -ENODEV;
2760
2761         mutex_lock(&vop->vop_lock);
2762
2763         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2764                 ret = -EINVAL;
2765                 goto out;
2766         }
2767
2768         if (vop_line_flag_irq_is_enabled(vop)) {
2769                 ret = -EBUSY;
2770                 goto out;
2771         }
2772
2773         reinit_completion(&vop->line_flag_completion);
2774         vop_line_flag_irq_enable(vop, line_num);
2775
2776         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2777                                                    msecs_to_jiffies(mstimeout));
2778         vop_line_flag_irq_disable(vop);
2779
2780         if (jiffies_left == 0) {
2781                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2782                 ret = -ETIMEDOUT;
2783                 goto out;
2784         }
2785
2786 out:
2787         mutex_unlock(&vop->vop_lock);
2788
2789         return ret;
2790 }
2791 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2792
2793 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
2794                              void *data)
2795 {
2796         if (event == DEVFREQ_PRECHANGE)
2797                 mutex_lock(&dmc_vop->vop_lock);
2798         else if (event == DEVFREQ_POSTCHANGE)
2799                 mutex_unlock(&dmc_vop->vop_lock);
2800
2801         return NOTIFY_OK;
2802 }
2803
2804 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
2805 {
2806         if (!dmc_vop)
2807                 return -ENOMEM;
2808
2809         dmc_vop->devfreq = devfreq;
2810         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
2811         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
2812                                   DEVFREQ_TRANSITION_NOTIFIER);
2813         return 0;
2814 }
2815 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
2816
2817 static int vop_bind(struct device *dev, struct device *master, void *data)
2818 {
2819         struct platform_device *pdev = to_platform_device(dev);
2820         const struct vop_data *vop_data;
2821         struct drm_device *drm_dev = data;
2822         struct vop *vop;
2823         struct resource *res;
2824         size_t alloc_size;
2825         int ret, irq, i;
2826         int num_wins = 0;
2827
2828         vop_data = of_device_get_match_data(dev);
2829         if (!vop_data)
2830                 return -ENODEV;
2831
2832         for (i = 0; i < vop_data->win_size; i++) {
2833                 const struct vop_win_data *win_data = &vop_data->win[i];
2834
2835                 num_wins += win_data->area_size + 1;
2836         }
2837
2838         /* Allocate vop struct and its vop_win array */
2839         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2840         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2841         if (!vop)
2842                 return -ENOMEM;
2843
2844         vop->dev = dev;
2845         vop->data = vop_data;
2846         vop->drm_dev = drm_dev;
2847         vop->num_wins = num_wins;
2848         dev_set_drvdata(dev, vop);
2849
2850         ret = vop_win_init(vop);
2851         if (ret)
2852                 return ret;
2853
2854         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
2855         if (!res) {
2856                 dev_warn(vop->dev, "failed to get vop register byname\n");
2857                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2858         }
2859         vop->regs = devm_ioremap_resource(dev, res);
2860         if (IS_ERR(vop->regs))
2861                 return PTR_ERR(vop->regs);
2862         vop->len = resource_size(res);
2863
2864         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2865         if (!vop->regsbak)
2866                 return -ENOMEM;
2867
2868         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
2869         vop->lut_regs = devm_ioremap_resource(dev, res);
2870         if (IS_ERR(vop->lut_regs)) {
2871                 dev_warn(vop->dev, "failed to get vop lut registers\n");
2872                 vop->lut_regs = NULL;
2873         }
2874         if (vop->lut_regs) {
2875                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
2876                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
2877                         dev_err(vop->dev, "unsupport lut sizes %d\n",
2878                                 vop->lut_len);
2879                         return -EINVAL;
2880                 }
2881         }
2882
2883         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2884         if (IS_ERR(vop->hclk)) {
2885                 dev_err(vop->dev, "failed to get hclk source\n");
2886                 return PTR_ERR(vop->hclk);
2887         }
2888         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2889         if (IS_ERR(vop->aclk)) {
2890                 dev_err(vop->dev, "failed to get aclk source\n");
2891                 return PTR_ERR(vop->aclk);
2892         }
2893         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2894         if (IS_ERR(vop->dclk)) {
2895                 dev_err(vop->dev, "failed to get dclk source\n");
2896                 return PTR_ERR(vop->dclk);
2897         }
2898
2899         vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
2900         if (PTR_ERR(vop->dclk_source) == -ENOENT) {
2901                 vop->dclk_source = NULL;
2902         } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
2903                 return -EPROBE_DEFER;
2904         } else if (IS_ERR(vop->dclk_source)) {
2905                 dev_err(vop->dev, "failed to get dclk source parent\n");
2906                 return PTR_ERR(vop->dclk_source);
2907         }
2908
2909         irq = platform_get_irq(pdev, 0);
2910         if (irq < 0) {
2911                 dev_err(dev, "cannot find irq for vop\n");
2912                 return irq;
2913         }
2914         vop->irq = (unsigned int)irq;
2915
2916         spin_lock_init(&vop->reg_lock);
2917         spin_lock_init(&vop->irq_lock);
2918         mutex_init(&vop->vop_lock);
2919
2920         mutex_init(&vop->vsync_mutex);
2921
2922         ret = devm_request_irq(dev, vop->irq, vop_isr,
2923                                IRQF_SHARED, dev_name(dev), vop);
2924         if (ret)
2925                 return ret;
2926
2927         /* IRQ is initially disabled; it gets enabled in power_on */
2928         disable_irq(vop->irq);
2929
2930         ret = vop_create_crtc(vop);
2931         if (ret)
2932                 return ret;
2933
2934         pm_runtime_enable(&pdev->dev);
2935
2936         dmc_vop = vop;
2937
2938         return 0;
2939 }
2940
2941 static void vop_unbind(struct device *dev, struct device *master, void *data)
2942 {
2943         struct vop *vop = dev_get_drvdata(dev);
2944
2945         pm_runtime_disable(dev);
2946         vop_destroy_crtc(vop);
2947 }
2948
2949 const struct component_ops vop_component_ops = {
2950         .bind = vop_bind,
2951         .unbind = vop_unbind,
2952 };
2953 EXPORT_SYMBOL_GPL(vop_component_ops);