drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/component.h>
  28
  29 #include <linux/reset.h>
  30 #include <linux/delay.h>
  31
  32 #include "rockchip_drm_drv.h"
  33 #include "rockchip_drm_gem.h"
  34 #include "rockchip_drm_fb.h"
  35 #include "rockchip_drm_vop.h"
  36
  37 #define VOP_REG(off, _mask, s) \
  38                 {.offset = off, \
  39                  .mask = _mask, \
  40                  .shift = s,}
  41
  42 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  43                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  44 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  45                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  46
  47 #define REG_SET(x, base, reg, v, mode) \
  48                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  49
  50 #define VOP_WIN_SET(x, win, name, v) \
  51                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  52 #define VOP_CTRL_SET(x, name, v) \
  53                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  54
  55 #define VOP_WIN_GET(x, win, name) \
  56                 vop_read_reg(x, win->base, &win->phy->name)
  57
  58 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  59                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  60
  61 #define to_vop(x) container_of(x, struct vop, crtc)
  62 #define to_vop_win(x) container_of(x, struct vop_win, base)
  63
  64 struct vop_win_state {
  65         struct list_head head;
  66         struct drm_framebuffer *fb;
  67         dma_addr_t yrgb_mst;
  68         struct drm_pending_vblank_event *event;
  69 };
  70
  71 struct vop_win {
  72         struct drm_plane base;
  73         const struct vop_win_data *data;
  74         struct vop *vop;
  75
  76         struct list_head pending;
  77         struct vop_win_state *active;
  78 };
  79
  80 struct vop {
  81         struct drm_crtc crtc;
  82         struct device *dev;
  83         struct drm_device *drm_dev;
  84         bool is_enabled;
  85
  86         int connector_type;
  87         int connector_out_mode;
  88
  89         /* mutex vsync_ work */
  90         struct mutex vsync_mutex;
  91         bool vsync_work_pending;
  92         struct completion dsp_hold_completion;
  93
  94         const struct vop_data *data;
  95
  96         uint32_t *regsbak;
  97         void __iomem *regs;
  98
  99         /* physical map length of vop register */
 100         uint32_t len;
 101
 102         /* one time only one process allowed to config the register */
 103         spinlock_t reg_lock;
 104         /* lock vop irq reg */
 105         spinlock_t irq_lock;
 106
 107         unsigned int irq;
 108
 109         /* vop AHP clk */
 110         struct clk *hclk;
 111         /* vop dclk */
 112         struct clk *dclk;
 113         /* vop share memory frequency */
 114         struct clk *aclk;
 115
 116         /* vop dclk reset */
 117         struct reset_control *dclk_rst;
 118
 119         int pipe;
 120
 121         struct vop_win win[];
 122 };
 123
 124 enum vop_data_format {
 125         VOP_FMT_ARGB8888 = 0,
 126         VOP_FMT_RGB888,
 127         VOP_FMT_RGB565,
 128         VOP_FMT_YUV420SP = 4,
 129         VOP_FMT_YUV422SP,
 130         VOP_FMT_YUV444SP,
 131 };
 132
 133 struct vop_reg_data {
 134         uint32_t offset;
 135         uint32_t value;
 136 };
 137
 138 struct vop_reg {
 139         uint32_t offset;
 140         uint32_t shift;
 141         uint32_t mask;
 142 };
 143
 144 struct vop_ctrl {
 145         struct vop_reg standby;
 146         struct vop_reg data_blank;
 147         struct vop_reg gate_en;
 148         struct vop_reg mmu_en;
 149         struct vop_reg rgb_en;
 150         struct vop_reg edp_en;
 151         struct vop_reg hdmi_en;
 152         struct vop_reg mipi_en;
 153         struct vop_reg out_mode;
 154         struct vop_reg dither_down;
 155         struct vop_reg dither_up;
 156         struct vop_reg pin_pol;
 157
 158         struct vop_reg htotal_pw;
 159         struct vop_reg hact_st_end;
 160         struct vop_reg vtotal_pw;
 161         struct vop_reg vact_st_end;
 162         struct vop_reg hpost_st_end;
 163         struct vop_reg vpost_st_end;
 164 };
 165
 166 struct vop_win_phy {
 167         const uint32_t *data_formats;
 168         uint32_t nformats;
 169
 170         struct vop_reg enable;
 171         struct vop_reg format;
 172         struct vop_reg rb_swap;
 173         struct vop_reg act_info;
 174         struct vop_reg dsp_info;
 175         struct vop_reg dsp_st;
 176         struct vop_reg yrgb_mst;
 177         struct vop_reg uv_mst;
 178         struct vop_reg yrgb_vir;
 179         struct vop_reg uv_vir;
 180
 181         struct vop_reg dst_alpha_ctl;
 182         struct vop_reg src_alpha_ctl;
 183 };
 184
 185 struct vop_win_data {
 186         uint32_t base;
 187         const struct vop_win_phy *phy;
 188         enum drm_plane_type type;
 189 };
 190
 191 struct vop_data {
 192         const struct vop_reg_data *init_table;
 193         unsigned int table_size;
 194         const struct vop_ctrl *ctrl;
 195         const struct vop_win_data *win;
 196         unsigned int win_size;
 197 };
 198
 199 static const uint32_t formats_01[] = {
 200         DRM_FORMAT_XRGB8888,
 201         DRM_FORMAT_ARGB8888,
 202         DRM_FORMAT_XBGR8888,
 203         DRM_FORMAT_ABGR8888,
 204         DRM_FORMAT_RGB888,
 205         DRM_FORMAT_BGR888,
 206         DRM_FORMAT_RGB565,
 207         DRM_FORMAT_BGR565,
 208         DRM_FORMAT_NV12,
 209         DRM_FORMAT_NV16,
 210         DRM_FORMAT_NV24,
 211 };
 212
 213 static const uint32_t formats_234[] = {
 214         DRM_FORMAT_XRGB8888,
 215         DRM_FORMAT_ARGB8888,
 216         DRM_FORMAT_XBGR8888,
 217         DRM_FORMAT_ABGR8888,
 218         DRM_FORMAT_RGB888,
 219         DRM_FORMAT_BGR888,
 220         DRM_FORMAT_RGB565,
 221         DRM_FORMAT_BGR565,
 222 };
 223
 224 static const struct vop_win_phy win01_data = {
 225         .data_formats = formats_01,
 226         .nformats = ARRAY_SIZE(formats_01),
 227         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 228         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 229         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
 230         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 231         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 232         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 233         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 234         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 235         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 236         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 237         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 238         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 239 };
 240
 241 static const struct vop_win_phy win23_data = {
 242         .data_formats = formats_234,
 243         .nformats = ARRAY_SIZE(formats_234),
 244         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 245         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 246         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 247         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 248         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 249         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 250         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 251         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 252         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 253 };
 254
 255 static const struct vop_ctrl ctrl_data = {
 256         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 257         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 258         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 259         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 260         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 261         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 262         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 263         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 264         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 265         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 266         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 267         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 268         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 269         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 270         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 271         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 272         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 273         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 274 };
 275
 276 static const struct vop_reg_data vop_init_reg_table[] = {
 277         {SYS_CTRL, 0x00c00000},
 278         {DSP_CTRL0, 0x00000000},
 279         {WIN0_CTRL0, 0x00000080},
 280         {WIN1_CTRL0, 0x00000080},
 281 };
 282
 283 /*
 284  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 285  * special support to get alpha blending working.  For now, just use overlay
 286  * window 3 for the drm cursor.
 287  *
 288  */
 289 static const struct vop_win_data rk3288_vop_win_data[] = {
 290         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 291         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 292         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 293         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 294 };
 295
 296 static const struct vop_data rk3288_vop = {
 297         .init_table = vop_init_reg_table,
 298         .table_size = ARRAY_SIZE(vop_init_reg_table),
 299         .ctrl = &ctrl_data,
 300         .win = rk3288_vop_win_data,
 301         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 302 };
 303
 304 static const struct of_device_id vop_driver_dt_match[] = {
 305         { .compatible = "rockchip,rk3288-vop",
 306           .data = &rk3288_vop },
 307         {},
 308 };
 309
 310 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 311 {
 312         writel(v, vop->regs + offset);
 313         vop->regsbak[offset >> 2] = v;
 314 }
 315
 316 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 317 {
 318         return readl(vop->regs + offset);
 319 }
 320
 321 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 322                                     const struct vop_reg *reg)
 323 {
 324         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 325 }
 326
 327 static inline void vop_cfg_done(struct vop *vop)
 328 {
 329         writel(0x01, vop->regs + REG_CFG_DONE);
 330 }
 331
 332 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 333                                   uint32_t mask, uint32_t v)
 334 {
 335         if (mask) {
 336                 uint32_t cached_val = vop->regsbak[offset >> 2];
 337
 338                 cached_val = (cached_val & ~mask) | v;
 339                 writel(cached_val, vop->regs + offset);
 340                 vop->regsbak[offset >> 2] = cached_val;
 341         }
 342 }
 343
 344 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 345                                           uint32_t mask, uint32_t v)
 346 {
 347         if (mask) {
 348                 uint32_t cached_val = vop->regsbak[offset >> 2];
 349
 350                 cached_val = (cached_val & ~mask) | v;
 351                 writel_relaxed(cached_val, vop->regs + offset);
 352                 vop->regsbak[offset >> 2] = cached_val;
 353         }
 354 }
 355
 356 static bool has_rb_swapped(uint32_t format)
 357 {
 358         switch (format) {
 359         case DRM_FORMAT_XBGR8888:
 360         case DRM_FORMAT_ABGR8888:
 361         case DRM_FORMAT_BGR888:
 362         case DRM_FORMAT_BGR565:
 363                 return true;
 364         default:
 365                 return false;
 366         }
 367 }
 368
 369 static enum vop_data_format vop_convert_format(uint32_t format)
 370 {
 371         switch (format) {
 372         case DRM_FORMAT_XRGB8888:
 373         case DRM_FORMAT_ARGB8888:
 374         case DRM_FORMAT_XBGR8888:
 375         case DRM_FORMAT_ABGR8888:
 376                 return VOP_FMT_ARGB8888;
 377         case DRM_FORMAT_RGB888:
 378         case DRM_FORMAT_BGR888:
 379                 return VOP_FMT_RGB888;
 380         case DRM_FORMAT_RGB565:
 381         case DRM_FORMAT_BGR565:
 382                 return VOP_FMT_RGB565;
 383         case DRM_FORMAT_NV12:
 384                 return VOP_FMT_YUV420SP;
 385         case DRM_FORMAT_NV16:
 386                 return VOP_FMT_YUV422SP;
 387         case DRM_FORMAT_NV24:
 388                 return VOP_FMT_YUV444SP;
 389         default:
 390                 DRM_ERROR("unsupport format[%08x]\n", format);
 391                 return -EINVAL;
 392         }
 393 }
 394
 395 static bool is_alpha_support(uint32_t format)
 396 {
 397         switch (format) {
 398         case DRM_FORMAT_ARGB8888:
 399         case DRM_FORMAT_ABGR8888:
 400                 return true;
 401         default:
 402                 return false;
 403         }
 404 }
 405
 406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 407 {
 408         unsigned long flags;
 409
 410         if (WARN_ON(!vop->is_enabled))
 411                 return;
 412
 413         spin_lock_irqsave(&vop->irq_lock, flags);
 414
 415         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 416                        DSP_HOLD_VALID_INTR_EN(1));
 417
 418         spin_unlock_irqrestore(&vop->irq_lock, flags);
 419 }
 420
 421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 422 {
 423         unsigned long flags;
 424
 425         if (WARN_ON(!vop->is_enabled))
 426                 return;
 427
 428         spin_lock_irqsave(&vop->irq_lock, flags);
 429
 430         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 431                        DSP_HOLD_VALID_INTR_EN(0));
 432
 433         spin_unlock_irqrestore(&vop->irq_lock, flags);
 434 }
 435
 436 static void vop_enable(struct drm_crtc *crtc)
 437 {
 438         struct vop *vop = to_vop(crtc);
 439         int ret;
 440
 441         if (vop->is_enabled)
 442                 return;
 443
 444         ret = pm_runtime_get_sync(vop->dev);
 445         if (ret < 0) {
 446                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 447                 return;
 448         }
 449
 450         ret = clk_enable(vop->hclk);
 451         if (ret < 0) {
 452                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 453                 return;
 454         }
 455
 456         ret = clk_enable(vop->dclk);
 457         if (ret < 0) {
 458                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 459                 goto err_disable_hclk;
 460         }
 461
 462         ret = clk_enable(vop->aclk);
 463         if (ret < 0) {
 464                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 465                 goto err_disable_dclk;
 466         }
 467
 468         /*
 469          * Slave iommu shares power, irq and clock with vop.  It was associated
 470          * automatically with this master device via common driver code.
 471          * Now that we have enabled the clock we attach it to the shared drm
 472          * mapping.
 473          */
 474         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 475         if (ret) {
 476                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 477                 goto err_disable_aclk;
 478         }
 479
 480         /*
 481          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 482          */
 483         vop->is_enabled = true;
 484
 485         spin_lock(&vop->reg_lock);
 486
 487         VOP_CTRL_SET(vop, standby, 0);
 488
 489         spin_unlock(&vop->reg_lock);
 490
 491         enable_irq(vop->irq);
 492
 493         drm_vblank_on(vop->drm_dev, vop->pipe);
 494
 495         return;
 496
 497 err_disable_aclk:
 498         clk_disable(vop->aclk);
 499 err_disable_dclk:
 500         clk_disable(vop->dclk);
 501 err_disable_hclk:
 502         clk_disable(vop->hclk);
 503 }
 504
 505 static void vop_disable(struct drm_crtc *crtc)
 506 {
 507         struct vop *vop = to_vop(crtc);
 508
 509         if (!vop->is_enabled)
 510                 return;
 511
 512         drm_vblank_off(crtc->dev, vop->pipe);
 513
 514         /*
 515          * Vop standby will take effect at end of current frame,
 516          * if dsp hold valid irq happen, it means standby complete.
 517          *
 518          * we must wait standby complete when we want to disable aclk,
 519          * if not, memory bus maybe dead.
 520          */
 521         reinit_completion(&vop->dsp_hold_completion);
 522         vop_dsp_hold_valid_irq_enable(vop);
 523
 524         spin_lock(&vop->reg_lock);
 525
 526         VOP_CTRL_SET(vop, standby, 1);
 527
 528         spin_unlock(&vop->reg_lock);
 529
 530         wait_for_completion(&vop->dsp_hold_completion);
 531
 532         vop_dsp_hold_valid_irq_disable(vop);
 533
 534         disable_irq(vop->irq);
 535
 536         vop->is_enabled = false;
 537
 538         /*
 539          * vop standby complete, so iommu detach is safe.
 540          */
 541         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 542
 543         clk_disable(vop->dclk);
 544         clk_disable(vop->aclk);
 545         clk_disable(vop->hclk);
 546         pm_runtime_put(vop->dev);
 547 }
 548
 549 /*
 550  * Caller must hold vsync_mutex.
 551  */
 552 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
 553 {
 554         struct vop_win_state *last;
 555         struct vop_win_state *active = vop_win->active;
 556
 557         if (list_empty(&vop_win->pending))
 558                 return active ? active->fb : NULL;
 559
 560         last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
 561         return last ? last->fb : NULL;
 562 }
 563
 564 /*
 565  * Caller must hold vsync_mutex.
 566  */
 567 static int vop_win_queue_fb(struct vop_win *vop_win,
 568                             struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
 569                             struct drm_pending_vblank_event *event)
 570 {
 571         struct vop_win_state *state;
 572
 573         state = kzalloc(sizeof(*state), GFP_KERNEL);
 574         if (!state)
 575                 return -ENOMEM;
 576
 577         state->fb = fb;
 578         state->yrgb_mst = yrgb_mst;
 579         state->event = event;
 580
 581         list_add_tail(&state->head, &vop_win->pending);
 582
 583         return 0;
 584 }
 585
 586 static int vop_update_plane_event(struct drm_plane *plane,
 587                                   struct drm_crtc *crtc,
 588                                   struct drm_framebuffer *fb, int crtc_x,
 589                                   int crtc_y, unsigned int crtc_w,
 590                                   unsigned int crtc_h, uint32_t src_x,
 591                                   uint32_t src_y, uint32_t src_w,
 592                                   uint32_t src_h,
 593                                   struct drm_pending_vblank_event *event)
 594 {
 595         struct vop_win *vop_win = to_vop_win(plane);
 596         const struct vop_win_data *win = vop_win->data;
 597         struct vop *vop = to_vop(crtc);
 598         struct drm_gem_object *obj;
 599         struct rockchip_gem_object *rk_obj;
 600         unsigned long offset;
 601         unsigned int actual_w;
 602         unsigned int actual_h;
 603         unsigned int dsp_stx;
 604         unsigned int dsp_sty;
 605         unsigned int y_vir_stride;
 606         dma_addr_t yrgb_mst;
 607         enum vop_data_format format;
 608         uint32_t val;
 609         bool is_alpha;
 610         bool rb_swap;
 611         bool visible;
 612         int ret;
 613         struct drm_rect dest = {
 614                 .x1 = crtc_x,
 615                 .y1 = crtc_y,
 616                 .x2 = crtc_x + crtc_w,
 617                 .y2 = crtc_y + crtc_h,
 618         };
 619         struct drm_rect src = {
 620                 /* 16.16 fixed point */
 621                 .x1 = src_x,
 622                 .y1 = src_y,
 623                 .x2 = src_x + src_w,
 624                 .y2 = src_y + src_h,
 625         };
 626         const struct drm_rect clip = {
 627                 .x2 = crtc->mode.hdisplay,
 628                 .y2 = crtc->mode.vdisplay,
 629         };
 630         bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
 631
 632         ret = drm_plane_helper_check_update(plane, crtc, fb,
 633                                             &src, &dest, &clip,
 634                                             DRM_PLANE_HELPER_NO_SCALING,
 635                                             DRM_PLANE_HELPER_NO_SCALING,
 636                                             can_position, false, &visible);
 637         if (ret)
 638                 return ret;
 639
 640         if (!visible)
 641                 return 0;
 642
 643         is_alpha = is_alpha_support(fb->pixel_format);
 644         rb_swap = has_rb_swapped(fb->pixel_format);
 645         format = vop_convert_format(fb->pixel_format);
 646         if (format < 0)
 647                 return format;
 648
 649         obj = rockchip_fb_get_gem_obj(fb, 0);
 650         if (!obj) {
 651                 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
 652                 return -EINVAL;
 653         }
 654
 655         rk_obj = to_rockchip_obj(obj);
 656
 657         actual_w = (src.x2 - src.x1) >> 16;
 658         actual_h = (src.y2 - src.y1) >> 16;
 659         crtc_x = max(0, crtc_x);
 660         crtc_y = max(0, crtc_y);
 661
 662         dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start;
 663         dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start;
 664
 665         offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
 666         offset += (src.y1 >> 16) * fb->pitches[0];
 667         yrgb_mst = rk_obj->dma_addr + offset;
 668
 669         y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3);
 670
 671         /*
 672          * If this plane update changes the plane's framebuffer, (or more
 673          * precisely, if this update has a different framebuffer than the last
 674          * update), enqueue it so we can track when it completes.
 675          *
 676          * Only when we discover that this update has completed, can we
 677          * unreference any previous framebuffers.
 678          */
 679         mutex_lock(&vop->vsync_mutex);
 680         if (fb != vop_win_last_pending_fb(vop_win)) {
 681                 ret = drm_vblank_get(plane->dev, vop->pipe);
 682                 if (ret) {
 683                         DRM_ERROR("failed to get vblank, %d\n", ret);
 684                         mutex_unlock(&vop->vsync_mutex);
 685                         return ret;
 686                 }
 687
 688                 drm_framebuffer_reference(fb);
 689
 690                 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
 691                 if (ret) {
 692                         drm_vblank_put(plane->dev, vop->pipe);
 693                         mutex_unlock(&vop->vsync_mutex);
 694                         return ret;
 695                 }
 696
 697                 vop->vsync_work_pending = true;
 698         }
 699         mutex_unlock(&vop->vsync_mutex);
 700
 701         spin_lock(&vop->reg_lock);
 702
 703         VOP_WIN_SET(vop, win, format, format);
 704         VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 705         VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
 706         val = (actual_h - 1) << 16;
 707         val |= (actual_w - 1) & 0xffff;
 708         VOP_WIN_SET(vop, win, act_info, val);
 709         VOP_WIN_SET(vop, win, dsp_info, val);
 710         val = (dsp_sty - 1) << 16;
 711         val |= (dsp_stx - 1) & 0xffff;
 712         VOP_WIN_SET(vop, win, dsp_st, val);
 713         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 714
 715         if (is_alpha) {
 716                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 717                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 718                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 719                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 720                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 721                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 722                         SRC_FACTOR_M0(ALPHA_ONE);
 723                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 724         } else {
 725                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 726         }
 727
 728         VOP_WIN_SET(vop, win, enable, 1);
 729
 730         vop_cfg_done(vop);
 731         spin_unlock(&vop->reg_lock);
 732
 733         return 0;
 734 }
 735
 736 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 737                             struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 738                             unsigned int crtc_w, unsigned int crtc_h,
 739                             uint32_t src_x, uint32_t src_y, uint32_t src_w,
 740                             uint32_t src_h)
 741 {
 742         return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
 743                                       crtc_h, src_x, src_y, src_w, src_h,
 744                                       NULL);
 745 }
 746
 747 static int vop_update_primary_plane(struct drm_crtc *crtc,
 748                                     struct drm_pending_vblank_event *event)
 749 {
 750         unsigned int crtc_w, crtc_h;
 751
 752         crtc_w = crtc->primary->fb->width - crtc->x;
 753         crtc_h = crtc->primary->fb->height - crtc->y;
 754
 755         return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
 756                                       0, 0, crtc_w, crtc_h, crtc->x << 16,
 757                                       crtc->y << 16, crtc_w << 16,
 758                                       crtc_h << 16, event);
 759 }
 760
 761 static int vop_disable_plane(struct drm_plane *plane)
 762 {
 763         struct vop_win *vop_win = to_vop_win(plane);
 764         const struct vop_win_data *win = vop_win->data;
 765         struct vop *vop;
 766         int ret;
 767
 768         if (!plane->crtc)
 769                 return 0;
 770
 771         vop = to_vop(plane->crtc);
 772
 773         ret = drm_vblank_get(plane->dev, vop->pipe);
 774         if (ret) {
 775                 DRM_ERROR("failed to get vblank, %d\n", ret);
 776                 return ret;
 777         }
 778
 779         mutex_lock(&vop->vsync_mutex);
 780
 781         ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
 782         if (ret) {
 783                 drm_vblank_put(plane->dev, vop->pipe);
 784                 mutex_unlock(&vop->vsync_mutex);
 785                 return ret;
 786         }
 787
 788         vop->vsync_work_pending = true;
 789         mutex_unlock(&vop->vsync_mutex);
 790
 791         spin_lock(&vop->reg_lock);
 792         VOP_WIN_SET(vop, win, enable, 0);
 793         vop_cfg_done(vop);
 794         spin_unlock(&vop->reg_lock);
 795
 796         return 0;
 797 }
 798
 799 static void vop_plane_destroy(struct drm_plane *plane)
 800 {
 801         vop_disable_plane(plane);
 802         drm_plane_cleanup(plane);
 803 }
 804
 805 static const struct drm_plane_funcs vop_plane_funcs = {
 806         .update_plane = vop_update_plane,
 807         .disable_plane = vop_disable_plane,
 808         .destroy = vop_plane_destroy,
 809 };
 810
 811 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 812                                   int connector_type,
 813                                   int out_mode)
 814 {
 815         struct vop *vop = to_vop(crtc);
 816
 817         vop->connector_type = connector_type;
 818         vop->connector_out_mode = out_mode;
 819
 820         return 0;
 821 }
 822 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 823
 824 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 825 {
 826         struct vop *vop = to_vop(crtc);
 827         unsigned long flags;
 828
 829         if (!vop->is_enabled)
 830                 return -EPERM;
 831
 832         spin_lock_irqsave(&vop->irq_lock, flags);
 833
 834         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
 835
 836         spin_unlock_irqrestore(&vop->irq_lock, flags);
 837
 838         return 0;
 839 }
 840
 841 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 842 {
 843         struct vop *vop = to_vop(crtc);
 844         unsigned long flags;
 845
 846         if (!vop->is_enabled)
 847                 return;
 848
 849         spin_lock_irqsave(&vop->irq_lock, flags);
 850         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
 851         spin_unlock_irqrestore(&vop->irq_lock, flags);
 852 }
 853
 854 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 855         .enable_vblank = vop_crtc_enable_vblank,
 856         .disable_vblank = vop_crtc_disable_vblank,
 857 };
 858
 859 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
 860 {
 861         DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
 862
 863         switch (mode) {
 864         case DRM_MODE_DPMS_ON:
 865                 vop_enable(crtc);
 866                 break;
 867         case DRM_MODE_DPMS_STANDBY:
 868         case DRM_MODE_DPMS_SUSPEND:
 869         case DRM_MODE_DPMS_OFF:
 870                 vop_disable(crtc);
 871                 break;
 872         default:
 873                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 874                 break;
 875         }
 876 }
 877
 878 static void vop_crtc_prepare(struct drm_crtc *crtc)
 879 {
 880         vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 881 }
 882
 883 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 884                                 const struct drm_display_mode *mode,
 885                                 struct drm_display_mode *adjusted_mode)
 886 {
 887         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
 888                 return false;
 889
 890         return true;
 891 }
 892
 893 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 894                                   struct drm_framebuffer *old_fb)
 895 {
 896         int ret;
 897
 898         crtc->x = x;
 899         crtc->y = y;
 900
 901         ret = vop_update_primary_plane(crtc, NULL);
 902         if (ret < 0) {
 903                 DRM_ERROR("fail to update plane\n");
 904                 return ret;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int vop_crtc_mode_set(struct drm_crtc *crtc,
 911                              struct drm_display_mode *mode,
 912                              struct drm_display_mode *adjusted_mode,
 913                              int x, int y, struct drm_framebuffer *fb)
 914 {
 915         struct vop *vop = to_vop(crtc);
 916         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 917         u16 hdisplay = adjusted_mode->hdisplay;
 918         u16 htotal = adjusted_mode->htotal;
 919         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 920         u16 hact_end = hact_st + hdisplay;
 921         u16 vdisplay = adjusted_mode->vdisplay;
 922         u16 vtotal = adjusted_mode->vtotal;
 923         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 924         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 925         u16 vact_end = vact_st + vdisplay;
 926         int ret, ret_clk;
 927         uint32_t val;
 928
 929         /*
 930          * disable dclk to stop frame scan, so that we can safe config mode and
 931          * enable iommu.
 932          */
 933         clk_disable(vop->dclk);
 934
 935         switch (vop->connector_type) {
 936         case DRM_MODE_CONNECTOR_LVDS:
 937                 VOP_CTRL_SET(vop, rgb_en, 1);
 938                 break;
 939         case DRM_MODE_CONNECTOR_eDP:
 940                 VOP_CTRL_SET(vop, edp_en, 1);
 941                 break;
 942         case DRM_MODE_CONNECTOR_HDMIA:
 943                 VOP_CTRL_SET(vop, hdmi_en, 1);
 944                 break;
 945         default:
 946                 DRM_ERROR("unsupport connector_type[%d]\n",
 947                           vop->connector_type);
 948                 ret = -EINVAL;
 949                 goto out;
 950         };
 951         VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
 952
 953         val = 0x8;
 954         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
 955         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
 956         VOP_CTRL_SET(vop, pin_pol, val);
 957
 958         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 959         val = hact_st << 16;
 960         val |= hact_end;
 961         VOP_CTRL_SET(vop, hact_st_end, val);
 962         VOP_CTRL_SET(vop, hpost_st_end, val);
 963
 964         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 965         val = vact_st << 16;
 966         val |= vact_end;
 967         VOP_CTRL_SET(vop, vact_st_end, val);
 968         VOP_CTRL_SET(vop, vpost_st_end, val);
 969
 970         ret = vop_crtc_mode_set_base(crtc, x, y, fb);
 971         if (ret)
 972                 goto out;
 973
 974         /*
 975          * reset dclk, take all mode config affect, so the clk would run in
 976          * correct frame.
 977          */
 978         reset_control_assert(vop->dclk_rst);
 979         usleep_range(10, 20);
 980         reset_control_deassert(vop->dclk_rst);
 981
 982         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 983 out:
 984         ret_clk = clk_enable(vop->dclk);
 985         if (ret_clk < 0) {
 986                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
 987                 return ret_clk;
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void vop_crtc_commit(struct drm_crtc *crtc)
 994 {
 995 }
 996
 997 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
 998         .dpms = vop_crtc_dpms,
 999         .prepare = vop_crtc_prepare,
1000         .mode_fixup = vop_crtc_mode_fixup,
1001         .mode_set = vop_crtc_mode_set,
1002         .mode_set_base = vop_crtc_mode_set_base,
1003         .commit = vop_crtc_commit,
1004 };
1005
1006 static int vop_crtc_page_flip(struct drm_crtc *crtc,
1007                               struct drm_framebuffer *fb,
1008                               struct drm_pending_vblank_event *event,
1009                               uint32_t page_flip_flags)
1010 {
1011         struct vop *vop = to_vop(crtc);
1012         struct drm_framebuffer *old_fb = crtc->primary->fb;
1013         int ret;
1014
1015         /* when the page flip is requested, crtc should be on */
1016         if (!vop->is_enabled) {
1017                 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1018                 return 0;
1019         }
1020
1021         crtc->primary->fb = fb;
1022
1023         ret = vop_update_primary_plane(crtc, event);
1024         if (ret)
1025                 crtc->primary->fb = old_fb;
1026
1027         return ret;
1028 }
1029
1030 static void vop_win_state_complete(struct vop_win *vop_win,
1031                                    struct vop_win_state *state)
1032 {
1033         struct vop *vop = vop_win->vop;
1034         struct drm_crtc *crtc = &vop->crtc;
1035         struct drm_device *drm = crtc->dev;
1036         unsigned long flags;
1037
1038         if (state->event) {
1039                 spin_lock_irqsave(&drm->event_lock, flags);
1040                 drm_send_vblank_event(drm, -1, state->event);
1041                 spin_unlock_irqrestore(&drm->event_lock, flags);
1042         }
1043
1044         list_del(&state->head);
1045         drm_vblank_put(crtc->dev, vop->pipe);
1046 }
1047
1048 static void vop_crtc_destroy(struct drm_crtc *crtc)
1049 {
1050         drm_crtc_cleanup(crtc);
1051 }
1052
1053 static const struct drm_crtc_funcs vop_crtc_funcs = {
1054         .set_config = drm_crtc_helper_set_config,
1055         .page_flip = vop_crtc_page_flip,
1056         .destroy = vop_crtc_destroy,
1057 };
1058
1059 static bool vop_win_state_is_active(struct vop_win *vop_win,
1060                                     struct vop_win_state *state)
1061 {
1062         bool active = false;
1063
1064         if (state->fb) {
1065                 dma_addr_t yrgb_mst;
1066
1067                 /* check yrgb_mst to tell if pending_fb is now front */
1068                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1069
1070                 active = (yrgb_mst == state->yrgb_mst);
1071         } else {
1072                 bool enabled;
1073
1074                 /* if enable bit is clear, plane is now disabled */
1075                 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1076
1077                 active = (enabled == 0);
1078         }
1079
1080         return active;
1081 }
1082
1083 static void vop_win_state_destroy(struct vop_win_state *state)
1084 {
1085         struct drm_framebuffer *fb = state->fb;
1086
1087         if (fb)
1088                 drm_framebuffer_unreference(fb);
1089
1090         kfree(state);
1091 }
1092
1093 static void vop_win_update_state(struct vop_win *vop_win)
1094 {
1095         struct vop_win_state *state, *n, *new_active = NULL;
1096
1097         /* Check if any pending states are now active */
1098         list_for_each_entry(state, &vop_win->pending, head)
1099                 if (vop_win_state_is_active(vop_win, state)) {
1100                         new_active = state;
1101                         break;
1102                 }
1103
1104         if (!new_active)
1105                 return;
1106
1107         /*
1108          * Destroy any 'skipped' pending states - states that were queued
1109          * before the newly active state.
1110          */
1111         list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1112                 if (state == new_active)
1113                         break;
1114                 vop_win_state_complete(vop_win, state);
1115                 vop_win_state_destroy(state);
1116         }
1117
1118         vop_win_state_complete(vop_win, new_active);
1119
1120         if (vop_win->active)
1121                 vop_win_state_destroy(vop_win->active);
1122         vop_win->active = new_active;
1123 }
1124
1125 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1126 {
1127         return !list_empty(&vop_win->pending);
1128 }
1129
1130 static irqreturn_t vop_isr_thread(int irq, void *data)
1131 {
1132         struct vop *vop = data;
1133         const struct vop_data *vop_data = vop->data;
1134         unsigned int i;
1135
1136         mutex_lock(&vop->vsync_mutex);
1137
1138         if (!vop->vsync_work_pending)
1139                 goto done;
1140
1141         vop->vsync_work_pending = false;
1142
1143         for (i = 0; i < vop_data->win_size; i++) {
1144                 struct vop_win *vop_win = &vop->win[i];
1145
1146                 vop_win_update_state(vop_win);
1147                 if (vop_win_has_pending_state(vop_win))
1148                         vop->vsync_work_pending = true;
1149         }
1150
1151 done:
1152         mutex_unlock(&vop->vsync_mutex);
1153
1154         return IRQ_HANDLED;
1155 }
1156
1157 static irqreturn_t vop_isr(int irq, void *data)
1158 {
1159         struct vop *vop = data;
1160         uint32_t intr0_reg, active_irqs;
1161         unsigned long flags;
1162         int ret = IRQ_NONE;
1163
1164         /*
1165          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1166          * must hold irq_lock to avoid a race with enable/disable_vblank().
1167         */
1168         spin_lock_irqsave(&vop->irq_lock, flags);
1169         intr0_reg = vop_readl(vop, INTR_CTRL0);
1170         active_irqs = intr0_reg & INTR_MASK;
1171         /* Clear all active interrupt sources */
1172         if (active_irqs)
1173                 vop_writel(vop, INTR_CTRL0,
1174                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1175         spin_unlock_irqrestore(&vop->irq_lock, flags);
1176
1177         /* This is expected for vop iommu irqs, since the irq is shared */
1178         if (!active_irqs)
1179                 return IRQ_NONE;
1180
1181         if (active_irqs & DSP_HOLD_VALID_INTR) {
1182                 complete(&vop->dsp_hold_completion);
1183                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1184                 ret = IRQ_HANDLED;
1185         }
1186
1187         if (active_irqs & FS_INTR) {
1188                 drm_handle_vblank(vop->drm_dev, vop->pipe);
1189                 active_irqs &= ~FS_INTR;
1190                 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1191         }
1192
1193         /* Unhandled irqs are spurious. */
1194         if (active_irqs)
1195                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1196
1197         return ret;
1198 }
1199
1200 static int vop_create_crtc(struct vop *vop)
1201 {
1202         const struct vop_data *vop_data = vop->data;
1203         struct device *dev = vop->dev;
1204         struct drm_device *drm_dev = vop->drm_dev;
1205         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1206         struct drm_crtc *crtc = &vop->crtc;
1207         struct device_node *port;
1208         int ret;
1209         int i;
1210
1211         /*
1212          * Create drm_plane for primary and cursor planes first, since we need
1213          * to pass them to drm_crtc_init_with_planes, which sets the
1214          * "possible_crtcs" to the newly initialized crtc.
1215          */
1216         for (i = 0; i < vop_data->win_size; i++) {
1217                 struct vop_win *vop_win = &vop->win[i];
1218                 const struct vop_win_data *win_data = vop_win->data;
1219
1220                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1221                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1222                         continue;
1223
1224                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1225                                                0, &vop_plane_funcs,
1226                                                win_data->phy->data_formats,
1227                                                win_data->phy->nformats,
1228                                                win_data->type);
1229                 if (ret) {
1230                         DRM_ERROR("failed to initialize plane\n");
1231                         goto err_cleanup_planes;
1232                 }
1233
1234                 plane = &vop_win->base;
1235                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1236                         primary = plane;
1237                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1238                         cursor = plane;
1239         }
1240
1241         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1242                                         &vop_crtc_funcs);
1243         if (ret)
1244                 return ret;
1245
1246         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1247
1248         /*
1249          * Create drm_planes for overlay windows with possible_crtcs restricted
1250          * to the newly created crtc.
1251          */
1252         for (i = 0; i < vop_data->win_size; i++) {
1253                 struct vop_win *vop_win = &vop->win[i];
1254                 const struct vop_win_data *win_data = vop_win->data;
1255                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1256
1257                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1258                         continue;
1259
1260                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1261                                                possible_crtcs,
1262                                                &vop_plane_funcs,
1263                                                win_data->phy->data_formats,
1264                                                win_data->phy->nformats,
1265                                                win_data->type);
1266                 if (ret) {
1267                         DRM_ERROR("failed to initialize overlay plane\n");
1268                         goto err_cleanup_crtc;
1269                 }
1270         }
1271
1272         port = of_get_child_by_name(dev->of_node, "port");
1273         if (!port) {
1274                 DRM_ERROR("no port node found in %s\n",
1275                           dev->of_node->full_name);
1276                 goto err_cleanup_crtc;
1277         }
1278
1279         init_completion(&vop->dsp_hold_completion);
1280         crtc->port = port;
1281         vop->pipe = drm_crtc_index(crtc);
1282         rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1283
1284         return 0;
1285
1286 err_cleanup_crtc:
1287         drm_crtc_cleanup(crtc);
1288 err_cleanup_planes:
1289         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1290                 drm_plane_cleanup(plane);
1291         return ret;
1292 }
1293
1294 static void vop_destroy_crtc(struct vop *vop)
1295 {
1296         struct drm_crtc *crtc = &vop->crtc;
1297
1298         rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1299         of_node_put(crtc->port);
1300         drm_crtc_cleanup(crtc);
1301 }
1302
1303 static int vop_initial(struct vop *vop)
1304 {
1305         const struct vop_data *vop_data = vop->data;
1306         const struct vop_reg_data *init_table = vop_data->init_table;
1307         struct reset_control *ahb_rst;
1308         int i, ret;
1309
1310         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1311         if (IS_ERR(vop->hclk)) {
1312                 dev_err(vop->dev, "failed to get hclk source\n");
1313                 return PTR_ERR(vop->hclk);
1314         }
1315         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1316         if (IS_ERR(vop->aclk)) {
1317                 dev_err(vop->dev, "failed to get aclk source\n");
1318                 return PTR_ERR(vop->aclk);
1319         }
1320         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1321         if (IS_ERR(vop->dclk)) {
1322                 dev_err(vop->dev, "failed to get dclk source\n");
1323                 return PTR_ERR(vop->dclk);
1324         }
1325
1326         ret = clk_prepare(vop->hclk);
1327         if (ret < 0) {
1328                 dev_err(vop->dev, "failed to prepare hclk\n");
1329                 return ret;
1330         }
1331
1332         ret = clk_prepare(vop->dclk);
1333         if (ret < 0) {
1334                 dev_err(vop->dev, "failed to prepare dclk\n");
1335                 goto err_unprepare_hclk;
1336         }
1337
1338         ret = clk_prepare(vop->aclk);
1339         if (ret < 0) {
1340                 dev_err(vop->dev, "failed to prepare aclk\n");
1341                 goto err_unprepare_dclk;
1342         }
1343
1344         /*
1345          * enable hclk, so that we can config vop register.
1346          */
1347         ret = clk_enable(vop->hclk);
1348         if (ret < 0) {
1349                 dev_err(vop->dev, "failed to prepare aclk\n");
1350                 goto err_unprepare_aclk;
1351         }
1352         /*
1353          * do hclk_reset, reset all vop registers.
1354          */
1355         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1356         if (IS_ERR(ahb_rst)) {
1357                 dev_err(vop->dev, "failed to get ahb reset\n");
1358                 ret = PTR_ERR(ahb_rst);
1359                 goto err_disable_hclk;
1360         }
1361         reset_control_assert(ahb_rst);
1362         usleep_range(10, 20);
1363         reset_control_deassert(ahb_rst);
1364
1365         memcpy(vop->regsbak, vop->regs, vop->len);
1366
1367         for (i = 0; i < vop_data->table_size; i++)
1368                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1369
1370         for (i = 0; i < vop_data->win_size; i++) {
1371                 const struct vop_win_data *win = &vop_data->win[i];
1372
1373                 VOP_WIN_SET(vop, win, enable, 0);
1374         }
1375
1376         vop_cfg_done(vop);
1377
1378         /*
1379          * do dclk_reset, let all config take affect.
1380          */
1381         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1382         if (IS_ERR(vop->dclk_rst)) {
1383                 dev_err(vop->dev, "failed to get dclk reset\n");
1384                 ret = PTR_ERR(vop->dclk_rst);
1385                 goto err_unprepare_aclk;
1386         }
1387         reset_control_assert(vop->dclk_rst);
1388         usleep_range(10, 20);
1389         reset_control_deassert(vop->dclk_rst);
1390
1391         clk_disable(vop->hclk);
1392
1393         vop->is_enabled = false;
1394
1395         return 0;
1396
1397 err_disable_hclk:
1398         clk_disable(vop->hclk);
1399 err_unprepare_aclk:
1400         clk_unprepare(vop->aclk);
1401 err_unprepare_dclk:
1402         clk_unprepare(vop->dclk);
1403 err_unprepare_hclk:
1404         clk_unprepare(vop->hclk);
1405         return ret;
1406 }
1407
1408 /*
1409  * Initialize the vop->win array elements.
1410  */
1411 static void vop_win_init(struct vop *vop)
1412 {
1413         const struct vop_data *vop_data = vop->data;
1414         unsigned int i;
1415
1416         for (i = 0; i < vop_data->win_size; i++) {
1417                 struct vop_win *vop_win = &vop->win[i];
1418                 const struct vop_win_data *win_data = &vop_data->win[i];
1419
1420                 vop_win->data = win_data;
1421                 vop_win->vop = vop;
1422                 INIT_LIST_HEAD(&vop_win->pending);
1423         }
1424 }
1425
1426 static int vop_bind(struct device *dev, struct device *master, void *data)
1427 {
1428         struct platform_device *pdev = to_platform_device(dev);
1429         const struct of_device_id *of_id;
1430         const struct vop_data *vop_data;
1431         struct drm_device *drm_dev = data;
1432         struct vop *vop;
1433         struct resource *res;
1434         size_t alloc_size;
1435         int ret, irq;
1436
1437         of_id = of_match_device(vop_driver_dt_match, dev);
1438         vop_data = of_id->data;
1439         if (!vop_data)
1440                 return -ENODEV;
1441
1442         /* Allocate vop struct and its vop_win array */
1443         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1444         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1445         if (!vop)
1446                 return -ENOMEM;
1447
1448         vop->dev = dev;
1449         vop->data = vop_data;
1450         vop->drm_dev = drm_dev;
1451         dev_set_drvdata(dev, vop);
1452
1453         vop_win_init(vop);
1454
1455         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1456         vop->len = resource_size(res);
1457         vop->regs = devm_ioremap_resource(dev, res);
1458         if (IS_ERR(vop->regs))
1459                 return PTR_ERR(vop->regs);
1460
1461         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1462         if (!vop->regsbak)
1463                 return -ENOMEM;
1464
1465         ret = vop_initial(vop);
1466         if (ret < 0) {
1467                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1468                 return ret;
1469         }
1470
1471         irq = platform_get_irq(pdev, 0);
1472         if (irq < 0) {
1473                 dev_err(dev, "cannot find irq for vop\n");
1474                 return irq;
1475         }
1476         vop->irq = (unsigned int)irq;
1477
1478         spin_lock_init(&vop->reg_lock);
1479         spin_lock_init(&vop->irq_lock);
1480
1481         mutex_init(&vop->vsync_mutex);
1482
1483         ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1484                                         IRQF_SHARED, dev_name(dev), vop);
1485         if (ret)
1486                 return ret;
1487
1488         /* IRQ is initially disabled; it gets enabled in power_on */
1489         disable_irq(vop->irq);
1490
1491         ret = vop_create_crtc(vop);
1492         if (ret)
1493                 return ret;
1494
1495         pm_runtime_enable(&pdev->dev);
1496         return 0;
1497 }
1498
1499 static void vop_unbind(struct device *dev, struct device *master, void *data)
1500 {
1501         struct vop *vop = dev_get_drvdata(dev);
1502
1503         pm_runtime_disable(dev);
1504         vop_destroy_crtc(vop);
1505 }
1506
1507 static const struct component_ops vop_component_ops = {
1508         .bind = vop_bind,
1509         .unbind = vop_unbind,
1510 };
1511
1512 static int vop_probe(struct platform_device *pdev)
1513 {
1514         struct device *dev = &pdev->dev;
1515
1516         if (!dev->of_node) {
1517                 dev_err(dev, "can't find vop devices\n");
1518                 return -ENODEV;
1519         }
1520
1521         return component_add(dev, &vop_component_ops);
1522 }
1523
1524 static int vop_remove(struct platform_device *pdev)
1525 {
1526         component_del(&pdev->dev, &vop_component_ops);
1527
1528         return 0;
1529 }
1530
1531 struct platform_driver vop_platform_driver = {
1532         .probe = vop_probe,
1533         .remove = vop_remove,
1534         .driver = {
1535                 .name = "rockchip-vop",
1536                 .owner = THIS_MODULE,
1537                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1538         },
1539 };
1540
1541 module_platform_driver(vop_platform_driver);
1542
1543 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1544 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1545 MODULE_LICENSE("GPL v2");