drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/devfreq.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/component.h>
  32
  33 #include <linux/reset.h>
  34 #include <linux/delay.h>
  35 #include <linux/sort.h>
  36 #include <uapi/drm/rockchip_drm.h>
  37
  38 #include "rockchip_drm_drv.h"
  39 #include "rockchip_drm_gem.h"
  40 #include "rockchip_drm_fb.h"
  41 #include "rockchip_drm_vop.h"
  42
  43 #define VOP_REG_SUPPORT(vop, reg) \
  44                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  45                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  46                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  47                 reg.mask))
  48
  49 #define VOP_WIN_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, win->phy->name)
  51
  52 #define VOP_CTRL_SUPPORT(vop, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  54
  55 #define VOP_INTR_SUPPORT(vop, name) \
  56                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  57
  58 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  59                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  60
  61 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  62         do { \
  63                 if (VOP_REG_SUPPORT(vop, reg)) \
  64                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  65                                   v, reg.write_mask, relaxed); \
  66                 else \
  67                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  68         } while(0)
  69
  70 #define REG_SET(x, name, off, reg, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  72 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  73                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  74
  75 #define VOP_WIN_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  77 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  78                 REG_SET(x, name, 0, win->ext->name, v, true)
  79 #define VOP_SCL_SET(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  81 #define VOP_SCL_SET_EXT(x, win, name, v) \
  82                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  83
  84 #define VOP_CTRL_SET(x, name, v) \
  85                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  86
  87 #define VOP_INTR_GET(vop, name) \
  88                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  89
  90 #define VOP_INTR_SET(vop, name, v) \
  91                 REG_SET(vop, name, 0, vop->data->intr->name, \
  92                         v, false)
  93 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  94                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  95                              mask, v, false)
  96
  97 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  98         do { \
  99                 int i, reg = 0, mask = 0; \
 100                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 101                         if (vop->data->intr->intrs[i] & type) { \
 102                                 reg |= (v) << i; \
 103                                 mask |= 1 << i; \
 104                         } \
 105                 } \
 106                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 107         } while (0)
 108 #define VOP_INTR_GET_TYPE(vop, name, type) \
 109                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 110
 111 #define VOP_CTRL_GET(x, name) \
 112                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 113
 114 #define VOP_WIN_GET(x, win, name) \
 115                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 116
 117 #define VOP_WIN_NAME(win, name) \
 118                 (vop_get_win_phy(win, &win->phy->name)->name)
 119
 120 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 121                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 122
 123 #define to_vop(x) container_of(x, struct vop, crtc)
 124 #define to_vop_win(x) container_of(x, struct vop_win, base)
 125 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 126
 127 struct vop_zpos {
 128         int win_id;
 129         int zpos;
 130 };
 131
 132 struct vop_plane_state {
 133         struct drm_plane_state base;
 134         int format;
 135         int zpos;
 136         unsigned int logo_ymirror;
 137         struct drm_rect src;
 138         struct drm_rect dest;
 139         dma_addr_t yrgb_mst;
 140         dma_addr_t uv_mst;
 141         const uint32_t *y2r_table;
 142         const uint32_t *r2r_table;
 143         const uint32_t *r2y_table;
 144         bool enable;
 145 };
 146
 147 struct vop_win {
 148         struct vop_win *parent;
 149         struct drm_plane base;
 150
 151         int win_id;
 152         int area_id;
 153         uint32_t offset;
 154         enum drm_plane_type type;
 155         const struct vop_win_phy *phy;
 156         const struct vop_csc *csc;
 157         const uint32_t *data_formats;
 158         uint32_t nformats;
 159         struct vop *vop;
 160
 161         struct drm_property *rotation_prop;
 162         struct vop_plane_state state;
 163 };
 164
 165 struct vop {
 166         struct drm_crtc crtc;
 167         struct device *dev;
 168         struct drm_device *drm_dev;
 169         struct drm_property *plane_zpos_prop;
 170         struct drm_property *plane_feature_prop;
 171         struct drm_property *feature_prop;
 172         bool is_iommu_enabled;
 173         bool is_iommu_needed;
 174         bool is_enabled;
 175
 176         /* mutex vsync_ work */
 177         struct mutex vsync_mutex;
 178         bool vsync_work_pending;
 179         bool loader_protect;
 180         struct completion dsp_hold_completion;
 181         struct completion wait_update_complete;
 182         struct drm_pending_vblank_event *event;
 183
 184         struct completion line_flag_completion;
 185
 186         const struct vop_data *data;
 187         int num_wins;
 188
 189         uint32_t *regsbak;
 190         void __iomem *regs;
 191
 192         /* physical map length of vop register */
 193         uint32_t len;
 194
 195         void __iomem *lut_regs;
 196         u32 *lut;
 197         u32 lut_len;
 198         bool lut_active;
 199
 200         /* one time only one process allowed to config the register */
 201         spinlock_t reg_lock;
 202         /* lock vop irq reg */
 203         spinlock_t irq_lock;
 204         /* mutex vop enable and disable */
 205         struct mutex vop_lock;
 206
 207         unsigned int irq;
 208
 209         /* vop AHP clk */
 210         struct clk *hclk;
 211         /* vop dclk */
 212         struct clk *dclk;
 213         /* vop share memory frequency */
 214         struct clk *aclk;
 215         /* vop source handling, optional */
 216         struct clk *dclk_source;
 217
 218         /* vop dclk reset */
 219         struct reset_control *dclk_rst;
 220
 221         struct devfreq *devfreq;
 222         struct notifier_block dmc_nb;
 223
 224         struct vop_win win[];
 225 };
 226
 227 struct vop *dmc_vop;
 228
 229 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 230 {
 231         writel(v, vop->regs + offset);
 232         vop->regsbak[offset >> 2] = v;
 233 }
 234
 235 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 236 {
 237         return readl(vop->regs + offset);
 238 }
 239
 240 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 241                                     const struct vop_reg *reg)
 242 {
 243         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 244 }
 245
 246 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 247                                   uint32_t mask, uint32_t shift, uint32_t v,
 248                                   bool write_mask, bool relaxed)
 249 {
 250         if (!mask)
 251                 return;
 252
 253         if (write_mask) {
 254                 v = ((v & mask) << shift) | (mask << (shift + 16));
 255         } else {
 256                 uint32_t cached_val = vop->regsbak[offset >> 2];
 257
 258                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 259                 vop->regsbak[offset >> 2] = v;
 260         }
 261
 262         if (relaxed)
 263                 writel_relaxed(v, vop->regs + offset);
 264         else
 265                 writel(v, vop->regs + offset);
 266 }
 267
 268 static inline const struct vop_win_phy *
 269 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 270 {
 271         if (!reg->mask && win->parent)
 272                 return win->parent->phy;
 273
 274         return win->phy;
 275 }
 276
 277 static inline uint32_t vop_get_intr_type(struct vop *vop,
 278                                          const struct vop_reg *reg, int type)
 279 {
 280         uint32_t i, ret = 0;
 281         uint32_t regs = vop_read_reg(vop, 0, reg);
 282
 283         for (i = 0; i < vop->data->intr->nintrs; i++) {
 284                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 285                         ret |= vop->data->intr->intrs[i];
 286         }
 287
 288         return ret;
 289 }
 290
 291 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 292 {
 293         int i;
 294
 295         if (!table)
 296                 return;
 297
 298         for (i = 0; i < 8; i++)
 299                 vop_writel(vop, offset + i * 4, table[i]);
 300 }
 301
 302 static inline void vop_cfg_done(struct vop *vop)
 303 {
 304         VOP_CTRL_SET(vop, cfg_done, 1);
 305 }
 306
 307 static bool vop_is_allwin_disabled(struct vop *vop)
 308 {
 309         int i;
 310
 311         for (i = 0; i < vop->num_wins; i++) {
 312                 struct vop_win *win = &vop->win[i];
 313
 314                 if (VOP_WIN_GET(vop, win, enable) != 0)
 315                         return false;
 316         }
 317
 318         return true;
 319 }
 320
 321 static bool vop_is_cfg_done_complete(struct vop *vop)
 322 {
 323         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 324 }
 325
 326 static bool vop_fs_irq_is_active(struct vop *vop)
 327 {
 328         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 329 }
 330
 331 static bool vop_line_flag_is_active(struct vop *vop)
 332 {
 333         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 334 }
 335
 336 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 337 {
 338         writel(v, vop->lut_regs + offset);
 339 }
 340
 341 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 342 {
 343         return readl(vop->lut_regs + offset);
 344 }
 345
 346 static bool has_rb_swapped(uint32_t format)
 347 {
 348         switch (format) {
 349         case DRM_FORMAT_XBGR8888:
 350         case DRM_FORMAT_ABGR8888:
 351         case DRM_FORMAT_BGR888:
 352         case DRM_FORMAT_BGR565:
 353                 return true;
 354         default:
 355                 return false;
 356         }
 357 }
 358
 359 static enum vop_data_format vop_convert_format(uint32_t format)
 360 {
 361         switch (format) {
 362         case DRM_FORMAT_XRGB8888:
 363         case DRM_FORMAT_ARGB8888:
 364         case DRM_FORMAT_XBGR8888:
 365         case DRM_FORMAT_ABGR8888:
 366                 return VOP_FMT_ARGB8888;
 367         case DRM_FORMAT_RGB888:
 368         case DRM_FORMAT_BGR888:
 369                 return VOP_FMT_RGB888;
 370         case DRM_FORMAT_RGB565:
 371         case DRM_FORMAT_BGR565:
 372                 return VOP_FMT_RGB565;
 373         case DRM_FORMAT_NV12:
 374         case DRM_FORMAT_NV12_10:
 375                 return VOP_FMT_YUV420SP;
 376         case DRM_FORMAT_NV16:
 377         case DRM_FORMAT_NV16_10:
 378                 return VOP_FMT_YUV422SP;
 379         case DRM_FORMAT_NV24:
 380         case DRM_FORMAT_NV24_10:
 381                 return VOP_FMT_YUV444SP;
 382         default:
 383                 DRM_ERROR("unsupport format[%08x]\n", format);
 384                 return -EINVAL;
 385         }
 386 }
 387
 388 static bool is_yuv_output(uint32_t bus_format)
 389 {
 390         switch (bus_format) {
 391         case MEDIA_BUS_FMT_YUV8_1X24:
 392         case MEDIA_BUS_FMT_YUV10_1X30:
 393                 return true;
 394         default:
 395                 return false;
 396         }
 397 }
 398
 399 static bool is_yuv_support(uint32_t format)
 400 {
 401         switch (format) {
 402         case DRM_FORMAT_NV12:
 403         case DRM_FORMAT_NV12_10:
 404         case DRM_FORMAT_NV16:
 405         case DRM_FORMAT_NV16_10:
 406         case DRM_FORMAT_NV24:
 407         case DRM_FORMAT_NV24_10:
 408                 return true;
 409         default:
 410                 return false;
 411         }
 412 }
 413
 414 static bool is_yuv_10bit(uint32_t format)
 415 {
 416         switch (format) {
 417         case DRM_FORMAT_NV12_10:
 418         case DRM_FORMAT_NV16_10:
 419         case DRM_FORMAT_NV24_10:
 420                 return true;
 421         default:
 422                 return false;
 423         }
 424 }
 425
 426 static bool is_alpha_support(uint32_t format)
 427 {
 428         switch (format) {
 429         case DRM_FORMAT_ARGB8888:
 430         case DRM_FORMAT_ABGR8888:
 431                 return true;
 432         default:
 433                 return false;
 434         }
 435 }
 436
 437 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 438                                   uint32_t dst, bool is_horizontal,
 439                                   int vsu_mode, int *vskiplines)
 440 {
 441         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 442
 443         if (is_horizontal) {
 444                 if (mode == SCALE_UP)
 445                         val = GET_SCL_FT_BIC(src, dst);
 446                 else if (mode == SCALE_DOWN)
 447                         val = GET_SCL_FT_BILI_DN(src, dst);
 448         } else {
 449                 if (mode == SCALE_UP) {
 450                         if (vsu_mode == SCALE_UP_BIL)
 451                                 val = GET_SCL_FT_BILI_UP(src, dst);
 452                         else
 453                                 val = GET_SCL_FT_BIC(src, dst);
 454                 } else if (mode == SCALE_DOWN) {
 455                         if (vskiplines) {
 456                                 *vskiplines = scl_get_vskiplines(src, dst);
 457                                 val = scl_get_bili_dn_vskip(src, dst,
 458                                                             *vskiplines);
 459                         } else {
 460                                 val = GET_SCL_FT_BILI_DN(src, dst);
 461                         }
 462                 }
 463         }
 464
 465         return val;
 466 }
 467
 468 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 469                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 470                                 uint32_t dst_h, uint32_t pixel_format)
 471 {
 472         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 473         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 474         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 475         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 476         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 477         bool is_yuv = is_yuv_support(pixel_format);
 478         uint16_t cbcr_src_w = src_w / hsub;
 479         uint16_t cbcr_src_h = src_h / vsub;
 480         uint16_t vsu_mode;
 481         uint16_t lb_mode;
 482         uint32_t val;
 483         int vskiplines = 0;
 484
 485         if (!win->phy->scl)
 486                 return;
 487
 488         if (!win->phy->scl->ext) {
 489                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 490                             scl_cal_scale2(src_w, dst_w));
 491                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 492                             scl_cal_scale2(src_h, dst_h));
 493                 if (is_yuv) {
 494                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 495                                     scl_cal_scale2(cbcr_src_w, dst_w));
 496                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 497                                     scl_cal_scale2(cbcr_src_h, dst_h));
 498                 }
 499                 return;
 500         }
 501
 502         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 503         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 504
 505         if (is_yuv) {
 506                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 507                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 508                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 509                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 510                 else
 511                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 512         } else {
 513                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 514                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 515                 else
 516                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 517         }
 518
 519         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 520         if (lb_mode == LB_RGB_3840X2) {
 521                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 522                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 523                         return;
 524                 }
 525                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 526                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 527                         return;
 528                 }
 529                 vsu_mode = SCALE_UP_BIL;
 530         } else if (lb_mode == LB_RGB_2560X4) {
 531                 vsu_mode = SCALE_UP_BIL;
 532         } else {
 533                 vsu_mode = SCALE_UP_BIC;
 534         }
 535
 536         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 537                                 true, 0, NULL);
 538         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 539         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 540                                 false, vsu_mode, &vskiplines);
 541         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 542
 543         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 544         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 545
 546         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 547         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 548         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 549         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 550         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 551         if (is_yuv) {
 552                 vskiplines = 0;
 553
 554                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 555                                         dst_w, true, 0, NULL);
 556                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 557                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 558                                         dst_h, false, vsu_mode, &vskiplines);
 559                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 560
 561                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 562                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 563                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 564                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 565                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 566                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 567                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 568         }
 569 }
 570
 571 /*
 572  * rk3399 colorspace path:
 573  *      Input        Win csc                     Output
 574  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 575  *    RGB        --> R2Y                  __/
 576  *
 577  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 578  *    RGB        --> 709To2020->R2Y       __/
 579  *
 580  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 581  *    RGB        --> R2Y                  __/
 582  *
 583  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 584  *    RGB        --> 709To2020->R2Y       __/
 585  *
 586  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 587  *    RGB        --> R2Y                  __/
 588  *
 589  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 590  *    RGB        --> R2Y(601)             __/
 591  *
 592  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 593  *    RGB        --> bypass               __/
 594  *
 595  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 596  *
 597  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 598  *
 599  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 600  *
 601  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 602  */
 603 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 604                          bool is_input_yuv, bool is_output_yuv,
 605                          int input_csc, int output_csc,
 606                          const uint32_t **y2r_table,
 607                          const uint32_t **r2r_table,
 608                          const uint32_t **r2y_table)
 609 {
 610         *y2r_table = NULL;
 611         *r2r_table = NULL;
 612         *r2y_table = NULL;
 613
 614         if (is_output_yuv) {
 615                 if (output_csc == CSC_BT2020) {
 616                         if (is_input_yuv) {
 617                                 if (input_csc == CSC_BT2020)
 618                                         return 0;
 619                                 *y2r_table = csc_table->y2r_bt709;
 620                         }
 621                         if (input_csc != CSC_BT2020)
 622                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 623                         *r2y_table = csc_table->r2y_bt2020;
 624                 } else {
 625                         if (is_input_yuv && input_csc == CSC_BT2020)
 626                                 *y2r_table = csc_table->y2r_bt2020;
 627                         if (input_csc == CSC_BT2020)
 628                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 629                         if (!is_input_yuv || *y2r_table) {
 630                                 if (output_csc == CSC_BT709)
 631                                         *r2y_table = csc_table->r2y_bt709;
 632                                 else
 633                                         *r2y_table = csc_table->r2y_bt601;
 634                         }
 635                 }
 636         } else {
 637                 if (!is_input_yuv)
 638                         return 0;
 639
 640                 /*
 641                  * is possible use bt2020 on rgb mode?
 642                  */
 643                 if (WARN_ON(output_csc == CSC_BT2020))
 644                         return -EINVAL;
 645
 646                 if (input_csc == CSC_BT2020)
 647                         *y2r_table = csc_table->y2r_bt2020;
 648                 else if (input_csc == CSC_BT709)
 649                         *y2r_table = csc_table->y2r_bt709;
 650                 else
 651                         *y2r_table = csc_table->y2r_bt601;
 652
 653                 if (input_csc == CSC_BT2020)
 654                         /*
 655                          * We don't have bt601 to bt709 table, force use bt709.
 656                          */
 657                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 658         }
 659
 660         return 0;
 661 }
 662
 663 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 664                                 struct drm_crtc_state *crtc_state)
 665 {
 666         struct vop *vop = to_vop(crtc);
 667         struct drm_atomic_state *state = crtc_state->state;
 668         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 669         const struct vop_csc_table *csc_table = vop->data->csc_table;
 670         struct drm_plane_state *pstate;
 671         struct drm_plane *plane;
 672         bool is_input_yuv, is_output_yuv;
 673         int ret;
 674
 675         if (!csc_table)
 676                 return 0;
 677
 678         is_output_yuv = is_yuv_output(s->bus_format);
 679
 680         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 681                 struct vop_plane_state *vop_plane_state;
 682
 683                 pstate = drm_atomic_get_plane_state(state, plane);
 684                 if (IS_ERR(pstate))
 685                         return PTR_ERR(pstate);
 686                 vop_plane_state = to_vop_plane_state(pstate);
 687
 688                 if (!pstate->fb)
 689                         continue;
 690                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 691
 692                 /*
 693                  * TODO: force set input and output csc mode.
 694                  */
 695                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 696                                     CSC_BT709, CSC_BT709,
 697                                     &vop_plane_state->y2r_table,
 698                                     &vop_plane_state->r2r_table,
 699                                     &vop_plane_state->r2y_table);
 700                 if (ret)
 701                         return ret;
 702         }
 703
 704         return 0;
 705 }
 706
 707 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 708 {
 709         unsigned long flags;
 710
 711         spin_lock_irqsave(&vop->irq_lock, flags);
 712
 713         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 714         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 715
 716         spin_unlock_irqrestore(&vop->irq_lock, flags);
 717 }
 718
 719 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 720 {
 721         unsigned long flags;
 722
 723         spin_lock_irqsave(&vop->irq_lock, flags);
 724
 725         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 726
 727         spin_unlock_irqrestore(&vop->irq_lock, flags);
 728 }
 729
 730 /*
 731  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 732  *     the "FRAME_SYNC" interrupt.
 733  * (2) the active data region of each frame ends at dsp_vact_end
 734  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 735  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 736  *
 737  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 738  * Interrupts
 739  * LINE_FLAG -------------------------------+
 740  * FRAME_SYNC ----+                         |
 741  *                |                         |
 742  *                v                         v
 743  *                | Vsync | Vbp |  Vactive  | Vfp |
 744  *                        ^     ^           ^     ^
 745  *                        |     |           |     |
 746  *                        |     |           |     |
 747  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 748  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 749  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 750  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 751  */
 752 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 753 {
 754         uint32_t line_flag_irq;
 755         unsigned long flags;
 756
 757         spin_lock_irqsave(&vop->irq_lock, flags);
 758
 759         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 760
 761         spin_unlock_irqrestore(&vop->irq_lock, flags);
 762
 763         return !!line_flag_irq;
 764 }
 765
 766 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 767 {
 768         unsigned long flags;
 769
 770         if (WARN_ON(!vop->is_enabled))
 771                 return;
 772
 773         spin_lock_irqsave(&vop->irq_lock, flags);
 774
 775         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 776         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 777         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 778
 779         spin_unlock_irqrestore(&vop->irq_lock, flags);
 780 }
 781
 782 static void vop_line_flag_irq_disable(struct vop *vop)
 783 {
 784         unsigned long flags;
 785
 786         if (WARN_ON(!vop->is_enabled))
 787                 return;
 788
 789         spin_lock_irqsave(&vop->irq_lock, flags);
 790
 791         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 792
 793         spin_unlock_irqrestore(&vop->irq_lock, flags);
 794 }
 795
 796 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 797 {
 798         struct vop *vop = to_vop(crtc);
 799         int i, dle, lut_idx;
 800
 801         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 802                 return;
 803
 804         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 805                 return;
 806
 807         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 808                 spin_lock(&vop->reg_lock);
 809                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 810                 vop_cfg_done(vop);
 811                 spin_unlock(&vop->reg_lock);
 812
 813 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 814                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 815                                 dle, !dle, 5, 33333);
 816         } else {
 817                 lut_idx = CTRL_GET(lut_buffer_index);
 818         }
 819
 820         for (i = 0; i < vop->lut_len; i++)
 821                 vop_write_lut(vop, i << 2, vop->lut[i]);
 822
 823         spin_lock(&vop->reg_lock);
 824
 825         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 826         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 827         vop_cfg_done(vop);
 828         vop->lut_active = true;
 829
 830         spin_unlock(&vop->reg_lock);
 831
 832         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 833                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 834                                    dle, dle != lut_idx, 5, 33333);
 835                 /* FIXME:
 836                  * update_gamma value auto clean to 0 by HW, should not
 837                  * bakeup it.
 838                  */
 839                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 840         }
 841 #undef CTRL_GET
 842 }
 843
 844 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 845                                     u16 blue, int regno)
 846 {
 847         struct vop *vop = to_vop(crtc);
 848         u32 lut_len = vop->lut_len;
 849         u32 r, g, b;
 850
 851         if (regno >= lut_len || !vop->lut)
 852                 return;
 853
 854         r = red * (lut_len - 1) / 0xffff;
 855         g = green * (lut_len - 1) / 0xffff;
 856         b = blue * (lut_len - 1) / 0xffff;
 857         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 858 }
 859
 860 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 861                                     u16 *blue, int regno)
 862 {
 863         struct vop *vop = to_vop(crtc);
 864         u32 lut_len = vop->lut_len;
 865         u32 r, g, b;
 866
 867         if (regno >= lut_len || !vop->lut)
 868                 return;
 869
 870         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 871         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 872         b = vop->lut[regno] & (lut_len - 1);
 873         *red = r * 0xffff / (lut_len - 1);
 874         *green = g * 0xffff / (lut_len - 1);
 875         *blue = b * 0xffff / (lut_len - 1);
 876 }
 877
 878 static void vop_power_enable(struct drm_crtc *crtc)
 879 {
 880         struct vop *vop = to_vop(crtc);
 881         int ret;
 882
 883         ret = clk_prepare_enable(vop->hclk);
 884         if (ret < 0) {
 885                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 886                 return;
 887         }
 888
 889         ret = clk_prepare_enable(vop->dclk);
 890         if (ret < 0) {
 891                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 892                 goto err_disable_hclk;
 893         }
 894
 895         ret = clk_prepare_enable(vop->aclk);
 896         if (ret < 0) {
 897                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 898                 goto err_disable_dclk;
 899         }
 900
 901         ret = pm_runtime_get_sync(vop->dev);
 902         if (ret < 0) {
 903                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 904                 return;
 905         }
 906
 907         memcpy(vop->regsbak, vop->regs, vop->len);
 908
 909         vop->is_enabled = true;
 910
 911         return;
 912
 913 err_disable_dclk:
 914         clk_disable_unprepare(vop->dclk);
 915 err_disable_hclk:
 916         clk_disable_unprepare(vop->hclk);
 917 }
 918
 919 static void vop_initial(struct drm_crtc *crtc)
 920 {
 921         struct vop *vop = to_vop(crtc);
 922         int i;
 923
 924         vop_power_enable(crtc);
 925
 926         VOP_CTRL_SET(vop, global_regdone_en, 1);
 927         VOP_CTRL_SET(vop, dsp_blank, 0);
 928
 929         /*
 930          * restore the lut table.
 931          */
 932         if (vop->lut_active)
 933                 vop_crtc_load_lut(crtc);
 934
 935         /*
 936          * We need to make sure that all windows are disabled before resume
 937          * the crtc. Otherwise we might try to scan from a destroyed
 938          * buffer later.
 939          */
 940         for (i = 0; i < vop->num_wins; i++) {
 941                 struct vop_win *win = &vop->win[i];
 942                 int channel = i * 2 + 1;
 943
 944                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 945                 if (win->phy->scl && win->phy->scl->ext) {
 946                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 947                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 948                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 949                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 950                 }
 951                 VOP_WIN_SET(vop, win, enable, 0);
 952                 VOP_WIN_SET(vop, win, gate, 1);
 953         }
 954         VOP_CTRL_SET(vop, afbdc_en, 0);
 955 }
 956
 957 static void vop_crtc_disable(struct drm_crtc *crtc)
 958 {
 959         struct vop *vop = to_vop(crtc);
 960
 961         mutex_lock(&vop->vop_lock);
 962         drm_crtc_vblank_off(crtc);
 963
 964         /*
 965          * Vop standby will take effect at end of current frame,
 966          * if dsp hold valid irq happen, it means standby complete.
 967          *
 968          * we must wait standby complete when we want to disable aclk,
 969          * if not, memory bus maybe dead.
 970          */
 971         reinit_completion(&vop->dsp_hold_completion);
 972         vop_dsp_hold_valid_irq_enable(vop);
 973
 974         spin_lock(&vop->reg_lock);
 975
 976         VOP_CTRL_SET(vop, standby, 1);
 977
 978         spin_unlock(&vop->reg_lock);
 979
 980         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 981                                              msecs_to_jiffies(50)));
 982
 983         vop_dsp_hold_valid_irq_disable(vop);
 984
 985         disable_irq(vop->irq);
 986
 987         vop->is_enabled = false;
 988         if (vop->is_iommu_enabled) {
 989                 /*
 990                  * vop standby complete, so iommu detach is safe.
 991                  */
 992                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 993                 vop->is_iommu_enabled = false;
 994         }
 995
 996         pm_runtime_put(vop->dev);
 997         clk_disable_unprepare(vop->dclk);
 998         clk_disable_unprepare(vop->aclk);
 999         clk_disable_unprepare(vop->hclk);
1000         mutex_unlock(&vop->vop_lock);
1001 }
1002
1003 static void vop_plane_destroy(struct drm_plane *plane)
1004 {
1005         drm_plane_cleanup(plane);
1006 }
1007
1008 static int vop_plane_prepare_fb(struct drm_plane *plane,
1009                                 const struct drm_plane_state *new_state)
1010 {
1011         if (plane->state->fb)
1012                 drm_framebuffer_reference(plane->state->fb);
1013
1014         return 0;
1015 }
1016
1017 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1018                                  const struct drm_plane_state *old_state)
1019 {
1020         if (old_state->fb)
1021                 drm_framebuffer_unreference(old_state->fb);
1022 }
1023
1024 static int vop_plane_atomic_check(struct drm_plane *plane,
1025                            struct drm_plane_state *state)
1026 {
1027         struct drm_crtc *crtc = state->crtc;
1028         struct drm_framebuffer *fb = state->fb;
1029         struct vop_win *win = to_vop_win(plane);
1030         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1031         struct drm_crtc_state *crtc_state;
1032         const struct vop_data *vop_data;
1033         struct vop *vop;
1034         bool visible;
1035         int ret;
1036         struct drm_rect *dest = &vop_plane_state->dest;
1037         struct drm_rect *src = &vop_plane_state->src;
1038         struct drm_rect clip;
1039         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1040                                         DRM_PLANE_HELPER_NO_SCALING;
1041         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1042                                         DRM_PLANE_HELPER_NO_SCALING;
1043         unsigned long offset;
1044         dma_addr_t dma_addr;
1045         u16 vdisplay;
1046
1047         crtc = crtc ? crtc : plane->state->crtc;
1048         /*
1049          * Both crtc or plane->state->crtc can be null.
1050          */
1051         if (!crtc || !fb)
1052                 goto out_disable;
1053
1054         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1055         if (IS_ERR(crtc_state))
1056                 return PTR_ERR(crtc_state);
1057
1058         src->x1 = state->src_x;
1059         src->y1 = state->src_y;
1060         src->x2 = state->src_x + state->src_w;
1061         src->y2 = state->src_y + state->src_h;
1062         dest->x1 = state->crtc_x;
1063         dest->y1 = state->crtc_y;
1064         dest->x2 = state->crtc_x + state->crtc_w;
1065         dest->y2 = state->crtc_y + state->crtc_h;
1066
1067         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1068         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1069                 vdisplay *= 2;
1070
1071         clip.x1 = 0;
1072         clip.y1 = 0;
1073         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1074         clip.y2 = vdisplay;
1075
1076         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1077                                             src, dest, &clip,
1078                                             min_scale,
1079                                             max_scale,
1080                                             true, true, &visible);
1081         if (ret)
1082                 return ret;
1083
1084         if (!visible)
1085                 goto out_disable;
1086
1087         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1088         if (vop_plane_state->format < 0)
1089                 return vop_plane_state->format;
1090
1091         vop = to_vop(crtc);
1092         vop_data = vop->data;
1093
1094         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1095             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1096                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1097                           drm_rect_width(src) >> 16,
1098                           drm_rect_height(src) >> 16,
1099                           vop_data->max_input.width,
1100                           vop_data->max_input.height);
1101                 return -EINVAL;
1102         }
1103
1104         /*
1105          * Src.x1 can be odd when do clip, but yuv plane start point
1106          * need align with 2 pixel.
1107          */
1108         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1109                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1110                 return -EINVAL;
1111         }
1112
1113         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1114         if (state->rotation & BIT(DRM_REFLECT_Y) ||
1115             (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1116                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1117         else
1118                 offset += (src->y1 >> 16) * fb->pitches[0];
1119
1120         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1121         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1122         if (is_yuv_support(fb->pixel_format)) {
1123                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1124                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1125                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1126
1127                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1128                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1129
1130                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1131                 dma_addr += offset + fb->offsets[1];
1132                 vop_plane_state->uv_mst = dma_addr;
1133         }
1134
1135         vop_plane_state->enable = true;
1136
1137         return 0;
1138
1139 out_disable:
1140         vop_plane_state->enable = false;
1141         return 0;
1142 }
1143
1144 static void vop_plane_atomic_disable(struct drm_plane *plane,
1145                                      struct drm_plane_state *old_state)
1146 {
1147         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1148         struct vop_win *win = to_vop_win(plane);
1149         struct vop *vop = to_vop(old_state->crtc);
1150
1151         if (!old_state->crtc)
1152                 return;
1153
1154         spin_lock(&vop->reg_lock);
1155
1156         /*
1157          * FIXUP: some of the vop scale would be abnormal after windows power
1158          * on/off so deinit scale to scale_none mode.
1159          */
1160         if (win->phy->scl && win->phy->scl->ext) {
1161                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1162                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1163                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1164                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1165         }
1166         VOP_WIN_SET(vop, win, enable, 0);
1167
1168         spin_unlock(&vop->reg_lock);
1169
1170         vop_plane_state->enable = false;
1171 }
1172
1173 static void vop_plane_atomic_update(struct drm_plane *plane,
1174                 struct drm_plane_state *old_state)
1175 {
1176         struct drm_plane_state *state = plane->state;
1177         struct drm_crtc *crtc = state->crtc;
1178         struct vop_win *win = to_vop_win(plane);
1179         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1180         struct rockchip_crtc_state *s;
1181         struct vop *vop;
1182         struct drm_framebuffer *fb = state->fb;
1183         unsigned int actual_w, actual_h;
1184         unsigned int dsp_stx, dsp_sty;
1185         uint32_t act_info, dsp_info, dsp_st;
1186         struct drm_rect *src = &vop_plane_state->src;
1187         struct drm_rect *dest = &vop_plane_state->dest;
1188         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1189         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1190         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1191         int ymirror, xmirror;
1192         uint32_t val;
1193         bool rb_swap;
1194
1195         /*
1196          * can't update plane when vop is disabled.
1197          */
1198         if (!crtc)
1199                 return;
1200
1201         if (!vop_plane_state->enable) {
1202                 vop_plane_atomic_disable(plane, old_state);
1203                 return;
1204         }
1205
1206         actual_w = drm_rect_width(src) >> 16;
1207         actual_h = drm_rect_height(src) >> 16;
1208         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1209
1210         dsp_info = (drm_rect_height(dest) - 1) << 16;
1211         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1212
1213         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1214         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1215         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1216
1217         ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1218                   (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1219         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1220
1221         vop = to_vop(state->crtc);
1222         s = to_rockchip_crtc_state(crtc->state);
1223
1224         spin_lock(&vop->reg_lock);
1225
1226         VOP_WIN_SET(vop, win, xmirror, xmirror);
1227         VOP_WIN_SET(vop, win, ymirror, ymirror);
1228         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1229         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1230         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1231         if (is_yuv_support(fb->pixel_format)) {
1232                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1233                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1234         }
1235         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1236
1237         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1238                             drm_rect_width(dest), drm_rect_height(dest),
1239                             fb->pixel_format);
1240
1241         VOP_WIN_SET(vop, win, act_info, act_info);
1242         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1243         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1244
1245         rb_swap = has_rb_swapped(fb->pixel_format);
1246         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1247
1248         if (is_alpha_support(fb->pixel_format) &&
1249             (s->dsp_layer_sel & 0x3) != win->win_id) {
1250                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1251                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1252                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1253                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1254                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1255                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1256                         SRC_FACTOR_M0(ALPHA_ONE);
1257                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1258                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1259                 VOP_WIN_SET(vop, win, alpha_en, 1);
1260         } else {
1261                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1262                 VOP_WIN_SET(vop, win, alpha_en, 0);
1263         }
1264
1265         if (win->csc) {
1266                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1267                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1268                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1269                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1270                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1271                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1272         }
1273         VOP_WIN_SET(vop, win, enable, 1);
1274         spin_unlock(&vop->reg_lock);
1275         vop->is_iommu_needed = true;
1276 }
1277
1278 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1279         .prepare_fb = vop_plane_prepare_fb,
1280         .cleanup_fb = vop_plane_cleanup_fb,
1281         .atomic_check = vop_plane_atomic_check,
1282         .atomic_update = vop_plane_atomic_update,
1283         .atomic_disable = vop_plane_atomic_disable,
1284 };
1285
1286 void vop_atomic_plane_reset(struct drm_plane *plane)
1287 {
1288         struct vop_win *win = to_vop_win(plane);
1289         struct vop_plane_state *vop_plane_state =
1290                                         to_vop_plane_state(plane->state);
1291
1292         if (plane->state && plane->state->fb)
1293                 drm_framebuffer_unreference(plane->state->fb);
1294
1295         kfree(vop_plane_state);
1296         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1297         if (!vop_plane_state)
1298                 return;
1299
1300         vop_plane_state->zpos = win->win_id;
1301         plane->state = &vop_plane_state->base;
1302         plane->state->plane = plane;
1303 }
1304
1305 struct drm_plane_state *
1306 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1307 {
1308         struct vop_plane_state *old_vop_plane_state;
1309         struct vop_plane_state *vop_plane_state;
1310
1311         if (WARN_ON(!plane->state))
1312                 return NULL;
1313
1314         old_vop_plane_state = to_vop_plane_state(plane->state);
1315         vop_plane_state = kmemdup(old_vop_plane_state,
1316                                   sizeof(*vop_plane_state), GFP_KERNEL);
1317         if (!vop_plane_state)
1318                 return NULL;
1319
1320         __drm_atomic_helper_plane_duplicate_state(plane,
1321                                                   &vop_plane_state->base);
1322
1323         return &vop_plane_state->base;
1324 }
1325
1326 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1327                                            struct drm_plane_state *state)
1328 {
1329         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1330
1331         __drm_atomic_helper_plane_destroy_state(plane, state);
1332
1333         kfree(vop_state);
1334 }
1335
1336 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1337                                          struct drm_plane_state *state,
1338                                          struct drm_property *property,
1339                                          uint64_t val)
1340 {
1341         struct rockchip_drm_private *private = plane->dev->dev_private;
1342         struct vop_win *win = to_vop_win(plane);
1343         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1344
1345         if (property == win->vop->plane_zpos_prop) {
1346                 plane_state->zpos = val;
1347                 return 0;
1348         }
1349
1350         if (property == win->rotation_prop) {
1351                 state->rotation = val;
1352                 return 0;
1353         }
1354
1355         if (property == private->logo_ymirror_prop) {
1356                 WARN_ON(!rockchip_fb_is_logo(state->fb));
1357                 plane_state->logo_ymirror = val;
1358                 return 0;
1359         }
1360
1361         DRM_ERROR("failed to set vop plane property\n");
1362         return -EINVAL;
1363 }
1364
1365 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1366                                          const struct drm_plane_state *state,
1367                                          struct drm_property *property,
1368                                          uint64_t *val)
1369 {
1370         struct vop_win *win = to_vop_win(plane);
1371         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1372
1373         if (property == win->vop->plane_zpos_prop) {
1374                 *val = plane_state->zpos;
1375                 return 0;
1376         }
1377
1378         if (property == win->rotation_prop) {
1379                 *val = state->rotation;
1380                 return 0;
1381         }
1382
1383         DRM_ERROR("failed to get vop plane property\n");
1384         return -EINVAL;
1385 }
1386
1387 static const struct drm_plane_funcs vop_plane_funcs = {
1388         .update_plane   = drm_atomic_helper_update_plane,
1389         .disable_plane  = drm_atomic_helper_disable_plane,
1390         .destroy = vop_plane_destroy,
1391         .reset = vop_atomic_plane_reset,
1392         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1393         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1394         .atomic_set_property = vop_atomic_plane_set_property,
1395         .atomic_get_property = vop_atomic_plane_get_property,
1396 };
1397
1398 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1399 {
1400         struct vop *vop = to_vop(crtc);
1401         unsigned long flags;
1402
1403         if (!vop->is_enabled)
1404                 return -EPERM;
1405
1406         spin_lock_irqsave(&vop->irq_lock, flags);
1407
1408         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1409         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1410
1411         spin_unlock_irqrestore(&vop->irq_lock, flags);
1412
1413         return 0;
1414 }
1415
1416 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1417 {
1418         struct vop *vop = to_vop(crtc);
1419         unsigned long flags;
1420
1421         if (!vop->is_enabled)
1422                 return;
1423
1424         spin_lock_irqsave(&vop->irq_lock, flags);
1425
1426         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1427
1428         spin_unlock_irqrestore(&vop->irq_lock, flags);
1429 }
1430
1431 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1432 {
1433         struct vop *vop = to_vop(crtc);
1434
1435         reinit_completion(&vop->wait_update_complete);
1436         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete,
1437                                              msecs_to_jiffies(1000)));
1438 }
1439
1440 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1441                                            struct drm_file *file_priv)
1442 {
1443         struct drm_device *drm = crtc->dev;
1444         struct vop *vop = to_vop(crtc);
1445         struct drm_pending_vblank_event *e;
1446         unsigned long flags;
1447
1448         spin_lock_irqsave(&drm->event_lock, flags);
1449         e = vop->event;
1450         if (e && e->base.file_priv == file_priv) {
1451                 vop->event = NULL;
1452
1453                 e->base.destroy(&e->base);
1454                 file_priv->event_space += sizeof(e->event);
1455         }
1456         spin_unlock_irqrestore(&drm->event_lock, flags);
1457 }
1458
1459 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1460 {
1461         struct vop *vop = to_vop(crtc);
1462
1463         if (on == vop->loader_protect)
1464                 return 0;
1465
1466         if (on) {
1467                 vop_power_enable(crtc);
1468                 enable_irq(vop->irq);
1469                 drm_crtc_vblank_on(crtc);
1470                 vop->loader_protect = true;
1471         } else {
1472                 vop_crtc_disable(crtc);
1473
1474                 vop->loader_protect = false;
1475         }
1476
1477         return 0;
1478 }
1479
1480 #define DEBUG_PRINT(args...) \
1481                 do { \
1482                         if (s) \
1483                                 seq_printf(s, args); \
1484                         else \
1485                                 printk(args); \
1486                 } while (0)
1487
1488 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1489 {
1490         struct vop_win *win = to_vop_win(plane);
1491         struct drm_plane_state *state = plane->state;
1492         struct vop_plane_state *pstate = to_vop_plane_state(state);
1493         struct drm_rect *src, *dest;
1494         struct drm_framebuffer *fb = state->fb;
1495         int i;
1496
1497         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1498                     pstate->enable ? "ACTIVE" : "DISABLED");
1499         if (!fb)
1500                 return 0;
1501
1502         src = &pstate->src;
1503         dest = &pstate->dest;
1504
1505         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1506                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1507         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1508         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1509                     src->y1 >> 16, drm_rect_width(src) >> 16,
1510                     drm_rect_height(src) >> 16);
1511         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1512                     drm_rect_width(dest), drm_rect_height(dest));
1513
1514         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1515                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1516                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1517                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1518         }
1519
1520         return 0;
1521 }
1522
1523 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1524 {
1525         struct vop *vop = to_vop(crtc);
1526         struct drm_crtc_state *crtc_state = crtc->state;
1527         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1528         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1529         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1530         struct drm_plane *plane;
1531         int i;
1532
1533         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1534                     crtc_state->active ? "ACTIVE" : "DISABLED");
1535
1536         if (!crtc_state->active)
1537                 return 0;
1538
1539         DEBUG_PRINT("    Connector: %s\n",
1540                     drm_get_connector_name(state->output_type));
1541         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1542                     state->bus_format, state->output_mode);
1543         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1544                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1545                     drm_mode_vrefresh(mode));
1546         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1547                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1548         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1549                     mode->hsync_end, mode->htotal);
1550         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1551                     mode->vsync_end, mode->vtotal);
1552
1553         for (i = 0; i < vop->num_wins; i++) {
1554                 plane = &vop->win[i].base;
1555                 vop_plane_info_dump(s, plane);
1556         }
1557
1558         return 0;
1559 }
1560
1561 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1562 {
1563         struct vop *vop = to_vop(crtc);
1564         struct drm_crtc_state *crtc_state = crtc->state;
1565         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1566         int i;
1567
1568         if (!crtc_state->active)
1569                 return;
1570
1571         for (i = 0; i < dump_len; i += 4) {
1572                 if (i % 16 == 0)
1573                         DEBUG_PRINT("\n0x%08x: ", i);
1574                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1575         }
1576 }
1577
1578 #undef DEBUG_PRINT
1579
1580 static enum drm_mode_status
1581 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1582                     int output_type)
1583 {
1584         struct vop *vop = to_vop(crtc);
1585         const struct vop_data *vop_data = vop->data;
1586         int request_clock = mode->clock;
1587         int clock;
1588
1589         if (mode->hdisplay > vop_data->max_output.width)
1590                 return MODE_BAD_HVALUE;
1591
1592         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1593                 request_clock *= 2;
1594         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1595
1596         /*
1597          * Hdmi or DisplayPort request a Accurate clock.
1598          */
1599         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1600             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1601                 if (clock != request_clock)
1602                         return MODE_CLOCK_RANGE;
1603
1604         return MODE_OK;
1605 }
1606
1607 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1608         .loader_protect = vop_crtc_loader_protect,
1609         .enable_vblank = vop_crtc_enable_vblank,
1610         .disable_vblank = vop_crtc_disable_vblank,
1611         .wait_for_update = vop_crtc_wait_for_update,
1612         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1613         .debugfs_dump = vop_crtc_debugfs_dump,
1614         .regs_dump = vop_crtc_regs_dump,
1615         .mode_valid = vop_crtc_mode_valid,
1616 };
1617
1618 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1619                                 const struct drm_display_mode *mode,
1620                                 struct drm_display_mode *adj_mode)
1621 {
1622         struct vop *vop = to_vop(crtc);
1623         const struct vop_data *vop_data = vop->data;
1624
1625         if (mode->hdisplay > vop_data->max_output.width)
1626                 return false;
1627
1628         drm_mode_set_crtcinfo(adj_mode,
1629                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1630
1631         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1632                 adj_mode->crtc_clock *= 2;
1633
1634         adj_mode->crtc_clock =
1635                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1636
1637         return true;
1638 }
1639
1640 static void vop_crtc_enable(struct drm_crtc *crtc)
1641 {
1642         struct vop *vop = to_vop(crtc);
1643         const struct vop_data *vop_data = vop->data;
1644         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1645         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1646         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1647         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1648         u16 htotal = adjusted_mode->crtc_htotal;
1649         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1650         u16 hact_end = hact_st + hdisplay;
1651         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1652         u16 vtotal = adjusted_mode->crtc_vtotal;
1653         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1654         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1655         u16 vact_end = vact_st + vdisplay;
1656         uint32_t val;
1657
1658         mutex_lock(&vop->vop_lock);
1659         vop_initial(crtc);
1660
1661         val = BIT(DCLK_INVERT);
1662         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1663                    0 : BIT(HSYNC_POSITIVE);
1664         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1665                    0 : BIT(VSYNC_POSITIVE);
1666         VOP_CTRL_SET(vop, pin_pol, val);
1667
1668         if (vop->dclk_source && s->pll && s->pll->pll) {
1669                 if (clk_set_parent(vop->dclk_source, s->pll->pll))
1670                         DRM_DEV_ERROR(vop->dev,
1671                                       "failed to set dclk's parents\n");
1672         }
1673
1674         switch (s->output_type) {
1675         case DRM_MODE_CONNECTOR_LVDS:
1676                 VOP_CTRL_SET(vop, rgb_en, 1);
1677                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1678                 break;
1679         case DRM_MODE_CONNECTOR_eDP:
1680                 VOP_CTRL_SET(vop, edp_en, 1);
1681                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1682                 break;
1683         case DRM_MODE_CONNECTOR_HDMIA:
1684                 VOP_CTRL_SET(vop, hdmi_en, 1);
1685                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1686                 break;
1687         case DRM_MODE_CONNECTOR_DSI:
1688                 VOP_CTRL_SET(vop, mipi_en, 1);
1689                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1690                 break;
1691         case DRM_MODE_CONNECTOR_DisplayPort:
1692                 val &= ~BIT(DCLK_INVERT);
1693                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1694                 VOP_CTRL_SET(vop, dp_en, 1);
1695                 break;
1696         default:
1697                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1698         }
1699
1700         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1701             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1702                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1703
1704         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1705         switch (s->bus_format) {
1706         case MEDIA_BUS_FMT_RGB565_1X16:
1707                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1708                 break;
1709         case MEDIA_BUS_FMT_RGB666_1X18:
1710         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1711                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1712                 break;
1713         case MEDIA_BUS_FMT_YUV8_1X24:
1714                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1715                 break;
1716         case MEDIA_BUS_FMT_YUV10_1X30:
1717                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1718                 break;
1719         case MEDIA_BUS_FMT_RGB888_1X24:
1720         default:
1721                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1722                 break;
1723         }
1724
1725         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1726                 val |= PRE_DITHER_DOWN_EN(0);
1727         else
1728                 val |= PRE_DITHER_DOWN_EN(1);
1729         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1730         VOP_CTRL_SET(vop, dither_down, val);
1731         VOP_CTRL_SET(vop, dclk_ddr,
1732                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1733         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1734         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1735         VOP_CTRL_SET(vop, dsp_background,
1736                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1737
1738         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1739         val = hact_st << 16;
1740         val |= hact_end;
1741         VOP_CTRL_SET(vop, hact_st_end, val);
1742         VOP_CTRL_SET(vop, hpost_st_end, val);
1743
1744         val = vact_st << 16;
1745         val |= vact_end;
1746         VOP_CTRL_SET(vop, vact_st_end, val);
1747         VOP_CTRL_SET(vop, vpost_st_end, val);
1748
1749         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1750         VOP_INTR_SET(vop, line_flag_num[1],
1751                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1752         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1753                 u16 vact_st_f1 = vtotal + vact_st + 1;
1754                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1755
1756                 val = vact_st_f1 << 16 | vact_end_f1;
1757                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1758                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1759
1760                 val = vtotal << 16 | (vtotal + vsync_len);
1761                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1762                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1763                 VOP_CTRL_SET(vop, p2i_en, 1);
1764                 vtotal += vtotal + 1;
1765         } else {
1766                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1767                 VOP_CTRL_SET(vop, p2i_en, 0);
1768         }
1769         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1770
1771         VOP_CTRL_SET(vop, core_dclk_div,
1772                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1773
1774         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1775
1776         vop_cfg_done(vop);
1777         /*
1778          * enable vop, all the register would take effect when vop exit standby
1779          */
1780         VOP_CTRL_SET(vop, standby, 0);
1781
1782         enable_irq(vop->irq);
1783         drm_crtc_vblank_on(crtc);
1784         mutex_unlock(&vop->vop_lock);
1785 }
1786
1787 static int vop_zpos_cmp(const void *a, const void *b)
1788 {
1789         struct vop_zpos *pa = (struct vop_zpos *)a;
1790         struct vop_zpos *pb = (struct vop_zpos *)b;
1791
1792         return pa->zpos - pb->zpos;
1793 }
1794
1795 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1796                                   struct drm_crtc_state *crtc_state)
1797 {
1798         struct vop *vop = to_vop(crtc);
1799         const struct vop_data *vop_data = vop->data;
1800         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1801         struct drm_atomic_state *state = crtc_state->state;
1802         struct drm_plane *plane;
1803         struct drm_plane_state *pstate;
1804         struct vop_plane_state *plane_state;
1805         struct vop_win *win;
1806         int afbdc_format;
1807         int i;
1808
1809         s->afbdc_en = 0;
1810
1811         for_each_plane_in_state(state, plane, pstate, i) {
1812                 struct drm_framebuffer *fb = pstate->fb;
1813                 struct drm_rect *src;
1814
1815                 win = to_vop_win(plane);
1816                 plane_state = to_vop_plane_state(pstate);
1817
1818                 if (pstate->crtc != crtc || !fb)
1819                         continue;
1820
1821                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1822                         continue;
1823
1824                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1825                         DRM_ERROR("not support afbdc\n");
1826                         return -EINVAL;
1827                 }
1828
1829                 switch (plane_state->format) {
1830                 case VOP_FMT_ARGB8888:
1831                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1832                         break;
1833                 case VOP_FMT_RGB888:
1834                         afbdc_format = AFBDC_FMT_U8U8U8;
1835                         break;
1836                 case VOP_FMT_RGB565:
1837                         afbdc_format = AFBDC_FMT_RGB565;
1838                         break;
1839                 default:
1840                         return -EINVAL;
1841                 }
1842
1843                 if (s->afbdc_en) {
1844                         DRM_ERROR("vop only support one afbc layer\n");
1845                         return -EINVAL;
1846                 }
1847
1848                 src = &plane_state->src;
1849                 if (src->x1 || src->y1 || fb->offsets[0]) {
1850                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1851                                   win->win_id);
1852                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1853                                   src->x1, src->y1, fb->offsets[0]);
1854                         return -EINVAL;
1855                 }
1856                 s->afbdc_win_format = afbdc_format;
1857                 s->afbdc_win_width = pstate->fb->width - 1;
1858                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1859                 s->afbdc_win_id = win->win_id;
1860                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1861                 s->afbdc_en = 1;
1862         }
1863
1864         return 0;
1865 }
1866
1867 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1868                                      struct drm_crtc_state *crtc_state)
1869 {
1870         struct rockchip_drm_private *private = crtc->dev->dev_private;
1871         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1872         struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1873         struct vop *vop = to_vop(crtc);
1874
1875         if (!vop->dclk_source)
1876                 return;
1877
1878         if (crtc_state->active) {
1879                 WARN_ON(s->pll && !s->pll->use_count);
1880                 if (!s->pll || s->pll->use_count > 1 ||
1881                     s->output_type != old_s->output_type) {
1882                         if (s->pll)
1883                                 s->pll->use_count--;
1884
1885                         if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1886                             !private->default_pll.use_count)
1887                                 s->pll = &private->default_pll;
1888                         else
1889                                 s->pll = &private->hdmi_pll;
1890
1891                         s->pll->use_count++;
1892                 }
1893         } else if (s->pll) {
1894                 s->pll->use_count--;
1895                 s->pll = NULL;
1896         }
1897         if (s->pll && s->pll != old_s->pll)
1898                 crtc_state->mode_changed = true;
1899 }
1900
1901 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1902                                  struct drm_crtc_state *crtc_state)
1903 {
1904         struct drm_atomic_state *state = crtc_state->state;
1905         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1906         struct vop *vop = to_vop(crtc);
1907         const struct vop_data *vop_data = vop->data;
1908         struct drm_plane *plane;
1909         struct drm_plane_state *pstate;
1910         struct vop_plane_state *plane_state;
1911         struct vop_zpos *pzpos;
1912         int dsp_layer_sel = 0;
1913         int i, j, cnt = 0, ret = 0;
1914
1915         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1916         if (ret)
1917                 return ret;
1918
1919         ret = vop_csc_atomic_check(crtc, crtc_state);
1920         if (ret)
1921                 return ret;
1922
1923         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1924         if (!pzpos)
1925                 return -ENOMEM;
1926
1927         for (i = 0; i < vop_data->win_size; i++) {
1928                 const struct vop_win_data *win_data = &vop_data->win[i];
1929                 struct vop_win *win;
1930
1931                 if (!win_data->phy)
1932                         continue;
1933
1934                 for (j = 0; j < vop->num_wins; j++) {
1935                         win = &vop->win[j];
1936
1937                         if (win->win_id == i && !win->area_id)
1938                                 break;
1939                 }
1940                 if (WARN_ON(j >= vop->num_wins)) {
1941                         ret = -EINVAL;
1942                         goto err_free_pzpos;
1943                 }
1944
1945                 plane = &win->base;
1946                 pstate = state->plane_states[drm_plane_index(plane)];
1947                 /*
1948                  * plane might not have changed, in which case take
1949                  * current state:
1950                  */
1951                 if (!pstate)
1952                         pstate = plane->state;
1953                 plane_state = to_vop_plane_state(pstate);
1954                 pzpos[cnt].zpos = plane_state->zpos;
1955                 pzpos[cnt++].win_id = win->win_id;
1956         }
1957
1958         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1959
1960         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1961                 const struct vop_win_data *win_data = &vop_data->win[i];
1962                 int shift = i * 2;
1963
1964                 if (win_data->phy) {
1965                         struct vop_zpos *zpos = &pzpos[cnt++];
1966
1967                         dsp_layer_sel |= zpos->win_id << shift;
1968                 } else {
1969                         dsp_layer_sel |= i << shift;
1970                 }
1971         }
1972
1973         s->dsp_layer_sel = dsp_layer_sel;
1974
1975         vop_dclk_source_generate(crtc, crtc_state);
1976
1977 err_free_pzpos:
1978         kfree(pzpos);
1979         return ret;
1980 }
1981
1982 static void vop_post_config(struct drm_crtc *crtc)
1983 {
1984         struct vop *vop = to_vop(crtc);
1985         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1986         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1987         u16 vtotal = mode->crtc_vtotal;
1988         u16 hdisplay = mode->crtc_hdisplay;
1989         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1990         u16 vdisplay = mode->crtc_vdisplay;
1991         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1992         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1993         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1994         u16 hact_end, vact_end;
1995         u32 val;
1996
1997         hact_st += hdisplay * (100 - s->left_margin) / 200;
1998         hact_end = hact_st + hsize;
1999         val = hact_st << 16;
2000         val |= hact_end;
2001         VOP_CTRL_SET(vop, hpost_st_end, val);
2002         vact_st += vdisplay * (100 - s->top_margin) / 200;
2003         vact_end = vact_st + vsize;
2004         val = vact_st << 16;
2005         val |= vact_end;
2006         VOP_CTRL_SET(vop, vpost_st_end, val);
2007         val = scl_cal_scale2(vdisplay, vsize) << 16;
2008         val |= scl_cal_scale2(hdisplay, hsize);
2009         VOP_CTRL_SET(vop, post_scl_factor, val);
2010         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
2011         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2012                 u16 vact_st_f1 = vtotal + vact_st + 1;
2013                 u16 vact_end_f1 = vact_st_f1 + vsize;
2014
2015                 val = vact_st_f1 << 16 | vact_end_f1;
2016                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2017         }
2018 }
2019
2020 static void vop_cfg_update(struct drm_crtc *crtc,
2021                            struct drm_crtc_state *old_crtc_state)
2022 {
2023         struct rockchip_crtc_state *s =
2024                         to_rockchip_crtc_state(crtc->state);
2025         struct vop *vop = to_vop(crtc);
2026
2027         spin_lock(&vop->reg_lock);
2028
2029         if (s->afbdc_en) {
2030                 uint32_t pic_size;
2031
2032                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2033                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2034                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2035                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2036                 pic_size = (s->afbdc_win_width & 0xffff);
2037                 pic_size |= s->afbdc_win_height << 16;
2038                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2039         }
2040
2041         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2042         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2043         vop_post_config(crtc);
2044
2045         spin_unlock(&vop->reg_lock);
2046 }
2047
2048 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2049                                   struct drm_crtc_state *old_crtc_state)
2050 {
2051         struct vop *vop = to_vop(crtc);
2052
2053         vop_cfg_update(crtc, old_crtc_state);
2054
2055         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2056                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2057                 int ret;
2058
2059                 if (need_wait_vblank) {
2060                         bool active;
2061
2062                         disable_irq(vop->irq);
2063                         drm_crtc_vblank_get(crtc);
2064                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2065
2066                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2067                                                         vop, active, active,
2068                                                         0, 50 * 1000);
2069                         if (ret)
2070                                 dev_err(vop->dev, "wait fs irq timeout\n");
2071
2072                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2073                         vop_cfg_done(vop);
2074
2075                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2076                                                         vop, active, active,
2077                                                         0, 50 * 1000);
2078                         if (ret)
2079                                 dev_err(vop->dev, "wait line flag timeout\n");
2080
2081                         enable_irq(vop->irq);
2082                 }
2083                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2084                 if (ret)
2085                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2086                                 ret);
2087
2088                 if (need_wait_vblank) {
2089                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2090                         drm_crtc_vblank_put(crtc);
2091                 }
2092
2093                 vop->is_iommu_enabled = true;
2094         }
2095
2096         vop_cfg_done(vop);
2097 }
2098
2099 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2100                                   struct drm_crtc_state *old_crtc_state)
2101 {
2102         struct vop *vop = to_vop(crtc);
2103
2104         if (crtc->state->event) {
2105                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2106
2107                 vop->event = crtc->state->event;
2108                 crtc->state->event = NULL;
2109         }
2110 }
2111
2112 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2113         .load_lut = vop_crtc_load_lut,
2114         .enable = vop_crtc_enable,
2115         .disable = vop_crtc_disable,
2116         .mode_fixup = vop_crtc_mode_fixup,
2117         .atomic_check = vop_crtc_atomic_check,
2118         .atomic_flush = vop_crtc_atomic_flush,
2119         .atomic_begin = vop_crtc_atomic_begin,
2120 };
2121
2122 static void vop_crtc_destroy(struct drm_crtc *crtc)
2123 {
2124         drm_crtc_cleanup(crtc);
2125 }
2126
2127 static void vop_crtc_reset(struct drm_crtc *crtc)
2128 {
2129         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2130
2131         if (crtc->state) {
2132                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2133                 kfree(s);
2134         }
2135
2136         s = kzalloc(sizeof(*s), GFP_KERNEL);
2137         if (!s)
2138                 return;
2139         crtc->state = &s->base;
2140         crtc->state->crtc = crtc;
2141         s->left_margin = 100;
2142         s->right_margin = 100;
2143         s->top_margin = 100;
2144         s->bottom_margin = 100;
2145 }
2146
2147 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2148 {
2149         struct rockchip_crtc_state *rockchip_state, *old_state;
2150
2151         old_state = to_rockchip_crtc_state(crtc->state);
2152         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2153         if (!rockchip_state)
2154                 return NULL;
2155
2156         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2157         return &rockchip_state->base;
2158 }
2159
2160 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2161                                    struct drm_crtc_state *state)
2162 {
2163         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2164
2165         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2166         kfree(s);
2167 }
2168
2169 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2170                                         const struct drm_crtc_state *state,
2171                                         struct drm_property *property,
2172                                         uint64_t *val)
2173 {
2174         struct drm_device *drm_dev = crtc->dev;
2175         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2176         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2177
2178         if (property == mode_config->tv_left_margin_property) {
2179                 *val = s->left_margin;
2180                 return 0;
2181         }
2182
2183         if (property == mode_config->tv_right_margin_property) {
2184                 *val = s->right_margin;
2185                 return 0;
2186         }
2187
2188         if (property == mode_config->tv_top_margin_property) {
2189                 *val = s->top_margin;
2190                 return 0;
2191         }
2192
2193         if (property == mode_config->tv_bottom_margin_property) {
2194                 *val = s->bottom_margin;
2195                 return 0;
2196         }
2197
2198         DRM_ERROR("failed to get vop crtc property\n");
2199         return -EINVAL;
2200 }
2201
2202 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2203                                         struct drm_crtc_state *state,
2204                                         struct drm_property *property,
2205                                         uint64_t val)
2206 {
2207         struct drm_device *drm_dev = crtc->dev;
2208         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2209         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2210
2211         if (property == mode_config->tv_left_margin_property) {
2212                 s->left_margin = val;
2213                 return 0;
2214         }
2215
2216         if (property == mode_config->tv_right_margin_property) {
2217                 s->right_margin = val;
2218                 return 0;
2219         }
2220
2221         if (property == mode_config->tv_top_margin_property) {
2222                 s->top_margin = val;
2223                 return 0;
2224         }
2225
2226         if (property == mode_config->tv_bottom_margin_property) {
2227                 s->bottom_margin = val;
2228                 return 0;
2229         }
2230
2231         DRM_ERROR("failed to set vop crtc property\n");
2232         return -EINVAL;
2233 }
2234
2235 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2236                                u16 *blue, uint32_t start, uint32_t size)
2237 {
2238         struct vop *vop = to_vop(crtc);
2239         int end = min_t(u32, start + size, vop->lut_len);
2240         int i;
2241
2242         if (!vop->lut)
2243                 return;
2244
2245         for (i = start; i < end; i++)
2246                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2247                                                blue[i], i);
2248
2249         vop_crtc_load_lut(crtc);
2250 }
2251
2252 static const struct drm_crtc_funcs vop_crtc_funcs = {
2253         .gamma_set = vop_crtc_gamma_set,
2254         .set_config = drm_atomic_helper_set_config,
2255         .page_flip = drm_atomic_helper_page_flip,
2256         .destroy = vop_crtc_destroy,
2257         .reset = vop_crtc_reset,
2258         .atomic_get_property = vop_crtc_atomic_get_property,
2259         .atomic_set_property = vop_crtc_atomic_set_property,
2260         .atomic_duplicate_state = vop_crtc_duplicate_state,
2261         .atomic_destroy_state = vop_crtc_destroy_state,
2262 };
2263
2264 static void vop_handle_vblank(struct vop *vop)
2265 {
2266         struct drm_device *drm = vop->drm_dev;
2267         struct drm_crtc *crtc = &vop->crtc;
2268         unsigned long flags;
2269
2270         if (!vop_is_cfg_done_complete(vop))
2271                 return;
2272
2273         if (vop->event) {
2274                 spin_lock_irqsave(&drm->event_lock, flags);
2275
2276                 drm_crtc_send_vblank_event(crtc, vop->event);
2277                 drm_crtc_vblank_put(crtc);
2278                 vop->event = NULL;
2279
2280                 spin_unlock_irqrestore(&drm->event_lock, flags);
2281         }
2282         if (!completion_done(&vop->wait_update_complete))
2283                 complete(&vop->wait_update_complete);
2284 }
2285
2286 static irqreturn_t vop_isr(int irq, void *data)
2287 {
2288         struct vop *vop = data;
2289         struct drm_crtc *crtc = &vop->crtc;
2290         uint32_t active_irqs;
2291         unsigned long flags;
2292         int ret = IRQ_NONE;
2293
2294         /*
2295          * interrupt register has interrupt status, enable and clear bits, we
2296          * must hold irq_lock to avoid a race with enable/disable_vblank().
2297         */
2298         spin_lock_irqsave(&vop->irq_lock, flags);
2299
2300         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2301         /* Clear all active interrupt sources */
2302         if (active_irqs)
2303                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2304
2305         spin_unlock_irqrestore(&vop->irq_lock, flags);
2306
2307         /* This is expected for vop iommu irqs, since the irq is shared */
2308         if (!active_irqs)
2309                 return IRQ_NONE;
2310
2311         if (active_irqs & DSP_HOLD_VALID_INTR) {
2312                 complete(&vop->dsp_hold_completion);
2313                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2314                 ret = IRQ_HANDLED;
2315         }
2316
2317         if (active_irqs & LINE_FLAG_INTR) {
2318                 complete(&vop->line_flag_completion);
2319                 active_irqs &= ~LINE_FLAG_INTR;
2320                 ret = IRQ_HANDLED;
2321         }
2322
2323         if (active_irqs & FS_INTR) {
2324                 drm_crtc_handle_vblank(crtc);
2325                 vop_handle_vblank(vop);
2326                 active_irqs &= ~FS_INTR;
2327                 ret = IRQ_HANDLED;
2328         }
2329
2330         /* Unhandled irqs are spurious. */
2331         if (active_irqs)
2332                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2333
2334         return ret;
2335 }
2336
2337 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2338                           unsigned long possible_crtcs)
2339 {
2340         struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2341         struct drm_plane *share = NULL;
2342         unsigned int rotations = 0;
2343         struct drm_property *prop;
2344         uint64_t feature = 0;
2345         int ret;
2346
2347         if (win->parent)
2348                 share = &win->parent->base;
2349
2350         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2351                                    possible_crtcs, &vop_plane_funcs,
2352                                    win->data_formats, win->nformats, win->type);
2353         if (ret) {
2354                 DRM_ERROR("failed to initialize plane\n");
2355                 return ret;
2356         }
2357         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2358         drm_object_attach_property(&win->base.base,
2359                                    vop->plane_zpos_prop, win->win_id);
2360
2361         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2362                 rotations |= BIT(DRM_REFLECT_X);
2363
2364         if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2365                 rotations |= BIT(DRM_REFLECT_Y);
2366
2367                 prop = drm_property_create_bool(vop->drm_dev,
2368                                                 DRM_MODE_PROP_ATOMIC,
2369                                                 "LOGO_YMIRROR");
2370                 if (!prop)
2371                         return -ENOMEM;
2372                 private->logo_ymirror_prop = prop;
2373         }
2374
2375         if (rotations) {
2376                 rotations |= BIT(DRM_ROTATE_0);
2377                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2378                                                          rotations);
2379                 if (!prop) {
2380                         DRM_ERROR("failed to create zpos property\n");
2381                         return -EINVAL;
2382                 }
2383                 drm_object_attach_property(&win->base.base, prop,
2384                                            BIT(DRM_ROTATE_0));
2385                 win->rotation_prop = prop;
2386         }
2387         if (win->phy->scl)
2388                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2389         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2390             VOP_WIN_SUPPORT(vop, win, alpha_en))
2391                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2392
2393         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2394                                    feature);
2395
2396         return 0;
2397 }
2398
2399 static int vop_create_crtc(struct vop *vop)
2400 {
2401         struct device *dev = vop->dev;
2402         const struct vop_data *vop_data = vop->data;
2403         struct drm_device *drm_dev = vop->drm_dev;
2404         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2405         struct drm_crtc *crtc = &vop->crtc;
2406         struct device_node *port;
2407         uint64_t feature = 0;
2408         int ret;
2409         int i;
2410
2411         /*
2412          * Create drm_plane for primary and cursor planes first, since we need
2413          * to pass them to drm_crtc_init_with_planes, which sets the
2414          * "possible_crtcs" to the newly initialized crtc.
2415          */
2416         for (i = 0; i < vop->num_wins; i++) {
2417                 struct vop_win *win = &vop->win[i];
2418
2419                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2420                     win->type != DRM_PLANE_TYPE_CURSOR)
2421                         continue;
2422
2423                 ret = vop_plane_init(vop, win, 0);
2424                 if (ret)
2425                         goto err_cleanup_planes;
2426
2427                 plane = &win->base;
2428                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2429                         primary = plane;
2430                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2431                         cursor = plane;
2432
2433         }
2434
2435         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2436                                         &vop_crtc_funcs, NULL);
2437         if (ret)
2438                 goto err_cleanup_planes;
2439
2440         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2441
2442         /*
2443          * Create drm_planes for overlay windows with possible_crtcs restricted
2444          * to the newly created crtc.
2445          */
2446         for (i = 0; i < vop->num_wins; i++) {
2447                 struct vop_win *win = &vop->win[i];
2448                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2449
2450                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2451                         continue;
2452
2453                 ret = vop_plane_init(vop, win, possible_crtcs);
2454                 if (ret)
2455                         goto err_cleanup_crtc;
2456         }
2457
2458         port = of_get_child_by_name(dev->of_node, "port");
2459         if (!port) {
2460                 DRM_ERROR("no port node found in %s\n",
2461                           dev->of_node->full_name);
2462                 ret = -ENOENT;
2463                 goto err_cleanup_crtc;
2464         }
2465
2466         init_completion(&vop->dsp_hold_completion);
2467         init_completion(&vop->wait_update_complete);
2468         init_completion(&vop->line_flag_completion);
2469         crtc->port = port;
2470         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2471
2472         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2473         if (ret)
2474                 goto err_unregister_crtc_funcs;
2475 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2476         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2477
2478         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2479         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2480         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2481         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2482 #undef VOP_ATTACH_MODE_CONFIG_PROP
2483
2484         if (vop_data->feature & VOP_FEATURE_AFBDC)
2485                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2486         drm_object_attach_property(&crtc->base, vop->feature_prop,
2487                                    feature);
2488         if (vop->lut_regs) {
2489                 u16 *r_base, *g_base, *b_base;
2490                 u32 lut_len = vop->lut_len;
2491
2492                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2493                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2494                                               GFP_KERNEL);
2495                 if (!vop->lut)
2496                         return -ENOMEM;
2497
2498                 r_base = crtc->gamma_store;
2499                 g_base = r_base + crtc->gamma_size;
2500                 b_base = g_base + crtc->gamma_size;
2501
2502                 for (i = 0; i < lut_len; i++) {
2503                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2504                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2505                                                        &g_base[i], &b_base[i],
2506                                                        i);
2507                 }
2508         }
2509
2510         return 0;
2511
2512 err_unregister_crtc_funcs:
2513         rockchip_unregister_crtc_funcs(crtc);
2514 err_cleanup_crtc:
2515         drm_crtc_cleanup(crtc);
2516 err_cleanup_planes:
2517         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2518                                  head)
2519                 drm_plane_cleanup(plane);
2520         return ret;
2521 }
2522
2523 static void vop_destroy_crtc(struct vop *vop)
2524 {
2525         struct drm_crtc *crtc = &vop->crtc;
2526         struct drm_device *drm_dev = vop->drm_dev;
2527         struct drm_plane *plane, *tmp;
2528
2529         rockchip_unregister_crtc_funcs(crtc);
2530         of_node_put(crtc->port);
2531
2532         /*
2533          * We need to cleanup the planes now.  Why?
2534          *
2535          * The planes are "&vop->win[i].base".  That means the memory is
2536          * all part of the big "struct vop" chunk of memory.  That memory
2537          * was devm allocated and associated with this component.  We need to
2538          * free it ourselves before vop_unbind() finishes.
2539          */
2540         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2541                                  head)
2542                 vop_plane_destroy(plane);
2543
2544         /*
2545          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2546          * references the CRTC.
2547          */
2548         drm_crtc_cleanup(crtc);
2549 }
2550
2551 /*
2552  * Initialize the vop->win array elements.
2553  */
2554 static int vop_win_init(struct vop *vop)
2555 {
2556         const struct vop_data *vop_data = vop->data;
2557         unsigned int i, j;
2558         unsigned int num_wins = 0;
2559         struct drm_property *prop;
2560         static const struct drm_prop_enum_list props[] = {
2561                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2562                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2563         };
2564         static const struct drm_prop_enum_list crtc_props[] = {
2565                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2566         };
2567
2568         for (i = 0; i < vop_data->win_size; i++) {
2569                 struct vop_win *vop_win = &vop->win[num_wins];
2570                 const struct vop_win_data *win_data = &vop_data->win[i];
2571
2572                 if (!win_data->phy)
2573                         continue;
2574
2575                 vop_win->phy = win_data->phy;
2576                 vop_win->csc = win_data->csc;
2577                 vop_win->offset = win_data->base;
2578                 vop_win->type = win_data->type;
2579                 vop_win->data_formats = win_data->phy->data_formats;
2580                 vop_win->nformats = win_data->phy->nformats;
2581                 vop_win->vop = vop;
2582                 vop_win->win_id = i;
2583                 vop_win->area_id = 0;
2584                 num_wins++;
2585
2586                 for (j = 0; j < win_data->area_size; j++) {
2587                         struct vop_win *vop_area = &vop->win[num_wins];
2588                         const struct vop_win_phy *area = win_data->area[j];
2589
2590                         vop_area->parent = vop_win;
2591                         vop_area->offset = vop_win->offset;
2592                         vop_area->phy = area;
2593                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2594                         vop_area->data_formats = vop_win->data_formats;
2595                         vop_area->nformats = vop_win->nformats;
2596                         vop_area->vop = vop;
2597                         vop_area->win_id = i;
2598                         vop_area->area_id = j;
2599                         num_wins++;
2600                 }
2601         }
2602
2603         vop->num_wins = num_wins;
2604
2605         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2606                                          "ZPOS", 0, vop->data->win_size);
2607         if (!prop) {
2608                 DRM_ERROR("failed to create zpos property\n");
2609                 return -EINVAL;
2610         }
2611         vop->plane_zpos_prop = prop;
2612
2613         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2614                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2615                                 props, ARRAY_SIZE(props),
2616                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2617                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2618         if (!vop->plane_feature_prop) {
2619                 DRM_ERROR("failed to create feature property\n");
2620                 return -EINVAL;
2621         }
2622
2623         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2624                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2625                                 crtc_props, ARRAY_SIZE(crtc_props),
2626                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2627         if (!vop->feature_prop) {
2628                 DRM_ERROR("failed to create vop feature property\n");
2629                 return -EINVAL;
2630         }
2631
2632         return 0;
2633 }
2634
2635 /**
2636  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2637  * @crtc: CRTC to enable line flag
2638  * @line_num: interested line number
2639  * @mstimeout: millisecond for timeout
2640  *
2641  * Driver would hold here until the interested line flag interrupt have
2642  * happened or timeout to wait.
2643  *
2644  * Returns:
2645  * Zero on success, negative errno on failure.
2646  */
2647 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2648                                 unsigned int mstimeout)
2649 {
2650         struct vop *vop = to_vop(crtc);
2651         unsigned long jiffies_left;
2652         int ret = 0;
2653
2654         if (!crtc || !vop->is_enabled)
2655                 return -ENODEV;
2656
2657         mutex_lock(&vop->vop_lock);
2658
2659         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2660                 ret = -EINVAL;
2661                 goto out;
2662         }
2663
2664         if (vop_line_flag_irq_is_enabled(vop)) {
2665                 ret = -EBUSY;
2666                 goto out;
2667         }
2668
2669         reinit_completion(&vop->line_flag_completion);
2670         vop_line_flag_irq_enable(vop, line_num);
2671
2672         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2673                                                    msecs_to_jiffies(mstimeout));
2674         vop_line_flag_irq_disable(vop);
2675
2676         if (jiffies_left == 0) {
2677                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2678                 ret = -ETIMEDOUT;
2679                 goto out;
2680         }
2681
2682 out:
2683         mutex_unlock(&vop->vop_lock);
2684
2685         return ret;
2686 }
2687 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2688
2689 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
2690                              void *data)
2691 {
2692         if (event == DEVFREQ_PRECHANGE)
2693                 mutex_lock(&dmc_vop->vop_lock);
2694         else if (event == DEVFREQ_POSTCHANGE)
2695                 mutex_unlock(&dmc_vop->vop_lock);
2696
2697         return NOTIFY_OK;
2698 }
2699
2700 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
2701 {
2702         if (!dmc_vop)
2703                 return -ENOMEM;
2704
2705         dmc_vop->devfreq = devfreq;
2706         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
2707         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
2708                                   DEVFREQ_TRANSITION_NOTIFIER);
2709         return 0;
2710 }
2711 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
2712
2713 static int vop_bind(struct device *dev, struct device *master, void *data)
2714 {
2715         struct platform_device *pdev = to_platform_device(dev);
2716         const struct vop_data *vop_data;
2717         struct drm_device *drm_dev = data;
2718         struct vop *vop;
2719         struct resource *res;
2720         size_t alloc_size;
2721         int ret, irq, i;
2722         int num_wins = 0;
2723
2724         vop_data = of_device_get_match_data(dev);
2725         if (!vop_data)
2726                 return -ENODEV;
2727
2728         for (i = 0; i < vop_data->win_size; i++) {
2729                 const struct vop_win_data *win_data = &vop_data->win[i];
2730
2731                 num_wins += win_data->area_size + 1;
2732         }
2733
2734         /* Allocate vop struct and its vop_win array */
2735         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2736         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2737         if (!vop)
2738                 return -ENOMEM;
2739
2740         vop->dev = dev;
2741         vop->data = vop_data;
2742         vop->drm_dev = drm_dev;
2743         vop->num_wins = num_wins;
2744         dev_set_drvdata(dev, vop);
2745
2746         ret = vop_win_init(vop);
2747         if (ret)
2748                 return ret;
2749
2750         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2751         vop->len = resource_size(res);
2752         vop->regs = devm_ioremap_resource(dev, res);
2753         if (IS_ERR(vop->regs))
2754                 return PTR_ERR(vop->regs);
2755
2756         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2757         if (!vop->regsbak)
2758                 return -ENOMEM;
2759
2760         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2761         vop->lut_regs = devm_ioremap_resource(dev, res);
2762         if (IS_ERR(vop->lut_regs)) {
2763                 dev_warn(vop->dev, "failed to get vop lut registers\n");
2764                 vop->lut_regs = NULL;
2765         }
2766         if (vop->lut_regs) {
2767                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
2768                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
2769                         dev_err(vop->dev, "unsupport lut sizes %d\n",
2770                                 vop->lut_len);
2771                         return -EINVAL;
2772                 }
2773         }
2774
2775         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2776         if (IS_ERR(vop->hclk)) {
2777                 dev_err(vop->dev, "failed to get hclk source\n");
2778                 return PTR_ERR(vop->hclk);
2779         }
2780         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2781         if (IS_ERR(vop->aclk)) {
2782                 dev_err(vop->dev, "failed to get aclk source\n");
2783                 return PTR_ERR(vop->aclk);
2784         }
2785         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2786         if (IS_ERR(vop->dclk)) {
2787                 dev_err(vop->dev, "failed to get dclk source\n");
2788                 return PTR_ERR(vop->dclk);
2789         }
2790
2791         vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
2792         if (PTR_ERR(vop->dclk_source) == -ENOENT) {
2793                 vop->dclk_source = NULL;
2794         } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
2795                 return -EPROBE_DEFER;
2796         } else if (IS_ERR(vop->dclk_source)) {
2797                 dev_err(vop->dev, "failed to get dclk source parent\n");
2798                 return PTR_ERR(vop->dclk_source);
2799         }
2800
2801         irq = platform_get_irq(pdev, 0);
2802         if (irq < 0) {
2803                 dev_err(dev, "cannot find irq for vop\n");
2804                 return irq;
2805         }
2806         vop->irq = (unsigned int)irq;
2807
2808         spin_lock_init(&vop->reg_lock);
2809         spin_lock_init(&vop->irq_lock);
2810         mutex_init(&vop->vop_lock);
2811
2812         mutex_init(&vop->vsync_mutex);
2813
2814         ret = devm_request_irq(dev, vop->irq, vop_isr,
2815                                IRQF_SHARED, dev_name(dev), vop);
2816         if (ret)
2817                 return ret;
2818
2819         /* IRQ is initially disabled; it gets enabled in power_on */
2820         disable_irq(vop->irq);
2821
2822         ret = vop_create_crtc(vop);
2823         if (ret)
2824                 return ret;
2825
2826         pm_runtime_enable(&pdev->dev);
2827
2828         dmc_vop = vop;
2829
2830         return 0;
2831 }
2832
2833 static void vop_unbind(struct device *dev, struct device *master, void *data)
2834 {
2835         struct vop *vop = dev_get_drvdata(dev);
2836
2837         pm_runtime_disable(dev);
2838         vop_destroy_crtc(vop);
2839 }
2840
2841 const struct component_ops vop_component_ops = {
2842         .bind = vop_bind,
2843         .unbind = vop_unbind,
2844 };
2845 EXPORT_SYMBOL_GPL(vop_component_ops);