drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/clk.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/component.h>
  29
  30 #include <linux/reset.h>
  31 #include <linux/delay.h>
  32
  33 #include "rockchip_drm_drv.h"
  34 #include "rockchip_drm_gem.h"
  35 #include "rockchip_drm_fb.h"
  36 #include "rockchip_drm_vop.h"
  37
  38 #define VOP_REG(off, _mask, s) \
  39                 {.offset = off, \
  40                  .mask = _mask, \
  41                  .shift = s,}
  42
  43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  44                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  46                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  47
  48 #define REG_SET(x, base, reg, v, mode) \
  49                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  50
  51 #define VOP_WIN_SET(x, win, name, v) \
  52                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  53 #define VOP_SCL_SET(x, win, name, v) \
  54                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  55 #define VOP_CTRL_SET(x, name, v) \
  56                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  57
  58 #define VOP_WIN_GET(x, win, name) \
  59                 vop_read_reg(x, win->base, &win->phy->name)
  60
  61 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  62                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  63
  64 #define to_vop(x) container_of(x, struct vop, crtc)
  65 #define to_vop_win(x) container_of(x, struct vop_win, base)
  66
  67 struct vop_win_state {
  68         struct list_head head;
  69         struct drm_framebuffer *fb;
  70         dma_addr_t yrgb_mst;
  71         struct drm_pending_vblank_event *event;
  72 };
  73
  74 struct vop_win {
  75         struct drm_plane base;
  76         const struct vop_win_data *data;
  77         struct vop *vop;
  78
  79         struct list_head pending;
  80         struct vop_win_state *active;
  81 };
  82
  83 struct vop {
  84         struct drm_crtc crtc;
  85         struct device *dev;
  86         struct drm_device *drm_dev;
  87         bool is_enabled;
  88
  89         int connector_type;
  90         int connector_out_mode;
  91
  92         /* mutex vsync_ work */
  93         struct mutex vsync_mutex;
  94         bool vsync_work_pending;
  95         struct completion dsp_hold_completion;
  96
  97         const struct vop_data *data;
  98
  99         uint32_t *regsbak;
 100         void __iomem *regs;
 101
 102         /* physical map length of vop register */
 103         uint32_t len;
 104
 105         /* one time only one process allowed to config the register */
 106         spinlock_t reg_lock;
 107         /* lock vop irq reg */
 108         spinlock_t irq_lock;
 109
 110         unsigned int irq;
 111
 112         /* vop AHP clk */
 113         struct clk *hclk;
 114         /* vop dclk */
 115         struct clk *dclk;
 116         /* vop share memory frequency */
 117         struct clk *aclk;
 118
 119         /* vop dclk reset */
 120         struct reset_control *dclk_rst;
 121
 122         int pipe;
 123
 124         struct vop_win win[];
 125 };
 126
 127 enum vop_data_format {
 128         VOP_FMT_ARGB8888 = 0,
 129         VOP_FMT_RGB888,
 130         VOP_FMT_RGB565,
 131         VOP_FMT_YUV420SP = 4,
 132         VOP_FMT_YUV422SP,
 133         VOP_FMT_YUV444SP,
 134 };
 135
 136 struct vop_reg_data {
 137         uint32_t offset;
 138         uint32_t value;
 139 };
 140
 141 struct vop_reg {
 142         uint32_t offset;
 143         uint32_t shift;
 144         uint32_t mask;
 145 };
 146
 147 struct vop_ctrl {
 148         struct vop_reg standby;
 149         struct vop_reg data_blank;
 150         struct vop_reg gate_en;
 151         struct vop_reg mmu_en;
 152         struct vop_reg rgb_en;
 153         struct vop_reg edp_en;
 154         struct vop_reg hdmi_en;
 155         struct vop_reg mipi_en;
 156         struct vop_reg out_mode;
 157         struct vop_reg dither_down;
 158         struct vop_reg dither_up;
 159         struct vop_reg pin_pol;
 160
 161         struct vop_reg htotal_pw;
 162         struct vop_reg hact_st_end;
 163         struct vop_reg vtotal_pw;
 164         struct vop_reg vact_st_end;
 165         struct vop_reg hpost_st_end;
 166         struct vop_reg vpost_st_end;
 167 };
 168
 169 struct vop_scl_regs {
 170         struct vop_reg cbcr_vsd_mode;
 171         struct vop_reg cbcr_vsu_mode;
 172         struct vop_reg cbcr_hsd_mode;
 173         struct vop_reg cbcr_ver_scl_mode;
 174         struct vop_reg cbcr_hor_scl_mode;
 175         struct vop_reg yrgb_vsd_mode;
 176         struct vop_reg yrgb_vsu_mode;
 177         struct vop_reg yrgb_hsd_mode;
 178         struct vop_reg yrgb_ver_scl_mode;
 179         struct vop_reg yrgb_hor_scl_mode;
 180         struct vop_reg line_load_mode;
 181         struct vop_reg cbcr_axi_gather_num;
 182         struct vop_reg yrgb_axi_gather_num;
 183         struct vop_reg vsd_cbcr_gt2;
 184         struct vop_reg vsd_cbcr_gt4;
 185         struct vop_reg vsd_yrgb_gt2;
 186         struct vop_reg vsd_yrgb_gt4;
 187         struct vop_reg bic_coe_sel;
 188         struct vop_reg cbcr_axi_gather_en;
 189         struct vop_reg yrgb_axi_gather_en;
 190
 191         struct vop_reg lb_mode;
 192         struct vop_reg scale_yrgb_x;
 193         struct vop_reg scale_yrgb_y;
 194         struct vop_reg scale_cbcr_x;
 195         struct vop_reg scale_cbcr_y;
 196 };
 197
 198 struct vop_win_phy {
 199         const struct vop_scl_regs *scl;
 200         const uint32_t *data_formats;
 201         uint32_t nformats;
 202
 203         struct vop_reg enable;
 204         struct vop_reg format;
 205         struct vop_reg rb_swap;
 206         struct vop_reg act_info;
 207         struct vop_reg dsp_info;
 208         struct vop_reg dsp_st;
 209         struct vop_reg yrgb_mst;
 210         struct vop_reg uv_mst;
 211         struct vop_reg yrgb_vir;
 212         struct vop_reg uv_vir;
 213
 214         struct vop_reg dst_alpha_ctl;
 215         struct vop_reg src_alpha_ctl;
 216 };
 217
 218 struct vop_win_data {
 219         uint32_t base;
 220         const struct vop_win_phy *phy;
 221         enum drm_plane_type type;
 222 };
 223
 224 struct vop_data {
 225         const struct vop_reg_data *init_table;
 226         unsigned int table_size;
 227         const struct vop_ctrl *ctrl;
 228         const struct vop_win_data *win;
 229         unsigned int win_size;
 230 };
 231
 232 static const uint32_t formats_01[] = {
 233         DRM_FORMAT_XRGB8888,
 234         DRM_FORMAT_ARGB8888,
 235         DRM_FORMAT_XBGR8888,
 236         DRM_FORMAT_ABGR8888,
 237         DRM_FORMAT_RGB888,
 238         DRM_FORMAT_BGR888,
 239         DRM_FORMAT_RGB565,
 240         DRM_FORMAT_BGR565,
 241         DRM_FORMAT_NV12,
 242         DRM_FORMAT_NV16,
 243         DRM_FORMAT_NV24,
 244 };
 245
 246 static const uint32_t formats_234[] = {
 247         DRM_FORMAT_XRGB8888,
 248         DRM_FORMAT_ARGB8888,
 249         DRM_FORMAT_XBGR8888,
 250         DRM_FORMAT_ABGR8888,
 251         DRM_FORMAT_RGB888,
 252         DRM_FORMAT_BGR888,
 253         DRM_FORMAT_RGB565,
 254         DRM_FORMAT_BGR565,
 255 };
 256
 257 static const struct vop_scl_regs win_full_scl = {
 258         .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
 259         .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
 260         .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
 261         .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
 262         .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
 263         .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
 264         .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
 265         .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
 266         .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
 267         .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
 268         .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
 269         .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
 270         .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
 271         .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
 272         .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
 273         .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
 274         .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
 275         .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
 276         .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
 277         .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
 278         .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
 279         .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 280         .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 281         .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 282         .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 283 };
 284
 285 static const struct vop_win_phy win01_data = {
 286         .scl = &win_full_scl,
 287         .data_formats = formats_01,
 288         .nformats = ARRAY_SIZE(formats_01),
 289         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 290         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 291         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
 292         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 293         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 294         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 295         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 296         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 297         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 298         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 299         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 300         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 301 };
 302
 303 static const struct vop_win_phy win23_data = {
 304         .data_formats = formats_234,
 305         .nformats = ARRAY_SIZE(formats_234),
 306         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 307         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 308         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 309         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 310         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 311         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 312         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 313         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 314         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 315 };
 316
 317 static const struct vop_ctrl ctrl_data = {
 318         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 319         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 320         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 321         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 322         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 323         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 324         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 325         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 326         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 327         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 328         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 329         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 330         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 331         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 332         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 333         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 334         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 335         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 336 };
 337
 338 static const struct vop_reg_data vop_init_reg_table[] = {
 339         {SYS_CTRL, 0x00c00000},
 340         {DSP_CTRL0, 0x00000000},
 341         {WIN0_CTRL0, 0x00000080},
 342         {WIN1_CTRL0, 0x00000080},
 343         /* TODO: Win2/3 support multiple area function, but we haven't found
 344          * a suitable way to use it yet, so let's just use them as other windows
 345          * with only area 0 enabled.
 346          */
 347         {WIN2_CTRL0, 0x00000010},
 348         {WIN3_CTRL0, 0x00000010},
 349 };
 350
 351 /*
 352  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 353  * special support to get alpha blending working.  For now, just use overlay
 354  * window 3 for the drm cursor.
 355  *
 356  */
 357 static const struct vop_win_data rk3288_vop_win_data[] = {
 358         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 359         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 360         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 361         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 362 };
 363
 364 static const struct vop_data rk3288_vop = {
 365         .init_table = vop_init_reg_table,
 366         .table_size = ARRAY_SIZE(vop_init_reg_table),
 367         .ctrl = &ctrl_data,
 368         .win = rk3288_vop_win_data,
 369         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 370 };
 371
 372 static const struct of_device_id vop_driver_dt_match[] = {
 373         { .compatible = "rockchip,rk3288-vop",
 374           .data = &rk3288_vop },
 375         {},
 376 };
 377 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 378
 379 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 380 {
 381         writel(v, vop->regs + offset);
 382         vop->regsbak[offset >> 2] = v;
 383 }
 384
 385 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 386 {
 387         return readl(vop->regs + offset);
 388 }
 389
 390 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 391                                     const struct vop_reg *reg)
 392 {
 393         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 394 }
 395
 396 static inline void vop_cfg_done(struct vop *vop)
 397 {
 398         writel(0x01, vop->regs + REG_CFG_DONE);
 399 }
 400
 401 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 402                                   uint32_t mask, uint32_t v)
 403 {
 404         if (mask) {
 405                 uint32_t cached_val = vop->regsbak[offset >> 2];
 406
 407                 cached_val = (cached_val & ~mask) | v;
 408                 writel(cached_val, vop->regs + offset);
 409                 vop->regsbak[offset >> 2] = cached_val;
 410         }
 411 }
 412
 413 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 414                                           uint32_t mask, uint32_t v)
 415 {
 416         if (mask) {
 417                 uint32_t cached_val = vop->regsbak[offset >> 2];
 418
 419                 cached_val = (cached_val & ~mask) | v;
 420                 writel_relaxed(cached_val, vop->regs + offset);
 421                 vop->regsbak[offset >> 2] = cached_val;
 422         }
 423 }
 424
 425 static bool has_rb_swapped(uint32_t format)
 426 {
 427         switch (format) {
 428         case DRM_FORMAT_XBGR8888:
 429         case DRM_FORMAT_ABGR8888:
 430         case DRM_FORMAT_BGR888:
 431         case DRM_FORMAT_BGR565:
 432                 return true;
 433         default:
 434                 return false;
 435         }
 436 }
 437
 438 static enum vop_data_format vop_convert_format(uint32_t format)
 439 {
 440         switch (format) {
 441         case DRM_FORMAT_XRGB8888:
 442         case DRM_FORMAT_ARGB8888:
 443         case DRM_FORMAT_XBGR8888:
 444         case DRM_FORMAT_ABGR8888:
 445                 return VOP_FMT_ARGB8888;
 446         case DRM_FORMAT_RGB888:
 447         case DRM_FORMAT_BGR888:
 448                 return VOP_FMT_RGB888;
 449         case DRM_FORMAT_RGB565:
 450         case DRM_FORMAT_BGR565:
 451                 return VOP_FMT_RGB565;
 452         case DRM_FORMAT_NV12:
 453                 return VOP_FMT_YUV420SP;
 454         case DRM_FORMAT_NV16:
 455                 return VOP_FMT_YUV422SP;
 456         case DRM_FORMAT_NV24:
 457                 return VOP_FMT_YUV444SP;
 458         default:
 459                 DRM_ERROR("unsupport format[%08x]\n", format);
 460                 return -EINVAL;
 461         }
 462 }
 463
 464 static bool is_yuv_support(uint32_t format)
 465 {
 466         switch (format) {
 467         case DRM_FORMAT_NV12:
 468         case DRM_FORMAT_NV16:
 469         case DRM_FORMAT_NV24:
 470                 return true;
 471         default:
 472                 return false;
 473         }
 474 }
 475
 476 static bool is_alpha_support(uint32_t format)
 477 {
 478         switch (format) {
 479         case DRM_FORMAT_ARGB8888:
 480         case DRM_FORMAT_ABGR8888:
 481                 return true;
 482         default:
 483                 return false;
 484         }
 485 }
 486
 487 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 488                                   uint32_t dst, bool is_horizontal,
 489                                   int vsu_mode, int *vskiplines)
 490 {
 491         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 492
 493         if (is_horizontal) {
 494                 if (mode == SCALE_UP)
 495                         val = GET_SCL_FT_BIC(src, dst);
 496                 else if (mode == SCALE_DOWN)
 497                         val = GET_SCL_FT_BILI_DN(src, dst);
 498         } else {
 499                 if (mode == SCALE_UP) {
 500                         if (vsu_mode == SCALE_UP_BIL)
 501                                 val = GET_SCL_FT_BILI_UP(src, dst);
 502                         else
 503                                 val = GET_SCL_FT_BIC(src, dst);
 504                 } else if (mode == SCALE_DOWN) {
 505                         if (vskiplines) {
 506                                 *vskiplines = scl_get_vskiplines(src, dst);
 507                                 val = scl_get_bili_dn_vskip(src, dst,
 508                                                             *vskiplines);
 509                         } else {
 510                                 val = GET_SCL_FT_BILI_DN(src, dst);
 511                         }
 512                 }
 513         }
 514
 515         return val;
 516 }
 517
 518 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 519                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 520                              uint32_t dst_h, uint32_t pixel_format)
 521 {
 522         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 523         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 524         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 525         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 526         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 527         bool is_yuv = is_yuv_support(pixel_format);
 528         uint16_t cbcr_src_w = src_w / hsub;
 529         uint16_t cbcr_src_h = src_h / vsub;
 530         uint16_t vsu_mode;
 531         uint16_t lb_mode;
 532         uint32_t val;
 533         int vskiplines;
 534
 535         if (dst_w > 3840) {
 536                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 537                 return;
 538         }
 539
 540         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 541         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 542
 543         if (is_yuv) {
 544                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 545                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 546                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 547                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 548                 else
 549                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 550         } else {
 551                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 552                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 553                 else
 554                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 555         }
 556
 557         VOP_SCL_SET(vop, win, lb_mode, lb_mode);
 558         if (lb_mode == LB_RGB_3840X2) {
 559                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 560                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 561                         return;
 562                 }
 563                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 564                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 565                         return;
 566                 }
 567                 vsu_mode = SCALE_UP_BIL;
 568         } else if (lb_mode == LB_RGB_2560X4) {
 569                 vsu_mode = SCALE_UP_BIL;
 570         } else {
 571                 vsu_mode = SCALE_UP_BIC;
 572         }
 573
 574         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 575                                 true, 0, NULL);
 576         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 577         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 578                                 false, vsu_mode, &vskiplines);
 579         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 580
 581         VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 582         VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 583
 584         VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 585         VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 586         VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 587         VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 588         VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
 589         if (is_yuv) {
 590                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 591                                         dst_w, true, 0, NULL);
 592                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 593                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 594                                         dst_h, false, vsu_mode, &vskiplines);
 595                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 596
 597                 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 598                 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 599                 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 600                 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 601                 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 602                 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 603                 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
 604         }
 605 }
 606
 607 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 608 {
 609         unsigned long flags;
 610
 611         if (WARN_ON(!vop->is_enabled))
 612                 return;
 613
 614         spin_lock_irqsave(&vop->irq_lock, flags);
 615
 616         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 617                        DSP_HOLD_VALID_INTR_EN(1));
 618
 619         spin_unlock_irqrestore(&vop->irq_lock, flags);
 620 }
 621
 622 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 623 {
 624         unsigned long flags;
 625
 626         if (WARN_ON(!vop->is_enabled))
 627                 return;
 628
 629         spin_lock_irqsave(&vop->irq_lock, flags);
 630
 631         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 632                        DSP_HOLD_VALID_INTR_EN(0));
 633
 634         spin_unlock_irqrestore(&vop->irq_lock, flags);
 635 }
 636
 637 static void vop_enable(struct drm_crtc *crtc)
 638 {
 639         struct vop *vop = to_vop(crtc);
 640         int ret;
 641
 642         if (vop->is_enabled)
 643                 return;
 644
 645         ret = pm_runtime_get_sync(vop->dev);
 646         if (ret < 0) {
 647                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 648                 return;
 649         }
 650
 651         ret = clk_enable(vop->hclk);
 652         if (ret < 0) {
 653                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 654                 return;
 655         }
 656
 657         ret = clk_enable(vop->dclk);
 658         if (ret < 0) {
 659                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 660                 goto err_disable_hclk;
 661         }
 662
 663         ret = clk_enable(vop->aclk);
 664         if (ret < 0) {
 665                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 666                 goto err_disable_dclk;
 667         }
 668
 669         /*
 670          * Slave iommu shares power, irq and clock with vop.  It was associated
 671          * automatically with this master device via common driver code.
 672          * Now that we have enabled the clock we attach it to the shared drm
 673          * mapping.
 674          */
 675         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 676         if (ret) {
 677                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 678                 goto err_disable_aclk;
 679         }
 680
 681         memcpy(vop->regs, vop->regsbak, vop->len);
 682         /*
 683          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 684          */
 685         vop->is_enabled = true;
 686
 687         spin_lock(&vop->reg_lock);
 688
 689         VOP_CTRL_SET(vop, standby, 0);
 690
 691         spin_unlock(&vop->reg_lock);
 692
 693         enable_irq(vop->irq);
 694
 695         drm_vblank_on(vop->drm_dev, vop->pipe);
 696
 697         return;
 698
 699 err_disable_aclk:
 700         clk_disable(vop->aclk);
 701 err_disable_dclk:
 702         clk_disable(vop->dclk);
 703 err_disable_hclk:
 704         clk_disable(vop->hclk);
 705 }
 706
 707 static void vop_disable(struct drm_crtc *crtc)
 708 {
 709         struct vop *vop = to_vop(crtc);
 710
 711         if (!vop->is_enabled)
 712                 return;
 713
 714         drm_vblank_off(crtc->dev, vop->pipe);
 715
 716         /*
 717          * Vop standby will take effect at end of current frame,
 718          * if dsp hold valid irq happen, it means standby complete.
 719          *
 720          * we must wait standby complete when we want to disable aclk,
 721          * if not, memory bus maybe dead.
 722          */
 723         reinit_completion(&vop->dsp_hold_completion);
 724         vop_dsp_hold_valid_irq_enable(vop);
 725
 726         spin_lock(&vop->reg_lock);
 727
 728         VOP_CTRL_SET(vop, standby, 1);
 729
 730         spin_unlock(&vop->reg_lock);
 731
 732         wait_for_completion(&vop->dsp_hold_completion);
 733
 734         vop_dsp_hold_valid_irq_disable(vop);
 735
 736         disable_irq(vop->irq);
 737
 738         vop->is_enabled = false;
 739
 740         /*
 741          * vop standby complete, so iommu detach is safe.
 742          */
 743         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 744
 745         clk_disable(vop->dclk);
 746         clk_disable(vop->aclk);
 747         clk_disable(vop->hclk);
 748         pm_runtime_put(vop->dev);
 749 }
 750
 751 /*
 752  * Caller must hold vsync_mutex.
 753  */
 754 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
 755 {
 756         struct vop_win_state *last;
 757         struct vop_win_state *active = vop_win->active;
 758
 759         if (list_empty(&vop_win->pending))
 760                 return active ? active->fb : NULL;
 761
 762         last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
 763         return last ? last->fb : NULL;
 764 }
 765
 766 /*
 767  * Caller must hold vsync_mutex.
 768  */
 769 static int vop_win_queue_fb(struct vop_win *vop_win,
 770                             struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
 771                             struct drm_pending_vblank_event *event)
 772 {
 773         struct vop_win_state *state;
 774
 775         state = kzalloc(sizeof(*state), GFP_KERNEL);
 776         if (!state)
 777                 return -ENOMEM;
 778
 779         state->fb = fb;
 780         state->yrgb_mst = yrgb_mst;
 781         state->event = event;
 782
 783         list_add_tail(&state->head, &vop_win->pending);
 784
 785         return 0;
 786 }
 787
 788 static int vop_update_plane_event(struct drm_plane *plane,
 789                                   struct drm_crtc *crtc,
 790                                   struct drm_framebuffer *fb, int crtc_x,
 791                                   int crtc_y, unsigned int crtc_w,
 792                                   unsigned int crtc_h, uint32_t src_x,
 793                                   uint32_t src_y, uint32_t src_w,
 794                                   uint32_t src_h,
 795                                   struct drm_pending_vblank_event *event)
 796 {
 797         struct vop_win *vop_win = to_vop_win(plane);
 798         const struct vop_win_data *win = vop_win->data;
 799         struct vop *vop = to_vop(crtc);
 800         struct drm_gem_object *obj;
 801         struct rockchip_gem_object *rk_obj;
 802         struct drm_gem_object *uv_obj;
 803         struct rockchip_gem_object *rk_uv_obj;
 804         unsigned long offset;
 805         unsigned int actual_w;
 806         unsigned int actual_h;
 807         unsigned int dsp_stx;
 808         unsigned int dsp_sty;
 809         unsigned int y_vir_stride;
 810         unsigned int uv_vir_stride = 0;
 811         dma_addr_t yrgb_mst;
 812         dma_addr_t uv_mst = 0;
 813         enum vop_data_format format;
 814         uint32_t val;
 815         bool is_alpha;
 816         bool rb_swap;
 817         bool is_yuv;
 818         bool visible;
 819         int ret;
 820         struct drm_rect dest = {
 821                 .x1 = crtc_x,
 822                 .y1 = crtc_y,
 823                 .x2 = crtc_x + crtc_w,
 824                 .y2 = crtc_y + crtc_h,
 825         };
 826         struct drm_rect src = {
 827                 /* 16.16 fixed point */
 828                 .x1 = src_x,
 829                 .y1 = src_y,
 830                 .x2 = src_x + src_w,
 831                 .y2 = src_y + src_h,
 832         };
 833         const struct drm_rect clip = {
 834                 .x2 = crtc->mode.hdisplay,
 835                 .y2 = crtc->mode.vdisplay,
 836         };
 837         bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
 838         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 839                                         DRM_PLANE_HELPER_NO_SCALING;
 840         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 841                                         DRM_PLANE_HELPER_NO_SCALING;
 842
 843         ret = drm_plane_helper_check_update(plane, crtc, fb,
 844                                             &src, &dest, &clip,
 845                                             min_scale,
 846                                             max_scale,
 847                                             can_position, false, &visible);
 848         if (ret)
 849                 return ret;
 850
 851         if (!visible)
 852                 return 0;
 853
 854         is_alpha = is_alpha_support(fb->pixel_format);
 855         rb_swap = has_rb_swapped(fb->pixel_format);
 856         is_yuv = is_yuv_support(fb->pixel_format);
 857
 858         format = vop_convert_format(fb->pixel_format);
 859         if (format < 0)
 860                 return format;
 861
 862         obj = rockchip_fb_get_gem_obj(fb, 0);
 863         if (!obj) {
 864                 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
 865                 return -EINVAL;
 866         }
 867
 868         rk_obj = to_rockchip_obj(obj);
 869
 870         if (is_yuv) {
 871                 /*
 872                  * Src.x1 can be odd when do clip, but yuv plane start point
 873                  * need align with 2 pixel.
 874                  */
 875                 val = (src.x1 >> 16) % 2;
 876                 src.x1 += val << 16;
 877                 src.x2 += val << 16;
 878         }
 879
 880         actual_w = (src.x2 - src.x1) >> 16;
 881         actual_h = (src.y2 - src.y1) >> 16;
 882
 883         dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 884         dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 885
 886         offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 887         offset += (src.y1 >> 16) * fb->pitches[0];
 888
 889         yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 890         y_vir_stride = fb->pitches[0] >> 2;
 891
 892         if (is_yuv) {
 893                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 894                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 895                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 896
 897                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 898                 if (!uv_obj) {
 899                         DRM_ERROR("fail to get uv object from framebuffer\n");
 900                         return -EINVAL;
 901                 }
 902                 rk_uv_obj = to_rockchip_obj(uv_obj);
 903                 uv_vir_stride = fb->pitches[1] >> 2;
 904
 905                 offset = (src.x1 >> 16) * bpp / hsub;
 906                 offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
 907
 908                 uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 909         }
 910
 911         /*
 912          * If this plane update changes the plane's framebuffer, (or more
 913          * precisely, if this update has a different framebuffer than the last
 914          * update), enqueue it so we can track when it completes.
 915          *
 916          * Only when we discover that this update has completed, can we
 917          * unreference any previous framebuffers.
 918          */
 919         mutex_lock(&vop->vsync_mutex);
 920         if (fb != vop_win_last_pending_fb(vop_win)) {
 921                 ret = drm_vblank_get(plane->dev, vop->pipe);
 922                 if (ret) {
 923                         DRM_ERROR("failed to get vblank, %d\n", ret);
 924                         mutex_unlock(&vop->vsync_mutex);
 925                         return ret;
 926                 }
 927
 928                 drm_framebuffer_reference(fb);
 929
 930                 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
 931                 if (ret) {
 932                         drm_vblank_put(plane->dev, vop->pipe);
 933                         mutex_unlock(&vop->vsync_mutex);
 934                         return ret;
 935                 }
 936
 937                 vop->vsync_work_pending = true;
 938         }
 939         mutex_unlock(&vop->vsync_mutex);
 940
 941         spin_lock(&vop->reg_lock);
 942
 943         VOP_WIN_SET(vop, win, format, format);
 944         VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 945         VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
 946         if (is_yuv) {
 947                 VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
 948                 VOP_WIN_SET(vop, win, uv_mst, uv_mst);
 949         }
 950
 951         if (win->phy->scl)
 952                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 953                                     dest.x2 - dest.x1, dest.y2 - dest.y1,
 954                                     fb->pixel_format);
 955
 956         val = (actual_h - 1) << 16;
 957         val |= (actual_w - 1) & 0xffff;
 958         VOP_WIN_SET(vop, win, act_info, val);
 959
 960         val = (dest.y2 - dest.y1 - 1) << 16;
 961         val |= (dest.x2 - dest.x1 - 1) & 0xffff;
 962         VOP_WIN_SET(vop, win, dsp_info, val);
 963         val = dsp_sty << 16;
 964         val |= dsp_stx & 0xffff;
 965         VOP_WIN_SET(vop, win, dsp_st, val);
 966         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 967
 968         if (is_alpha) {
 969                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 970                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 971                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 972                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 973                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 974                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 975                         SRC_FACTOR_M0(ALPHA_ONE);
 976                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 977         } else {
 978                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 979         }
 980
 981         VOP_WIN_SET(vop, win, enable, 1);
 982
 983         vop_cfg_done(vop);
 984         spin_unlock(&vop->reg_lock);
 985
 986         return 0;
 987 }
 988
 989 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 990                             struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 991                             unsigned int crtc_w, unsigned int crtc_h,
 992                             uint32_t src_x, uint32_t src_y, uint32_t src_w,
 993                             uint32_t src_h)
 994 {
 995         return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
 996                                       crtc_h, src_x, src_y, src_w, src_h,
 997                                       NULL);
 998 }
 999
1000 static int vop_update_primary_plane(struct drm_crtc *crtc,
1001                                     struct drm_pending_vblank_event *event)
1002 {
1003         unsigned int crtc_w, crtc_h;
1004
1005         crtc_w = crtc->primary->fb->width - crtc->x;
1006         crtc_h = crtc->primary->fb->height - crtc->y;
1007
1008         return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
1009                                       0, 0, crtc_w, crtc_h, crtc->x << 16,
1010                                       crtc->y << 16, crtc_w << 16,
1011                                       crtc_h << 16, event);
1012 }
1013
1014 static int vop_disable_plane(struct drm_plane *plane)
1015 {
1016         struct vop_win *vop_win = to_vop_win(plane);
1017         const struct vop_win_data *win = vop_win->data;
1018         struct vop *vop;
1019         int ret;
1020
1021         if (!plane->crtc)
1022                 return 0;
1023
1024         vop = to_vop(plane->crtc);
1025
1026         ret = drm_vblank_get(plane->dev, vop->pipe);
1027         if (ret) {
1028                 DRM_ERROR("failed to get vblank, %d\n", ret);
1029                 return ret;
1030         }
1031
1032         mutex_lock(&vop->vsync_mutex);
1033
1034         ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
1035         if (ret) {
1036                 drm_vblank_put(plane->dev, vop->pipe);
1037                 mutex_unlock(&vop->vsync_mutex);
1038                 return ret;
1039         }
1040
1041         vop->vsync_work_pending = true;
1042         mutex_unlock(&vop->vsync_mutex);
1043
1044         spin_lock(&vop->reg_lock);
1045         VOP_WIN_SET(vop, win, enable, 0);
1046         vop_cfg_done(vop);
1047         spin_unlock(&vop->reg_lock);
1048
1049         return 0;
1050 }
1051
1052 static void vop_plane_destroy(struct drm_plane *plane)
1053 {
1054         vop_disable_plane(plane);
1055         drm_plane_cleanup(plane);
1056 }
1057
1058 static const struct drm_plane_funcs vop_plane_funcs = {
1059         .update_plane = vop_update_plane,
1060         .disable_plane = vop_disable_plane,
1061         .destroy = vop_plane_destroy,
1062 };
1063
1064 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1065                                   int connector_type,
1066                                   int out_mode)
1067 {
1068         struct vop *vop = to_vop(crtc);
1069
1070         vop->connector_type = connector_type;
1071         vop->connector_out_mode = out_mode;
1072
1073         return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
1076
1077 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1078 {
1079         struct vop *vop = to_vop(crtc);
1080         unsigned long flags;
1081
1082         if (!vop->is_enabled)
1083                 return -EPERM;
1084
1085         spin_lock_irqsave(&vop->irq_lock, flags);
1086
1087         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
1088
1089         spin_unlock_irqrestore(&vop->irq_lock, flags);
1090
1091         return 0;
1092 }
1093
1094 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1095 {
1096         struct vop *vop = to_vop(crtc);
1097         unsigned long flags;
1098
1099         if (!vop->is_enabled)
1100                 return;
1101
1102         spin_lock_irqsave(&vop->irq_lock, flags);
1103         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
1104         spin_unlock_irqrestore(&vop->irq_lock, flags);
1105 }
1106
1107 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1108         .enable_vblank = vop_crtc_enable_vblank,
1109         .disable_vblank = vop_crtc_disable_vblank,
1110 };
1111
1112 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
1113 {
1114         DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
1115
1116         switch (mode) {
1117         case DRM_MODE_DPMS_ON:
1118                 vop_enable(crtc);
1119                 break;
1120         case DRM_MODE_DPMS_STANDBY:
1121         case DRM_MODE_DPMS_SUSPEND:
1122         case DRM_MODE_DPMS_OFF:
1123                 vop_disable(crtc);
1124                 break;
1125         default:
1126                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
1127                 break;
1128         }
1129 }
1130
1131 static void vop_crtc_prepare(struct drm_crtc *crtc)
1132 {
1133         vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1134 }
1135
1136 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1137                                 const struct drm_display_mode *mode,
1138                                 struct drm_display_mode *adjusted_mode)
1139 {
1140         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1141                 return false;
1142
1143         return true;
1144 }
1145
1146 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1147                                   struct drm_framebuffer *old_fb)
1148 {
1149         int ret;
1150
1151         crtc->x = x;
1152         crtc->y = y;
1153
1154         ret = vop_update_primary_plane(crtc, NULL);
1155         if (ret < 0) {
1156                 DRM_ERROR("fail to update plane\n");
1157                 return ret;
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int vop_crtc_mode_set(struct drm_crtc *crtc,
1164                              struct drm_display_mode *mode,
1165                              struct drm_display_mode *adjusted_mode,
1166                              int x, int y, struct drm_framebuffer *fb)
1167 {
1168         struct vop *vop = to_vop(crtc);
1169         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1170         u16 hdisplay = adjusted_mode->hdisplay;
1171         u16 htotal = adjusted_mode->htotal;
1172         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1173         u16 hact_end = hact_st + hdisplay;
1174         u16 vdisplay = adjusted_mode->vdisplay;
1175         u16 vtotal = adjusted_mode->vtotal;
1176         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1177         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1178         u16 vact_end = vact_st + vdisplay;
1179         int ret, ret_clk;
1180         uint32_t val;
1181
1182         /*
1183          * disable dclk to stop frame scan, so that we can safe config mode and
1184          * enable iommu.
1185          */
1186         clk_disable(vop->dclk);
1187
1188         switch (vop->connector_type) {
1189         case DRM_MODE_CONNECTOR_LVDS:
1190                 VOP_CTRL_SET(vop, rgb_en, 1);
1191                 break;
1192         case DRM_MODE_CONNECTOR_eDP:
1193                 VOP_CTRL_SET(vop, edp_en, 1);
1194                 break;
1195         case DRM_MODE_CONNECTOR_HDMIA:
1196                 VOP_CTRL_SET(vop, hdmi_en, 1);
1197                 break;
1198         default:
1199                 DRM_ERROR("unsupport connector_type[%d]\n",
1200                           vop->connector_type);
1201                 ret = -EINVAL;
1202                 goto out;
1203         };
1204         VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
1205
1206         val = 0x8;
1207         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1208         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1209         VOP_CTRL_SET(vop, pin_pol, val);
1210
1211         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1212         val = hact_st << 16;
1213         val |= hact_end;
1214         VOP_CTRL_SET(vop, hact_st_end, val);
1215         VOP_CTRL_SET(vop, hpost_st_end, val);
1216
1217         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1218         val = vact_st << 16;
1219         val |= vact_end;
1220         VOP_CTRL_SET(vop, vact_st_end, val);
1221         VOP_CTRL_SET(vop, vpost_st_end, val);
1222
1223         ret = vop_crtc_mode_set_base(crtc, x, y, fb);
1224         if (ret)
1225                 goto out;
1226
1227         /*
1228          * reset dclk, take all mode config affect, so the clk would run in
1229          * correct frame.
1230          */
1231         reset_control_assert(vop->dclk_rst);
1232         usleep_range(10, 20);
1233         reset_control_deassert(vop->dclk_rst);
1234
1235         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1236 out:
1237         ret_clk = clk_enable(vop->dclk);
1238         if (ret_clk < 0) {
1239                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
1240                 return ret_clk;
1241         }
1242
1243         return ret;
1244 }
1245
1246 static void vop_crtc_commit(struct drm_crtc *crtc)
1247 {
1248 }
1249
1250 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1251         .dpms = vop_crtc_dpms,
1252         .prepare = vop_crtc_prepare,
1253         .mode_fixup = vop_crtc_mode_fixup,
1254         .mode_set = vop_crtc_mode_set,
1255         .mode_set_base = vop_crtc_mode_set_base,
1256         .commit = vop_crtc_commit,
1257 };
1258
1259 static int vop_crtc_page_flip(struct drm_crtc *crtc,
1260                               struct drm_framebuffer *fb,
1261                               struct drm_pending_vblank_event *event,
1262                               uint32_t page_flip_flags)
1263 {
1264         struct vop *vop = to_vop(crtc);
1265         struct drm_framebuffer *old_fb = crtc->primary->fb;
1266         int ret;
1267
1268         /* when the page flip is requested, crtc should be on */
1269         if (!vop->is_enabled) {
1270                 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1271                 return 0;
1272         }
1273
1274         crtc->primary->fb = fb;
1275
1276         ret = vop_update_primary_plane(crtc, event);
1277         if (ret)
1278                 crtc->primary->fb = old_fb;
1279
1280         return ret;
1281 }
1282
1283 static void vop_win_state_complete(struct vop_win *vop_win,
1284                                    struct vop_win_state *state)
1285 {
1286         struct vop *vop = vop_win->vop;
1287         struct drm_crtc *crtc = &vop->crtc;
1288         struct drm_device *drm = crtc->dev;
1289         unsigned long flags;
1290
1291         if (state->event) {
1292                 spin_lock_irqsave(&drm->event_lock, flags);
1293                 drm_crtc_send_vblank_event(crtc, state->event);
1294                 spin_unlock_irqrestore(&drm->event_lock, flags);
1295         }
1296
1297         list_del(&state->head);
1298         drm_vblank_put(crtc->dev, vop->pipe);
1299 }
1300
1301 static void vop_crtc_destroy(struct drm_crtc *crtc)
1302 {
1303         drm_crtc_cleanup(crtc);
1304 }
1305
1306 static const struct drm_crtc_funcs vop_crtc_funcs = {
1307         .set_config = drm_crtc_helper_set_config,
1308         .page_flip = vop_crtc_page_flip,
1309         .destroy = vop_crtc_destroy,
1310 };
1311
1312 static bool vop_win_state_is_active(struct vop_win *vop_win,
1313                                     struct vop_win_state *state)
1314 {
1315         bool active = false;
1316
1317         if (state->fb) {
1318                 dma_addr_t yrgb_mst;
1319
1320                 /* check yrgb_mst to tell if pending_fb is now front */
1321                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1322
1323                 active = (yrgb_mst == state->yrgb_mst);
1324         } else {
1325                 bool enabled;
1326
1327                 /* if enable bit is clear, plane is now disabled */
1328                 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1329
1330                 active = (enabled == 0);
1331         }
1332
1333         return active;
1334 }
1335
1336 static void vop_win_state_destroy(struct vop_win_state *state)
1337 {
1338         struct drm_framebuffer *fb = state->fb;
1339
1340         if (fb)
1341                 drm_framebuffer_unreference(fb);
1342
1343         kfree(state);
1344 }
1345
1346 static void vop_win_update_state(struct vop_win *vop_win)
1347 {
1348         struct vop_win_state *state, *n, *new_active = NULL;
1349
1350         /* Check if any pending states are now active */
1351         list_for_each_entry(state, &vop_win->pending, head)
1352                 if (vop_win_state_is_active(vop_win, state)) {
1353                         new_active = state;
1354                         break;
1355                 }
1356
1357         if (!new_active)
1358                 return;
1359
1360         /*
1361          * Destroy any 'skipped' pending states - states that were queued
1362          * before the newly active state.
1363          */
1364         list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1365                 if (state == new_active)
1366                         break;
1367                 vop_win_state_complete(vop_win, state);
1368                 vop_win_state_destroy(state);
1369         }
1370
1371         vop_win_state_complete(vop_win, new_active);
1372
1373         if (vop_win->active)
1374                 vop_win_state_destroy(vop_win->active);
1375         vop_win->active = new_active;
1376 }
1377
1378 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1379 {
1380         return !list_empty(&vop_win->pending);
1381 }
1382
1383 static irqreturn_t vop_isr_thread(int irq, void *data)
1384 {
1385         struct vop *vop = data;
1386         const struct vop_data *vop_data = vop->data;
1387         unsigned int i;
1388
1389         mutex_lock(&vop->vsync_mutex);
1390
1391         if (!vop->vsync_work_pending)
1392                 goto done;
1393
1394         vop->vsync_work_pending = false;
1395
1396         for (i = 0; i < vop_data->win_size; i++) {
1397                 struct vop_win *vop_win = &vop->win[i];
1398
1399                 vop_win_update_state(vop_win);
1400                 if (vop_win_has_pending_state(vop_win))
1401                         vop->vsync_work_pending = true;
1402         }
1403
1404 done:
1405         mutex_unlock(&vop->vsync_mutex);
1406
1407         return IRQ_HANDLED;
1408 }
1409
1410 static irqreturn_t vop_isr(int irq, void *data)
1411 {
1412         struct vop *vop = data;
1413         uint32_t intr0_reg, active_irqs;
1414         unsigned long flags;
1415         int ret = IRQ_NONE;
1416
1417         /*
1418          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1419          * must hold irq_lock to avoid a race with enable/disable_vblank().
1420         */
1421         spin_lock_irqsave(&vop->irq_lock, flags);
1422         intr0_reg = vop_readl(vop, INTR_CTRL0);
1423         active_irqs = intr0_reg & INTR_MASK;
1424         /* Clear all active interrupt sources */
1425         if (active_irqs)
1426                 vop_writel(vop, INTR_CTRL0,
1427                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1428         spin_unlock_irqrestore(&vop->irq_lock, flags);
1429
1430         /* This is expected for vop iommu irqs, since the irq is shared */
1431         if (!active_irqs)
1432                 return IRQ_NONE;
1433
1434         if (active_irqs & DSP_HOLD_VALID_INTR) {
1435                 complete(&vop->dsp_hold_completion);
1436                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1437                 ret = IRQ_HANDLED;
1438         }
1439
1440         if (active_irqs & FS_INTR) {
1441                 drm_handle_vblank(vop->drm_dev, vop->pipe);
1442                 active_irqs &= ~FS_INTR;
1443                 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1444         }
1445
1446         /* Unhandled irqs are spurious. */
1447         if (active_irqs)
1448                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1449
1450         return ret;
1451 }
1452
1453 static int vop_create_crtc(struct vop *vop)
1454 {
1455         const struct vop_data *vop_data = vop->data;
1456         struct device *dev = vop->dev;
1457         struct drm_device *drm_dev = vop->drm_dev;
1458         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1459         struct drm_crtc *crtc = &vop->crtc;
1460         struct device_node *port;
1461         int ret;
1462         int i;
1463
1464         /*
1465          * Create drm_plane for primary and cursor planes first, since we need
1466          * to pass them to drm_crtc_init_with_planes, which sets the
1467          * "possible_crtcs" to the newly initialized crtc.
1468          */
1469         for (i = 0; i < vop_data->win_size; i++) {
1470                 struct vop_win *vop_win = &vop->win[i];
1471                 const struct vop_win_data *win_data = vop_win->data;
1472
1473                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1474                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1475                         continue;
1476
1477                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1478                                                0, &vop_plane_funcs,
1479                                                win_data->phy->data_formats,
1480                                                win_data->phy->nformats,
1481                                                win_data->type);
1482                 if (ret) {
1483                         DRM_ERROR("failed to initialize plane\n");
1484                         goto err_cleanup_planes;
1485                 }
1486
1487                 plane = &vop_win->base;
1488                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1489                         primary = plane;
1490                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1491                         cursor = plane;
1492         }
1493
1494         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1495                                         &vop_crtc_funcs);
1496         if (ret)
1497                 return ret;
1498
1499         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1500
1501         /*
1502          * Create drm_planes for overlay windows with possible_crtcs restricted
1503          * to the newly created crtc.
1504          */
1505         for (i = 0; i < vop_data->win_size; i++) {
1506                 struct vop_win *vop_win = &vop->win[i];
1507                 const struct vop_win_data *win_data = vop_win->data;
1508                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1509
1510                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1511                         continue;
1512
1513                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1514                                                possible_crtcs,
1515                                                &vop_plane_funcs,
1516                                                win_data->phy->data_formats,
1517                                                win_data->phy->nformats,
1518                                                win_data->type);
1519                 if (ret) {
1520                         DRM_ERROR("failed to initialize overlay plane\n");
1521                         goto err_cleanup_crtc;
1522                 }
1523         }
1524
1525         port = of_get_child_by_name(dev->of_node, "port");
1526         if (!port) {
1527                 DRM_ERROR("no port node found in %s\n",
1528                           dev->of_node->full_name);
1529                 goto err_cleanup_crtc;
1530         }
1531
1532         init_completion(&vop->dsp_hold_completion);
1533         crtc->port = port;
1534         vop->pipe = drm_crtc_index(crtc);
1535         rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1536
1537         return 0;
1538
1539 err_cleanup_crtc:
1540         drm_crtc_cleanup(crtc);
1541 err_cleanup_planes:
1542         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1543                 drm_plane_cleanup(plane);
1544         return ret;
1545 }
1546
1547 static void vop_destroy_crtc(struct vop *vop)
1548 {
1549         struct drm_crtc *crtc = &vop->crtc;
1550
1551         rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1552         of_node_put(crtc->port);
1553         drm_crtc_cleanup(crtc);
1554 }
1555
1556 static int vop_initial(struct vop *vop)
1557 {
1558         const struct vop_data *vop_data = vop->data;
1559         const struct vop_reg_data *init_table = vop_data->init_table;
1560         struct reset_control *ahb_rst;
1561         int i, ret;
1562
1563         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1564         if (IS_ERR(vop->hclk)) {
1565                 dev_err(vop->dev, "failed to get hclk source\n");
1566                 return PTR_ERR(vop->hclk);
1567         }
1568         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1569         if (IS_ERR(vop->aclk)) {
1570                 dev_err(vop->dev, "failed to get aclk source\n");
1571                 return PTR_ERR(vop->aclk);
1572         }
1573         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1574         if (IS_ERR(vop->dclk)) {
1575                 dev_err(vop->dev, "failed to get dclk source\n");
1576                 return PTR_ERR(vop->dclk);
1577         }
1578
1579         ret = clk_prepare(vop->dclk);
1580         if (ret < 0) {
1581                 dev_err(vop->dev, "failed to prepare dclk\n");
1582                 return ret;
1583         }
1584
1585         /* Enable both the hclk and aclk to setup the vop */
1586         ret = clk_prepare_enable(vop->hclk);
1587         if (ret < 0) {
1588                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1589                 goto err_unprepare_dclk;
1590         }
1591
1592         ret = clk_prepare_enable(vop->aclk);
1593         if (ret < 0) {
1594                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1595                 goto err_disable_hclk;
1596         }
1597
1598         /*
1599          * do hclk_reset, reset all vop registers.
1600          */
1601         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1602         if (IS_ERR(ahb_rst)) {
1603                 dev_err(vop->dev, "failed to get ahb reset\n");
1604                 ret = PTR_ERR(ahb_rst);
1605                 goto err_disable_aclk;
1606         }
1607         reset_control_assert(ahb_rst);
1608         usleep_range(10, 20);
1609         reset_control_deassert(ahb_rst);
1610
1611         memcpy(vop->regsbak, vop->regs, vop->len);
1612
1613         for (i = 0; i < vop_data->table_size; i++)
1614                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1615
1616         for (i = 0; i < vop_data->win_size; i++) {
1617                 const struct vop_win_data *win = &vop_data->win[i];
1618
1619                 VOP_WIN_SET(vop, win, enable, 0);
1620         }
1621
1622         vop_cfg_done(vop);
1623
1624         /*
1625          * do dclk_reset, let all config take affect.
1626          */
1627         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1628         if (IS_ERR(vop->dclk_rst)) {
1629                 dev_err(vop->dev, "failed to get dclk reset\n");
1630                 ret = PTR_ERR(vop->dclk_rst);
1631                 goto err_disable_aclk;
1632         }
1633         reset_control_assert(vop->dclk_rst);
1634         usleep_range(10, 20);
1635         reset_control_deassert(vop->dclk_rst);
1636
1637         clk_disable(vop->hclk);
1638         clk_disable(vop->aclk);
1639
1640         vop->is_enabled = false;
1641
1642         return 0;
1643
1644 err_disable_aclk:
1645         clk_disable_unprepare(vop->aclk);
1646 err_disable_hclk:
1647         clk_disable_unprepare(vop->hclk);
1648 err_unprepare_dclk:
1649         clk_unprepare(vop->dclk);
1650         return ret;
1651 }
1652
1653 /*
1654  * Initialize the vop->win array elements.
1655  */
1656 static void vop_win_init(struct vop *vop)
1657 {
1658         const struct vop_data *vop_data = vop->data;
1659         unsigned int i;
1660
1661         for (i = 0; i < vop_data->win_size; i++) {
1662                 struct vop_win *vop_win = &vop->win[i];
1663                 const struct vop_win_data *win_data = &vop_data->win[i];
1664
1665                 vop_win->data = win_data;
1666                 vop_win->vop = vop;
1667                 INIT_LIST_HEAD(&vop_win->pending);
1668         }
1669 }
1670
1671 static int vop_bind(struct device *dev, struct device *master, void *data)
1672 {
1673         struct platform_device *pdev = to_platform_device(dev);
1674         const struct of_device_id *of_id;
1675         const struct vop_data *vop_data;
1676         struct drm_device *drm_dev = data;
1677         struct vop *vop;
1678         struct resource *res;
1679         size_t alloc_size;
1680         int ret, irq;
1681
1682         of_id = of_match_device(vop_driver_dt_match, dev);
1683         vop_data = of_id->data;
1684         if (!vop_data)
1685                 return -ENODEV;
1686
1687         /* Allocate vop struct and its vop_win array */
1688         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1689         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1690         if (!vop)
1691                 return -ENOMEM;
1692
1693         vop->dev = dev;
1694         vop->data = vop_data;
1695         vop->drm_dev = drm_dev;
1696         dev_set_drvdata(dev, vop);
1697
1698         vop_win_init(vop);
1699
1700         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1701         vop->len = resource_size(res);
1702         vop->regs = devm_ioremap_resource(dev, res);
1703         if (IS_ERR(vop->regs))
1704                 return PTR_ERR(vop->regs);
1705
1706         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1707         if (!vop->regsbak)
1708                 return -ENOMEM;
1709
1710         ret = vop_initial(vop);
1711         if (ret < 0) {
1712                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1713                 return ret;
1714         }
1715
1716         irq = platform_get_irq(pdev, 0);
1717         if (irq < 0) {
1718                 dev_err(dev, "cannot find irq for vop\n");
1719                 return irq;
1720         }
1721         vop->irq = (unsigned int)irq;
1722
1723         spin_lock_init(&vop->reg_lock);
1724         spin_lock_init(&vop->irq_lock);
1725
1726         mutex_init(&vop->vsync_mutex);
1727
1728         ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1729                                         IRQF_SHARED, dev_name(dev), vop);
1730         if (ret)
1731                 return ret;
1732
1733         /* IRQ is initially disabled; it gets enabled in power_on */
1734         disable_irq(vop->irq);
1735
1736         ret = vop_create_crtc(vop);
1737         if (ret)
1738                 return ret;
1739
1740         pm_runtime_enable(&pdev->dev);
1741         return 0;
1742 }
1743
1744 static void vop_unbind(struct device *dev, struct device *master, void *data)
1745 {
1746         struct vop *vop = dev_get_drvdata(dev);
1747
1748         pm_runtime_disable(dev);
1749         vop_destroy_crtc(vop);
1750 }
1751
1752 static const struct component_ops vop_component_ops = {
1753         .bind = vop_bind,
1754         .unbind = vop_unbind,
1755 };
1756
1757 static int vop_probe(struct platform_device *pdev)
1758 {
1759         struct device *dev = &pdev->dev;
1760
1761         if (!dev->of_node) {
1762                 dev_err(dev, "can't find vop devices\n");
1763                 return -ENODEV;
1764         }
1765
1766         return component_add(dev, &vop_component_ops);
1767 }
1768
1769 static int vop_remove(struct platform_device *pdev)
1770 {
1771         component_del(&pdev->dev, &vop_component_ops);
1772
1773         return 0;
1774 }
1775
1776 struct platform_driver vop_platform_driver = {
1777         .probe = vop_probe,
1778         .remove = vop_remove,
1779         .driver = {
1780                 .name = "rockchip-vop",
1781                 .owner = THIS_MODULE,
1782                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1783         },
1784 };
1785
1786 module_platform_driver(vop_platform_driver);
1787
1788 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1789 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1790 MODULE_LICENSE("GPL v2");