drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/devfreq.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/component.h>
  32
  33 #include <linux/reset.h>
  34 #include <linux/delay.h>
  35 #include <linux/sort.h>
  36 #include <uapi/drm/rockchip_drm.h>
  37
  38 #include "rockchip_drm_drv.h"
  39 #include "rockchip_drm_gem.h"
  40 #include "rockchip_drm_fb.h"
  41 #include "rockchip_drm_vop.h"
  42
  43 #define VOP_REG_SUPPORT(vop, reg) \
  44                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  45                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  46                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  47                 reg.mask))
  48
  49 #define VOP_WIN_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, win->phy->name)
  51
  52 #define VOP_CTRL_SUPPORT(vop, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  54
  55 #define VOP_INTR_SUPPORT(vop, name) \
  56                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  57
  58 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  59                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  60
  61 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  62         do { \
  63                 if (VOP_REG_SUPPORT(vop, reg)) \
  64                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  65                                   v, reg.write_mask, relaxed); \
  66                 else \
  67                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  68         } while(0)
  69
  70 #define REG_SET(x, name, off, reg, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  72 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  73                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  74
  75 #define VOP_WIN_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  77 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  78                 REG_SET(x, name, 0, win->ext->name, v, true)
  79 #define VOP_SCL_SET(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  81 #define VOP_SCL_SET_EXT(x, win, name, v) \
  82                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  83
  84 #define VOP_CTRL_SET(x, name, v) \
  85                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  86
  87 #define VOP_INTR_GET(vop, name) \
  88                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  89
  90 #define VOP_INTR_SET(vop, name, v) \
  91                 REG_SET(vop, name, 0, vop->data->intr->name, \
  92                         v, false)
  93 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  94                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  95                              mask, v, false)
  96
  97 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  98         do { \
  99                 int i, reg = 0, mask = 0; \
 100                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 101                         if (vop->data->intr->intrs[i] & type) { \
 102                                 reg |= (v) << i; \
 103                                 mask |= 1 << i; \
 104                         } \
 105                 } \
 106                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 107         } while (0)
 108 #define VOP_INTR_GET_TYPE(vop, name, type) \
 109                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 110
 111 #define VOP_CTRL_GET(x, name) \
 112                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 113
 114 #define VOP_WIN_GET(x, win, name) \
 115                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 116
 117 #define VOP_WIN_NAME(win, name) \
 118                 (vop_get_win_phy(win, &win->phy->name)->name)
 119
 120 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 121                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 122
 123 #define to_vop(x) container_of(x, struct vop, crtc)
 124 #define to_vop_win(x) container_of(x, struct vop_win, base)
 125 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 126
 127 struct vop_zpos {
 128         int win_id;
 129         int zpos;
 130 };
 131
 132 struct vop_plane_state {
 133         struct drm_plane_state base;
 134         int format;
 135         int zpos;
 136         struct drm_rect src;
 137         struct drm_rect dest;
 138         dma_addr_t yrgb_mst;
 139         dma_addr_t uv_mst;
 140         const uint32_t *y2r_table;
 141         const uint32_t *r2r_table;
 142         const uint32_t *r2y_table;
 143         bool enable;
 144 };
 145
 146 struct vop_win {
 147         struct vop_win *parent;
 148         struct drm_plane base;
 149
 150         int win_id;
 151         int area_id;
 152         uint32_t offset;
 153         enum drm_plane_type type;
 154         const struct vop_win_phy *phy;
 155         const struct vop_csc *csc;
 156         const uint32_t *data_formats;
 157         uint32_t nformats;
 158         struct vop *vop;
 159
 160         struct drm_property *rotation_prop;
 161         struct vop_plane_state state;
 162 };
 163
 164 struct vop {
 165         struct drm_crtc crtc;
 166         struct device *dev;
 167         struct drm_device *drm_dev;
 168         struct drm_property *plane_zpos_prop;
 169         struct drm_property *plane_feature_prop;
 170         struct drm_property *feature_prop;
 171         bool is_iommu_enabled;
 172         bool is_iommu_needed;
 173         bool is_enabled;
 174
 175         /* mutex vsync_ work */
 176         struct mutex vsync_mutex;
 177         bool vsync_work_pending;
 178         bool loader_protect;
 179         struct completion dsp_hold_completion;
 180         struct completion wait_update_complete;
 181         struct drm_pending_vblank_event *event;
 182
 183         struct completion line_flag_completion;
 184
 185         const struct vop_data *data;
 186         int num_wins;
 187
 188         uint32_t *regsbak;
 189         void __iomem *regs;
 190
 191         /* physical map length of vop register */
 192         uint32_t len;
 193
 194         void __iomem *lut_regs;
 195         u32 *lut;
 196         u32 lut_len;
 197         bool lut_active;
 198
 199         /* one time only one process allowed to config the register */
 200         spinlock_t reg_lock;
 201         /* lock vop irq reg */
 202         spinlock_t irq_lock;
 203         /* mutex vop enable and disable */
 204         struct mutex vop_lock;
 205
 206         unsigned int irq;
 207
 208         /* vop AHP clk */
 209         struct clk *hclk;
 210         /* vop dclk */
 211         struct clk *dclk;
 212         /* vop share memory frequency */
 213         struct clk *aclk;
 214
 215         /* vop dclk reset */
 216         struct reset_control *dclk_rst;
 217
 218         struct devfreq *devfreq;
 219         struct notifier_block dmc_nb;
 220
 221         struct vop_win win[];
 222 };
 223
 224 struct vop *dmc_vop;
 225
 226 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 227 {
 228         writel(v, vop->regs + offset);
 229         vop->regsbak[offset >> 2] = v;
 230 }
 231
 232 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 233 {
 234         return readl(vop->regs + offset);
 235 }
 236
 237 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 238                                     const struct vop_reg *reg)
 239 {
 240         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 241 }
 242
 243 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 244                                   uint32_t mask, uint32_t shift, uint32_t v,
 245                                   bool write_mask, bool relaxed)
 246 {
 247         if (!mask)
 248                 return;
 249
 250         if (write_mask) {
 251                 v = ((v & mask) << shift) | (mask << (shift + 16));
 252         } else {
 253                 uint32_t cached_val = vop->regsbak[offset >> 2];
 254
 255                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 256                 vop->regsbak[offset >> 2] = v;
 257         }
 258
 259         if (relaxed)
 260                 writel_relaxed(v, vop->regs + offset);
 261         else
 262                 writel(v, vop->regs + offset);
 263 }
 264
 265 static inline const struct vop_win_phy *
 266 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 267 {
 268         if (!reg->mask && win->parent)
 269                 return win->parent->phy;
 270
 271         return win->phy;
 272 }
 273
 274 static inline uint32_t vop_get_intr_type(struct vop *vop,
 275                                          const struct vop_reg *reg, int type)
 276 {
 277         uint32_t i, ret = 0;
 278         uint32_t regs = vop_read_reg(vop, 0, reg);
 279
 280         for (i = 0; i < vop->data->intr->nintrs; i++) {
 281                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 282                         ret |= vop->data->intr->intrs[i];
 283         }
 284
 285         return ret;
 286 }
 287
 288 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 289 {
 290         int i;
 291
 292         if (!table)
 293                 return;
 294
 295         for (i = 0; i < 8; i++)
 296                 vop_writel(vop, offset + i * 4, table[i]);
 297 }
 298
 299 static inline void vop_cfg_done(struct vop *vop)
 300 {
 301         VOP_CTRL_SET(vop, cfg_done, 1);
 302 }
 303
 304 static bool vop_is_allwin_disabled(struct vop *vop)
 305 {
 306         int i;
 307
 308         for (i = 0; i < vop->num_wins; i++) {
 309                 struct vop_win *win = &vop->win[i];
 310
 311                 if (VOP_WIN_GET(vop, win, enable) != 0)
 312                         return false;
 313         }
 314
 315         return true;
 316 }
 317
 318 static bool vop_is_cfg_done_complete(struct vop *vop)
 319 {
 320         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 321 }
 322
 323 static bool vop_fs_irq_is_active(struct vop *vop)
 324 {
 325         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 326 }
 327
 328 static bool vop_line_flag_is_active(struct vop *vop)
 329 {
 330         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 331 }
 332
 333 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 334 {
 335         writel(v, vop->lut_regs + offset);
 336 }
 337
 338 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 339 {
 340         return readl(vop->lut_regs + offset);
 341 }
 342
 343 static bool has_rb_swapped(uint32_t format)
 344 {
 345         switch (format) {
 346         case DRM_FORMAT_XBGR8888:
 347         case DRM_FORMAT_ABGR8888:
 348         case DRM_FORMAT_BGR888:
 349         case DRM_FORMAT_BGR565:
 350                 return true;
 351         default:
 352                 return false;
 353         }
 354 }
 355
 356 static enum vop_data_format vop_convert_format(uint32_t format)
 357 {
 358         switch (format) {
 359         case DRM_FORMAT_XRGB8888:
 360         case DRM_FORMAT_ARGB8888:
 361         case DRM_FORMAT_XBGR8888:
 362         case DRM_FORMAT_ABGR8888:
 363                 return VOP_FMT_ARGB8888;
 364         case DRM_FORMAT_RGB888:
 365         case DRM_FORMAT_BGR888:
 366                 return VOP_FMT_RGB888;
 367         case DRM_FORMAT_RGB565:
 368         case DRM_FORMAT_BGR565:
 369                 return VOP_FMT_RGB565;
 370         case DRM_FORMAT_NV12:
 371         case DRM_FORMAT_NV12_10:
 372                 return VOP_FMT_YUV420SP;
 373         case DRM_FORMAT_NV16:
 374         case DRM_FORMAT_NV16_10:
 375                 return VOP_FMT_YUV422SP;
 376         case DRM_FORMAT_NV24:
 377         case DRM_FORMAT_NV24_10:
 378                 return VOP_FMT_YUV444SP;
 379         default:
 380                 DRM_ERROR("unsupport format[%08x]\n", format);
 381                 return -EINVAL;
 382         }
 383 }
 384
 385 static bool is_yuv_output(uint32_t bus_format)
 386 {
 387         switch (bus_format) {
 388         case MEDIA_BUS_FMT_YUV8_1X24:
 389         case MEDIA_BUS_FMT_YUV10_1X30:
 390                 return true;
 391         default:
 392                 return false;
 393         }
 394 }
 395
 396 static bool is_yuv_support(uint32_t format)
 397 {
 398         switch (format) {
 399         case DRM_FORMAT_NV12:
 400         case DRM_FORMAT_NV12_10:
 401         case DRM_FORMAT_NV16:
 402         case DRM_FORMAT_NV16_10:
 403         case DRM_FORMAT_NV24:
 404         case DRM_FORMAT_NV24_10:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410
 411 static bool is_yuv_10bit(uint32_t format)
 412 {
 413         switch (format) {
 414         case DRM_FORMAT_NV12_10:
 415         case DRM_FORMAT_NV16_10:
 416         case DRM_FORMAT_NV24_10:
 417                 return true;
 418         default:
 419                 return false;
 420         }
 421 }
 422
 423 static bool is_alpha_support(uint32_t format)
 424 {
 425         switch (format) {
 426         case DRM_FORMAT_ARGB8888:
 427         case DRM_FORMAT_ABGR8888:
 428                 return true;
 429         default:
 430                 return false;
 431         }
 432 }
 433
 434 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 435                                   uint32_t dst, bool is_horizontal,
 436                                   int vsu_mode, int *vskiplines)
 437 {
 438         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 439
 440         if (is_horizontal) {
 441                 if (mode == SCALE_UP)
 442                         val = GET_SCL_FT_BIC(src, dst);
 443                 else if (mode == SCALE_DOWN)
 444                         val = GET_SCL_FT_BILI_DN(src, dst);
 445         } else {
 446                 if (mode == SCALE_UP) {
 447                         if (vsu_mode == SCALE_UP_BIL)
 448                                 val = GET_SCL_FT_BILI_UP(src, dst);
 449                         else
 450                                 val = GET_SCL_FT_BIC(src, dst);
 451                 } else if (mode == SCALE_DOWN) {
 452                         if (vskiplines) {
 453                                 *vskiplines = scl_get_vskiplines(src, dst);
 454                                 val = scl_get_bili_dn_vskip(src, dst,
 455                                                             *vskiplines);
 456                         } else {
 457                                 val = GET_SCL_FT_BILI_DN(src, dst);
 458                         }
 459                 }
 460         }
 461
 462         return val;
 463 }
 464
 465 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 466                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 467                                 uint32_t dst_h, uint32_t pixel_format)
 468 {
 469         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 470         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 471         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 472         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 473         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 474         bool is_yuv = is_yuv_support(pixel_format);
 475         uint16_t cbcr_src_w = src_w / hsub;
 476         uint16_t cbcr_src_h = src_h / vsub;
 477         uint16_t vsu_mode;
 478         uint16_t lb_mode;
 479         uint32_t val;
 480         int vskiplines = 0;
 481
 482         if (!win->phy->scl)
 483                 return;
 484
 485         if (!win->phy->scl->ext) {
 486                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 487                             scl_cal_scale2(src_w, dst_w));
 488                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 489                             scl_cal_scale2(src_h, dst_h));
 490                 if (is_yuv) {
 491                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 492                                     scl_cal_scale2(cbcr_src_w, dst_w));
 493                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 494                                     scl_cal_scale2(cbcr_src_h, dst_h));
 495                 }
 496                 return;
 497         }
 498
 499         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 500         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 501
 502         if (is_yuv) {
 503                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 504                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 505                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 506                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 507                 else
 508                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 509         } else {
 510                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 511                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 512                 else
 513                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 514         }
 515
 516         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 517         if (lb_mode == LB_RGB_3840X2) {
 518                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 519                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 520                         return;
 521                 }
 522                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 523                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 524                         return;
 525                 }
 526                 vsu_mode = SCALE_UP_BIL;
 527         } else if (lb_mode == LB_RGB_2560X4) {
 528                 vsu_mode = SCALE_UP_BIL;
 529         } else {
 530                 vsu_mode = SCALE_UP_BIC;
 531         }
 532
 533         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 534                                 true, 0, NULL);
 535         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 536         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 537                                 false, vsu_mode, &vskiplines);
 538         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 539
 540         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 541         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 542
 543         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 544         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 545         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 546         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 547         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 548         if (is_yuv) {
 549                 vskiplines = 0;
 550
 551                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 552                                         dst_w, true, 0, NULL);
 553                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 554                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 555                                         dst_h, false, vsu_mode, &vskiplines);
 556                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 557
 558                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 559                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 560                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 561                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 562                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 563                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 564                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 565         }
 566 }
 567
 568 /*
 569  * rk3399 colorspace path:
 570  *      Input        Win csc                     Output
 571  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 572  *    RGB        --> R2Y                  __/
 573  *
 574  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 575  *    RGB        --> 709To2020->R2Y       __/
 576  *
 577  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 578  *    RGB        --> R2Y                  __/
 579  *
 580  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 581  *    RGB        --> 709To2020->R2Y       __/
 582  *
 583  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 584  *    RGB        --> R2Y                  __/
 585  *
 586  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 587  *    RGB        --> R2Y(601)             __/
 588  *
 589  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 590  *    RGB        --> bypass               __/
 591  *
 592  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 593  *
 594  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 595  *
 596  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 597  *
 598  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 599  */
 600 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 601                          bool is_input_yuv, bool is_output_yuv,
 602                          int input_csc, int output_csc,
 603                          const uint32_t **y2r_table,
 604                          const uint32_t **r2r_table,
 605                          const uint32_t **r2y_table)
 606 {
 607         *y2r_table = NULL;
 608         *r2r_table = NULL;
 609         *r2y_table = NULL;
 610
 611         if (is_output_yuv) {
 612                 if (output_csc == CSC_BT2020) {
 613                         if (is_input_yuv) {
 614                                 if (input_csc == CSC_BT2020)
 615                                         return 0;
 616                                 *y2r_table = csc_table->y2r_bt709;
 617                         }
 618                         if (input_csc != CSC_BT2020)
 619                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 620                         *r2y_table = csc_table->r2y_bt2020;
 621                 } else {
 622                         if (is_input_yuv && input_csc == CSC_BT2020)
 623                                 *y2r_table = csc_table->y2r_bt2020;
 624                         if (input_csc == CSC_BT2020)
 625                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 626                         if (!is_input_yuv || *y2r_table) {
 627                                 if (output_csc == CSC_BT709)
 628                                         *r2y_table = csc_table->r2y_bt709;
 629                                 else
 630                                         *r2y_table = csc_table->r2y_bt601;
 631                         }
 632                 }
 633         } else {
 634                 if (!is_input_yuv)
 635                         return 0;
 636
 637                 /*
 638                  * is possible use bt2020 on rgb mode?
 639                  */
 640                 if (WARN_ON(output_csc == CSC_BT2020))
 641                         return -EINVAL;
 642
 643                 if (input_csc == CSC_BT2020)
 644                         *y2r_table = csc_table->y2r_bt2020;
 645                 else if (input_csc == CSC_BT709)
 646                         *y2r_table = csc_table->y2r_bt709;
 647                 else
 648                         *y2r_table = csc_table->y2r_bt601;
 649
 650                 if (input_csc == CSC_BT2020)
 651                         /*
 652                          * We don't have bt601 to bt709 table, force use bt709.
 653                          */
 654                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 661                                 struct drm_crtc_state *crtc_state)
 662 {
 663         struct vop *vop = to_vop(crtc);
 664         struct drm_atomic_state *state = crtc_state->state;
 665         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 666         const struct vop_csc_table *csc_table = vop->data->csc_table;
 667         struct drm_plane_state *pstate;
 668         struct drm_plane *plane;
 669         bool is_input_yuv, is_output_yuv;
 670         int ret;
 671
 672         if (!csc_table)
 673                 return 0;
 674
 675         is_output_yuv = is_yuv_output(s->bus_format);
 676
 677         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 678                 struct vop_plane_state *vop_plane_state;
 679
 680                 pstate = drm_atomic_get_plane_state(state, plane);
 681                 if (IS_ERR(pstate))
 682                         return PTR_ERR(pstate);
 683                 vop_plane_state = to_vop_plane_state(pstate);
 684
 685                 if (!pstate->fb)
 686                         continue;
 687                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 688
 689                 /*
 690                  * TODO: force set input and output csc mode.
 691                  */
 692                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 693                                     CSC_BT709, CSC_BT709,
 694                                     &vop_plane_state->y2r_table,
 695                                     &vop_plane_state->r2r_table,
 696                                     &vop_plane_state->r2y_table);
 697                 if (ret)
 698                         return ret;
 699         }
 700
 701         return 0;
 702 }
 703
 704 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 705 {
 706         unsigned long flags;
 707
 708         spin_lock_irqsave(&vop->irq_lock, flags);
 709
 710         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 711         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 712
 713         spin_unlock_irqrestore(&vop->irq_lock, flags);
 714 }
 715
 716 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 717 {
 718         unsigned long flags;
 719
 720         spin_lock_irqsave(&vop->irq_lock, flags);
 721
 722         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 723
 724         spin_unlock_irqrestore(&vop->irq_lock, flags);
 725 }
 726
 727 /*
 728  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 729  *     the "FRAME_SYNC" interrupt.
 730  * (2) the active data region of each frame ends at dsp_vact_end
 731  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 732  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 733  *
 734  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 735  * Interrupts
 736  * LINE_FLAG -------------------------------+
 737  * FRAME_SYNC ----+                         |
 738  *                |                         |
 739  *                v                         v
 740  *                | Vsync | Vbp |  Vactive  | Vfp |
 741  *                        ^     ^           ^     ^
 742  *                        |     |           |     |
 743  *                        |     |           |     |
 744  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 745  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 746  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 747  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 748  */
 749 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 750 {
 751         uint32_t line_flag_irq;
 752         unsigned long flags;
 753
 754         spin_lock_irqsave(&vop->irq_lock, flags);
 755
 756         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 757
 758         spin_unlock_irqrestore(&vop->irq_lock, flags);
 759
 760         return !!line_flag_irq;
 761 }
 762
 763 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 764 {
 765         unsigned long flags;
 766
 767         if (WARN_ON(!vop->is_enabled))
 768                 return;
 769
 770         spin_lock_irqsave(&vop->irq_lock, flags);
 771
 772         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 773         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 774         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 775
 776         spin_unlock_irqrestore(&vop->irq_lock, flags);
 777 }
 778
 779 static void vop_line_flag_irq_disable(struct vop *vop)
 780 {
 781         unsigned long flags;
 782
 783         if (WARN_ON(!vop->is_enabled))
 784                 return;
 785
 786         spin_lock_irqsave(&vop->irq_lock, flags);
 787
 788         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 789
 790         spin_unlock_irqrestore(&vop->irq_lock, flags);
 791 }
 792
 793 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 794 {
 795         struct vop *vop = to_vop(crtc);
 796         int i, dle, lut_idx;
 797
 798         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 799                 return;
 800
 801         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 802                 return;
 803
 804         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 805                 spin_lock(&vop->reg_lock);
 806                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 807                 vop_cfg_done(vop);
 808                 spin_unlock(&vop->reg_lock);
 809
 810 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 811                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 812                                 dle, !dle, 5, 33333);
 813         } else {
 814                 lut_idx = CTRL_GET(lut_buffer_index);
 815         }
 816
 817         for (i = 0; i < vop->lut_len; i++)
 818                 vop_write_lut(vop, i << 2, vop->lut[i]);
 819
 820         spin_lock(&vop->reg_lock);
 821
 822         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 823         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 824         vop_cfg_done(vop);
 825         vop->lut_active = true;
 826
 827         spin_unlock(&vop->reg_lock);
 828
 829         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 830                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 831                                    dle, dle != lut_idx, 5, 33333);
 832                 /* FIXME:
 833                  * update_gamma value auto clean to 0 by HW, should not
 834                  * bakeup it.
 835                  */
 836                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 837         }
 838 #undef CTRL_GET
 839 }
 840
 841 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 842                                     u16 blue, int regno)
 843 {
 844         struct vop *vop = to_vop(crtc);
 845         u32 lut_len = vop->lut_len;
 846         u32 r, g, b;
 847
 848         if (regno >= lut_len || !vop->lut)
 849                 return;
 850
 851         r = red * (lut_len - 1) / 0xffff;
 852         g = green * (lut_len - 1) / 0xffff;
 853         b = blue * (lut_len - 1) / 0xffff;
 854         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 855 }
 856
 857 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 858                                     u16 *blue, int regno)
 859 {
 860         struct vop *vop = to_vop(crtc);
 861         u32 lut_len = vop->lut_len;
 862         u32 r, g, b;
 863
 864         if (regno >= lut_len || !vop->lut)
 865                 return;
 866
 867         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 868         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 869         b = vop->lut[regno] & (lut_len - 1);
 870         *red = r * 0xffff / (lut_len - 1);
 871         *green = g * 0xffff / (lut_len - 1);
 872         *blue = b * 0xffff / (lut_len - 1);
 873 }
 874
 875 static void vop_power_enable(struct drm_crtc *crtc)
 876 {
 877         struct vop *vop = to_vop(crtc);
 878         int ret;
 879
 880         ret = clk_prepare_enable(vop->hclk);
 881         if (ret < 0) {
 882                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 883                 return;
 884         }
 885
 886         ret = clk_prepare_enable(vop->dclk);
 887         if (ret < 0) {
 888                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 889                 goto err_disable_hclk;
 890         }
 891
 892         ret = clk_prepare_enable(vop->aclk);
 893         if (ret < 0) {
 894                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 895                 goto err_disable_dclk;
 896         }
 897
 898         ret = pm_runtime_get_sync(vop->dev);
 899         if (ret < 0) {
 900                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 901                 return;
 902         }
 903
 904         memcpy(vop->regsbak, vop->regs, vop->len);
 905
 906         vop->is_enabled = true;
 907
 908         return;
 909
 910 err_disable_dclk:
 911         clk_disable_unprepare(vop->dclk);
 912 err_disable_hclk:
 913         clk_disable_unprepare(vop->hclk);
 914 }
 915
 916 static void vop_initial(struct drm_crtc *crtc)
 917 {
 918         struct vop *vop = to_vop(crtc);
 919         int i;
 920
 921         vop_power_enable(crtc);
 922
 923         VOP_CTRL_SET(vop, global_regdone_en, 1);
 924         VOP_CTRL_SET(vop, dsp_blank, 0);
 925
 926         /*
 927          * restore the lut table.
 928          */
 929         if (vop->lut_active)
 930                 vop_crtc_load_lut(crtc);
 931
 932         /*
 933          * We need to make sure that all windows are disabled before resume
 934          * the crtc. Otherwise we might try to scan from a destroyed
 935          * buffer later.
 936          */
 937         for (i = 0; i < vop->num_wins; i++) {
 938                 struct vop_win *win = &vop->win[i];
 939                 int channel = i * 2 + 1;
 940
 941                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 942                 if (win->phy->scl && win->phy->scl->ext) {
 943                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 944                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 945                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 946                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 947                 }
 948                 VOP_WIN_SET(vop, win, enable, 0);
 949                 VOP_WIN_SET(vop, win, gate, 1);
 950         }
 951         VOP_CTRL_SET(vop, afbdc_en, 0);
 952 }
 953
 954 static void vop_crtc_disable(struct drm_crtc *crtc)
 955 {
 956         struct vop *vop = to_vop(crtc);
 957
 958         mutex_lock(&vop->vop_lock);
 959         drm_crtc_vblank_off(crtc);
 960
 961         /*
 962          * Vop standby will take effect at end of current frame,
 963          * if dsp hold valid irq happen, it means standby complete.
 964          *
 965          * we must wait standby complete when we want to disable aclk,
 966          * if not, memory bus maybe dead.
 967          */
 968         reinit_completion(&vop->dsp_hold_completion);
 969         vop_dsp_hold_valid_irq_enable(vop);
 970
 971         spin_lock(&vop->reg_lock);
 972
 973         VOP_CTRL_SET(vop, standby, 1);
 974
 975         spin_unlock(&vop->reg_lock);
 976
 977         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 978                                              msecs_to_jiffies(50)));
 979
 980         vop_dsp_hold_valid_irq_disable(vop);
 981
 982         disable_irq(vop->irq);
 983
 984         vop->is_enabled = false;
 985         if (vop->is_iommu_enabled) {
 986                 /*
 987                  * vop standby complete, so iommu detach is safe.
 988                  */
 989                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 990                 vop->is_iommu_enabled = false;
 991         }
 992
 993         pm_runtime_put(vop->dev);
 994         clk_disable_unprepare(vop->dclk);
 995         clk_disable_unprepare(vop->aclk);
 996         clk_disable_unprepare(vop->hclk);
 997         mutex_unlock(&vop->vop_lock);
 998 }
 999
1000 static void vop_plane_destroy(struct drm_plane *plane)
1001 {
1002         drm_plane_cleanup(plane);
1003 }
1004
1005 static int vop_plane_prepare_fb(struct drm_plane *plane,
1006                                 const struct drm_plane_state *new_state)
1007 {
1008         if (plane->state->fb)
1009                 drm_framebuffer_reference(plane->state->fb);
1010
1011         return 0;
1012 }
1013
1014 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1015                                  const struct drm_plane_state *old_state)
1016 {
1017         if (old_state->fb)
1018                 drm_framebuffer_unreference(old_state->fb);
1019 }
1020
1021 static int vop_plane_atomic_check(struct drm_plane *plane,
1022                            struct drm_plane_state *state)
1023 {
1024         struct drm_crtc *crtc = state->crtc;
1025         struct drm_framebuffer *fb = state->fb;
1026         struct vop_win *win = to_vop_win(plane);
1027         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1028         struct drm_crtc_state *crtc_state;
1029         const struct vop_data *vop_data;
1030         struct vop *vop;
1031         bool visible;
1032         int ret;
1033         struct drm_rect *dest = &vop_plane_state->dest;
1034         struct drm_rect *src = &vop_plane_state->src;
1035         struct drm_rect clip;
1036         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1037                                         DRM_PLANE_HELPER_NO_SCALING;
1038         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1039                                         DRM_PLANE_HELPER_NO_SCALING;
1040         unsigned long offset;
1041         dma_addr_t dma_addr;
1042         u16 vdisplay;
1043
1044         crtc = crtc ? crtc : plane->state->crtc;
1045         /*
1046          * Both crtc or plane->state->crtc can be null.
1047          */
1048         if (!crtc || !fb)
1049                 goto out_disable;
1050
1051         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1052         if (IS_ERR(crtc_state))
1053                 return PTR_ERR(crtc_state);
1054
1055         src->x1 = state->src_x;
1056         src->y1 = state->src_y;
1057         src->x2 = state->src_x + state->src_w;
1058         src->y2 = state->src_y + state->src_h;
1059         dest->x1 = state->crtc_x;
1060         dest->y1 = state->crtc_y;
1061         dest->x2 = state->crtc_x + state->crtc_w;
1062         dest->y2 = state->crtc_y + state->crtc_h;
1063
1064         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1065         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1066                 vdisplay *= 2;
1067
1068         clip.x1 = 0;
1069         clip.y1 = 0;
1070         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1071         clip.y2 = vdisplay;
1072
1073         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1074                                             src, dest, &clip,
1075                                             min_scale,
1076                                             max_scale,
1077                                             true, true, &visible);
1078         if (ret)
1079                 return ret;
1080
1081         if (!visible)
1082                 goto out_disable;
1083
1084         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1085         if (vop_plane_state->format < 0)
1086                 return vop_plane_state->format;
1087
1088         vop = to_vop(crtc);
1089         vop_data = vop->data;
1090
1091         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1092             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1093                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1094                           drm_rect_width(src) >> 16,
1095                           drm_rect_height(src) >> 16,
1096                           vop_data->max_input.width,
1097                           vop_data->max_input.height);
1098                 return -EINVAL;
1099         }
1100
1101         /*
1102          * Src.x1 can be odd when do clip, but yuv plane start point
1103          * need align with 2 pixel.
1104          */
1105         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1106                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1107                 return -EINVAL;
1108         }
1109
1110         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1111         if (state->rotation & BIT(DRM_REFLECT_Y))
1112                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1113         else
1114                 offset += (src->y1 >> 16) * fb->pitches[0];
1115
1116         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1117         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1118         if (is_yuv_support(fb->pixel_format)) {
1119                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1120                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1121                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1122
1123                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1124                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1125
1126                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1127                 dma_addr += offset + fb->offsets[1];
1128                 vop_plane_state->uv_mst = dma_addr;
1129         }
1130
1131         vop_plane_state->enable = true;
1132
1133         return 0;
1134
1135 out_disable:
1136         vop_plane_state->enable = false;
1137         return 0;
1138 }
1139
1140 static void vop_plane_atomic_disable(struct drm_plane *plane,
1141                                      struct drm_plane_state *old_state)
1142 {
1143         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1144         struct vop_win *win = to_vop_win(plane);
1145         struct vop *vop = to_vop(old_state->crtc);
1146
1147         if (!old_state->crtc)
1148                 return;
1149
1150         spin_lock(&vop->reg_lock);
1151
1152         /*
1153          * FIXUP: some of the vop scale would be abnormal after windows power
1154          * on/off so deinit scale to scale_none mode.
1155          */
1156         if (win->phy->scl && win->phy->scl->ext) {
1157                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1158                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1159                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1160                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1161         }
1162         VOP_WIN_SET(vop, win, enable, 0);
1163
1164         spin_unlock(&vop->reg_lock);
1165
1166         vop_plane_state->enable = false;
1167 }
1168
1169 static void vop_plane_atomic_update(struct drm_plane *plane,
1170                 struct drm_plane_state *old_state)
1171 {
1172         struct drm_plane_state *state = plane->state;
1173         struct drm_crtc *crtc = state->crtc;
1174         struct vop_win *win = to_vop_win(plane);
1175         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1176         struct rockchip_crtc_state *s;
1177         struct vop *vop;
1178         struct drm_framebuffer *fb = state->fb;
1179         unsigned int actual_w, actual_h;
1180         unsigned int dsp_stx, dsp_sty;
1181         uint32_t act_info, dsp_info, dsp_st;
1182         struct drm_rect *src = &vop_plane_state->src;
1183         struct drm_rect *dest = &vop_plane_state->dest;
1184         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1185         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1186         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1187         int ymirror, xmirror;
1188         uint32_t val;
1189         bool rb_swap;
1190
1191         /*
1192          * can't update plane when vop is disabled.
1193          */
1194         if (!crtc)
1195                 return;
1196
1197         if (!vop_plane_state->enable) {
1198                 vop_plane_atomic_disable(plane, old_state);
1199                 return;
1200         }
1201
1202         actual_w = drm_rect_width(src) >> 16;
1203         actual_h = drm_rect_height(src) >> 16;
1204         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1205
1206         dsp_info = (drm_rect_height(dest) - 1) << 16;
1207         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1208
1209         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1210         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1211         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1212
1213         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1214         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1215
1216         vop = to_vop(state->crtc);
1217         s = to_rockchip_crtc_state(crtc->state);
1218
1219         spin_lock(&vop->reg_lock);
1220
1221         VOP_WIN_SET(vop, win, xmirror, xmirror);
1222         VOP_WIN_SET(vop, win, ymirror, ymirror);
1223         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1224         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1225         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1226         if (is_yuv_support(fb->pixel_format)) {
1227                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1228                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1229         }
1230         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1231
1232         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1233                             drm_rect_width(dest), drm_rect_height(dest),
1234                             fb->pixel_format);
1235
1236         VOP_WIN_SET(vop, win, act_info, act_info);
1237         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1238         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1239
1240         rb_swap = has_rb_swapped(fb->pixel_format);
1241         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1242
1243         if (is_alpha_support(fb->pixel_format) &&
1244             (s->dsp_layer_sel & 0x3) != win->win_id) {
1245                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1246                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1247                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1248                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1249                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1250                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1251                         SRC_FACTOR_M0(ALPHA_ONE);
1252                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1253                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1254                 VOP_WIN_SET(vop, win, alpha_en, 1);
1255         } else {
1256                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1257                 VOP_WIN_SET(vop, win, alpha_en, 0);
1258         }
1259
1260         if (win->csc) {
1261                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1262                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1263                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1264                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1265                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1266                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1267         }
1268         VOP_WIN_SET(vop, win, enable, 1);
1269         spin_unlock(&vop->reg_lock);
1270         vop->is_iommu_needed = true;
1271 }
1272
1273 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1274         .prepare_fb = vop_plane_prepare_fb,
1275         .cleanup_fb = vop_plane_cleanup_fb,
1276         .atomic_check = vop_plane_atomic_check,
1277         .atomic_update = vop_plane_atomic_update,
1278         .atomic_disable = vop_plane_atomic_disable,
1279 };
1280
1281 void vop_atomic_plane_reset(struct drm_plane *plane)
1282 {
1283         struct vop_win *win = to_vop_win(plane);
1284         struct vop_plane_state *vop_plane_state =
1285                                         to_vop_plane_state(plane->state);
1286
1287         if (plane->state && plane->state->fb)
1288                 drm_framebuffer_unreference(plane->state->fb);
1289
1290         kfree(vop_plane_state);
1291         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1292         if (!vop_plane_state)
1293                 return;
1294
1295         vop_plane_state->zpos = win->win_id;
1296         plane->state = &vop_plane_state->base;
1297         plane->state->plane = plane;
1298 }
1299
1300 struct drm_plane_state *
1301 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1302 {
1303         struct vop_plane_state *old_vop_plane_state;
1304         struct vop_plane_state *vop_plane_state;
1305
1306         if (WARN_ON(!plane->state))
1307                 return NULL;
1308
1309         old_vop_plane_state = to_vop_plane_state(plane->state);
1310         vop_plane_state = kmemdup(old_vop_plane_state,
1311                                   sizeof(*vop_plane_state), GFP_KERNEL);
1312         if (!vop_plane_state)
1313                 return NULL;
1314
1315         __drm_atomic_helper_plane_duplicate_state(plane,
1316                                                   &vop_plane_state->base);
1317
1318         return &vop_plane_state->base;
1319 }
1320
1321 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1322                                            struct drm_plane_state *state)
1323 {
1324         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1325
1326         __drm_atomic_helper_plane_destroy_state(plane, state);
1327
1328         kfree(vop_state);
1329 }
1330
1331 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1332                                          struct drm_plane_state *state,
1333                                          struct drm_property *property,
1334                                          uint64_t val)
1335 {
1336         struct vop_win *win = to_vop_win(plane);
1337         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1338
1339         if (property == win->vop->plane_zpos_prop) {
1340                 plane_state->zpos = val;
1341                 return 0;
1342         }
1343
1344         if (property == win->rotation_prop) {
1345                 state->rotation = val;
1346                 return 0;
1347         }
1348
1349         DRM_ERROR("failed to set vop plane property\n");
1350         return -EINVAL;
1351 }
1352
1353 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1354                                          const struct drm_plane_state *state,
1355                                          struct drm_property *property,
1356                                          uint64_t *val)
1357 {
1358         struct vop_win *win = to_vop_win(plane);
1359         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1360
1361         if (property == win->vop->plane_zpos_prop) {
1362                 *val = plane_state->zpos;
1363                 return 0;
1364         }
1365
1366         if (property == win->rotation_prop) {
1367                 *val = state->rotation;
1368                 return 0;
1369         }
1370
1371         DRM_ERROR("failed to get vop plane property\n");
1372         return -EINVAL;
1373 }
1374
1375 static const struct drm_plane_funcs vop_plane_funcs = {
1376         .update_plane   = drm_atomic_helper_update_plane,
1377         .disable_plane  = drm_atomic_helper_disable_plane,
1378         .destroy = vop_plane_destroy,
1379         .reset = vop_atomic_plane_reset,
1380         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1381         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1382         .atomic_set_property = vop_atomic_plane_set_property,
1383         .atomic_get_property = vop_atomic_plane_get_property,
1384 };
1385
1386 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1387 {
1388         struct vop *vop = to_vop(crtc);
1389         unsigned long flags;
1390
1391         if (!vop->is_enabled)
1392                 return -EPERM;
1393
1394         spin_lock_irqsave(&vop->irq_lock, flags);
1395
1396         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1397         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1398
1399         spin_unlock_irqrestore(&vop->irq_lock, flags);
1400
1401         return 0;
1402 }
1403
1404 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1405 {
1406         struct vop *vop = to_vop(crtc);
1407         unsigned long flags;
1408
1409         if (!vop->is_enabled)
1410                 return;
1411
1412         spin_lock_irqsave(&vop->irq_lock, flags);
1413
1414         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1415
1416         spin_unlock_irqrestore(&vop->irq_lock, flags);
1417 }
1418
1419 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1420 {
1421         struct vop *vop = to_vop(crtc);
1422
1423         reinit_completion(&vop->wait_update_complete);
1424         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete,
1425                                              msecs_to_jiffies(1000)));
1426 }
1427
1428 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1429                                            struct drm_file *file_priv)
1430 {
1431         struct drm_device *drm = crtc->dev;
1432         struct vop *vop = to_vop(crtc);
1433         struct drm_pending_vblank_event *e;
1434         unsigned long flags;
1435
1436         spin_lock_irqsave(&drm->event_lock, flags);
1437         e = vop->event;
1438         if (e && e->base.file_priv == file_priv) {
1439                 vop->event = NULL;
1440
1441                 e->base.destroy(&e->base);
1442                 file_priv->event_space += sizeof(e->event);
1443         }
1444         spin_unlock_irqrestore(&drm->event_lock, flags);
1445 }
1446
1447 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1448 {
1449         struct vop *vop = to_vop(crtc);
1450
1451         if (on == vop->loader_protect)
1452                 return 0;
1453
1454         if (on) {
1455                 vop_power_enable(crtc);
1456                 enable_irq(vop->irq);
1457                 drm_crtc_vblank_on(crtc);
1458                 vop->loader_protect = true;
1459         } else {
1460                 vop_crtc_disable(crtc);
1461
1462                 vop->loader_protect = false;
1463         }
1464
1465         return 0;
1466 }
1467
1468 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1469 {
1470         struct vop_win *win = to_vop_win(plane);
1471         struct drm_plane_state *state = plane->state;
1472         struct vop_plane_state *pstate = to_vop_plane_state(state);
1473         struct drm_rect *src, *dest;
1474         struct drm_framebuffer *fb = state->fb;
1475         int i;
1476
1477         seq_printf(s, "    win%d-%d: %s\n", win->win_id, win->area_id,
1478                    pstate->enable ? "ACTIVE" : "DISABLED");
1479         if (!fb)
1480                 return 0;
1481
1482         src = &pstate->src;
1483         dest = &pstate->dest;
1484
1485         seq_printf(s, "\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1486                    fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1487         seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1488         seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1489                    src->y1 >> 16, drm_rect_width(src) >> 16,
1490                    drm_rect_height(src) >> 16);
1491         seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1492                    drm_rect_width(dest), drm_rect_height(dest));
1493
1494         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1495                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1496                 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1497                            i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1498         }
1499
1500         return 0;
1501 }
1502
1503 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1504 {
1505         struct vop *vop = to_vop(crtc);
1506         struct drm_crtc_state *crtc_state = crtc->state;
1507         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1508         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1509         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1510         struct drm_plane *plane;
1511         int i;
1512
1513         seq_printf(s, "VOP [%s]: %s\n", dev_name(vop->dev),
1514                    crtc_state->active ? "ACTIVE" : "DISABLED");
1515
1516         if (!crtc_state->active)
1517                 return 0;
1518
1519         seq_printf(s, "    Connector: %s\n",
1520                    drm_get_connector_name(state->output_type));
1521         seq_printf(s, "\tbus_format[%x] output_mode[%x]\n",
1522                    state->bus_format, state->output_mode);
1523         seq_printf(s, "    Display mode: %dx%d%s%d\n",
1524                    mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1525                    drm_mode_vrefresh(mode));
1526         seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1527                    mode->clock, mode->crtc_clock, mode->type, mode->flags);
1528         seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1529                    mode->hsync_end, mode->htotal);
1530         seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1531                    mode->vsync_end, mode->vtotal);
1532
1533         for (i = 0; i < vop->num_wins; i++) {
1534                 plane = &vop->win[i].base;
1535                 vop_plane_info_dump(s, plane);
1536         }
1537
1538         return 0;
1539 }
1540
1541 static enum drm_mode_status
1542 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1543                     int output_type)
1544 {
1545         struct vop *vop = to_vop(crtc);
1546         const struct vop_data *vop_data = vop->data;
1547         int request_clock = mode->clock;
1548         int clock;
1549
1550         if (mode->hdisplay > vop_data->max_output.width)
1551                 return MODE_BAD_HVALUE;
1552         if (mode->vdisplay > vop_data->max_output.height)
1553                 return MODE_BAD_VVALUE;
1554
1555         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1556                 request_clock *= 2;
1557         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1558
1559         /*
1560          * Hdmi or DisplayPort request a Accurate clock.
1561          */
1562         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1563             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1564                 if (clock != request_clock)
1565                         return MODE_CLOCK_RANGE;
1566
1567         return MODE_OK;
1568 }
1569
1570 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1571         .loader_protect = vop_crtc_loader_protect,
1572         .enable_vblank = vop_crtc_enable_vblank,
1573         .disable_vblank = vop_crtc_disable_vblank,
1574         .wait_for_update = vop_crtc_wait_for_update,
1575         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1576         .debugfs_dump = vop_crtc_debugfs_dump,
1577         .mode_valid = vop_crtc_mode_valid,
1578 };
1579
1580 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1581                                 const struct drm_display_mode *mode,
1582                                 struct drm_display_mode *adj_mode)
1583 {
1584         struct vop *vop = to_vop(crtc);
1585         const struct vop_data *vop_data = vop->data;
1586
1587         if (mode->hdisplay > vop_data->max_output.width ||
1588             mode->vdisplay > vop_data->max_output.height)
1589                 return false;
1590
1591         drm_mode_set_crtcinfo(adj_mode,
1592                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1593
1594         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1595                 adj_mode->crtc_clock *= 2;
1596
1597         adj_mode->crtc_clock =
1598                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1599
1600         return true;
1601 }
1602
1603 static void vop_crtc_enable(struct drm_crtc *crtc)
1604 {
1605         struct vop *vop = to_vop(crtc);
1606         const struct vop_data *vop_data = vop->data;
1607         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1608         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1609         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1610         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1611         u16 htotal = adjusted_mode->crtc_htotal;
1612         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1613         u16 hact_end = hact_st + hdisplay;
1614         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1615         u16 vtotal = adjusted_mode->crtc_vtotal;
1616         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1617         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1618         u16 vact_end = vact_st + vdisplay;
1619         uint32_t val;
1620
1621         mutex_lock(&vop->vop_lock);
1622         vop_initial(crtc);
1623
1624         val = BIT(DCLK_INVERT);
1625         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1626                    0 : BIT(HSYNC_POSITIVE);
1627         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1628                    0 : BIT(VSYNC_POSITIVE);
1629         VOP_CTRL_SET(vop, pin_pol, val);
1630         switch (s->output_type) {
1631         case DRM_MODE_CONNECTOR_LVDS:
1632                 VOP_CTRL_SET(vop, rgb_en, 1);
1633                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1634                 break;
1635         case DRM_MODE_CONNECTOR_eDP:
1636                 VOP_CTRL_SET(vop, edp_en, 1);
1637                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1638                 break;
1639         case DRM_MODE_CONNECTOR_HDMIA:
1640                 VOP_CTRL_SET(vop, hdmi_en, 1);
1641                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1642                 break;
1643         case DRM_MODE_CONNECTOR_DSI:
1644                 VOP_CTRL_SET(vop, mipi_en, 1);
1645                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1646                 break;
1647         case DRM_MODE_CONNECTOR_DisplayPort:
1648                 val &= ~BIT(DCLK_INVERT);
1649                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1650                 VOP_CTRL_SET(vop, dp_en, 1);
1651                 break;
1652         default:
1653                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1654         }
1655
1656         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1657             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1658                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1659
1660         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1661         switch (s->bus_format) {
1662         case MEDIA_BUS_FMT_RGB565_1X16:
1663                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1664                 break;
1665         case MEDIA_BUS_FMT_RGB666_1X18:
1666         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1667                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1668                 break;
1669         case MEDIA_BUS_FMT_YUV8_1X24:
1670                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1671                 break;
1672         case MEDIA_BUS_FMT_YUV10_1X30:
1673                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1674                 break;
1675         case MEDIA_BUS_FMT_RGB888_1X24:
1676         default:
1677                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1678                 break;
1679         }
1680
1681         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1682                 val |= PRE_DITHER_DOWN_EN(0);
1683         else
1684                 val |= PRE_DITHER_DOWN_EN(1);
1685         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1686         VOP_CTRL_SET(vop, dither_down, val);
1687         VOP_CTRL_SET(vop, dclk_ddr,
1688                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1689         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1690         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1691         VOP_CTRL_SET(vop, dsp_background,
1692                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1693
1694         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1695         val = hact_st << 16;
1696         val |= hact_end;
1697         VOP_CTRL_SET(vop, hact_st_end, val);
1698         VOP_CTRL_SET(vop, hpost_st_end, val);
1699
1700         val = vact_st << 16;
1701         val |= vact_end;
1702         VOP_CTRL_SET(vop, vact_st_end, val);
1703         VOP_CTRL_SET(vop, vpost_st_end, val);
1704         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1705                 u16 vact_st_f1 = vtotal + vact_st + 1;
1706                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1707
1708                 val = vact_st_f1 << 16 | vact_end_f1;
1709                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1710                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1711
1712                 val = vtotal << 16 | (vtotal + vsync_len);
1713                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1714                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1715                 VOP_CTRL_SET(vop, p2i_en, 1);
1716                 vtotal += vtotal + 1;
1717         } else {
1718                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1719                 VOP_CTRL_SET(vop, p2i_en, 0);
1720         }
1721         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1722
1723         VOP_CTRL_SET(vop, core_dclk_div,
1724                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1725
1726         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1727
1728         vop_cfg_done(vop);
1729         /*
1730          * enable vop, all the register would take effect when vop exit standby
1731          */
1732         VOP_CTRL_SET(vop, standby, 0);
1733
1734         enable_irq(vop->irq);
1735         drm_crtc_vblank_on(crtc);
1736         mutex_unlock(&vop->vop_lock);
1737 }
1738
1739 static int vop_zpos_cmp(const void *a, const void *b)
1740 {
1741         struct vop_zpos *pa = (struct vop_zpos *)a;
1742         struct vop_zpos *pb = (struct vop_zpos *)b;
1743
1744         return pa->zpos - pb->zpos;
1745 }
1746
1747 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1748                                   struct drm_crtc_state *crtc_state)
1749 {
1750         struct vop *vop = to_vop(crtc);
1751         const struct vop_data *vop_data = vop->data;
1752         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1753         struct drm_atomic_state *state = crtc_state->state;
1754         struct drm_plane *plane;
1755         struct drm_plane_state *pstate;
1756         struct vop_plane_state *plane_state;
1757         struct vop_win *win;
1758         int afbdc_format;
1759         int i;
1760
1761         s->afbdc_en = 0;
1762
1763         for_each_plane_in_state(state, plane, pstate, i) {
1764                 struct drm_framebuffer *fb = pstate->fb;
1765                 struct drm_rect *src;
1766
1767                 win = to_vop_win(plane);
1768                 plane_state = to_vop_plane_state(pstate);
1769
1770                 if (pstate->crtc != crtc || !fb)
1771                         continue;
1772
1773                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1774                         continue;
1775
1776                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1777                         DRM_ERROR("not support afbdc\n");
1778                         return -EINVAL;
1779                 }
1780
1781                 switch (plane_state->format) {
1782                 case VOP_FMT_ARGB8888:
1783                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1784                         break;
1785                 case VOP_FMT_RGB888:
1786                         afbdc_format = AFBDC_FMT_U8U8U8;
1787                         break;
1788                 case VOP_FMT_RGB565:
1789                         afbdc_format = AFBDC_FMT_RGB565;
1790                         break;
1791                 default:
1792                         return -EINVAL;
1793                 }
1794
1795                 if (s->afbdc_en) {
1796                         DRM_ERROR("vop only support one afbc layer\n");
1797                         return -EINVAL;
1798                 }
1799
1800                 src = &plane_state->src;
1801                 if (src->x1 || src->y1 || fb->offsets[0]) {
1802                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1803                                   win->win_id);
1804                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1805                                   src->x1, src->y1, fb->offsets[0]);
1806                         return -EINVAL;
1807                 }
1808                 s->afbdc_win_format = afbdc_format;
1809                 s->afbdc_win_width = pstate->fb->width - 1;
1810                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1811                 s->afbdc_win_id = win->win_id;
1812                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1813                 s->afbdc_en = 1;
1814         }
1815
1816         return 0;
1817 }
1818
1819 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1820                                  struct drm_crtc_state *crtc_state)
1821 {
1822         struct drm_atomic_state *state = crtc_state->state;
1823         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1824         struct vop *vop = to_vop(crtc);
1825         const struct vop_data *vop_data = vop->data;
1826         struct drm_plane *plane;
1827         struct drm_plane_state *pstate;
1828         struct vop_plane_state *plane_state;
1829         struct vop_zpos *pzpos;
1830         int dsp_layer_sel = 0;
1831         int i, j, cnt = 0, ret = 0;
1832
1833         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1834         if (ret)
1835                 return ret;
1836
1837         ret = vop_csc_atomic_check(crtc, crtc_state);
1838         if (ret)
1839                 return ret;
1840
1841         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1842         if (!pzpos)
1843                 return -ENOMEM;
1844
1845         for (i = 0; i < vop_data->win_size; i++) {
1846                 const struct vop_win_data *win_data = &vop_data->win[i];
1847                 struct vop_win *win;
1848
1849                 if (!win_data->phy)
1850                         continue;
1851
1852                 for (j = 0; j < vop->num_wins; j++) {
1853                         win = &vop->win[j];
1854
1855                         if (win->win_id == i && !win->area_id)
1856                                 break;
1857                 }
1858                 if (WARN_ON(j >= vop->num_wins)) {
1859                         ret = -EINVAL;
1860                         goto err_free_pzpos;
1861                 }
1862
1863                 plane = &win->base;
1864                 pstate = state->plane_states[drm_plane_index(plane)];
1865                 /*
1866                  * plane might not have changed, in which case take
1867                  * current state:
1868                  */
1869                 if (!pstate)
1870                         pstate = plane->state;
1871                 plane_state = to_vop_plane_state(pstate);
1872                 pzpos[cnt].zpos = plane_state->zpos;
1873                 pzpos[cnt++].win_id = win->win_id;
1874         }
1875
1876         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1877
1878         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1879                 const struct vop_win_data *win_data = &vop_data->win[i];
1880                 int shift = i * 2;
1881
1882                 if (win_data->phy) {
1883                         struct vop_zpos *zpos = &pzpos[cnt++];
1884
1885                         dsp_layer_sel |= zpos->win_id << shift;
1886                 } else {
1887                         dsp_layer_sel |= i << shift;
1888                 }
1889         }
1890
1891         s->dsp_layer_sel = dsp_layer_sel;
1892
1893 err_free_pzpos:
1894         kfree(pzpos);
1895         return ret;
1896 }
1897
1898 static void vop_post_config(struct drm_crtc *crtc)
1899 {
1900         struct vop *vop = to_vop(crtc);
1901         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1902         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1903         u16 vtotal = mode->crtc_vtotal;
1904         u16 hdisplay = mode->crtc_hdisplay;
1905         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1906         u16 vdisplay = mode->crtc_vdisplay;
1907         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1908         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1909         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1910         u16 hact_end, vact_end;
1911         u32 val;
1912
1913         hact_st += hdisplay * (100 - s->left_margin) / 200;
1914         hact_end = hact_st + hsize;
1915         val = hact_st << 16;
1916         val |= hact_end;
1917         VOP_CTRL_SET(vop, hpost_st_end, val);
1918         vact_st += vdisplay * (100 - s->top_margin) / 200;
1919         vact_end = vact_st + vsize;
1920         val = vact_st << 16;
1921         val |= vact_end;
1922         VOP_CTRL_SET(vop, vpost_st_end, val);
1923         val = scl_cal_scale2(vdisplay, vsize) << 16;
1924         val |= scl_cal_scale2(hdisplay, hsize);
1925         VOP_CTRL_SET(vop, post_scl_factor, val);
1926         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1927         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1928                 u16 vact_st_f1 = vtotal + vact_st + 1;
1929                 u16 vact_end_f1 = vact_st_f1 + vsize;
1930
1931                 val = vact_st_f1 << 16 | vact_end_f1;
1932                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1933         }
1934 }
1935
1936 static void vop_cfg_update(struct drm_crtc *crtc,
1937                            struct drm_crtc_state *old_crtc_state)
1938 {
1939         struct rockchip_crtc_state *s =
1940                         to_rockchip_crtc_state(crtc->state);
1941         struct vop *vop = to_vop(crtc);
1942
1943         spin_lock(&vop->reg_lock);
1944
1945         if (s->afbdc_en) {
1946                 uint32_t pic_size;
1947
1948                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1949                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1950                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1951                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1952                 pic_size = (s->afbdc_win_width & 0xffff);
1953                 pic_size |= s->afbdc_win_height << 16;
1954                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1955         }
1956
1957         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1958         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1959         vop_post_config(crtc);
1960
1961         spin_unlock(&vop->reg_lock);
1962 }
1963
1964 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1965                                   struct drm_crtc_state *old_crtc_state)
1966 {
1967         struct vop *vop = to_vop(crtc);
1968
1969         vop_cfg_update(crtc, old_crtc_state);
1970
1971         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1972                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1973                 int ret;
1974
1975                 if (need_wait_vblank) {
1976                         bool active;
1977
1978                         disable_irq(vop->irq);
1979                         drm_crtc_vblank_get(crtc);
1980                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1981
1982                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1983                                                         vop, active, active,
1984                                                         0, 50 * 1000);
1985                         if (ret)
1986                                 dev_err(vop->dev, "wait fs irq timeout\n");
1987
1988                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1989                         vop_cfg_done(vop);
1990
1991                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1992                                                         vop, active, active,
1993                                                         0, 50 * 1000);
1994                         if (ret)
1995                                 dev_err(vop->dev, "wait line flag timeout\n");
1996
1997                         enable_irq(vop->irq);
1998                 }
1999                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2000                 if (ret)
2001                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2002                                 ret);
2003
2004                 if (need_wait_vblank) {
2005                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2006                         drm_crtc_vblank_put(crtc);
2007                 }
2008
2009                 vop->is_iommu_enabled = true;
2010         }
2011
2012         vop_cfg_done(vop);
2013 }
2014
2015 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2016                                   struct drm_crtc_state *old_crtc_state)
2017 {
2018         struct vop *vop = to_vop(crtc);
2019
2020         if (crtc->state->event) {
2021                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2022
2023                 vop->event = crtc->state->event;
2024                 crtc->state->event = NULL;
2025         }
2026 }
2027
2028 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2029         .load_lut = vop_crtc_load_lut,
2030         .enable = vop_crtc_enable,
2031         .disable = vop_crtc_disable,
2032         .mode_fixup = vop_crtc_mode_fixup,
2033         .atomic_check = vop_crtc_atomic_check,
2034         .atomic_flush = vop_crtc_atomic_flush,
2035         .atomic_begin = vop_crtc_atomic_begin,
2036 };
2037
2038 static void vop_crtc_destroy(struct drm_crtc *crtc)
2039 {
2040         drm_crtc_cleanup(crtc);
2041 }
2042
2043 static void vop_crtc_reset(struct drm_crtc *crtc)
2044 {
2045         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2046
2047         if (crtc->state) {
2048                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2049                 kfree(s);
2050         }
2051
2052         s = kzalloc(sizeof(*s), GFP_KERNEL);
2053         if (!s)
2054                 return;
2055         crtc->state = &s->base;
2056         crtc->state->crtc = crtc;
2057         s->left_margin = 100;
2058         s->right_margin = 100;
2059         s->top_margin = 100;
2060         s->bottom_margin = 100;
2061 }
2062
2063 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2064 {
2065         struct rockchip_crtc_state *rockchip_state, *old_state;
2066
2067         old_state = to_rockchip_crtc_state(crtc->state);
2068         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2069         if (!rockchip_state)
2070                 return NULL;
2071
2072         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2073         return &rockchip_state->base;
2074 }
2075
2076 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2077                                    struct drm_crtc_state *state)
2078 {
2079         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2080
2081         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2082         kfree(s);
2083 }
2084
2085 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2086                                         const struct drm_crtc_state *state,
2087                                         struct drm_property *property,
2088                                         uint64_t *val)
2089 {
2090         struct drm_device *drm_dev = crtc->dev;
2091         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2092         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2093
2094         if (property == mode_config->tv_left_margin_property) {
2095                 *val = s->left_margin;
2096                 return 0;
2097         }
2098
2099         if (property == mode_config->tv_right_margin_property) {
2100                 *val = s->right_margin;
2101                 return 0;
2102         }
2103
2104         if (property == mode_config->tv_top_margin_property) {
2105                 *val = s->top_margin;
2106                 return 0;
2107         }
2108
2109         if (property == mode_config->tv_bottom_margin_property) {
2110                 *val = s->bottom_margin;
2111                 return 0;
2112         }
2113
2114         DRM_ERROR("failed to get vop crtc property\n");
2115         return -EINVAL;
2116 }
2117
2118 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2119                                         struct drm_crtc_state *state,
2120                                         struct drm_property *property,
2121                                         uint64_t val)
2122 {
2123         struct drm_device *drm_dev = crtc->dev;
2124         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2125         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2126
2127         if (property == mode_config->tv_left_margin_property) {
2128                 s->left_margin = val;
2129                 return 0;
2130         }
2131
2132         if (property == mode_config->tv_right_margin_property) {
2133                 s->right_margin = val;
2134                 return 0;
2135         }
2136
2137         if (property == mode_config->tv_top_margin_property) {
2138                 s->top_margin = val;
2139                 return 0;
2140         }
2141
2142         if (property == mode_config->tv_bottom_margin_property) {
2143                 s->bottom_margin = val;
2144                 return 0;
2145         }
2146
2147         DRM_ERROR("failed to set vop crtc property\n");
2148         return -EINVAL;
2149 }
2150
2151 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2152                                u16 *blue, uint32_t start, uint32_t size)
2153 {
2154         struct vop *vop = to_vop(crtc);
2155         int end = min_t(u32, start + size, vop->lut_len);
2156         int i;
2157
2158         if (!vop->lut)
2159                 return;
2160
2161         for (i = start; i < end; i++)
2162                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2163                                                blue[i], i);
2164
2165         vop_crtc_load_lut(crtc);
2166 }
2167
2168 static const struct drm_crtc_funcs vop_crtc_funcs = {
2169         .gamma_set = vop_crtc_gamma_set,
2170         .set_config = drm_atomic_helper_set_config,
2171         .page_flip = drm_atomic_helper_page_flip,
2172         .destroy = vop_crtc_destroy,
2173         .reset = vop_crtc_reset,
2174         .atomic_get_property = vop_crtc_atomic_get_property,
2175         .atomic_set_property = vop_crtc_atomic_set_property,
2176         .atomic_duplicate_state = vop_crtc_duplicate_state,
2177         .atomic_destroy_state = vop_crtc_destroy_state,
2178 };
2179
2180 static void vop_handle_vblank(struct vop *vop)
2181 {
2182         struct drm_device *drm = vop->drm_dev;
2183         struct drm_crtc *crtc = &vop->crtc;
2184         unsigned long flags;
2185
2186         if (!vop_is_cfg_done_complete(vop))
2187                 return;
2188
2189         if (vop->event) {
2190                 spin_lock_irqsave(&drm->event_lock, flags);
2191
2192                 drm_crtc_send_vblank_event(crtc, vop->event);
2193                 drm_crtc_vblank_put(crtc);
2194                 vop->event = NULL;
2195
2196                 spin_unlock_irqrestore(&drm->event_lock, flags);
2197         }
2198         if (!completion_done(&vop->wait_update_complete))
2199                 complete(&vop->wait_update_complete);
2200 }
2201
2202 static irqreturn_t vop_isr(int irq, void *data)
2203 {
2204         struct vop *vop = data;
2205         struct drm_crtc *crtc = &vop->crtc;
2206         uint32_t active_irqs;
2207         unsigned long flags;
2208         int ret = IRQ_NONE;
2209
2210         /*
2211          * interrupt register has interrupt status, enable and clear bits, we
2212          * must hold irq_lock to avoid a race with enable/disable_vblank().
2213         */
2214         spin_lock_irqsave(&vop->irq_lock, flags);
2215
2216         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2217         /* Clear all active interrupt sources */
2218         if (active_irqs)
2219                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2220
2221         spin_unlock_irqrestore(&vop->irq_lock, flags);
2222
2223         /* This is expected for vop iommu irqs, since the irq is shared */
2224         if (!active_irqs)
2225                 return IRQ_NONE;
2226
2227         if (active_irqs & DSP_HOLD_VALID_INTR) {
2228                 complete(&vop->dsp_hold_completion);
2229                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2230                 ret = IRQ_HANDLED;
2231         }
2232
2233         if (active_irqs & LINE_FLAG_INTR) {
2234                 complete(&vop->line_flag_completion);
2235                 active_irqs &= ~LINE_FLAG_INTR;
2236                 ret = IRQ_HANDLED;
2237         }
2238
2239         if (active_irqs & FS_INTR) {
2240                 drm_crtc_handle_vblank(crtc);
2241                 vop_handle_vblank(vop);
2242                 active_irqs &= ~FS_INTR;
2243                 ret = IRQ_HANDLED;
2244         }
2245
2246         /* Unhandled irqs are spurious. */
2247         if (active_irqs)
2248                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2249
2250         return ret;
2251 }
2252
2253 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2254                           unsigned long possible_crtcs)
2255 {
2256         struct drm_plane *share = NULL;
2257         unsigned int rotations = 0;
2258         struct drm_property *prop;
2259         uint64_t feature = 0;
2260         int ret;
2261
2262         if (win->parent)
2263                 share = &win->parent->base;
2264
2265         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2266                                    possible_crtcs, &vop_plane_funcs,
2267                                    win->data_formats, win->nformats, win->type);
2268         if (ret) {
2269                 DRM_ERROR("failed to initialize plane\n");
2270                 return ret;
2271         }
2272         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2273         drm_object_attach_property(&win->base.base,
2274                                    vop->plane_zpos_prop, win->win_id);
2275
2276         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2277                 rotations |= BIT(DRM_REFLECT_X);
2278
2279         if (VOP_WIN_SUPPORT(vop, win, ymirror))
2280                 rotations |= BIT(DRM_REFLECT_Y);
2281
2282         if (rotations) {
2283                 rotations |= BIT(DRM_ROTATE_0);
2284                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2285                                                          rotations);
2286                 if (!prop) {
2287                         DRM_ERROR("failed to create zpos property\n");
2288                         return -EINVAL;
2289                 }
2290                 drm_object_attach_property(&win->base.base, prop,
2291                                            BIT(DRM_ROTATE_0));
2292                 win->rotation_prop = prop;
2293         }
2294         if (win->phy->scl)
2295                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2296         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2297             VOP_WIN_SUPPORT(vop, win, alpha_en))
2298                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2299
2300         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2301                                    feature);
2302
2303         return 0;
2304 }
2305
2306 static int vop_create_crtc(struct vop *vop)
2307 {
2308         struct device *dev = vop->dev;
2309         const struct vop_data *vop_data = vop->data;
2310         struct drm_device *drm_dev = vop->drm_dev;
2311         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2312         struct drm_crtc *crtc = &vop->crtc;
2313         struct device_node *port;
2314         uint64_t feature = 0;
2315         int ret;
2316         int i;
2317
2318         /*
2319          * Create drm_plane for primary and cursor planes first, since we need
2320          * to pass them to drm_crtc_init_with_planes, which sets the
2321          * "possible_crtcs" to the newly initialized crtc.
2322          */
2323         for (i = 0; i < vop->num_wins; i++) {
2324                 struct vop_win *win = &vop->win[i];
2325
2326                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2327                     win->type != DRM_PLANE_TYPE_CURSOR)
2328                         continue;
2329
2330                 ret = vop_plane_init(vop, win, 0);
2331                 if (ret)
2332                         goto err_cleanup_planes;
2333
2334                 plane = &win->base;
2335                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2336                         primary = plane;
2337                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2338                         cursor = plane;
2339
2340         }
2341
2342         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2343                                         &vop_crtc_funcs, NULL);
2344         if (ret)
2345                 goto err_cleanup_planes;
2346
2347         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2348
2349         /*
2350          * Create drm_planes for overlay windows with possible_crtcs restricted
2351          * to the newly created crtc.
2352          */
2353         for (i = 0; i < vop->num_wins; i++) {
2354                 struct vop_win *win = &vop->win[i];
2355                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2356
2357                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2358                         continue;
2359
2360                 ret = vop_plane_init(vop, win, possible_crtcs);
2361                 if (ret)
2362                         goto err_cleanup_crtc;
2363         }
2364
2365         port = of_get_child_by_name(dev->of_node, "port");
2366         if (!port) {
2367                 DRM_ERROR("no port node found in %s\n",
2368                           dev->of_node->full_name);
2369                 ret = -ENOENT;
2370                 goto err_cleanup_crtc;
2371         }
2372
2373         init_completion(&vop->dsp_hold_completion);
2374         init_completion(&vop->wait_update_complete);
2375         init_completion(&vop->line_flag_completion);
2376         crtc->port = port;
2377         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2378
2379         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2380         if (ret)
2381                 goto err_unregister_crtc_funcs;
2382 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2383         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2384
2385         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2386         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2387         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2388         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2389 #undef VOP_ATTACH_MODE_CONFIG_PROP
2390
2391         if (vop_data->feature & VOP_FEATURE_AFBDC)
2392                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2393         drm_object_attach_property(&crtc->base, vop->feature_prop,
2394                                    feature);
2395         if (vop->lut_regs) {
2396                 u16 *r_base, *g_base, *b_base;
2397                 u32 lut_len = vop->lut_len;
2398
2399                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2400                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2401                                               GFP_KERNEL);
2402                 if (!vop->lut)
2403                         return -ENOMEM;
2404
2405                 r_base = crtc->gamma_store;
2406                 g_base = r_base + crtc->gamma_size;
2407                 b_base = g_base + crtc->gamma_size;
2408
2409                 for (i = 0; i < lut_len; i++) {
2410                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2411                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2412                                                        &g_base[i], &b_base[i],
2413                                                        i);
2414                 }
2415         }
2416
2417         return 0;
2418
2419 err_unregister_crtc_funcs:
2420         rockchip_unregister_crtc_funcs(crtc);
2421 err_cleanup_crtc:
2422         drm_crtc_cleanup(crtc);
2423 err_cleanup_planes:
2424         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2425                                  head)
2426                 drm_plane_cleanup(plane);
2427         return ret;
2428 }
2429
2430 static void vop_destroy_crtc(struct vop *vop)
2431 {
2432         struct drm_crtc *crtc = &vop->crtc;
2433         struct drm_device *drm_dev = vop->drm_dev;
2434         struct drm_plane *plane, *tmp;
2435
2436         rockchip_unregister_crtc_funcs(crtc);
2437         of_node_put(crtc->port);
2438
2439         /*
2440          * We need to cleanup the planes now.  Why?
2441          *
2442          * The planes are "&vop->win[i].base".  That means the memory is
2443          * all part of the big "struct vop" chunk of memory.  That memory
2444          * was devm allocated and associated with this component.  We need to
2445          * free it ourselves before vop_unbind() finishes.
2446          */
2447         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2448                                  head)
2449                 vop_plane_destroy(plane);
2450
2451         /*
2452          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2453          * references the CRTC.
2454          */
2455         drm_crtc_cleanup(crtc);
2456 }
2457
2458 /*
2459  * Initialize the vop->win array elements.
2460  */
2461 static int vop_win_init(struct vop *vop)
2462 {
2463         const struct vop_data *vop_data = vop->data;
2464         unsigned int i, j;
2465         unsigned int num_wins = 0;
2466         struct drm_property *prop;
2467         static const struct drm_prop_enum_list props[] = {
2468                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2469                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2470         };
2471         static const struct drm_prop_enum_list crtc_props[] = {
2472                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2473         };
2474
2475         for (i = 0; i < vop_data->win_size; i++) {
2476                 struct vop_win *vop_win = &vop->win[num_wins];
2477                 const struct vop_win_data *win_data = &vop_data->win[i];
2478
2479                 if (!win_data->phy)
2480                         continue;
2481
2482                 vop_win->phy = win_data->phy;
2483                 vop_win->csc = win_data->csc;
2484                 vop_win->offset = win_data->base;
2485                 vop_win->type = win_data->type;
2486                 vop_win->data_formats = win_data->phy->data_formats;
2487                 vop_win->nformats = win_data->phy->nformats;
2488                 vop_win->vop = vop;
2489                 vop_win->win_id = i;
2490                 vop_win->area_id = 0;
2491                 num_wins++;
2492
2493                 for (j = 0; j < win_data->area_size; j++) {
2494                         struct vop_win *vop_area = &vop->win[num_wins];
2495                         const struct vop_win_phy *area = win_data->area[j];
2496
2497                         vop_area->parent = vop_win;
2498                         vop_area->offset = vop_win->offset;
2499                         vop_area->phy = area;
2500                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2501                         vop_area->data_formats = vop_win->data_formats;
2502                         vop_area->nformats = vop_win->nformats;
2503                         vop_area->vop = vop;
2504                         vop_area->win_id = i;
2505                         vop_area->area_id = j;
2506                         num_wins++;
2507                 }
2508         }
2509
2510         vop->num_wins = num_wins;
2511
2512         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2513                                          "ZPOS", 0, vop->data->win_size);
2514         if (!prop) {
2515                 DRM_ERROR("failed to create zpos property\n");
2516                 return -EINVAL;
2517         }
2518         vop->plane_zpos_prop = prop;
2519
2520         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2521                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2522                                 props, ARRAY_SIZE(props),
2523                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2524                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2525         if (!vop->plane_feature_prop) {
2526                 DRM_ERROR("failed to create feature property\n");
2527                 return -EINVAL;
2528         }
2529
2530         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2531                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2532                                 crtc_props, ARRAY_SIZE(crtc_props),
2533                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2534         if (!vop->feature_prop) {
2535                 DRM_ERROR("failed to create vop feature property\n");
2536                 return -EINVAL;
2537         }
2538
2539         return 0;
2540 }
2541
2542 /**
2543  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2544  * @crtc: CRTC to enable line flag
2545  * @line_num: interested line number
2546  * @mstimeout: millisecond for timeout
2547  *
2548  * Driver would hold here until the interested line flag interrupt have
2549  * happened or timeout to wait.
2550  *
2551  * Returns:
2552  * Zero on success, negative errno on failure.
2553  */
2554 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2555                                 unsigned int mstimeout)
2556 {
2557         struct vop *vop = to_vop(crtc);
2558         unsigned long jiffies_left;
2559         int ret = 0;
2560
2561         if (!crtc || !vop->is_enabled)
2562                 return -ENODEV;
2563
2564         mutex_lock(&vop->vop_lock);
2565
2566         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2567                 ret = -EINVAL;
2568                 goto out;
2569         }
2570
2571         if (vop_line_flag_irq_is_enabled(vop)) {
2572                 ret = -EBUSY;
2573                 goto out;
2574         }
2575
2576         reinit_completion(&vop->line_flag_completion);
2577         vop_line_flag_irq_enable(vop, line_num);
2578
2579         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2580                                                    msecs_to_jiffies(mstimeout));
2581         vop_line_flag_irq_disable(vop);
2582
2583         if (jiffies_left == 0) {
2584                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2585                 ret = -ETIMEDOUT;
2586                 goto out;
2587         }
2588
2589 out:
2590         mutex_unlock(&vop->vop_lock);
2591
2592         return ret;
2593 }
2594 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2595
2596 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
2597                              void *data)
2598 {
2599         if (event == DEVFREQ_PRECHANGE)
2600                 mutex_lock(&dmc_vop->vop_lock);
2601         else if (event == DEVFREQ_POSTCHANGE)
2602                 mutex_unlock(&dmc_vop->vop_lock);
2603
2604         return NOTIFY_OK;
2605 }
2606
2607 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
2608 {
2609         if (!dmc_vop)
2610                 return -ENOMEM;
2611
2612         dmc_vop->devfreq = devfreq;
2613         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
2614         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
2615                                   DEVFREQ_TRANSITION_NOTIFIER);
2616         return 0;
2617 }
2618 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
2619
2620 static int vop_bind(struct device *dev, struct device *master, void *data)
2621 {
2622         struct platform_device *pdev = to_platform_device(dev);
2623         const struct vop_data *vop_data;
2624         struct drm_device *drm_dev = data;
2625         struct vop *vop;
2626         struct resource *res;
2627         size_t alloc_size;
2628         int ret, irq, i;
2629         int num_wins = 0;
2630
2631         vop_data = of_device_get_match_data(dev);
2632         if (!vop_data)
2633                 return -ENODEV;
2634
2635         for (i = 0; i < vop_data->win_size; i++) {
2636                 const struct vop_win_data *win_data = &vop_data->win[i];
2637
2638                 num_wins += win_data->area_size + 1;
2639         }
2640
2641         /* Allocate vop struct and its vop_win array */
2642         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2643         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2644         if (!vop)
2645                 return -ENOMEM;
2646
2647         vop->dev = dev;
2648         vop->data = vop_data;
2649         vop->drm_dev = drm_dev;
2650         vop->num_wins = num_wins;
2651         dev_set_drvdata(dev, vop);
2652
2653         ret = vop_win_init(vop);
2654         if (ret)
2655                 return ret;
2656
2657         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2658         vop->len = resource_size(res);
2659         vop->regs = devm_ioremap_resource(dev, res);
2660         if (IS_ERR(vop->regs))
2661                 return PTR_ERR(vop->regs);
2662
2663         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2664         if (!vop->regsbak)
2665                 return -ENOMEM;
2666
2667         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2668         vop->lut_regs = devm_ioremap_resource(dev, res);
2669         if (IS_ERR(vop->lut_regs)) {
2670                 dev_warn(vop->dev, "failed to get vop lut registers\n");
2671                 vop->lut_regs = NULL;
2672         }
2673         if (vop->lut_regs) {
2674                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
2675                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
2676                         dev_err(vop->dev, "unsupport lut sizes %d\n",
2677                                 vop->lut_len);
2678                         return -EINVAL;
2679                 }
2680         }
2681
2682         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2683         if (IS_ERR(vop->hclk)) {
2684                 dev_err(vop->dev, "failed to get hclk source\n");
2685                 return PTR_ERR(vop->hclk);
2686         }
2687         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2688         if (IS_ERR(vop->aclk)) {
2689                 dev_err(vop->dev, "failed to get aclk source\n");
2690                 return PTR_ERR(vop->aclk);
2691         }
2692         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2693         if (IS_ERR(vop->dclk)) {
2694                 dev_err(vop->dev, "failed to get dclk source\n");
2695                 return PTR_ERR(vop->dclk);
2696         }
2697
2698         irq = platform_get_irq(pdev, 0);
2699         if (irq < 0) {
2700                 dev_err(dev, "cannot find irq for vop\n");
2701                 return irq;
2702         }
2703         vop->irq = (unsigned int)irq;
2704
2705         spin_lock_init(&vop->reg_lock);
2706         spin_lock_init(&vop->irq_lock);
2707         mutex_init(&vop->vop_lock);
2708
2709         mutex_init(&vop->vsync_mutex);
2710
2711         ret = devm_request_irq(dev, vop->irq, vop_isr,
2712                                IRQF_SHARED, dev_name(dev), vop);
2713         if (ret)
2714                 return ret;
2715
2716         /* IRQ is initially disabled; it gets enabled in power_on */
2717         disable_irq(vop->irq);
2718
2719         ret = vop_create_crtc(vop);
2720         if (ret)
2721                 return ret;
2722
2723         pm_runtime_enable(&pdev->dev);
2724
2725         dmc_vop = vop;
2726
2727         return 0;
2728 }
2729
2730 static void vop_unbind(struct device *dev, struct device *master, void *data)
2731 {
2732         struct vop *vop = dev_get_drvdata(dev);
2733
2734         pm_runtime_disable(dev);
2735         vop_destroy_crtc(vop);
2736 }
2737
2738 const struct component_ops vop_component_ops = {
2739         .bind = vop_bind,
2740         .unbind = vop_unbind,
2741 };
2742 EXPORT_SYMBOL_GPL(vop_component_ops);