2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/iopoll.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
28 #include <linux/of_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/component.h>
32 #include <linux/reset.h>
33 #include <linux/delay.h>
34 #include <linux/sort.h>
35 #include <uapi/drm/rockchip_drm.h>
37 #include "rockchip_drm_drv.h"
38 #include "rockchip_drm_gem.h"
39 #include "rockchip_drm_fb.h"
40 #include "rockchip_drm_vop.h"
42 #define VOP_REG_SUPPORT(vop, reg) \
43 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
44 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
45 reg.end_minor >= VOP_MINOR(vop->data->version) && \
48 #define VOP_WIN_SUPPORT(vop, win, name) \
49 VOP_REG_SUPPORT(vop, win->phy->name)
51 #define VOP_CTRL_SUPPORT(vop, name) \
52 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
54 #define VOP_INTR_SUPPORT(vop, name) \
55 VOP_REG_SUPPORT(vop, vop->data->intr->name)
57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
58 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
62 if (VOP_REG_SUPPORT(vop, reg)) \
63 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
64 v, reg.write_mask, relaxed); \
66 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
69 #define REG_SET(x, name, off, reg, v, relaxed) \
70 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
72 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
74 #define VOP_WIN_SET(x, win, name, v) \
75 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
77 REG_SET(x, name, 0, win->ext->name, v, true)
78 #define VOP_SCL_SET(x, win, name, v) \
79 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
80 #define VOP_SCL_SET_EXT(x, win, name, v) \
81 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
83 #define VOP_CTRL_SET(x, name, v) \
84 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
86 #define VOP_INTR_GET(vop, name) \
87 vop_read_reg(vop, 0, &vop->data->ctrl->name)
89 #define VOP_INTR_SET(vop, name, v) \
90 REG_SET(vop, name, 0, vop->data->intr->name, \
92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
93 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
98 int i, reg = 0, mask = 0; \
99 for (i = 0; i < vop->data->intr->nintrs; i++) { \
100 if (vop->data->intr->intrs[i] & type) { \
105 VOP_INTR_SET_MASK(vop, name, mask, reg); \
107 #define VOP_INTR_GET_TYPE(vop, name, type) \
108 vop_get_intr_type(vop, &vop->data->intr->name, type)
110 #define VOP_CTRL_GET(x, name) \
111 vop_read_reg(x, 0, &vop->data->ctrl->name)
113 #define VOP_WIN_GET(x, win, name) \
114 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
116 #define VOP_WIN_NAME(win, name) \
117 (vop_get_win_phy(win, &win->phy->name)->name)
119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
120 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
122 #define to_vop(x) container_of(x, struct vop, crtc)
123 #define to_vop_win(x) container_of(x, struct vop_win, base)
124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
131 struct vop_plane_state {
132 struct drm_plane_state base;
136 struct drm_rect dest;
139 const uint32_t *y2r_table;
140 const uint32_t *r2r_table;
141 const uint32_t *r2y_table;
146 struct vop_win *parent;
147 struct drm_plane base;
152 enum drm_plane_type type;
153 const struct vop_win_phy *phy;
154 const struct vop_csc *csc;
155 const uint32_t *data_formats;
159 struct drm_property *rotation_prop;
160 struct vop_plane_state state;
164 struct drm_crtc crtc;
166 struct drm_device *drm_dev;
167 struct drm_property *plane_zpos_prop;
168 struct drm_property *plane_feature_prop;
169 struct drm_property *feature_prop;
170 bool is_iommu_enabled;
171 bool is_iommu_needed;
174 /* mutex vsync_ work */
175 struct mutex vsync_mutex;
176 bool vsync_work_pending;
178 struct completion dsp_hold_completion;
179 struct completion wait_update_complete;
180 struct drm_pending_vblank_event *event;
182 struct completion line_flag_completion;
184 const struct vop_data *data;
190 /* physical map length of vop register */
193 /* one time only one process allowed to config the register */
195 /* lock vop irq reg */
204 /* vop share memory frequency */
208 struct reset_control *dclk_rst;
210 struct vop_win win[];
213 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
215 writel(v, vop->regs + offset);
216 vop->regsbak[offset >> 2] = v;
219 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
221 return readl(vop->regs + offset);
224 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
225 const struct vop_reg *reg)
227 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
230 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
231 uint32_t mask, uint32_t shift, uint32_t v,
232 bool write_mask, bool relaxed)
238 v = ((v & mask) << shift) | (mask << (shift + 16));
240 uint32_t cached_val = vop->regsbak[offset >> 2];
242 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
243 vop->regsbak[offset >> 2] = v;
247 writel_relaxed(v, vop->regs + offset);
249 writel(v, vop->regs + offset);
252 static inline const struct vop_win_phy *
253 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
255 if (!reg->mask && win->parent)
256 return win->parent->phy;
261 static inline uint32_t vop_get_intr_type(struct vop *vop,
262 const struct vop_reg *reg, int type)
265 uint32_t regs = vop_read_reg(vop, 0, reg);
267 for (i = 0; i < vop->data->intr->nintrs; i++) {
268 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
269 ret |= vop->data->intr->intrs[i];
275 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
282 for (i = 0; i < 8; i++)
283 vop_writel(vop, offset + i * 4, table[i]);
286 static inline void vop_cfg_done(struct vop *vop)
288 VOP_CTRL_SET(vop, cfg_done, 1);
291 static bool vop_is_allwin_disabled(struct vop *vop)
295 for (i = 0; i < vop->num_wins; i++) {
296 struct vop_win *win = &vop->win[i];
298 if (VOP_WIN_GET(vop, win, enable) != 0)
305 static bool vop_is_cfg_done_complete(struct vop *vop)
307 return VOP_CTRL_GET(vop, cfg_done) ? false : true;
310 static bool vop_fs_irq_is_active(struct vop *vop)
312 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
315 static bool vop_line_flag_is_active(struct vop *vop)
317 return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
320 static bool has_rb_swapped(uint32_t format)
323 case DRM_FORMAT_XBGR8888:
324 case DRM_FORMAT_ABGR8888:
325 case DRM_FORMAT_BGR888:
326 case DRM_FORMAT_BGR565:
333 static enum vop_data_format vop_convert_format(uint32_t format)
336 case DRM_FORMAT_XRGB8888:
337 case DRM_FORMAT_ARGB8888:
338 case DRM_FORMAT_XBGR8888:
339 case DRM_FORMAT_ABGR8888:
340 return VOP_FMT_ARGB8888;
341 case DRM_FORMAT_RGB888:
342 case DRM_FORMAT_BGR888:
343 return VOP_FMT_RGB888;
344 case DRM_FORMAT_RGB565:
345 case DRM_FORMAT_BGR565:
346 return VOP_FMT_RGB565;
347 case DRM_FORMAT_NV12:
348 case DRM_FORMAT_NV12_10:
349 return VOP_FMT_YUV420SP;
350 case DRM_FORMAT_NV16:
351 case DRM_FORMAT_NV16_10:
352 return VOP_FMT_YUV422SP;
353 case DRM_FORMAT_NV24:
354 case DRM_FORMAT_NV24_10:
355 return VOP_FMT_YUV444SP;
357 DRM_ERROR("unsupport format[%08x]\n", format);
362 static bool is_yuv_support(uint32_t format)
365 case DRM_FORMAT_NV12:
366 case DRM_FORMAT_NV12_10:
367 case DRM_FORMAT_NV16:
368 case DRM_FORMAT_NV16_10:
369 case DRM_FORMAT_NV24:
370 case DRM_FORMAT_NV24_10:
377 static bool is_yuv_10bit(uint32_t format)
380 case DRM_FORMAT_NV12_10:
381 case DRM_FORMAT_NV16_10:
382 case DRM_FORMAT_NV24_10:
389 static bool is_alpha_support(uint32_t format)
392 case DRM_FORMAT_ARGB8888:
393 case DRM_FORMAT_ABGR8888:
400 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
401 uint32_t dst, bool is_horizontal,
402 int vsu_mode, int *vskiplines)
404 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
407 if (mode == SCALE_UP)
408 val = GET_SCL_FT_BIC(src, dst);
409 else if (mode == SCALE_DOWN)
410 val = GET_SCL_FT_BILI_DN(src, dst);
412 if (mode == SCALE_UP) {
413 if (vsu_mode == SCALE_UP_BIL)
414 val = GET_SCL_FT_BILI_UP(src, dst);
416 val = GET_SCL_FT_BIC(src, dst);
417 } else if (mode == SCALE_DOWN) {
419 *vskiplines = scl_get_vskiplines(src, dst);
420 val = scl_get_bili_dn_vskip(src, dst,
423 val = GET_SCL_FT_BILI_DN(src, dst);
431 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
432 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
433 uint32_t dst_h, uint32_t pixel_format)
435 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
436 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
437 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
438 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
439 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
440 bool is_yuv = is_yuv_support(pixel_format);
441 uint16_t cbcr_src_w = src_w / hsub;
442 uint16_t cbcr_src_h = src_h / vsub;
451 if (!win->phy->scl->ext) {
452 VOP_SCL_SET(vop, win, scale_yrgb_x,
453 scl_cal_scale2(src_w, dst_w));
454 VOP_SCL_SET(vop, win, scale_yrgb_y,
455 scl_cal_scale2(src_h, dst_h));
457 VOP_SCL_SET(vop, win, scale_cbcr_x,
458 scl_cal_scale2(cbcr_src_w, dst_w));
459 VOP_SCL_SET(vop, win, scale_cbcr_y,
460 scl_cal_scale2(cbcr_src_h, dst_h));
465 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
466 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
469 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
470 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
471 if (cbcr_hor_scl_mode == SCALE_DOWN)
472 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
474 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
476 if (yrgb_hor_scl_mode == SCALE_DOWN)
477 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
479 lb_mode = scl_vop_cal_lb_mode(src_w, false);
482 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
483 if (lb_mode == LB_RGB_3840X2) {
484 if (yrgb_ver_scl_mode != SCALE_NONE) {
485 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
488 if (cbcr_ver_scl_mode != SCALE_NONE) {
489 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
492 vsu_mode = SCALE_UP_BIL;
493 } else if (lb_mode == LB_RGB_2560X4) {
494 vsu_mode = SCALE_UP_BIL;
496 vsu_mode = SCALE_UP_BIC;
499 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
501 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
502 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
503 false, vsu_mode, &vskiplines);
504 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
506 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
507 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
509 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
510 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
511 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
512 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
513 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
517 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
518 dst_w, true, 0, NULL);
519 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
520 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
521 dst_h, false, vsu_mode, &vskiplines);
522 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
524 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
525 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
526 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
527 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
528 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
529 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
530 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
535 * rk3399 colorspace path:
536 * Input Win csc Output
537 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
540 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
541 * RGB --> 709To2020->R2Y __/
543 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
546 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
547 * RGB --> 709To2020->R2Y __/
549 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
552 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
553 * RGB --> R2Y(601) __/
555 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
558 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
560 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
562 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
564 * 11. RGB --> bypass --> RGB_OUTPUT(709)
566 static int vop_csc_setup(const struct vop_csc_table *csc_table,
567 bool is_input_yuv, bool is_output_yuv,
568 int input_csc, int output_csc,
569 const uint32_t **y2r_table,
570 const uint32_t **r2r_table,
571 const uint32_t **r2y_table)
578 if (output_csc == CSC_BT2020) {
580 if (input_csc == CSC_BT2020)
582 *y2r_table = csc_table->y2r_bt709;
584 if (input_csc != CSC_BT2020)
585 *r2r_table = csc_table->r2r_bt709_to_bt2020;
586 *r2y_table = csc_table->r2y_bt2020;
588 if (is_input_yuv && input_csc == CSC_BT2020)
589 *y2r_table = csc_table->y2r_bt2020;
590 if (input_csc == CSC_BT2020)
591 *r2r_table = csc_table->r2r_bt2020_to_bt709;
592 if (!is_input_yuv || *y2r_table) {
593 if (output_csc == CSC_BT709)
594 *r2y_table = csc_table->r2y_bt709;
596 *r2y_table = csc_table->r2y_bt601;
604 * is possible use bt2020 on rgb mode?
606 if (WARN_ON(output_csc == CSC_BT2020))
609 if (input_csc == CSC_BT2020)
610 *y2r_table = csc_table->y2r_bt2020;
611 else if (input_csc == CSC_BT709)
612 *y2r_table = csc_table->y2r_bt709;
614 *y2r_table = csc_table->y2r_bt601;
616 if (input_csc == CSC_BT2020)
618 * We don't have bt601 to bt709 table, force use bt709.
620 *r2r_table = csc_table->r2r_bt2020_to_bt709;
626 static int vop_csc_atomic_check(struct drm_crtc *crtc,
627 struct drm_crtc_state *crtc_state)
629 struct vop *vop = to_vop(crtc);
630 struct drm_atomic_state *state = crtc_state->state;
631 const struct vop_csc_table *csc_table = vop->data->csc_table;
632 struct drm_plane_state *pstate;
633 struct drm_plane *plane;
640 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
641 struct vop_plane_state *vop_plane_state;
643 pstate = drm_atomic_get_plane_state(state, plane);
645 return PTR_ERR(pstate);
646 vop_plane_state = to_vop_plane_state(pstate);
650 is_yuv = is_yuv_support(pstate->fb->pixel_format);
653 * TODO: force set input and output csc mode.
655 ret = vop_csc_setup(csc_table, is_yuv, false,
656 CSC_BT709, CSC_BT709,
657 &vop_plane_state->y2r_table,
658 &vop_plane_state->r2r_table,
659 &vop_plane_state->r2y_table);
667 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
671 spin_lock_irqsave(&vop->irq_lock, flags);
673 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
674 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
676 spin_unlock_irqrestore(&vop->irq_lock, flags);
679 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
683 spin_lock_irqsave(&vop->irq_lock, flags);
685 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
687 spin_unlock_irqrestore(&vop->irq_lock, flags);
691 * (1) each frame starts at the start of the Vsync pulse which is signaled by
692 * the "FRAME_SYNC" interrupt.
693 * (2) the active data region of each frame ends at dsp_vact_end
694 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
695 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
697 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
699 * LINE_FLAG -------------------------------+
703 * | Vsync | Vbp | Vactive | Vfp |
707 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
708 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
709 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
710 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
712 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
714 uint32_t line_flag_irq;
717 spin_lock_irqsave(&vop->irq_lock, flags);
719 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
721 spin_unlock_irqrestore(&vop->irq_lock, flags);
723 return !!line_flag_irq;
726 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
730 if (WARN_ON(!vop->is_enabled))
733 spin_lock_irqsave(&vop->irq_lock, flags);
735 VOP_INTR_SET(vop, line_flag_num[0], line_num);
736 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
737 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
739 spin_unlock_irqrestore(&vop->irq_lock, flags);
742 static void vop_line_flag_irq_disable(struct vop *vop)
746 if (WARN_ON(!vop->is_enabled))
749 spin_lock_irqsave(&vop->irq_lock, flags);
751 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
753 spin_unlock_irqrestore(&vop->irq_lock, flags);
756 static void vop_power_enable(struct drm_crtc *crtc)
758 struct vop *vop = to_vop(crtc);
761 ret = clk_prepare_enable(vop->hclk);
763 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
767 ret = clk_prepare_enable(vop->dclk);
769 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
770 goto err_disable_hclk;
773 ret = clk_prepare_enable(vop->aclk);
775 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
776 goto err_disable_dclk;
779 ret = pm_runtime_get_sync(vop->dev);
781 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
785 memcpy(vop->regsbak, vop->regs, vop->len);
787 vop->is_enabled = true;
792 clk_disable_unprepare(vop->dclk);
794 clk_disable_unprepare(vop->hclk);
797 static void vop_initial(struct drm_crtc *crtc)
799 struct vop *vop = to_vop(crtc);
802 vop_power_enable(crtc);
804 VOP_CTRL_SET(vop, global_regdone_en, 1);
805 VOP_CTRL_SET(vop, dsp_blank, 0);
808 * We need to make sure that all windows are disabled before resume
809 * the crtc. Otherwise we might try to scan from a destroyed
812 for (i = 0; i < vop->num_wins; i++) {
813 struct vop_win *win = &vop->win[i];
815 if (win->phy->scl && win->phy->scl->ext) {
816 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
817 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
818 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
819 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
821 VOP_WIN_SET(vop, win, enable, 0);
822 VOP_WIN_SET(vop, win, gate, 1);
824 VOP_CTRL_SET(vop, afbdc_en, 0);
827 static void vop_crtc_disable(struct drm_crtc *crtc)
829 struct vop *vop = to_vop(crtc);
831 drm_crtc_vblank_off(crtc);
834 * Vop standby will take effect at end of current frame,
835 * if dsp hold valid irq happen, it means standby complete.
837 * we must wait standby complete when we want to disable aclk,
838 * if not, memory bus maybe dead.
840 reinit_completion(&vop->dsp_hold_completion);
841 vop_dsp_hold_valid_irq_enable(vop);
843 spin_lock(&vop->reg_lock);
845 VOP_CTRL_SET(vop, standby, 1);
847 spin_unlock(&vop->reg_lock);
849 WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
850 msecs_to_jiffies(50)));
852 vop_dsp_hold_valid_irq_disable(vop);
854 disable_irq(vop->irq);
856 vop->is_enabled = false;
857 if (vop->is_iommu_enabled) {
859 * vop standby complete, so iommu detach is safe.
861 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
862 vop->is_iommu_enabled = false;
865 pm_runtime_put(vop->dev);
866 clk_disable_unprepare(vop->dclk);
867 clk_disable_unprepare(vop->aclk);
868 clk_disable_unprepare(vop->hclk);
871 static void vop_plane_destroy(struct drm_plane *plane)
873 drm_plane_cleanup(plane);
876 static int vop_plane_prepare_fb(struct drm_plane *plane,
877 const struct drm_plane_state *new_state)
879 if (plane->state->fb)
880 drm_framebuffer_reference(plane->state->fb);
885 static void vop_plane_cleanup_fb(struct drm_plane *plane,
886 const struct drm_plane_state *old_state)
889 drm_framebuffer_unreference(old_state->fb);
892 static int vop_plane_atomic_check(struct drm_plane *plane,
893 struct drm_plane_state *state)
895 struct drm_crtc *crtc = state->crtc;
896 struct drm_framebuffer *fb = state->fb;
897 struct vop_win *win = to_vop_win(plane);
898 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
899 struct drm_crtc_state *crtc_state;
900 const struct vop_data *vop_data;
904 struct drm_rect *dest = &vop_plane_state->dest;
905 struct drm_rect *src = &vop_plane_state->src;
906 struct drm_rect clip;
907 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
908 DRM_PLANE_HELPER_NO_SCALING;
909 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
910 DRM_PLANE_HELPER_NO_SCALING;
911 unsigned long offset;
914 crtc = crtc ? crtc : plane->state->crtc;
916 * Both crtc or plane->state->crtc can be null.
921 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
922 if (IS_ERR(crtc_state))
923 return PTR_ERR(crtc_state);
925 src->x1 = state->src_x;
926 src->y1 = state->src_y;
927 src->x2 = state->src_x + state->src_w;
928 src->y2 = state->src_y + state->src_h;
929 dest->x1 = state->crtc_x;
930 dest->y1 = state->crtc_y;
931 dest->x2 = state->crtc_x + state->crtc_w;
932 dest->y2 = state->crtc_y + state->crtc_h;
936 clip.x2 = crtc_state->mode.hdisplay;
937 clip.y2 = crtc_state->mode.vdisplay;
939 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
943 true, true, &visible);
950 vop_plane_state->format = vop_convert_format(fb->pixel_format);
951 if (vop_plane_state->format < 0)
952 return vop_plane_state->format;
955 vop_data = vop->data;
957 if (drm_rect_width(src) >> 16 > vop_data->max_input_fb.width ||
958 drm_rect_height(src) >> 16 > vop_data->max_input_fb.height) {
959 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
960 drm_rect_width(src) >> 16,
961 drm_rect_height(src) >> 16,
962 vop_data->max_input_fb.width,
963 vop_data->max_input_fb.height);
967 if (drm_rect_width(dest) >> 16 > vop_data->max_input_fb.width ||
968 drm_rect_height(dest) >> 16 > vop_data->max_input_fb.height) {
969 DRM_ERROR("Invalid destination: %dx%d. max output: %dx%d\n",
970 drm_rect_width(dest),
971 drm_rect_height(dest),
972 vop_data->max_output_fb.width,
973 vop_data->max_output_fb.height);
978 * Src.x1 can be odd when do clip, but yuv plane start point
979 * need align with 2 pixel.
981 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
984 offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
985 if (state->rotation & BIT(DRM_REFLECT_Y))
986 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
988 offset += (src->y1 >> 16) * fb->pitches[0];
990 dma_addr = rockchip_fb_get_dma_addr(fb, 0);
991 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
992 if (is_yuv_support(fb->pixel_format)) {
993 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
994 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
995 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
997 offset = (src->x1 >> 16) * bpp / hsub / 8;
998 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1000 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1001 dma_addr += offset + fb->offsets[1];
1002 vop_plane_state->uv_mst = dma_addr;
1005 vop_plane_state->enable = true;
1010 vop_plane_state->enable = false;
1014 static void vop_plane_atomic_disable(struct drm_plane *plane,
1015 struct drm_plane_state *old_state)
1017 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1018 struct vop_win *win = to_vop_win(plane);
1019 struct vop *vop = to_vop(old_state->crtc);
1021 if (!old_state->crtc)
1024 spin_lock(&vop->reg_lock);
1027 * FIXUP: some of the vop scale would be abnormal after windows power
1028 * on/off so deinit scale to scale_none mode.
1030 if (win->phy->scl && win->phy->scl->ext) {
1031 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1032 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1033 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1034 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1036 VOP_WIN_SET(vop, win, enable, 0);
1038 spin_unlock(&vop->reg_lock);
1040 vop_plane_state->enable = false;
1043 static void vop_plane_atomic_update(struct drm_plane *plane,
1044 struct drm_plane_state *old_state)
1046 struct drm_plane_state *state = plane->state;
1047 struct drm_crtc *crtc = state->crtc;
1048 struct vop_win *win = to_vop_win(plane);
1049 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1050 struct rockchip_crtc_state *s;
1052 struct drm_framebuffer *fb = state->fb;
1053 unsigned int actual_w, actual_h;
1054 unsigned int dsp_stx, dsp_sty;
1055 uint32_t act_info, dsp_info, dsp_st;
1056 struct drm_rect *src = &vop_plane_state->src;
1057 struct drm_rect *dest = &vop_plane_state->dest;
1058 const uint32_t *y2r_table = vop_plane_state->y2r_table;
1059 const uint32_t *r2r_table = vop_plane_state->r2r_table;
1060 const uint32_t *r2y_table = vop_plane_state->r2y_table;
1061 int ymirror, xmirror;
1066 * can't update plane when vop is disabled.
1071 if (!vop_plane_state->enable) {
1072 vop_plane_atomic_disable(plane, old_state);
1076 actual_w = drm_rect_width(src) >> 16;
1077 actual_h = drm_rect_height(src) >> 16;
1078 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1080 dsp_info = (drm_rect_height(dest) - 1) << 16;
1081 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1083 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1084 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1085 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1087 ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1088 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1090 vop = to_vop(state->crtc);
1091 s = to_rockchip_crtc_state(crtc->state);
1093 spin_lock(&vop->reg_lock);
1095 VOP_WIN_SET(vop, win, xmirror, xmirror);
1096 VOP_WIN_SET(vop, win, ymirror, ymirror);
1097 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1098 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1099 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1100 if (is_yuv_support(fb->pixel_format)) {
1101 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1102 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1104 VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1106 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1107 drm_rect_width(dest), drm_rect_height(dest),
1110 VOP_WIN_SET(vop, win, act_info, act_info);
1111 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1112 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1114 rb_swap = has_rb_swapped(fb->pixel_format);
1115 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1117 if (is_alpha_support(fb->pixel_format) &&
1118 (s->dsp_layer_sel & 0x3) != win->win_id) {
1119 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1120 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1121 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1122 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1123 SRC_BLEND_M0(ALPHA_PER_PIX) |
1124 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1125 SRC_FACTOR_M0(ALPHA_ONE);
1126 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1127 VOP_WIN_SET(vop, win, alpha_mode, 1);
1128 VOP_WIN_SET(vop, win, alpha_en, 1);
1130 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1131 VOP_WIN_SET(vop, win, alpha_en, 0);
1135 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1136 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1137 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1138 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1139 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1140 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1142 VOP_WIN_SET(vop, win, enable, 1);
1143 spin_unlock(&vop->reg_lock);
1144 vop->is_iommu_needed = true;
1147 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1148 .prepare_fb = vop_plane_prepare_fb,
1149 .cleanup_fb = vop_plane_cleanup_fb,
1150 .atomic_check = vop_plane_atomic_check,
1151 .atomic_update = vop_plane_atomic_update,
1152 .atomic_disable = vop_plane_atomic_disable,
1155 void vop_atomic_plane_reset(struct drm_plane *plane)
1157 struct vop_win *win = to_vop_win(plane);
1158 struct vop_plane_state *vop_plane_state =
1159 to_vop_plane_state(plane->state);
1161 if (plane->state && plane->state->fb)
1162 drm_framebuffer_unreference(plane->state->fb);
1164 kfree(vop_plane_state);
1165 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1166 if (!vop_plane_state)
1169 vop_plane_state->zpos = win->win_id;
1170 plane->state = &vop_plane_state->base;
1171 plane->state->plane = plane;
1174 struct drm_plane_state *
1175 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1177 struct vop_plane_state *old_vop_plane_state;
1178 struct vop_plane_state *vop_plane_state;
1180 if (WARN_ON(!plane->state))
1183 old_vop_plane_state = to_vop_plane_state(plane->state);
1184 vop_plane_state = kmemdup(old_vop_plane_state,
1185 sizeof(*vop_plane_state), GFP_KERNEL);
1186 if (!vop_plane_state)
1189 __drm_atomic_helper_plane_duplicate_state(plane,
1190 &vop_plane_state->base);
1192 return &vop_plane_state->base;
1195 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1196 struct drm_plane_state *state)
1198 struct vop_plane_state *vop_state = to_vop_plane_state(state);
1200 __drm_atomic_helper_plane_destroy_state(plane, state);
1205 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1206 struct drm_plane_state *state,
1207 struct drm_property *property,
1210 struct vop_win *win = to_vop_win(plane);
1211 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1213 if (property == win->vop->plane_zpos_prop) {
1214 plane_state->zpos = val;
1218 if (property == win->rotation_prop) {
1219 state->rotation = val;
1223 DRM_ERROR("failed to set vop plane property\n");
1227 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1228 const struct drm_plane_state *state,
1229 struct drm_property *property,
1232 struct vop_win *win = to_vop_win(plane);
1233 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1235 if (property == win->vop->plane_zpos_prop) {
1236 *val = plane_state->zpos;
1240 if (property == win->rotation_prop) {
1241 *val = state->rotation;
1245 DRM_ERROR("failed to get vop plane property\n");
1249 static const struct drm_plane_funcs vop_plane_funcs = {
1250 .update_plane = drm_atomic_helper_update_plane,
1251 .disable_plane = drm_atomic_helper_disable_plane,
1252 .destroy = vop_plane_destroy,
1253 .reset = vop_atomic_plane_reset,
1254 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1255 .atomic_destroy_state = vop_atomic_plane_destroy_state,
1256 .atomic_set_property = vop_atomic_plane_set_property,
1257 .atomic_get_property = vop_atomic_plane_get_property,
1260 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1262 struct vop *vop = to_vop(crtc);
1263 unsigned long flags;
1265 if (!vop->is_enabled)
1268 spin_lock_irqsave(&vop->irq_lock, flags);
1270 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1271 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1273 spin_unlock_irqrestore(&vop->irq_lock, flags);
1278 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1280 struct vop *vop = to_vop(crtc);
1281 unsigned long flags;
1283 if (!vop->is_enabled)
1286 spin_lock_irqsave(&vop->irq_lock, flags);
1288 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1290 spin_unlock_irqrestore(&vop->irq_lock, flags);
1293 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1295 struct vop *vop = to_vop(crtc);
1297 reinit_completion(&vop->wait_update_complete);
1298 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1301 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1302 struct drm_file *file_priv)
1304 struct drm_device *drm = crtc->dev;
1305 struct vop *vop = to_vop(crtc);
1306 struct drm_pending_vblank_event *e;
1307 unsigned long flags;
1309 spin_lock_irqsave(&drm->event_lock, flags);
1311 if (e && e->base.file_priv == file_priv) {
1314 e->base.destroy(&e->base);
1315 file_priv->event_space += sizeof(e->event);
1317 spin_unlock_irqrestore(&drm->event_lock, flags);
1320 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1322 struct vop *vop = to_vop(crtc);
1324 if (on == vop->loader_protect)
1328 vop_power_enable(crtc);
1329 enable_irq(vop->irq);
1330 drm_crtc_vblank_on(crtc);
1331 vop->loader_protect = true;
1333 vop_crtc_disable(crtc);
1335 vop->loader_protect = false;
1341 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1343 struct vop_win *win = to_vop_win(plane);
1344 struct drm_plane_state *state = plane->state;
1345 struct vop_plane_state *pstate = to_vop_plane_state(state);
1346 struct drm_rect *src, *dest;
1347 struct drm_framebuffer *fb = state->fb;
1350 seq_printf(s, "win%d-%d: status=%s\n", win->win_id, win->area_id,
1351 pstate->enable ? "active" : "disabled");
1356 dest = &pstate->dest;
1358 seq_printf(s, "\tformat: %s\n", drm_get_format_name(fb->pixel_format));
1359 seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1360 seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1361 src->y1 >> 16, drm_rect_width(src) >> 16,
1362 drm_rect_height(src) >> 16);
1363 seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1364 drm_rect_width(dest), drm_rect_height(dest));
1366 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1367 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1368 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1369 i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1375 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1377 struct vop *vop = to_vop(crtc);
1378 struct drm_crtc_state *crtc_state = crtc->state;
1379 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1380 struct drm_plane *plane;
1383 seq_printf(s, "vop name: %s status=%s\n", dev_name(vop->dev),
1384 crtc_state->active ? "active" : "disabled");
1386 if (!crtc_state->active)
1389 seq_printf(s, "Display mode: %s fps[%d] clk[%d] type[%d] flag[%x]\n",
1390 mode->name, drm_mode_vrefresh(mode), mode->clock,
1391 mode->type, mode->flags);
1392 seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1393 mode->hsync_end, mode->htotal);
1394 seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1395 mode->vsync_end, mode->vtotal);
1397 for (i = 0; i < vop->num_wins; i++) {
1398 plane = &vop->win[i].base;
1399 vop_plane_info_dump(s, plane);
1405 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1406 .loader_protect = vop_crtc_loader_protect,
1407 .enable_vblank = vop_crtc_enable_vblank,
1408 .disable_vblank = vop_crtc_disable_vblank,
1409 .wait_for_update = vop_crtc_wait_for_update,
1410 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1411 .debugfs_dump = vop_crtc_debugfs_dump,
1414 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1415 const struct drm_display_mode *mode,
1416 struct drm_display_mode *adjusted_mode)
1418 struct vop *vop = to_vop(crtc);
1419 const struct vop_data *vop_data = vop->data;
1421 if (mode->hdisplay > vop_data->max_disably_output.width ||
1422 mode->vdisplay > vop_data->max_disably_output.height)
1425 adjusted_mode->clock =
1426 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1431 static void vop_crtc_enable(struct drm_crtc *crtc)
1433 struct vop *vop = to_vop(crtc);
1434 const struct vop_data *vop_data = vop->data;
1435 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1436 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1437 u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1438 u16 hdisplay = adjusted_mode->crtc_hdisplay;
1439 u16 htotal = adjusted_mode->crtc_htotal;
1440 u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1441 u16 hact_end = hact_st + hdisplay;
1442 u16 vdisplay = adjusted_mode->crtc_vdisplay;
1443 u16 vtotal = adjusted_mode->crtc_vtotal;
1444 u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1445 u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1446 u16 vact_end = vact_st + vdisplay;
1447 uint32_t version = vop->data->version;
1452 * If dclk rate is zero, mean that scanout is stop,
1453 * we don't need wait any more.
1455 * Since vop version(3,4), vop timing is frame effect, not need config
1456 * timing register on vblank.
1458 if (clk_get_rate(vop->dclk) &&
1459 !(VOP_MAJOR(version) == 3 && VOP_MINOR(version) >= 4)) {
1461 * Rk3288 vop timing register is immediately, when configure
1462 * display timing on display time, may cause tearing.
1464 * Vop standby will take effect at end of current frame,
1465 * if dsp hold valid irq happen, it means standby complete.
1468 * standby and wait complete --> |----
1471 * |---> dsp hold irq
1472 * configure display timing --> |
1474 * | new frame start.
1477 reinit_completion(&vop->dsp_hold_completion);
1478 vop_dsp_hold_valid_irq_enable(vop);
1480 spin_lock(&vop->reg_lock);
1482 VOP_CTRL_SET(vop, standby, 1);
1484 spin_unlock(&vop->reg_lock);
1486 WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
1487 msecs_to_jiffies(50)));
1489 vop_dsp_hold_valid_irq_disable(vop);
1492 val = BIT(DCLK_INVERT);
1493 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1494 0 : BIT(HSYNC_POSITIVE);
1495 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1496 0 : BIT(VSYNC_POSITIVE);
1497 VOP_CTRL_SET(vop, pin_pol, val);
1498 switch (s->output_type) {
1499 case DRM_MODE_CONNECTOR_LVDS:
1500 VOP_CTRL_SET(vop, rgb_en, 1);
1501 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1503 case DRM_MODE_CONNECTOR_eDP:
1504 VOP_CTRL_SET(vop, edp_en, 1);
1505 VOP_CTRL_SET(vop, edp_pin_pol, val);
1507 case DRM_MODE_CONNECTOR_HDMIA:
1508 VOP_CTRL_SET(vop, hdmi_en, 1);
1509 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1511 case DRM_MODE_CONNECTOR_DSI:
1512 VOP_CTRL_SET(vop, mipi_en, 1);
1513 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1515 case DRM_MODE_CONNECTOR_DisplayPort:
1516 val &= ~BIT(DCLK_INVERT);
1517 VOP_CTRL_SET(vop, dp_pin_pol, val);
1518 VOP_CTRL_SET(vop, dp_en, 1);
1521 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1524 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1525 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1526 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1528 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1529 switch (s->bus_format) {
1530 case MEDIA_BUS_FMT_RGB565_1X16:
1531 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1533 case MEDIA_BUS_FMT_RGB666_1X18:
1534 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1535 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1537 case MEDIA_BUS_FMT_RGB888_1X24:
1539 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1542 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1543 val |= PRE_DITHER_DOWN_EN(0);
1545 val |= PRE_DITHER_DOWN_EN(1);
1546 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1547 VOP_CTRL_SET(vop, dither_down, val);
1549 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1550 val = hact_st << 16;
1552 VOP_CTRL_SET(vop, hact_st_end, val);
1553 VOP_CTRL_SET(vop, hpost_st_end, val);
1555 VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1556 val = vact_st << 16;
1558 VOP_CTRL_SET(vop, vact_st_end, val);
1559 VOP_CTRL_SET(vop, vpost_st_end, val);
1560 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1561 u16 vact_st_f1 = vtotal + vact_st + 1;
1562 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1564 val = vact_st_f1 << 16 | vact_end_f1;
1565 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1566 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1568 val = vtotal << 16 | (vtotal + vsync_len);
1569 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1570 VOP_CTRL_SET(vop, dsp_interlace, 1);
1571 VOP_CTRL_SET(vop, p2i_en, 1);
1573 VOP_CTRL_SET(vop, dsp_interlace, 0);
1574 VOP_CTRL_SET(vop, p2i_en, 0);
1577 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1581 * enable vop, all the register would take effect when vop exit standby
1583 VOP_CTRL_SET(vop, standby, 0);
1585 enable_irq(vop->irq);
1586 drm_crtc_vblank_on(crtc);
1589 static int vop_zpos_cmp(const void *a, const void *b)
1591 struct vop_zpos *pa = (struct vop_zpos *)a;
1592 struct vop_zpos *pb = (struct vop_zpos *)b;
1594 return pa->zpos - pb->zpos;
1597 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1598 struct drm_crtc_state *crtc_state)
1600 struct vop *vop = to_vop(crtc);
1601 const struct vop_data *vop_data = vop->data;
1602 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1603 struct drm_atomic_state *state = crtc_state->state;
1604 struct drm_plane *plane;
1605 struct drm_plane_state *pstate;
1606 struct vop_plane_state *plane_state;
1607 struct vop_win *win;
1613 for_each_plane_in_state(state, plane, pstate, i) {
1614 struct drm_framebuffer *fb = pstate->fb;
1615 struct drm_rect *src;
1617 win = to_vop_win(plane);
1618 plane_state = to_vop_plane_state(pstate);
1620 if (pstate->crtc != crtc || !fb)
1623 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1626 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1627 DRM_ERROR("not support afbdc\n");
1631 switch (plane_state->format) {
1632 case VOP_FMT_ARGB8888:
1633 afbdc_format = AFBDC_FMT_U8U8U8U8;
1635 case VOP_FMT_RGB888:
1636 afbdc_format = AFBDC_FMT_U8U8U8;
1638 case VOP_FMT_RGB565:
1639 afbdc_format = AFBDC_FMT_RGB565;
1646 DRM_ERROR("vop only support one afbc layer\n");
1650 src = &plane_state->src;
1651 if (src->x1 || src->y1 || fb->offsets[0]) {
1652 DRM_ERROR("win[%d] afbdc not support offset display\n",
1654 DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1655 src->x1, src->y1, fb->offsets[0]);
1658 s->afbdc_win_format = afbdc_format;
1659 s->afbdc_win_width = pstate->fb->width - 1;
1660 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1661 s->afbdc_win_id = win->win_id;
1662 s->afbdc_win_ptr = plane_state->yrgb_mst;
1669 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1670 struct drm_crtc_state *crtc_state)
1672 struct drm_atomic_state *state = crtc_state->state;
1673 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1674 struct vop *vop = to_vop(crtc);
1675 const struct vop_data *vop_data = vop->data;
1676 struct drm_plane *plane;
1677 struct drm_plane_state *pstate;
1678 struct vop_plane_state *plane_state;
1679 struct vop_zpos *pzpos;
1680 int dsp_layer_sel = 0;
1681 int i, j, cnt = 0, ret = 0;
1683 ret = vop_afbdc_atomic_check(crtc, crtc_state);
1687 ret = vop_csc_atomic_check(crtc, crtc_state);
1691 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1695 for (i = 0; i < vop_data->win_size; i++) {
1696 const struct vop_win_data *win_data = &vop_data->win[i];
1697 struct vop_win *win;
1702 for (j = 0; j < vop->num_wins; j++) {
1705 if (win->win_id == i && !win->area_id)
1708 if (WARN_ON(j >= vop->num_wins)) {
1710 goto err_free_pzpos;
1714 pstate = state->plane_states[drm_plane_index(plane)];
1716 * plane might not have changed, in which case take
1720 pstate = plane->state;
1721 plane_state = to_vop_plane_state(pstate);
1722 pzpos[cnt].zpos = plane_state->zpos;
1723 pzpos[cnt++].win_id = win->win_id;
1726 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1728 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1729 const struct vop_win_data *win_data = &vop_data->win[i];
1732 if (win_data->phy) {
1733 struct vop_zpos *zpos = &pzpos[cnt++];
1735 dsp_layer_sel |= zpos->win_id << shift;
1737 dsp_layer_sel |= i << shift;
1741 s->dsp_layer_sel = dsp_layer_sel;
1748 static void vop_post_config(struct drm_crtc *crtc)
1750 struct vop *vop = to_vop(crtc);
1751 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1752 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1753 u16 vtotal = mode->crtc_vtotal;
1754 u16 hdisplay = mode->crtc_hdisplay;
1755 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1756 u16 vdisplay = mode->crtc_vdisplay;
1757 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1758 u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1759 u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1760 u16 hact_end, vact_end;
1763 hact_st += hdisplay * (100 - s->left_margin) / 200;
1764 hact_end = hact_st + hsize;
1765 val = hact_st << 16;
1767 VOP_CTRL_SET(vop, hpost_st_end, val);
1768 vact_st += vdisplay * (100 - s->top_margin) / 200;
1769 vact_end = vact_st + vsize;
1770 val = vact_st << 16;
1772 VOP_CTRL_SET(vop, vpost_st_end, val);
1773 val = scl_cal_scale2(vdisplay, vsize) << 16;
1774 val |= scl_cal_scale2(hdisplay, hsize);
1775 VOP_CTRL_SET(vop, post_scl_factor, val);
1776 VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1777 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1778 u16 vact_st_f1 = vtotal + vact_st + 1;
1779 u16 vact_end_f1 = vact_st_f1 + vsize;
1781 val = vact_st_f1 << 16 | vact_end_f1;
1782 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1786 static void vop_cfg_update(struct drm_crtc *crtc,
1787 struct drm_crtc_state *old_crtc_state)
1789 struct rockchip_crtc_state *s =
1790 to_rockchip_crtc_state(crtc->state);
1791 struct vop *vop = to_vop(crtc);
1793 spin_lock(&vop->reg_lock);
1798 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1799 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1800 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1801 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1802 pic_size = (s->afbdc_win_width & 0xffff);
1803 pic_size |= s->afbdc_win_height << 16;
1804 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1807 VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1808 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1809 vop_post_config(crtc);
1811 spin_unlock(&vop->reg_lock);
1814 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1815 struct drm_crtc_state *old_crtc_state)
1817 struct vop *vop = to_vop(crtc);
1819 vop_cfg_update(crtc, old_crtc_state);
1821 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1822 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1825 if (need_wait_vblank) {
1828 disable_irq(vop->irq);
1829 drm_crtc_vblank_get(crtc);
1830 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1832 ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1833 vop, active, active,
1836 dev_err(vop->dev, "wait fs irq timeout\n");
1838 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1841 ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1842 vop, active, active,
1845 dev_err(vop->dev, "wait line flag timeout\n");
1847 enable_irq(vop->irq);
1849 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1851 dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1854 if (need_wait_vblank) {
1855 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1856 drm_crtc_vblank_put(crtc);
1859 vop->is_iommu_enabled = true;
1865 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1866 struct drm_crtc_state *old_crtc_state)
1868 struct vop *vop = to_vop(crtc);
1870 if (crtc->state->event) {
1871 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1873 vop->event = crtc->state->event;
1874 crtc->state->event = NULL;
1878 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1879 .enable = vop_crtc_enable,
1880 .disable = vop_crtc_disable,
1881 .mode_fixup = vop_crtc_mode_fixup,
1882 .atomic_check = vop_crtc_atomic_check,
1883 .atomic_flush = vop_crtc_atomic_flush,
1884 .atomic_begin = vop_crtc_atomic_begin,
1887 static void vop_crtc_destroy(struct drm_crtc *crtc)
1889 drm_crtc_cleanup(crtc);
1892 static void vop_crtc_reset(struct drm_crtc *crtc)
1894 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1897 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1901 s = kzalloc(sizeof(*s), GFP_KERNEL);
1904 crtc->state = &s->base;
1905 crtc->state->crtc = crtc;
1906 s->left_margin = 100;
1907 s->right_margin = 100;
1908 s->top_margin = 100;
1909 s->bottom_margin = 100;
1912 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1914 struct rockchip_crtc_state *rockchip_state, *old_state;
1916 old_state = to_rockchip_crtc_state(crtc->state);
1917 rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1918 if (!rockchip_state)
1921 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1922 return &rockchip_state->base;
1925 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1926 struct drm_crtc_state *state)
1928 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1930 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1934 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
1935 const struct drm_crtc_state *state,
1936 struct drm_property *property,
1939 struct drm_device *drm_dev = crtc->dev;
1940 struct drm_mode_config *mode_config = &drm_dev->mode_config;
1941 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1943 if (property == mode_config->tv_left_margin_property) {
1944 *val = s->left_margin;
1948 if (property == mode_config->tv_right_margin_property) {
1949 *val = s->right_margin;
1953 if (property == mode_config->tv_top_margin_property) {
1954 *val = s->top_margin;
1958 if (property == mode_config->tv_bottom_margin_property) {
1959 *val = s->bottom_margin;
1963 DRM_ERROR("failed to get vop crtc property\n");
1967 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
1968 struct drm_crtc_state *state,
1969 struct drm_property *property,
1972 struct drm_device *drm_dev = crtc->dev;
1973 struct drm_mode_config *mode_config = &drm_dev->mode_config;
1974 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1976 if (property == mode_config->tv_left_margin_property) {
1977 s->left_margin = val;
1981 if (property == mode_config->tv_right_margin_property) {
1982 s->right_margin = val;
1986 if (property == mode_config->tv_top_margin_property) {
1987 s->top_margin = val;
1991 if (property == mode_config->tv_bottom_margin_property) {
1992 s->bottom_margin = val;
1996 DRM_ERROR("failed to set vop crtc property\n");
2000 static const struct drm_crtc_funcs vop_crtc_funcs = {
2001 .set_config = drm_atomic_helper_set_config,
2002 .page_flip = drm_atomic_helper_page_flip,
2003 .destroy = vop_crtc_destroy,
2004 .reset = vop_crtc_reset,
2005 .atomic_get_property = vop_crtc_atomic_get_property,
2006 .atomic_set_property = vop_crtc_atomic_set_property,
2007 .atomic_duplicate_state = vop_crtc_duplicate_state,
2008 .atomic_destroy_state = vop_crtc_destroy_state,
2011 static void vop_handle_vblank(struct vop *vop)
2013 struct drm_device *drm = vop->drm_dev;
2014 struct drm_crtc *crtc = &vop->crtc;
2015 unsigned long flags;
2017 if (!vop_is_cfg_done_complete(vop))
2021 spin_lock_irqsave(&drm->event_lock, flags);
2023 drm_crtc_send_vblank_event(crtc, vop->event);
2024 drm_crtc_vblank_put(crtc);
2027 spin_unlock_irqrestore(&drm->event_lock, flags);
2029 if (!completion_done(&vop->wait_update_complete))
2030 complete(&vop->wait_update_complete);
2033 static irqreturn_t vop_isr(int irq, void *data)
2035 struct vop *vop = data;
2036 struct drm_crtc *crtc = &vop->crtc;
2037 uint32_t active_irqs;
2038 unsigned long flags;
2042 * interrupt register has interrupt status, enable and clear bits, we
2043 * must hold irq_lock to avoid a race with enable/disable_vblank().
2045 spin_lock_irqsave(&vop->irq_lock, flags);
2047 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2048 /* Clear all active interrupt sources */
2050 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2052 spin_unlock_irqrestore(&vop->irq_lock, flags);
2054 /* This is expected for vop iommu irqs, since the irq is shared */
2058 if (active_irqs & DSP_HOLD_VALID_INTR) {
2059 complete(&vop->dsp_hold_completion);
2060 active_irqs &= ~DSP_HOLD_VALID_INTR;
2064 if (active_irqs & LINE_FLAG_INTR) {
2065 complete(&vop->line_flag_completion);
2066 active_irqs &= ~LINE_FLAG_INTR;
2070 if (active_irqs & FS_INTR) {
2071 drm_crtc_handle_vblank(crtc);
2072 vop_handle_vblank(vop);
2073 active_irqs &= ~FS_INTR;
2077 /* Unhandled irqs are spurious. */
2079 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2084 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2085 unsigned long possible_crtcs)
2087 struct drm_plane *share = NULL;
2088 unsigned int rotations = 0;
2089 struct drm_property *prop;
2090 uint64_t feature = 0;
2094 share = &win->parent->base;
2096 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2097 possible_crtcs, &vop_plane_funcs,
2098 win->data_formats, win->nformats, win->type);
2100 DRM_ERROR("failed to initialize plane\n");
2103 drm_plane_helper_add(&win->base, &plane_helper_funcs);
2104 drm_object_attach_property(&win->base.base,
2105 vop->plane_zpos_prop, win->win_id);
2107 if (VOP_WIN_SUPPORT(vop, win, xmirror))
2108 rotations |= BIT(DRM_REFLECT_X);
2110 if (VOP_WIN_SUPPORT(vop, win, ymirror))
2111 rotations |= BIT(DRM_REFLECT_Y);
2114 rotations |= BIT(DRM_ROTATE_0);
2115 prop = drm_mode_create_rotation_property(vop->drm_dev,
2118 DRM_ERROR("failed to create zpos property\n");
2121 drm_object_attach_property(&win->base.base, prop,
2123 win->rotation_prop = prop;
2126 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2127 if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2128 VOP_WIN_SUPPORT(vop, win, alpha_en))
2129 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2131 drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2137 static int vop_create_crtc(struct vop *vop)
2139 struct device *dev = vop->dev;
2140 const struct vop_data *vop_data = vop->data;
2141 struct drm_device *drm_dev = vop->drm_dev;
2142 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2143 struct drm_crtc *crtc = &vop->crtc;
2144 struct device_node *port;
2145 uint64_t feature = 0;
2150 * Create drm_plane for primary and cursor planes first, since we need
2151 * to pass them to drm_crtc_init_with_planes, which sets the
2152 * "possible_crtcs" to the newly initialized crtc.
2154 for (i = 0; i < vop->num_wins; i++) {
2155 struct vop_win *win = &vop->win[i];
2157 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2158 win->type != DRM_PLANE_TYPE_CURSOR)
2161 ret = vop_plane_init(vop, win, 0);
2163 goto err_cleanup_planes;
2166 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2168 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2173 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2174 &vop_crtc_funcs, NULL);
2176 goto err_cleanup_planes;
2178 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2181 * Create drm_planes for overlay windows with possible_crtcs restricted
2182 * to the newly created crtc.
2184 for (i = 0; i < vop->num_wins; i++) {
2185 struct vop_win *win = &vop->win[i];
2186 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2188 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2191 ret = vop_plane_init(vop, win, possible_crtcs);
2193 goto err_cleanup_crtc;
2196 port = of_get_child_by_name(dev->of_node, "port");
2198 DRM_ERROR("no port node found in %s\n",
2199 dev->of_node->full_name);
2201 goto err_cleanup_crtc;
2204 init_completion(&vop->dsp_hold_completion);
2205 init_completion(&vop->wait_update_complete);
2206 init_completion(&vop->line_flag_completion);
2208 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2210 ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2212 goto err_unregister_crtc_funcs;
2213 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2214 drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2216 VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2217 VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2218 VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2219 VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2220 #undef VOP_ATTACH_MODE_CONFIG_PROP
2222 if (vop_data->feature & VOP_FEATURE_AFBDC)
2223 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2224 drm_object_attach_property(&crtc->base, vop->feature_prop,
2229 err_unregister_crtc_funcs:
2230 rockchip_unregister_crtc_funcs(crtc);
2232 drm_crtc_cleanup(crtc);
2234 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2236 drm_plane_cleanup(plane);
2240 static void vop_destroy_crtc(struct vop *vop)
2242 struct drm_crtc *crtc = &vop->crtc;
2243 struct drm_device *drm_dev = vop->drm_dev;
2244 struct drm_plane *plane, *tmp;
2246 rockchip_unregister_crtc_funcs(crtc);
2247 of_node_put(crtc->port);
2250 * We need to cleanup the planes now. Why?
2252 * The planes are "&vop->win[i].base". That means the memory is
2253 * all part of the big "struct vop" chunk of memory. That memory
2254 * was devm allocated and associated with this component. We need to
2255 * free it ourselves before vop_unbind() finishes.
2257 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2259 vop_plane_destroy(plane);
2262 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2263 * references the CRTC.
2265 drm_crtc_cleanup(crtc);
2269 * Initialize the vop->win array elements.
2271 static int vop_win_init(struct vop *vop)
2273 const struct vop_data *vop_data = vop->data;
2275 unsigned int num_wins = 0;
2276 struct drm_property *prop;
2277 static const struct drm_prop_enum_list props[] = {
2278 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2279 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2281 static const struct drm_prop_enum_list crtc_props[] = {
2282 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2285 for (i = 0; i < vop_data->win_size; i++) {
2286 struct vop_win *vop_win = &vop->win[num_wins];
2287 const struct vop_win_data *win_data = &vop_data->win[i];
2292 vop_win->phy = win_data->phy;
2293 vop_win->csc = win_data->csc;
2294 vop_win->offset = win_data->base;
2295 vop_win->type = win_data->type;
2296 vop_win->data_formats = win_data->phy->data_formats;
2297 vop_win->nformats = win_data->phy->nformats;
2299 vop_win->win_id = i;
2300 vop_win->area_id = 0;
2303 for (j = 0; j < win_data->area_size; j++) {
2304 struct vop_win *vop_area = &vop->win[num_wins];
2305 const struct vop_win_phy *area = win_data->area[j];
2307 vop_area->parent = vop_win;
2308 vop_area->offset = vop_win->offset;
2309 vop_area->phy = area;
2310 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2311 vop_area->data_formats = vop_win->data_formats;
2312 vop_area->nformats = vop_win->nformats;
2313 vop_area->vop = vop;
2314 vop_area->win_id = i;
2315 vop_area->area_id = j;
2320 vop->num_wins = num_wins;
2322 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2323 "ZPOS", 0, vop->data->win_size);
2325 DRM_ERROR("failed to create zpos property\n");
2328 vop->plane_zpos_prop = prop;
2330 vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2331 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2332 props, ARRAY_SIZE(props),
2333 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2334 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2335 if (!vop->plane_feature_prop) {
2336 DRM_ERROR("failed to create feature property\n");
2340 vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2341 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2342 crtc_props, ARRAY_SIZE(crtc_props),
2343 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2344 if (!vop->feature_prop) {
2345 DRM_ERROR("failed to create vop feature property\n");
2353 * rockchip_drm_wait_line_flag - acqiure the give line flag event
2354 * @crtc: CRTC to enable line flag
2355 * @line_num: interested line number
2356 * @mstimeout: millisecond for timeout
2358 * Driver would hold here until the interested line flag interrupt have
2359 * happened or timeout to wait.
2362 * Zero on success, negative errno on failure.
2364 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2365 unsigned int mstimeout)
2367 struct vop *vop = to_vop(crtc);
2368 unsigned long jiffies_left;
2370 if (!crtc || !vop->is_enabled)
2373 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2376 if (vop_line_flag_irq_is_enabled(vop))
2379 reinit_completion(&vop->line_flag_completion);
2380 vop_line_flag_irq_enable(vop, line_num);
2382 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2383 msecs_to_jiffies(mstimeout));
2384 vop_line_flag_irq_disable(vop);
2386 if (jiffies_left == 0) {
2387 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2393 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2395 static int vop_bind(struct device *dev, struct device *master, void *data)
2397 struct platform_device *pdev = to_platform_device(dev);
2398 const struct vop_data *vop_data;
2399 struct drm_device *drm_dev = data;
2401 struct resource *res;
2406 vop_data = of_device_get_match_data(dev);
2410 for (i = 0; i < vop_data->win_size; i++) {
2411 const struct vop_win_data *win_data = &vop_data->win[i];
2413 num_wins += win_data->area_size + 1;
2416 /* Allocate vop struct and its vop_win array */
2417 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2418 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2423 vop->data = vop_data;
2424 vop->drm_dev = drm_dev;
2425 vop->num_wins = num_wins;
2426 dev_set_drvdata(dev, vop);
2428 ret = vop_win_init(vop);
2432 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2433 vop->len = resource_size(res);
2434 vop->regs = devm_ioremap_resource(dev, res);
2435 if (IS_ERR(vop->regs))
2436 return PTR_ERR(vop->regs);
2438 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2442 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2443 if (IS_ERR(vop->hclk)) {
2444 dev_err(vop->dev, "failed to get hclk source\n");
2445 return PTR_ERR(vop->hclk);
2447 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2448 if (IS_ERR(vop->aclk)) {
2449 dev_err(vop->dev, "failed to get aclk source\n");
2450 return PTR_ERR(vop->aclk);
2452 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2453 if (IS_ERR(vop->dclk)) {
2454 dev_err(vop->dev, "failed to get dclk source\n");
2455 return PTR_ERR(vop->dclk);
2458 irq = platform_get_irq(pdev, 0);
2460 dev_err(dev, "cannot find irq for vop\n");
2463 vop->irq = (unsigned int)irq;
2465 spin_lock_init(&vop->reg_lock);
2466 spin_lock_init(&vop->irq_lock);
2468 mutex_init(&vop->vsync_mutex);
2470 ret = devm_request_irq(dev, vop->irq, vop_isr,
2471 IRQF_SHARED, dev_name(dev), vop);
2475 /* IRQ is initially disabled; it gets enabled in power_on */
2476 disable_irq(vop->irq);
2478 ret = vop_create_crtc(vop);
2482 pm_runtime_enable(&pdev->dev);
2486 static void vop_unbind(struct device *dev, struct device *master, void *data)
2488 struct vop *vop = dev_get_drvdata(dev);
2490 pm_runtime_disable(dev);
2491 vop_destroy_crtc(vop);
2494 const struct component_ops vop_component_ops = {
2496 .unbind = vop_unbind,
2498 EXPORT_SYMBOL_GPL(vop_component_ops);