drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33
  34 #include "rockchip_drm_drv.h"
  35 #include "rockchip_drm_gem.h"
  36 #include "rockchip_drm_fb.h"
  37 #include "rockchip_drm_vop.h"
  38
  39 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
  40                 vop_mask_write(x, off, mask, shift, v, write_mask, true)
  41
  42 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
  43                 vop_mask_write(x, off, mask, shift, v, write_mask, false)
  44
  45 #define REG_SET(x, off, reg, v, mode) \
  46                 __REG_SET_##mode(x, off + reg.offset, \
  47                                  reg.mask, reg.shift, v, reg.write_mask)
  48 #define REG_SET_MASK(x, off, reg, mask, v, mode) \
  49                 __REG_SET_##mode(x, off + reg.offset, \
  50                                  mask, reg.shift, v, reg.write_mask)
  51
  52 #define VOP_WIN_SET(x, win, name, v) \
  53                 REG_SET(x, win->offset, VOP_WIN_NAME(win, name), v, RELAXED)
  54 #define VOP_SCL_SET(x, win, name, v) \
  55                 REG_SET(x, win->offset, win->phy->scl->name, v, RELAXED)
  56 #define VOP_SCL_SET_EXT(x, win, name, v) \
  57                 REG_SET(x, win->offset, win->phy->scl->ext->name, v, RELAXED)
  58
  59 #define VOP_CTRL_SET(x, name, v) \
  60                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  61
  62 #define VOP_INTR_GET(vop, name) \
  63                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  64
  65 #define VOP_INTR_SET(vop, name, mask, v) \
  66                 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
  67 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  68         do { \
  69                 int i, reg = 0, mask = 0; \
  70                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  71                         if (vop->data->intr->intrs[i] & type) { \
  72                                 reg |= (v) << i; \
  73                                 mask |= 1 << i; \
  74                         } \
  75                 } \
  76                 VOP_INTR_SET(vop, name, mask, reg); \
  77         } while (0)
  78 #define VOP_INTR_GET_TYPE(vop, name, type) \
  79                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  80
  81 #define VOP_WIN_GET(x, win, name) \
  82                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
  83
  84 #define VOP_WIN_NAME(win, name) \
  85                 (vop_get_win_phy(win, &win->phy->name)->name)
  86
  87 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  88                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
  89
  90 #define to_vop(x) container_of(x, struct vop, crtc)
  91 #define to_vop_win(x) container_of(x, struct vop_win, base)
  92 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  93
  94 struct vop_plane_state {
  95         struct drm_plane_state base;
  96         int format;
  97         struct drm_rect src;
  98         struct drm_rect dest;
  99         dma_addr_t yrgb_mst;
 100         bool enable;
 101 };
 102
 103 struct vop_win {
 104         struct vop_win *parent;
 105         struct drm_plane base;
 106
 107         uint32_t offset;
 108         enum drm_plane_type type;
 109         const struct vop_win_phy *phy;
 110         const uint32_t *data_formats;
 111         uint32_t nformats;
 112         struct vop *vop;
 113
 114         struct vop_plane_state state;
 115 };
 116
 117 struct vop {
 118         struct drm_crtc crtc;
 119         struct device *dev;
 120         struct drm_device *drm_dev;
 121         bool is_enabled;
 122
 123         /* mutex vsync_ work */
 124         struct mutex vsync_mutex;
 125         bool vsync_work_pending;
 126         struct completion dsp_hold_completion;
 127         struct completion wait_update_complete;
 128         struct drm_pending_vblank_event *event;
 129
 130         const struct vop_data *data;
 131         int num_wins;
 132
 133         uint32_t *regsbak;
 134         void __iomem *regs;
 135
 136         /* physical map length of vop register */
 137         uint32_t len;
 138
 139         /* one time only one process allowed to config the register */
 140         spinlock_t reg_lock;
 141         /* lock vop irq reg */
 142         spinlock_t irq_lock;
 143
 144         unsigned int irq;
 145
 146         /* vop AHP clk */
 147         struct clk *hclk;
 148         /* vop dclk */
 149         struct clk *dclk;
 150         /* vop share memory frequency */
 151         struct clk *aclk;
 152
 153         /* vop dclk reset */
 154         struct reset_control *dclk_rst;
 155
 156         struct vop_win win[];
 157 };
 158
 159 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 160 {
 161         writel(v, vop->regs + offset);
 162         vop->regsbak[offset >> 2] = v;
 163 }
 164
 165 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 166 {
 167         return readl(vop->regs + offset);
 168 }
 169
 170 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 171                                     const struct vop_reg *reg)
 172 {
 173         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 174 }
 175
 176 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 177                                   uint32_t mask, uint32_t shift, uint32_t v,
 178                                   bool write_mask, bool relaxed)
 179 {
 180         if (!mask)
 181                 return;
 182
 183         if (write_mask) {
 184                 v = (v << shift) | (mask << (shift + 16));
 185         } else {
 186                 uint32_t cached_val = vop->regsbak[offset >> 2];
 187
 188                 v = (cached_val & ~(mask << shift)) | (v << shift);
 189                 vop->regsbak[offset >> 2] = v;
 190         }
 191
 192         if (relaxed)
 193                 writel_relaxed(v, vop->regs + offset);
 194         else
 195                 writel(v, vop->regs + offset);
 196 }
 197
 198 static inline const struct vop_win_phy *
 199 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 200 {
 201         if (!reg->mask && win->parent)
 202                 return win->parent->phy;
 203
 204         return win->phy;
 205 }
 206
 207 static inline uint32_t vop_get_intr_type(struct vop *vop,
 208                                          const struct vop_reg *reg, int type)
 209 {
 210         uint32_t i, ret = 0;
 211         uint32_t regs = vop_read_reg(vop, 0, reg);
 212
 213         for (i = 0; i < vop->data->intr->nintrs; i++) {
 214                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 215                         ret |= vop->data->intr->intrs[i];
 216         }
 217
 218         return ret;
 219 }
 220
 221 static inline void vop_cfg_done(struct vop *vop)
 222 {
 223         VOP_CTRL_SET(vop, cfg_done, 1);
 224 }
 225
 226 static bool has_rb_swapped(uint32_t format)
 227 {
 228         switch (format) {
 229         case DRM_FORMAT_XBGR8888:
 230         case DRM_FORMAT_ABGR8888:
 231         case DRM_FORMAT_BGR888:
 232         case DRM_FORMAT_BGR565:
 233                 return true;
 234         default:
 235                 return false;
 236         }
 237 }
 238
 239 static enum vop_data_format vop_convert_format(uint32_t format)
 240 {
 241         switch (format) {
 242         case DRM_FORMAT_XRGB8888:
 243         case DRM_FORMAT_ARGB8888:
 244         case DRM_FORMAT_XBGR8888:
 245         case DRM_FORMAT_ABGR8888:
 246                 return VOP_FMT_ARGB8888;
 247         case DRM_FORMAT_RGB888:
 248         case DRM_FORMAT_BGR888:
 249                 return VOP_FMT_RGB888;
 250         case DRM_FORMAT_RGB565:
 251         case DRM_FORMAT_BGR565:
 252                 return VOP_FMT_RGB565;
 253         case DRM_FORMAT_NV12:
 254                 return VOP_FMT_YUV420SP;
 255         case DRM_FORMAT_NV16:
 256                 return VOP_FMT_YUV422SP;
 257         case DRM_FORMAT_NV24:
 258                 return VOP_FMT_YUV444SP;
 259         default:
 260                 DRM_ERROR("unsupport format[%08x]\n", format);
 261                 return -EINVAL;
 262         }
 263 }
 264
 265 static bool is_yuv_support(uint32_t format)
 266 {
 267         switch (format) {
 268         case DRM_FORMAT_NV12:
 269         case DRM_FORMAT_NV16:
 270         case DRM_FORMAT_NV24:
 271                 return true;
 272         default:
 273                 return false;
 274         }
 275 }
 276
 277 static bool is_alpha_support(uint32_t format)
 278 {
 279         switch (format) {
 280         case DRM_FORMAT_ARGB8888:
 281         case DRM_FORMAT_ABGR8888:
 282                 return true;
 283         default:
 284                 return false;
 285         }
 286 }
 287
 288 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 289                                   uint32_t dst, bool is_horizontal,
 290                                   int vsu_mode, int *vskiplines)
 291 {
 292         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 293
 294         if (is_horizontal) {
 295                 if (mode == SCALE_UP)
 296                         val = GET_SCL_FT_BIC(src, dst);
 297                 else if (mode == SCALE_DOWN)
 298                         val = GET_SCL_FT_BILI_DN(src, dst);
 299         } else {
 300                 if (mode == SCALE_UP) {
 301                         if (vsu_mode == SCALE_UP_BIL)
 302                                 val = GET_SCL_FT_BILI_UP(src, dst);
 303                         else
 304                                 val = GET_SCL_FT_BIC(src, dst);
 305                 } else if (mode == SCALE_DOWN) {
 306                         if (vskiplines) {
 307                                 *vskiplines = scl_get_vskiplines(src, dst);
 308                                 val = scl_get_bili_dn_vskip(src, dst,
 309                                                             *vskiplines);
 310                         } else {
 311                                 val = GET_SCL_FT_BILI_DN(src, dst);
 312                         }
 313                 }
 314         }
 315
 316         return val;
 317 }
 318
 319 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 320                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 321                                 uint32_t dst_h, uint32_t pixel_format)
 322 {
 323         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 324         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 325         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 326         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 327         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 328         bool is_yuv = is_yuv_support(pixel_format);
 329         uint16_t cbcr_src_w = src_w / hsub;
 330         uint16_t cbcr_src_h = src_h / vsub;
 331         uint16_t vsu_mode;
 332         uint16_t lb_mode;
 333         uint32_t val;
 334         int vskiplines;
 335
 336         if (!win->phy->scl)
 337                 return;
 338
 339         if (dst_w > 3840) {
 340                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 341                 return;
 342         }
 343
 344         if (!win->phy->scl->ext) {
 345                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 346                             scl_cal_scale2(src_w, dst_w));
 347                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 348                             scl_cal_scale2(src_h, dst_h));
 349                 if (is_yuv) {
 350                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 351                                     scl_cal_scale2(src_w, dst_w));
 352                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 353                                     scl_cal_scale2(src_h, dst_h));
 354                 }
 355                 return;
 356         }
 357
 358         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 359         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 360
 361         if (is_yuv) {
 362                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 363                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 364                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 365                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 366                 else
 367                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 368         } else {
 369                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 370                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 371                 else
 372                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 373         }
 374
 375         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 376         if (lb_mode == LB_RGB_3840X2) {
 377                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 378                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 379                         return;
 380                 }
 381                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 382                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 383                         return;
 384                 }
 385                 vsu_mode = SCALE_UP_BIL;
 386         } else if (lb_mode == LB_RGB_2560X4) {
 387                 vsu_mode = SCALE_UP_BIL;
 388         } else {
 389                 vsu_mode = SCALE_UP_BIC;
 390         }
 391
 392         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 393                                 true, 0, NULL);
 394         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 395         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 396                                 false, vsu_mode, &vskiplines);
 397         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 398
 399         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 400         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 401
 402         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 403         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 404         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 405         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 406         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 407         if (is_yuv) {
 408                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 409                                         dst_w, true, 0, NULL);
 410                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 411                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 412                                         dst_h, false, vsu_mode, &vskiplines);
 413                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 414
 415                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 416                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 417                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 418                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 419                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 420                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 421                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 422         }
 423 }
 424
 425 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 426 {
 427         unsigned long flags;
 428
 429         if (WARN_ON(!vop->is_enabled))
 430                 return;
 431
 432         spin_lock_irqsave(&vop->irq_lock, flags);
 433
 434         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 435
 436         spin_unlock_irqrestore(&vop->irq_lock, flags);
 437 }
 438
 439 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 440 {
 441         unsigned long flags;
 442
 443         if (WARN_ON(!vop->is_enabled))
 444                 return;
 445
 446         spin_lock_irqsave(&vop->irq_lock, flags);
 447
 448         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 449
 450         spin_unlock_irqrestore(&vop->irq_lock, flags);
 451 }
 452
 453 static void vop_enable(struct drm_crtc *crtc)
 454 {
 455         struct vop *vop = to_vop(crtc);
 456         int ret;
 457
 458         if (vop->is_enabled)
 459                 return;
 460
 461         ret = pm_runtime_get_sync(vop->dev);
 462         if (ret < 0) {
 463                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 464                 return;
 465         }
 466
 467         ret = clk_enable(vop->hclk);
 468         if (ret < 0) {
 469                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 470                 return;
 471         }
 472
 473         ret = clk_enable(vop->dclk);
 474         if (ret < 0) {
 475                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 476                 goto err_disable_hclk;
 477         }
 478
 479         ret = clk_enable(vop->aclk);
 480         if (ret < 0) {
 481                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 482                 goto err_disable_dclk;
 483         }
 484
 485         /*
 486          * Slave iommu shares power, irq and clock with vop.  It was associated
 487          * automatically with this master device via common driver code.
 488          * Now that we have enabled the clock we attach it to the shared drm
 489          * mapping.
 490          */
 491         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 492         if (ret) {
 493                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 494                 goto err_disable_aclk;
 495         }
 496
 497         memcpy(vop->regs, vop->regsbak, vop->len);
 498         /*
 499          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 500          */
 501         vop->is_enabled = true;
 502
 503         spin_lock(&vop->reg_lock);
 504
 505         VOP_CTRL_SET(vop, standby, 0);
 506
 507         spin_unlock(&vop->reg_lock);
 508
 509         enable_irq(vop->irq);
 510
 511         drm_crtc_vblank_on(crtc);
 512
 513         return;
 514
 515 err_disable_aclk:
 516         clk_disable(vop->aclk);
 517 err_disable_dclk:
 518         clk_disable(vop->dclk);
 519 err_disable_hclk:
 520         clk_disable(vop->hclk);
 521 }
 522
 523 static void vop_crtc_disable(struct drm_crtc *crtc)
 524 {
 525         struct vop *vop = to_vop(crtc);
 526         int i;
 527
 528         if (!vop->is_enabled)
 529                 return;
 530
 531         /*
 532          * We need to make sure that all windows are disabled before we
 533          * disable that crtc. Otherwise we might try to scan from a destroyed
 534          * buffer later.
 535          */
 536         for (i = 0; i < vop->num_wins; i++) {
 537                 struct vop_win *win = &vop->win[i];
 538
 539                 spin_lock(&vop->reg_lock);
 540                 VOP_WIN_SET(vop, win, enable, 0);
 541                 spin_unlock(&vop->reg_lock);
 542         }
 543
 544         drm_crtc_vblank_off(crtc);
 545
 546         /*
 547          * Vop standby will take effect at end of current frame,
 548          * if dsp hold valid irq happen, it means standby complete.
 549          *
 550          * we must wait standby complete when we want to disable aclk,
 551          * if not, memory bus maybe dead.
 552          */
 553         reinit_completion(&vop->dsp_hold_completion);
 554         vop_dsp_hold_valid_irq_enable(vop);
 555
 556         spin_lock(&vop->reg_lock);
 557
 558         VOP_CTRL_SET(vop, standby, 1);
 559
 560         spin_unlock(&vop->reg_lock);
 561
 562         wait_for_completion(&vop->dsp_hold_completion);
 563
 564         vop_dsp_hold_valid_irq_disable(vop);
 565
 566         disable_irq(vop->irq);
 567
 568         vop->is_enabled = false;
 569
 570         /*
 571          * vop standby complete, so iommu detach is safe.
 572          */
 573         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 574
 575         clk_disable(vop->dclk);
 576         clk_disable(vop->aclk);
 577         clk_disable(vop->hclk);
 578         pm_runtime_put(vop->dev);
 579 }
 580
 581 static void vop_plane_destroy(struct drm_plane *plane)
 582 {
 583         drm_plane_cleanup(plane);
 584 }
 585
 586 static int vop_plane_atomic_check(struct drm_plane *plane,
 587                            struct drm_plane_state *state)
 588 {
 589         struct drm_crtc *crtc = state->crtc;
 590         struct drm_framebuffer *fb = state->fb;
 591         struct vop_win *win = to_vop_win(plane);
 592         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 593         bool visible;
 594         int ret;
 595         struct drm_rect *dest = &vop_plane_state->dest;
 596         struct drm_rect *src = &vop_plane_state->src;
 597         struct drm_rect clip;
 598         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 599                                         DRM_PLANE_HELPER_NO_SCALING;
 600         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 601                                         DRM_PLANE_HELPER_NO_SCALING;
 602
 603         crtc = crtc ? crtc : plane->state->crtc;
 604         /*
 605          * Both crtc or plane->state->crtc can be null.
 606          */
 607         if (!crtc || !fb)
 608                 goto out_disable;
 609         src->x1 = state->src_x;
 610         src->y1 = state->src_y;
 611         src->x2 = state->src_x + state->src_w;
 612         src->y2 = state->src_y + state->src_h;
 613         dest->x1 = state->crtc_x;
 614         dest->y1 = state->crtc_y;
 615         dest->x2 = state->crtc_x + state->crtc_w;
 616         dest->y2 = state->crtc_y + state->crtc_h;
 617
 618         clip.x1 = 0;
 619         clip.y1 = 0;
 620         clip.x2 = crtc->mode.hdisplay;
 621         clip.y2 = crtc->mode.vdisplay;
 622
 623         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 624                                             src, dest, &clip,
 625                                             min_scale,
 626                                             max_scale,
 627                                             true, true, &visible);
 628         if (ret)
 629                 return ret;
 630
 631         if (!visible)
 632                 goto out_disable;
 633
 634         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 635         if (vop_plane_state->format < 0)
 636                 return vop_plane_state->format;
 637
 638         /*
 639          * Src.x1 can be odd when do clip, but yuv plane start point
 640          * need align with 2 pixel.
 641          */
 642         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 643                 return -EINVAL;
 644
 645         vop_plane_state->enable = true;
 646
 647         return 0;
 648
 649 out_disable:
 650         vop_plane_state->enable = false;
 651         return 0;
 652 }
 653
 654 static void vop_plane_atomic_disable(struct drm_plane *plane,
 655                                      struct drm_plane_state *old_state)
 656 {
 657         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 658         struct vop_win *win = to_vop_win(plane);
 659         struct vop *vop = to_vop(old_state->crtc);
 660
 661         if (!old_state->crtc)
 662                 return;
 663
 664         spin_lock(&vop->reg_lock);
 665
 666         VOP_WIN_SET(vop, win, enable, 0);
 667
 668         spin_unlock(&vop->reg_lock);
 669
 670         vop_plane_state->enable = false;
 671 }
 672
 673 static void vop_plane_atomic_update(struct drm_plane *plane,
 674                 struct drm_plane_state *old_state)
 675 {
 676         struct drm_plane_state *state = plane->state;
 677         struct drm_crtc *crtc = state->crtc;
 678         struct vop_win *win = to_vop_win(plane);
 679         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 680         struct vop *vop = to_vop(state->crtc);
 681         struct drm_framebuffer *fb = state->fb;
 682         unsigned int actual_w, actual_h;
 683         unsigned int dsp_stx, dsp_sty;
 684         uint32_t act_info, dsp_info, dsp_st;
 685         struct drm_rect *src = &vop_plane_state->src;
 686         struct drm_rect *dest = &vop_plane_state->dest;
 687         struct drm_gem_object *obj, *uv_obj;
 688         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 689         unsigned long offset;
 690         dma_addr_t dma_addr;
 691         uint32_t val;
 692         bool rb_swap;
 693
 694         /*
 695          * can't update plane when vop is disabled.
 696          */
 697         if (!crtc)
 698                 return;
 699
 700         if (WARN_ON(!vop->is_enabled))
 701                 return;
 702
 703         if (!vop_plane_state->enable) {
 704                 vop_plane_atomic_disable(plane, old_state);
 705                 return;
 706         }
 707
 708         obj = rockchip_fb_get_gem_obj(fb, 0);
 709         rk_obj = to_rockchip_obj(obj);
 710
 711         actual_w = drm_rect_width(src) >> 16;
 712         actual_h = drm_rect_height(src) >> 16;
 713         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 714
 715         dsp_info = (drm_rect_height(dest) - 1) << 16;
 716         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 717
 718         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 719         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 720         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 721
 722         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 723         offset += (src->y1 >> 16) * fb->pitches[0];
 724         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 725
 726         spin_lock(&vop->reg_lock);
 727
 728         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 729         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 730         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 731         if (is_yuv_support(fb->pixel_format)) {
 732                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 733                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 734                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 735
 736                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 737                 rk_uv_obj = to_rockchip_obj(uv_obj);
 738
 739                 offset = (src->x1 >> 16) * bpp / hsub;
 740                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 741
 742                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 743                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 744                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 745         }
 746
 747         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 748                             drm_rect_width(dest), drm_rect_height(dest),
 749                             fb->pixel_format);
 750
 751         VOP_WIN_SET(vop, win, act_info, act_info);
 752         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 753         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 754
 755         rb_swap = has_rb_swapped(fb->pixel_format);
 756         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 757
 758         if (is_alpha_support(fb->pixel_format)) {
 759                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 760                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 761                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 762                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 763                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 764                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 765                         SRC_FACTOR_M0(ALPHA_ONE);
 766                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 767         } else {
 768                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 769         }
 770
 771         VOP_WIN_SET(vop, win, enable, 1);
 772         spin_unlock(&vop->reg_lock);
 773 }
 774
 775 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 776         .atomic_check = vop_plane_atomic_check,
 777         .atomic_update = vop_plane_atomic_update,
 778         .atomic_disable = vop_plane_atomic_disable,
 779 };
 780
 781 void vop_atomic_plane_reset(struct drm_plane *plane)
 782 {
 783         struct vop_plane_state *vop_plane_state =
 784                                         to_vop_plane_state(plane->state);
 785
 786         if (plane->state && plane->state->fb)
 787                 drm_framebuffer_unreference(plane->state->fb);
 788
 789         kfree(vop_plane_state);
 790         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 791         if (!vop_plane_state)
 792                 return;
 793
 794         plane->state = &vop_plane_state->base;
 795         plane->state->plane = plane;
 796 }
 797
 798 struct drm_plane_state *
 799 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 800 {
 801         struct vop_plane_state *old_vop_plane_state;
 802         struct vop_plane_state *vop_plane_state;
 803
 804         if (WARN_ON(!plane->state))
 805                 return NULL;
 806
 807         old_vop_plane_state = to_vop_plane_state(plane->state);
 808         vop_plane_state = kmemdup(old_vop_plane_state,
 809                                   sizeof(*vop_plane_state), GFP_KERNEL);
 810         if (!vop_plane_state)
 811                 return NULL;
 812
 813         __drm_atomic_helper_plane_duplicate_state(plane,
 814                                                   &vop_plane_state->base);
 815
 816         return &vop_plane_state->base;
 817 }
 818
 819 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 820                                            struct drm_plane_state *state)
 821 {
 822         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 823
 824         __drm_atomic_helper_plane_destroy_state(plane, state);
 825
 826         kfree(vop_state);
 827 }
 828
 829 static const struct drm_plane_funcs vop_plane_funcs = {
 830         .update_plane   = drm_atomic_helper_update_plane,
 831         .disable_plane  = drm_atomic_helper_disable_plane,
 832         .destroy = vop_plane_destroy,
 833         .reset = vop_atomic_plane_reset,
 834         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 835         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 836 };
 837
 838 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 839 {
 840         struct vop *vop = to_vop(crtc);
 841         unsigned long flags;
 842
 843         if (WARN_ON(!vop->is_enabled))
 844                 return -EPERM;
 845
 846         spin_lock_irqsave(&vop->irq_lock, flags);
 847
 848         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 849
 850         spin_unlock_irqrestore(&vop->irq_lock, flags);
 851
 852         return 0;
 853 }
 854
 855 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 856 {
 857         struct vop *vop = to_vop(crtc);
 858         unsigned long flags;
 859
 860         if (WARN_ON(!vop->is_enabled))
 861                 return;
 862
 863         spin_lock_irqsave(&vop->irq_lock, flags);
 864
 865         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 866
 867         spin_unlock_irqrestore(&vop->irq_lock, flags);
 868 }
 869
 870 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 871 {
 872         struct vop *vop = to_vop(crtc);
 873
 874         reinit_completion(&vop->wait_update_complete);
 875         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
 876 }
 877
 878 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
 879                                            struct drm_file *file_priv)
 880 {
 881         struct drm_device *drm = crtc->dev;
 882         struct vop *vop = to_vop(crtc);
 883         struct drm_pending_vblank_event *e;
 884         unsigned long flags;
 885
 886         spin_lock_irqsave(&drm->event_lock, flags);
 887         e = vop->event;
 888         if (e && e->base.file_priv == file_priv) {
 889                 vop->event = NULL;
 890
 891                 e->base.destroy(&e->base);
 892                 file_priv->event_space += sizeof(e->event);
 893         }
 894         spin_unlock_irqrestore(&drm->event_lock, flags);
 895 }
 896
 897 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 898         .enable_vblank = vop_crtc_enable_vblank,
 899         .disable_vblank = vop_crtc_disable_vblank,
 900         .wait_for_update = vop_crtc_wait_for_update,
 901         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
 902 };
 903
 904 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 905                                 const struct drm_display_mode *mode,
 906                                 struct drm_display_mode *adjusted_mode)
 907 {
 908         struct vop *vop = to_vop(crtc);
 909
 910         adjusted_mode->clock =
 911                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
 912
 913         return true;
 914 }
 915
 916 static void vop_crtc_enable(struct drm_crtc *crtc)
 917 {
 918         struct vop *vop = to_vop(crtc);
 919         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 920         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 921         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 922         u16 hdisplay = adjusted_mode->hdisplay;
 923         u16 htotal = adjusted_mode->htotal;
 924         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 925         u16 hact_end = hact_st + hdisplay;
 926         u16 vdisplay = adjusted_mode->vdisplay;
 927         u16 vtotal = adjusted_mode->vtotal;
 928         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 929         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 930         u16 vact_end = vact_st + vdisplay;
 931         uint32_t val;
 932
 933         vop_enable(crtc);
 934         /*
 935          * If dclk rate is zero, mean that scanout is stop,
 936          * we don't need wait any more.
 937          */
 938         if (clk_get_rate(vop->dclk)) {
 939                 /*
 940                  * Rk3288 vop timing register is immediately, when configure
 941                  * display timing on display time, may cause tearing.
 942                  *
 943                  * Vop standby will take effect at end of current frame,
 944                  * if dsp hold valid irq happen, it means standby complete.
 945                  *
 946                  * mode set:
 947                  *    standby and wait complete --> |----
 948                  *                                  | display time
 949                  *                                  |----
 950                  *                                  |---> dsp hold irq
 951                  *     configure display timing --> |
 952                  *         standby exit             |
 953                  *                                  | new frame start.
 954                  */
 955
 956                 reinit_completion(&vop->dsp_hold_completion);
 957                 vop_dsp_hold_valid_irq_enable(vop);
 958
 959                 spin_lock(&vop->reg_lock);
 960
 961                 VOP_CTRL_SET(vop, standby, 1);
 962
 963                 spin_unlock(&vop->reg_lock);
 964
 965                 wait_for_completion(&vop->dsp_hold_completion);
 966
 967                 vop_dsp_hold_valid_irq_disable(vop);
 968         }
 969
 970         val = 0x8;
 971         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
 972         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
 973         VOP_CTRL_SET(vop, pin_pol, val);
 974         switch (s->output_type) {
 975         case DRM_MODE_CONNECTOR_LVDS:
 976                 VOP_CTRL_SET(vop, rgb_en, 1);
 977                 break;
 978         case DRM_MODE_CONNECTOR_eDP:
 979                 VOP_CTRL_SET(vop, edp_en, 1);
 980                 break;
 981         case DRM_MODE_CONNECTOR_HDMIA:
 982                 VOP_CTRL_SET(vop, hdmi_en, 1);
 983                 break;
 984         case DRM_MODE_CONNECTOR_DSI:
 985                 VOP_CTRL_SET(vop, mipi_en, 1);
 986                 break;
 987         default:
 988                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
 989         }
 990         VOP_CTRL_SET(vop, out_mode, s->output_mode);
 991
 992         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 993         val = hact_st << 16;
 994         val |= hact_end;
 995         VOP_CTRL_SET(vop, hact_st_end, val);
 996         VOP_CTRL_SET(vop, hpost_st_end, val);
 997
 998         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 999         val = vact_st << 16;
1000         val |= vact_end;
1001         VOP_CTRL_SET(vop, vact_st_end, val);
1002         VOP_CTRL_SET(vop, vpost_st_end, val);
1003
1004         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1005
1006         VOP_CTRL_SET(vop, standby, 0);
1007 }
1008
1009 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1010                                   struct drm_crtc_state *old_crtc_state)
1011 {
1012         struct vop *vop = to_vop(crtc);
1013
1014         if (WARN_ON(!vop->is_enabled))
1015                 return;
1016
1017         spin_lock(&vop->reg_lock);
1018
1019         vop_cfg_done(vop);
1020
1021         spin_unlock(&vop->reg_lock);
1022 }
1023
1024 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1025                                   struct drm_crtc_state *old_crtc_state)
1026 {
1027         struct vop *vop = to_vop(crtc);
1028
1029         if (crtc->state->event) {
1030                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1031
1032                 vop->event = crtc->state->event;
1033                 crtc->state->event = NULL;
1034         }
1035 }
1036
1037 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1038         .enable = vop_crtc_enable,
1039         .disable = vop_crtc_disable,
1040         .mode_fixup = vop_crtc_mode_fixup,
1041         .atomic_flush = vop_crtc_atomic_flush,
1042         .atomic_begin = vop_crtc_atomic_begin,
1043 };
1044
1045 static void vop_crtc_destroy(struct drm_crtc *crtc)
1046 {
1047         drm_crtc_cleanup(crtc);
1048 }
1049
1050 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1051 {
1052         struct rockchip_crtc_state *rockchip_state;
1053
1054         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1055         if (!rockchip_state)
1056                 return NULL;
1057
1058         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1059         return &rockchip_state->base;
1060 }
1061
1062 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1063                                    struct drm_crtc_state *state)
1064 {
1065         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1066
1067         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1068         kfree(s);
1069 }
1070
1071 static const struct drm_crtc_funcs vop_crtc_funcs = {
1072         .set_config = drm_atomic_helper_set_config,
1073         .page_flip = drm_atomic_helper_page_flip,
1074         .destroy = vop_crtc_destroy,
1075         .reset = drm_atomic_helper_crtc_reset,
1076         .atomic_duplicate_state = vop_crtc_duplicate_state,
1077         .atomic_destroy_state = vop_crtc_destroy_state,
1078 };
1079
1080 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1081 {
1082         struct drm_plane *plane = &vop_win->base;
1083         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1084         dma_addr_t yrgb_mst;
1085
1086         if (!state->enable)
1087                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1088
1089         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1090
1091         return yrgb_mst == state->yrgb_mst;
1092 }
1093
1094 static void vop_handle_vblank(struct vop *vop)
1095 {
1096         struct drm_device *drm = vop->drm_dev;
1097         struct drm_crtc *crtc = &vop->crtc;
1098         unsigned long flags;
1099         int i;
1100
1101         for (i = 0; i < vop->num_wins; i++) {
1102                 if (!vop_win_pending_is_complete(&vop->win[i]))
1103                         return;
1104         }
1105
1106         if (vop->event) {
1107                 spin_lock_irqsave(&drm->event_lock, flags);
1108
1109                 drm_crtc_send_vblank_event(crtc, vop->event);
1110                 drm_crtc_vblank_put(crtc);
1111                 vop->event = NULL;
1112
1113                 spin_unlock_irqrestore(&drm->event_lock, flags);
1114         }
1115         if (!completion_done(&vop->wait_update_complete))
1116                 complete(&vop->wait_update_complete);
1117 }
1118
1119 static irqreturn_t vop_isr(int irq, void *data)
1120 {
1121         struct vop *vop = data;
1122         struct drm_crtc *crtc = &vop->crtc;
1123         uint32_t active_irqs;
1124         unsigned long flags;
1125         int ret = IRQ_NONE;
1126
1127         /*
1128          * interrupt register has interrupt status, enable and clear bits, we
1129          * must hold irq_lock to avoid a race with enable/disable_vblank().
1130         */
1131         spin_lock_irqsave(&vop->irq_lock, flags);
1132
1133         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1134         /* Clear all active interrupt sources */
1135         if (active_irqs)
1136                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1137
1138         spin_unlock_irqrestore(&vop->irq_lock, flags);
1139
1140         /* This is expected for vop iommu irqs, since the irq is shared */
1141         if (!active_irqs)
1142                 return IRQ_NONE;
1143
1144         if (active_irqs & DSP_HOLD_VALID_INTR) {
1145                 complete(&vop->dsp_hold_completion);
1146                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1147                 ret = IRQ_HANDLED;
1148         }
1149
1150         if (active_irqs & FS_INTR) {
1151                 drm_crtc_handle_vblank(crtc);
1152                 vop_handle_vblank(vop);
1153                 active_irqs &= ~FS_INTR;
1154                 ret = IRQ_HANDLED;
1155         }
1156
1157         /* Unhandled irqs are spurious. */
1158         if (active_irqs)
1159                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1160
1161         return ret;
1162 }
1163
1164 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1165                           unsigned long possible_crtcs)
1166 {
1167         struct drm_plane *share = NULL;
1168         int ret;
1169
1170         if (win->parent)
1171                 share = &win->parent->base;
1172
1173         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1174                                    possible_crtcs, &vop_plane_funcs,
1175                                    win->data_formats, win->nformats, win->type);
1176         if (ret) {
1177                 DRM_ERROR("failed to initialize plane\n");
1178                 return ret;
1179         }
1180         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1181
1182         return 0;
1183 }
1184
1185 static int vop_create_crtc(struct vop *vop)
1186 {
1187         struct device *dev = vop->dev;
1188         struct drm_device *drm_dev = vop->drm_dev;
1189         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1190         struct drm_crtc *crtc = &vop->crtc;
1191         struct device_node *port;
1192         int ret;
1193         int i;
1194
1195         /*
1196          * Create drm_plane for primary and cursor planes first, since we need
1197          * to pass them to drm_crtc_init_with_planes, which sets the
1198          * "possible_crtcs" to the newly initialized crtc.
1199          */
1200         for (i = 0; i < vop->num_wins; i++) {
1201                 struct vop_win *win = &vop->win[i];
1202
1203                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1204                     win->type != DRM_PLANE_TYPE_CURSOR)
1205                         continue;
1206
1207                 if (vop_plane_init(vop, win, 0))
1208                         goto err_cleanup_planes;
1209
1210                 plane = &win->base;
1211                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1212                         primary = plane;
1213                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1214                         cursor = plane;
1215
1216         }
1217
1218         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1219                                         &vop_crtc_funcs, NULL);
1220         if (ret)
1221                 goto err_cleanup_planes;
1222
1223         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1224
1225         /*
1226          * Create drm_planes for overlay windows with possible_crtcs restricted
1227          * to the newly created crtc.
1228          */
1229         for (i = 0; i < vop->num_wins; i++) {
1230                 struct vop_win *win = &vop->win[i];
1231                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1232
1233                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1234                         continue;
1235
1236                 if (vop_plane_init(vop, win, possible_crtcs))
1237                         goto err_cleanup_crtc;
1238         }
1239
1240         port = of_get_child_by_name(dev->of_node, "port");
1241         if (!port) {
1242                 DRM_ERROR("no port node found in %s\n",
1243                           dev->of_node->full_name);
1244                 ret = -ENOENT;
1245                 goto err_cleanup_crtc;
1246         }
1247
1248         init_completion(&vop->dsp_hold_completion);
1249         init_completion(&vop->wait_update_complete);
1250         crtc->port = port;
1251         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1252
1253         return 0;
1254
1255 err_cleanup_crtc:
1256         drm_crtc_cleanup(crtc);
1257 err_cleanup_planes:
1258         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1259                                  head)
1260                 drm_plane_cleanup(plane);
1261         return ret;
1262 }
1263
1264 static void vop_destroy_crtc(struct vop *vop)
1265 {
1266         struct drm_crtc *crtc = &vop->crtc;
1267         struct drm_device *drm_dev = vop->drm_dev;
1268         struct drm_plane *plane, *tmp;
1269
1270         rockchip_unregister_crtc_funcs(crtc);
1271         of_node_put(crtc->port);
1272
1273         /*
1274          * We need to cleanup the planes now.  Why?
1275          *
1276          * The planes are "&vop->win[i].base".  That means the memory is
1277          * all part of the big "struct vop" chunk of memory.  That memory
1278          * was devm allocated and associated with this component.  We need to
1279          * free it ourselves before vop_unbind() finishes.
1280          */
1281         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1282                                  head)
1283                 vop_plane_destroy(plane);
1284
1285         /*
1286          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1287          * references the CRTC.
1288          */
1289         drm_crtc_cleanup(crtc);
1290 }
1291
1292 static int vop_initial(struct vop *vop)
1293 {
1294         const struct vop_data *vop_data = vop->data;
1295         const struct vop_reg_data *init_table = vop_data->init_table;
1296         struct reset_control *ahb_rst;
1297         int i, ret;
1298
1299         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1300         if (IS_ERR(vop->hclk)) {
1301                 dev_err(vop->dev, "failed to get hclk source\n");
1302                 return PTR_ERR(vop->hclk);
1303         }
1304         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1305         if (IS_ERR(vop->aclk)) {
1306                 dev_err(vop->dev, "failed to get aclk source\n");
1307                 return PTR_ERR(vop->aclk);
1308         }
1309         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1310         if (IS_ERR(vop->dclk)) {
1311                 dev_err(vop->dev, "failed to get dclk source\n");
1312                 return PTR_ERR(vop->dclk);
1313         }
1314
1315         ret = clk_prepare(vop->dclk);
1316         if (ret < 0) {
1317                 dev_err(vop->dev, "failed to prepare dclk\n");
1318                 return ret;
1319         }
1320
1321         /* Enable both the hclk and aclk to setup the vop */
1322         ret = clk_prepare_enable(vop->hclk);
1323         if (ret < 0) {
1324                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1325                 goto err_unprepare_dclk;
1326         }
1327
1328         ret = clk_prepare_enable(vop->aclk);
1329         if (ret < 0) {
1330                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1331                 goto err_disable_hclk;
1332         }
1333
1334         /*
1335          * do hclk_reset, reset all vop registers.
1336          */
1337         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1338         if (IS_ERR(ahb_rst)) {
1339                 dev_err(vop->dev, "failed to get ahb reset\n");
1340                 ret = PTR_ERR(ahb_rst);
1341                 goto err_disable_aclk;
1342         }
1343         reset_control_assert(ahb_rst);
1344         usleep_range(10, 20);
1345         reset_control_deassert(ahb_rst);
1346
1347         memcpy(vop->regsbak, vop->regs, vop->len);
1348
1349         for (i = 0; i < vop_data->table_size; i++)
1350                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1351
1352         for (i = 0; i < vop->num_wins; i++) {
1353                 struct vop_win *win = &vop->win[i];
1354
1355                 VOP_WIN_SET(vop, win, enable, 0);
1356         }
1357
1358         vop_cfg_done(vop);
1359
1360         /*
1361          * do dclk_reset, let all config take affect.
1362          */
1363         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1364         if (IS_ERR(vop->dclk_rst)) {
1365                 dev_err(vop->dev, "failed to get dclk reset\n");
1366                 ret = PTR_ERR(vop->dclk_rst);
1367                 goto err_disable_aclk;
1368         }
1369         reset_control_assert(vop->dclk_rst);
1370         usleep_range(10, 20);
1371         reset_control_deassert(vop->dclk_rst);
1372
1373         clk_disable(vop->hclk);
1374         clk_disable(vop->aclk);
1375
1376         vop->is_enabled = false;
1377
1378         return 0;
1379
1380 err_disable_aclk:
1381         clk_disable_unprepare(vop->aclk);
1382 err_disable_hclk:
1383         clk_disable_unprepare(vop->hclk);
1384 err_unprepare_dclk:
1385         clk_unprepare(vop->dclk);
1386         return ret;
1387 }
1388
1389 /*
1390  * Initialize the vop->win array elements.
1391  */
1392 static void vop_win_init(struct vop *vop)
1393 {
1394         const struct vop_data *vop_data = vop->data;
1395         unsigned int i, j;
1396         unsigned int num_wins = 0;
1397
1398         for (i = 0; i < vop_data->win_size; i++) {
1399                 struct vop_win *vop_win = &vop->win[num_wins];
1400                 const struct vop_win_data *win_data = &vop_data->win[i];
1401
1402                 vop_win->phy = win_data->phy;
1403                 vop_win->offset = win_data->base;
1404                 vop_win->type = win_data->type;
1405                 vop_win->data_formats = win_data->phy->data_formats;
1406                 vop_win->nformats = win_data->phy->nformats;
1407                 vop_win->vop = vop;
1408                 num_wins++;
1409
1410                 for (j = 0; j < win_data->area_size; j++) {
1411                         struct vop_win *vop_area = &vop->win[num_wins];
1412                         const struct vop_win_phy *area = win_data->area[j];
1413
1414                         vop_area->parent = vop_win;
1415                         vop_area->offset = vop_win->offset;
1416                         vop_area->phy = area;
1417                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1418                         vop_area->data_formats = vop_win->data_formats;
1419                         vop_area->nformats = vop_win->nformats;
1420                         vop_area->vop = vop;
1421                         num_wins++;
1422                 }
1423         }
1424 }
1425
1426 static int vop_bind(struct device *dev, struct device *master, void *data)
1427 {
1428         struct platform_device *pdev = to_platform_device(dev);
1429         const struct vop_data *vop_data;
1430         struct drm_device *drm_dev = data;
1431         struct vop *vop;
1432         struct resource *res;
1433         size_t alloc_size;
1434         int ret, irq, i;
1435         int num_wins = 0;
1436
1437         vop_data = of_device_get_match_data(dev);
1438         if (!vop_data)
1439                 return -ENODEV;
1440
1441         for (i = 0; i < vop_data->win_size; i++) {
1442                 const struct vop_win_data *win_data = &vop_data->win[i];
1443
1444                 num_wins += win_data->area_size + 1;
1445         }
1446
1447         /* Allocate vop struct and its vop_win array */
1448         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1449         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1450         if (!vop)
1451                 return -ENOMEM;
1452
1453         vop->dev = dev;
1454         vop->data = vop_data;
1455         vop->drm_dev = drm_dev;
1456         vop->num_wins = num_wins;
1457         dev_set_drvdata(dev, vop);
1458
1459         vop_win_init(vop);
1460
1461         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1462         vop->len = resource_size(res);
1463         vop->regs = devm_ioremap_resource(dev, res);
1464         if (IS_ERR(vop->regs))
1465                 return PTR_ERR(vop->regs);
1466
1467         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1468         if (!vop->regsbak)
1469                 return -ENOMEM;
1470
1471         ret = vop_initial(vop);
1472         if (ret < 0) {
1473                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1474                 return ret;
1475         }
1476
1477         irq = platform_get_irq(pdev, 0);
1478         if (irq < 0) {
1479                 dev_err(dev, "cannot find irq for vop\n");
1480                 return irq;
1481         }
1482         vop->irq = (unsigned int)irq;
1483
1484         spin_lock_init(&vop->reg_lock);
1485         spin_lock_init(&vop->irq_lock);
1486
1487         mutex_init(&vop->vsync_mutex);
1488
1489         ret = devm_request_irq(dev, vop->irq, vop_isr,
1490                                IRQF_SHARED, dev_name(dev), vop);
1491         if (ret)
1492                 return ret;
1493
1494         /* IRQ is initially disabled; it gets enabled in power_on */
1495         disable_irq(vop->irq);
1496
1497         ret = vop_create_crtc(vop);
1498         if (ret)
1499                 return ret;
1500
1501         pm_runtime_enable(&pdev->dev);
1502         return 0;
1503 }
1504
1505 static void vop_unbind(struct device *dev, struct device *master, void *data)
1506 {
1507         struct vop *vop = dev_get_drvdata(dev);
1508
1509         pm_runtime_disable(dev);
1510         vop_destroy_crtc(vop);
1511 }
1512
1513 const struct component_ops vop_component_ops = {
1514         .bind = vop_bind,
1515         .unbind = vop_unbind,
1516 };
1517 EXPORT_SYMBOL_GPL(vop_component_ops);