2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/iopoll.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
28 #include <linux/of_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/component.h>
32 #include <linux/reset.h>
33 #include <linux/delay.h>
34 #include <linux/sort.h>
35 #include <uapi/drm/rockchip_drm.h>
37 #include "rockchip_drm_drv.h"
38 #include "rockchip_drm_gem.h"
39 #include "rockchip_drm_fb.h"
40 #include "rockchip_drm_vop.h"
42 #define VOP_REG_SUPPORT(vop, reg) \
43 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
44 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
45 reg.end_minor >= VOP_MINOR(vop->data->version) && \
48 #define VOP_WIN_SUPPORT(vop, win, name) \
49 VOP_REG_SUPPORT(vop, win->phy->name)
51 #define VOP_CTRL_SUPPORT(vop, name) \
52 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
54 #define VOP_INTR_SUPPORT(vop, name) \
55 VOP_REG_SUPPORT(vop, vop->data->intr->name)
57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
58 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
62 if (VOP_REG_SUPPORT(vop, reg)) \
63 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
64 v, reg.write_mask, relaxed); \
66 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
69 #define REG_SET(x, name, off, reg, v, relaxed) \
70 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
72 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
74 #define VOP_WIN_SET(x, win, name, v) \
75 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
77 REG_SET(x, name, 0, win->ext->name, v, true)
78 #define VOP_SCL_SET(x, win, name, v) \
79 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
80 #define VOP_SCL_SET_EXT(x, win, name, v) \
81 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
83 #define VOP_CTRL_SET(x, name, v) \
84 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
86 #define VOP_INTR_GET(vop, name) \
87 vop_read_reg(vop, 0, &vop->data->ctrl->name)
89 #define VOP_INTR_SET(vop, name, v) \
90 REG_SET(vop, name, 0, vop->data->intr->name, \
92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
93 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
98 int i, reg = 0, mask = 0; \
99 for (i = 0; i < vop->data->intr->nintrs; i++) { \
100 if (vop->data->intr->intrs[i] & type) { \
105 VOP_INTR_SET_MASK(vop, name, mask, reg); \
107 #define VOP_INTR_GET_TYPE(vop, name, type) \
108 vop_get_intr_type(vop, &vop->data->intr->name, type)
110 #define VOP_CTRL_GET(x, name) \
111 vop_read_reg(x, 0, &vop->data->ctrl->name)
113 #define VOP_WIN_GET(x, win, name) \
114 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
116 #define VOP_WIN_NAME(win, name) \
117 (vop_get_win_phy(win, &win->phy->name)->name)
119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
120 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
122 #define to_vop(x) container_of(x, struct vop, crtc)
123 #define to_vop_win(x) container_of(x, struct vop_win, base)
124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
131 struct vop_plane_state {
132 struct drm_plane_state base;
136 struct drm_rect dest;
139 const uint32_t *y2r_table;
140 const uint32_t *r2r_table;
141 const uint32_t *r2y_table;
146 struct vop_win *parent;
147 struct drm_plane base;
152 enum drm_plane_type type;
153 const struct vop_win_phy *phy;
154 const struct vop_csc *csc;
155 const uint32_t *data_formats;
159 struct drm_property *rotation_prop;
160 struct vop_plane_state state;
164 struct drm_crtc crtc;
166 struct drm_device *drm_dev;
167 struct drm_property *plane_zpos_prop;
168 struct drm_property *plane_feature_prop;
169 struct drm_property *feature_prop;
170 bool is_iommu_enabled;
171 bool is_iommu_needed;
174 /* mutex vsync_ work */
175 struct mutex vsync_mutex;
176 bool vsync_work_pending;
178 struct completion dsp_hold_completion;
179 struct completion wait_update_complete;
180 struct drm_pending_vblank_event *event;
182 struct completion line_flag_completion;
184 const struct vop_data *data;
190 /* physical map length of vop register */
193 /* one time only one process allowed to config the register */
195 /* lock vop irq reg */
204 /* vop share memory frequency */
208 struct reset_control *dclk_rst;
210 struct vop_win win[];
213 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
215 writel(v, vop->regs + offset);
216 vop->regsbak[offset >> 2] = v;
219 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
221 return readl(vop->regs + offset);
224 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
225 const struct vop_reg *reg)
227 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
230 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
231 uint32_t mask, uint32_t shift, uint32_t v,
232 bool write_mask, bool relaxed)
238 v = ((v & mask) << shift) | (mask << (shift + 16));
240 uint32_t cached_val = vop->regsbak[offset >> 2];
242 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
243 vop->regsbak[offset >> 2] = v;
247 writel_relaxed(v, vop->regs + offset);
249 writel(v, vop->regs + offset);
252 static inline const struct vop_win_phy *
253 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
255 if (!reg->mask && win->parent)
256 return win->parent->phy;
261 static inline uint32_t vop_get_intr_type(struct vop *vop,
262 const struct vop_reg *reg, int type)
265 uint32_t regs = vop_read_reg(vop, 0, reg);
267 for (i = 0; i < vop->data->intr->nintrs; i++) {
268 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
269 ret |= vop->data->intr->intrs[i];
275 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
282 for (i = 0; i < 8; i++)
283 vop_writel(vop, offset + i * 4, table[i]);
286 static inline void vop_cfg_done(struct vop *vop)
288 VOP_CTRL_SET(vop, cfg_done, 1);
291 static bool vop_is_allwin_disabled(struct vop *vop)
295 for (i = 0; i < vop->num_wins; i++) {
296 struct vop_win *win = &vop->win[i];
298 if (VOP_WIN_GET(vop, win, enable) != 0)
305 static bool vop_is_cfg_done_complete(struct vop *vop)
307 return VOP_CTRL_GET(vop, cfg_done) ? false : true;
310 static bool vop_fs_irq_is_active(struct vop *vop)
312 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
315 static bool vop_line_flag_is_active(struct vop *vop)
317 return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
320 static bool has_rb_swapped(uint32_t format)
323 case DRM_FORMAT_XBGR8888:
324 case DRM_FORMAT_ABGR8888:
325 case DRM_FORMAT_BGR888:
326 case DRM_FORMAT_BGR565:
333 static enum vop_data_format vop_convert_format(uint32_t format)
336 case DRM_FORMAT_XRGB8888:
337 case DRM_FORMAT_ARGB8888:
338 case DRM_FORMAT_XBGR8888:
339 case DRM_FORMAT_ABGR8888:
340 return VOP_FMT_ARGB8888;
341 case DRM_FORMAT_RGB888:
342 case DRM_FORMAT_BGR888:
343 return VOP_FMT_RGB888;
344 case DRM_FORMAT_RGB565:
345 case DRM_FORMAT_BGR565:
346 return VOP_FMT_RGB565;
347 case DRM_FORMAT_NV12:
348 case DRM_FORMAT_NV12_10:
349 return VOP_FMT_YUV420SP;
350 case DRM_FORMAT_NV16:
351 case DRM_FORMAT_NV16_10:
352 return VOP_FMT_YUV422SP;
353 case DRM_FORMAT_NV24:
354 case DRM_FORMAT_NV24_10:
355 return VOP_FMT_YUV444SP;
357 DRM_ERROR("unsupport format[%08x]\n", format);
362 static bool is_yuv_output(uint32_t bus_format)
364 switch (bus_format) {
365 case MEDIA_BUS_FMT_YUV8_1X24:
366 case MEDIA_BUS_FMT_YUV10_1X30:
373 static bool is_yuv_support(uint32_t format)
376 case DRM_FORMAT_NV12:
377 case DRM_FORMAT_NV12_10:
378 case DRM_FORMAT_NV16:
379 case DRM_FORMAT_NV16_10:
380 case DRM_FORMAT_NV24:
381 case DRM_FORMAT_NV24_10:
388 static bool is_yuv_10bit(uint32_t format)
391 case DRM_FORMAT_NV12_10:
392 case DRM_FORMAT_NV16_10:
393 case DRM_FORMAT_NV24_10:
400 static bool is_alpha_support(uint32_t format)
403 case DRM_FORMAT_ARGB8888:
404 case DRM_FORMAT_ABGR8888:
411 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
412 uint32_t dst, bool is_horizontal,
413 int vsu_mode, int *vskiplines)
415 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
418 if (mode == SCALE_UP)
419 val = GET_SCL_FT_BIC(src, dst);
420 else if (mode == SCALE_DOWN)
421 val = GET_SCL_FT_BILI_DN(src, dst);
423 if (mode == SCALE_UP) {
424 if (vsu_mode == SCALE_UP_BIL)
425 val = GET_SCL_FT_BILI_UP(src, dst);
427 val = GET_SCL_FT_BIC(src, dst);
428 } else if (mode == SCALE_DOWN) {
430 *vskiplines = scl_get_vskiplines(src, dst);
431 val = scl_get_bili_dn_vskip(src, dst,
434 val = GET_SCL_FT_BILI_DN(src, dst);
442 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
443 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
444 uint32_t dst_h, uint32_t pixel_format)
446 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
447 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
448 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
449 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
450 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
451 bool is_yuv = is_yuv_support(pixel_format);
452 uint16_t cbcr_src_w = src_w / hsub;
453 uint16_t cbcr_src_h = src_h / vsub;
462 if (!win->phy->scl->ext) {
463 VOP_SCL_SET(vop, win, scale_yrgb_x,
464 scl_cal_scale2(src_w, dst_w));
465 VOP_SCL_SET(vop, win, scale_yrgb_y,
466 scl_cal_scale2(src_h, dst_h));
468 VOP_SCL_SET(vop, win, scale_cbcr_x,
469 scl_cal_scale2(cbcr_src_w, dst_w));
470 VOP_SCL_SET(vop, win, scale_cbcr_y,
471 scl_cal_scale2(cbcr_src_h, dst_h));
476 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
477 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
480 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
481 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
482 if (cbcr_hor_scl_mode == SCALE_DOWN)
483 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
485 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
487 if (yrgb_hor_scl_mode == SCALE_DOWN)
488 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
490 lb_mode = scl_vop_cal_lb_mode(src_w, false);
493 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
494 if (lb_mode == LB_RGB_3840X2) {
495 if (yrgb_ver_scl_mode != SCALE_NONE) {
496 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
499 if (cbcr_ver_scl_mode != SCALE_NONE) {
500 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
503 vsu_mode = SCALE_UP_BIL;
504 } else if (lb_mode == LB_RGB_2560X4) {
505 vsu_mode = SCALE_UP_BIL;
507 vsu_mode = SCALE_UP_BIC;
510 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
512 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
513 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
514 false, vsu_mode, &vskiplines);
515 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
517 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
518 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
520 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
521 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
522 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
523 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
524 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
528 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
529 dst_w, true, 0, NULL);
530 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
531 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
532 dst_h, false, vsu_mode, &vskiplines);
533 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
535 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
536 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
537 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
538 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
539 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
540 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
541 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
546 * rk3399 colorspace path:
547 * Input Win csc Output
548 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
551 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
552 * RGB --> 709To2020->R2Y __/
554 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
557 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
558 * RGB --> 709To2020->R2Y __/
560 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
563 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
564 * RGB --> R2Y(601) __/
566 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
569 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
571 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
573 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
575 * 11. RGB --> bypass --> RGB_OUTPUT(709)
577 static int vop_csc_setup(const struct vop_csc_table *csc_table,
578 bool is_input_yuv, bool is_output_yuv,
579 int input_csc, int output_csc,
580 const uint32_t **y2r_table,
581 const uint32_t **r2r_table,
582 const uint32_t **r2y_table)
589 if (output_csc == CSC_BT2020) {
591 if (input_csc == CSC_BT2020)
593 *y2r_table = csc_table->y2r_bt709;
595 if (input_csc != CSC_BT2020)
596 *r2r_table = csc_table->r2r_bt709_to_bt2020;
597 *r2y_table = csc_table->r2y_bt2020;
599 if (is_input_yuv && input_csc == CSC_BT2020)
600 *y2r_table = csc_table->y2r_bt2020;
601 if (input_csc == CSC_BT2020)
602 *r2r_table = csc_table->r2r_bt2020_to_bt709;
603 if (!is_input_yuv || *y2r_table) {
604 if (output_csc == CSC_BT709)
605 *r2y_table = csc_table->r2y_bt709;
607 *r2y_table = csc_table->r2y_bt601;
615 * is possible use bt2020 on rgb mode?
617 if (WARN_ON(output_csc == CSC_BT2020))
620 if (input_csc == CSC_BT2020)
621 *y2r_table = csc_table->y2r_bt2020;
622 else if (input_csc == CSC_BT709)
623 *y2r_table = csc_table->y2r_bt709;
625 *y2r_table = csc_table->y2r_bt601;
627 if (input_csc == CSC_BT2020)
629 * We don't have bt601 to bt709 table, force use bt709.
631 *r2r_table = csc_table->r2r_bt2020_to_bt709;
637 static int vop_csc_atomic_check(struct drm_crtc *crtc,
638 struct drm_crtc_state *crtc_state)
640 struct vop *vop = to_vop(crtc);
641 struct drm_atomic_state *state = crtc_state->state;
642 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
643 const struct vop_csc_table *csc_table = vop->data->csc_table;
644 struct drm_plane_state *pstate;
645 struct drm_plane *plane;
646 bool is_input_yuv, is_output_yuv;
652 is_output_yuv = is_yuv_output(s->bus_format);
654 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
655 struct vop_plane_state *vop_plane_state;
657 pstate = drm_atomic_get_plane_state(state, plane);
659 return PTR_ERR(pstate);
660 vop_plane_state = to_vop_plane_state(pstate);
664 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
667 * TODO: force set input and output csc mode.
669 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
670 CSC_BT709, CSC_BT709,
671 &vop_plane_state->y2r_table,
672 &vop_plane_state->r2r_table,
673 &vop_plane_state->r2y_table);
681 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
685 spin_lock_irqsave(&vop->irq_lock, flags);
687 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
688 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
690 spin_unlock_irqrestore(&vop->irq_lock, flags);
693 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
697 spin_lock_irqsave(&vop->irq_lock, flags);
699 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
701 spin_unlock_irqrestore(&vop->irq_lock, flags);
705 * (1) each frame starts at the start of the Vsync pulse which is signaled by
706 * the "FRAME_SYNC" interrupt.
707 * (2) the active data region of each frame ends at dsp_vact_end
708 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
709 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
711 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
713 * LINE_FLAG -------------------------------+
717 * | Vsync | Vbp | Vactive | Vfp |
721 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
722 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
723 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
724 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
726 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
728 uint32_t line_flag_irq;
731 spin_lock_irqsave(&vop->irq_lock, flags);
733 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
735 spin_unlock_irqrestore(&vop->irq_lock, flags);
737 return !!line_flag_irq;
740 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
744 if (WARN_ON(!vop->is_enabled))
747 spin_lock_irqsave(&vop->irq_lock, flags);
749 VOP_INTR_SET(vop, line_flag_num[0], line_num);
750 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
751 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
753 spin_unlock_irqrestore(&vop->irq_lock, flags);
756 static void vop_line_flag_irq_disable(struct vop *vop)
760 if (WARN_ON(!vop->is_enabled))
763 spin_lock_irqsave(&vop->irq_lock, flags);
765 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
767 spin_unlock_irqrestore(&vop->irq_lock, flags);
770 static void vop_power_enable(struct drm_crtc *crtc)
772 struct vop *vop = to_vop(crtc);
775 ret = clk_prepare_enable(vop->hclk);
777 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
781 ret = clk_prepare_enable(vop->dclk);
783 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
784 goto err_disable_hclk;
787 ret = clk_prepare_enable(vop->aclk);
789 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
790 goto err_disable_dclk;
793 ret = pm_runtime_get_sync(vop->dev);
795 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
799 memcpy(vop->regsbak, vop->regs, vop->len);
801 vop->is_enabled = true;
806 clk_disable_unprepare(vop->dclk);
808 clk_disable_unprepare(vop->hclk);
811 static void vop_initial(struct drm_crtc *crtc)
813 struct vop *vop = to_vop(crtc);
816 vop_power_enable(crtc);
818 VOP_CTRL_SET(vop, global_regdone_en, 1);
819 VOP_CTRL_SET(vop, dsp_blank, 0);
822 * We need to make sure that all windows are disabled before resume
823 * the crtc. Otherwise we might try to scan from a destroyed
826 for (i = 0; i < vop->num_wins; i++) {
827 struct vop_win *win = &vop->win[i];
828 int channel = i * 2 + 1;
830 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
831 if (win->phy->scl && win->phy->scl->ext) {
832 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
833 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
834 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
835 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
837 VOP_WIN_SET(vop, win, enable, 0);
838 VOP_WIN_SET(vop, win, gate, 1);
840 VOP_CTRL_SET(vop, afbdc_en, 0);
843 static void vop_crtc_disable(struct drm_crtc *crtc)
845 struct vop *vop = to_vop(crtc);
847 drm_crtc_vblank_off(crtc);
850 * Vop standby will take effect at end of current frame,
851 * if dsp hold valid irq happen, it means standby complete.
853 * we must wait standby complete when we want to disable aclk,
854 * if not, memory bus maybe dead.
856 reinit_completion(&vop->dsp_hold_completion);
857 vop_dsp_hold_valid_irq_enable(vop);
859 spin_lock(&vop->reg_lock);
861 VOP_CTRL_SET(vop, standby, 1);
863 spin_unlock(&vop->reg_lock);
865 WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
866 msecs_to_jiffies(50)));
868 vop_dsp_hold_valid_irq_disable(vop);
870 disable_irq(vop->irq);
872 vop->is_enabled = false;
873 if (vop->is_iommu_enabled) {
875 * vop standby complete, so iommu detach is safe.
877 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
878 vop->is_iommu_enabled = false;
881 pm_runtime_put(vop->dev);
882 clk_disable_unprepare(vop->dclk);
883 clk_disable_unprepare(vop->aclk);
884 clk_disable_unprepare(vop->hclk);
887 static void vop_plane_destroy(struct drm_plane *plane)
889 drm_plane_cleanup(plane);
892 static int vop_plane_prepare_fb(struct drm_plane *plane,
893 const struct drm_plane_state *new_state)
895 if (plane->state->fb)
896 drm_framebuffer_reference(plane->state->fb);
901 static void vop_plane_cleanup_fb(struct drm_plane *plane,
902 const struct drm_plane_state *old_state)
905 drm_framebuffer_unreference(old_state->fb);
908 static int vop_plane_atomic_check(struct drm_plane *plane,
909 struct drm_plane_state *state)
911 struct drm_crtc *crtc = state->crtc;
912 struct drm_framebuffer *fb = state->fb;
913 struct vop_win *win = to_vop_win(plane);
914 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
915 struct drm_crtc_state *crtc_state;
916 const struct vop_data *vop_data;
920 struct drm_rect *dest = &vop_plane_state->dest;
921 struct drm_rect *src = &vop_plane_state->src;
922 struct drm_rect clip;
923 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
924 DRM_PLANE_HELPER_NO_SCALING;
925 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
926 DRM_PLANE_HELPER_NO_SCALING;
927 unsigned long offset;
931 crtc = crtc ? crtc : plane->state->crtc;
933 * Both crtc or plane->state->crtc can be null.
938 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
939 if (IS_ERR(crtc_state))
940 return PTR_ERR(crtc_state);
942 src->x1 = state->src_x;
943 src->y1 = state->src_y;
944 src->x2 = state->src_x + state->src_w;
945 src->y2 = state->src_y + state->src_h;
946 dest->x1 = state->crtc_x;
947 dest->y1 = state->crtc_y;
948 dest->x2 = state->crtc_x + state->crtc_w;
949 dest->y2 = state->crtc_y + state->crtc_h;
951 vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
952 if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
957 clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
960 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
964 true, true, &visible);
971 vop_plane_state->format = vop_convert_format(fb->pixel_format);
972 if (vop_plane_state->format < 0)
973 return vop_plane_state->format;
976 vop_data = vop->data;
978 if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
979 drm_rect_height(src) >> 16 > vop_data->max_input.height) {
980 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
981 drm_rect_width(src) >> 16,
982 drm_rect_height(src) >> 16,
983 vop_data->max_input.width,
984 vop_data->max_input.height);
989 * Src.x1 can be odd when do clip, but yuv plane start point
990 * need align with 2 pixel.
992 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
993 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
997 offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
998 if (state->rotation & BIT(DRM_REFLECT_Y))
999 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1001 offset += (src->y1 >> 16) * fb->pitches[0];
1003 dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1004 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1005 if (is_yuv_support(fb->pixel_format)) {
1006 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1007 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1008 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1010 offset = (src->x1 >> 16) * bpp / hsub / 8;
1011 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1013 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1014 dma_addr += offset + fb->offsets[1];
1015 vop_plane_state->uv_mst = dma_addr;
1018 vop_plane_state->enable = true;
1023 vop_plane_state->enable = false;
1027 static void vop_plane_atomic_disable(struct drm_plane *plane,
1028 struct drm_plane_state *old_state)
1030 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1031 struct vop_win *win = to_vop_win(plane);
1032 struct vop *vop = to_vop(old_state->crtc);
1034 if (!old_state->crtc)
1037 spin_lock(&vop->reg_lock);
1040 * FIXUP: some of the vop scale would be abnormal after windows power
1041 * on/off so deinit scale to scale_none mode.
1043 if (win->phy->scl && win->phy->scl->ext) {
1044 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1045 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1046 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1047 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1049 VOP_WIN_SET(vop, win, enable, 0);
1051 spin_unlock(&vop->reg_lock);
1053 vop_plane_state->enable = false;
1056 static void vop_plane_atomic_update(struct drm_plane *plane,
1057 struct drm_plane_state *old_state)
1059 struct drm_plane_state *state = plane->state;
1060 struct drm_crtc *crtc = state->crtc;
1061 struct vop_win *win = to_vop_win(plane);
1062 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1063 struct rockchip_crtc_state *s;
1065 struct drm_framebuffer *fb = state->fb;
1066 unsigned int actual_w, actual_h;
1067 unsigned int dsp_stx, dsp_sty;
1068 uint32_t act_info, dsp_info, dsp_st;
1069 struct drm_rect *src = &vop_plane_state->src;
1070 struct drm_rect *dest = &vop_plane_state->dest;
1071 const uint32_t *y2r_table = vop_plane_state->y2r_table;
1072 const uint32_t *r2r_table = vop_plane_state->r2r_table;
1073 const uint32_t *r2y_table = vop_plane_state->r2y_table;
1074 int ymirror, xmirror;
1079 * can't update plane when vop is disabled.
1084 if (!vop_plane_state->enable) {
1085 vop_plane_atomic_disable(plane, old_state);
1089 actual_w = drm_rect_width(src) >> 16;
1090 actual_h = drm_rect_height(src) >> 16;
1091 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1093 dsp_info = (drm_rect_height(dest) - 1) << 16;
1094 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1096 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1097 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1098 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1100 ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1101 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1103 vop = to_vop(state->crtc);
1104 s = to_rockchip_crtc_state(crtc->state);
1106 spin_lock(&vop->reg_lock);
1108 VOP_WIN_SET(vop, win, xmirror, xmirror);
1109 VOP_WIN_SET(vop, win, ymirror, ymirror);
1110 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1111 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1112 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1113 if (is_yuv_support(fb->pixel_format)) {
1114 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1115 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1117 VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1119 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1120 drm_rect_width(dest), drm_rect_height(dest),
1123 VOP_WIN_SET(vop, win, act_info, act_info);
1124 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1125 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1127 rb_swap = has_rb_swapped(fb->pixel_format);
1128 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1130 if (is_alpha_support(fb->pixel_format) &&
1131 (s->dsp_layer_sel & 0x3) != win->win_id) {
1132 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1133 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1134 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1135 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1136 SRC_BLEND_M0(ALPHA_PER_PIX) |
1137 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1138 SRC_FACTOR_M0(ALPHA_ONE);
1139 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1140 VOP_WIN_SET(vop, win, alpha_mode, 1);
1141 VOP_WIN_SET(vop, win, alpha_en, 1);
1143 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1144 VOP_WIN_SET(vop, win, alpha_en, 0);
1148 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1149 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1150 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1151 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1152 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1153 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1155 VOP_WIN_SET(vop, win, enable, 1);
1156 spin_unlock(&vop->reg_lock);
1157 vop->is_iommu_needed = true;
1160 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1161 .prepare_fb = vop_plane_prepare_fb,
1162 .cleanup_fb = vop_plane_cleanup_fb,
1163 .atomic_check = vop_plane_atomic_check,
1164 .atomic_update = vop_plane_atomic_update,
1165 .atomic_disable = vop_plane_atomic_disable,
1168 void vop_atomic_plane_reset(struct drm_plane *plane)
1170 struct vop_win *win = to_vop_win(plane);
1171 struct vop_plane_state *vop_plane_state =
1172 to_vop_plane_state(plane->state);
1174 if (plane->state && plane->state->fb)
1175 drm_framebuffer_unreference(plane->state->fb);
1177 kfree(vop_plane_state);
1178 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1179 if (!vop_plane_state)
1182 vop_plane_state->zpos = win->win_id;
1183 plane->state = &vop_plane_state->base;
1184 plane->state->plane = plane;
1187 struct drm_plane_state *
1188 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1190 struct vop_plane_state *old_vop_plane_state;
1191 struct vop_plane_state *vop_plane_state;
1193 if (WARN_ON(!plane->state))
1196 old_vop_plane_state = to_vop_plane_state(plane->state);
1197 vop_plane_state = kmemdup(old_vop_plane_state,
1198 sizeof(*vop_plane_state), GFP_KERNEL);
1199 if (!vop_plane_state)
1202 __drm_atomic_helper_plane_duplicate_state(plane,
1203 &vop_plane_state->base);
1205 return &vop_plane_state->base;
1208 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1209 struct drm_plane_state *state)
1211 struct vop_plane_state *vop_state = to_vop_plane_state(state);
1213 __drm_atomic_helper_plane_destroy_state(plane, state);
1218 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1219 struct drm_plane_state *state,
1220 struct drm_property *property,
1223 struct vop_win *win = to_vop_win(plane);
1224 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1226 if (property == win->vop->plane_zpos_prop) {
1227 plane_state->zpos = val;
1231 if (property == win->rotation_prop) {
1232 state->rotation = val;
1236 DRM_ERROR("failed to set vop plane property\n");
1240 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1241 const struct drm_plane_state *state,
1242 struct drm_property *property,
1245 struct vop_win *win = to_vop_win(plane);
1246 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1248 if (property == win->vop->plane_zpos_prop) {
1249 *val = plane_state->zpos;
1253 if (property == win->rotation_prop) {
1254 *val = state->rotation;
1258 DRM_ERROR("failed to get vop plane property\n");
1262 static const struct drm_plane_funcs vop_plane_funcs = {
1263 .update_plane = drm_atomic_helper_update_plane,
1264 .disable_plane = drm_atomic_helper_disable_plane,
1265 .destroy = vop_plane_destroy,
1266 .reset = vop_atomic_plane_reset,
1267 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1268 .atomic_destroy_state = vop_atomic_plane_destroy_state,
1269 .atomic_set_property = vop_atomic_plane_set_property,
1270 .atomic_get_property = vop_atomic_plane_get_property,
1273 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1275 struct vop *vop = to_vop(crtc);
1276 unsigned long flags;
1278 if (!vop->is_enabled)
1281 spin_lock_irqsave(&vop->irq_lock, flags);
1283 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1284 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1286 spin_unlock_irqrestore(&vop->irq_lock, flags);
1291 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1293 struct vop *vop = to_vop(crtc);
1294 unsigned long flags;
1296 if (!vop->is_enabled)
1299 spin_lock_irqsave(&vop->irq_lock, flags);
1301 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1303 spin_unlock_irqrestore(&vop->irq_lock, flags);
1306 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1308 struct vop *vop = to_vop(crtc);
1310 reinit_completion(&vop->wait_update_complete);
1311 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1314 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1315 struct drm_file *file_priv)
1317 struct drm_device *drm = crtc->dev;
1318 struct vop *vop = to_vop(crtc);
1319 struct drm_pending_vblank_event *e;
1320 unsigned long flags;
1322 spin_lock_irqsave(&drm->event_lock, flags);
1324 if (e && e->base.file_priv == file_priv) {
1327 e->base.destroy(&e->base);
1328 file_priv->event_space += sizeof(e->event);
1330 spin_unlock_irqrestore(&drm->event_lock, flags);
1333 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1335 struct vop *vop = to_vop(crtc);
1337 if (on == vop->loader_protect)
1341 vop_power_enable(crtc);
1342 enable_irq(vop->irq);
1343 drm_crtc_vblank_on(crtc);
1344 vop->loader_protect = true;
1346 vop_crtc_disable(crtc);
1348 vop->loader_protect = false;
1354 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1356 struct vop_win *win = to_vop_win(plane);
1357 struct drm_plane_state *state = plane->state;
1358 struct vop_plane_state *pstate = to_vop_plane_state(state);
1359 struct drm_rect *src, *dest;
1360 struct drm_framebuffer *fb = state->fb;
1363 seq_printf(s, " win%d-%d: %s\n", win->win_id, win->area_id,
1364 pstate->enable ? "ACTIVE" : "DISABLED");
1369 dest = &pstate->dest;
1371 seq_printf(s, "\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1372 fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1373 seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1374 seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1375 src->y1 >> 16, drm_rect_width(src) >> 16,
1376 drm_rect_height(src) >> 16);
1377 seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1378 drm_rect_width(dest), drm_rect_height(dest));
1380 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1381 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1382 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1383 i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1389 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1391 struct vop *vop = to_vop(crtc);
1392 struct drm_crtc_state *crtc_state = crtc->state;
1393 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1394 struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1395 bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1396 struct drm_plane *plane;
1399 seq_printf(s, "VOP [%s]: %s\n", dev_name(vop->dev),
1400 crtc_state->active ? "ACTIVE" : "DISABLED");
1402 if (!crtc_state->active)
1405 seq_printf(s, " Connector: %s\n",
1406 drm_get_connector_name(state->output_type));
1407 seq_printf(s, "\tbus_format[%x] output_mode[%x]\n",
1408 state->bus_format, state->output_mode);
1409 seq_printf(s, " Display mode: %dx%d%s%d\n",
1410 mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1411 drm_mode_vrefresh(mode));
1412 seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1413 mode->clock, mode->crtc_clock, mode->type, mode->flags);
1414 seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1415 mode->hsync_end, mode->htotal);
1416 seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1417 mode->vsync_end, mode->vtotal);
1419 for (i = 0; i < vop->num_wins; i++) {
1420 plane = &vop->win[i].base;
1421 vop_plane_info_dump(s, plane);
1427 static enum drm_mode_status
1428 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1431 struct vop *vop = to_vop(crtc);
1432 const struct vop_data *vop_data = vop->data;
1433 int request_clock = mode->clock;
1436 if (mode->hdisplay > vop_data->max_output.width)
1437 return MODE_BAD_HVALUE;
1438 if (mode->vdisplay > vop_data->max_output.height)
1439 return MODE_BAD_VVALUE;
1441 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1443 clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1446 * Hdmi or DisplayPort request a Accurate clock.
1448 if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1449 output_type == DRM_MODE_CONNECTOR_DisplayPort)
1450 if (clock != request_clock)
1451 return MODE_CLOCK_RANGE;
1456 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1457 .loader_protect = vop_crtc_loader_protect,
1458 .enable_vblank = vop_crtc_enable_vblank,
1459 .disable_vblank = vop_crtc_disable_vblank,
1460 .wait_for_update = vop_crtc_wait_for_update,
1461 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1462 .debugfs_dump = vop_crtc_debugfs_dump,
1463 .mode_valid = vop_crtc_mode_valid,
1466 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1467 const struct drm_display_mode *mode,
1468 struct drm_display_mode *adj_mode)
1470 struct vop *vop = to_vop(crtc);
1471 const struct vop_data *vop_data = vop->data;
1473 if (mode->hdisplay > vop_data->max_output.width ||
1474 mode->vdisplay > vop_data->max_output.height)
1477 drm_mode_set_crtcinfo(adj_mode,
1478 CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1480 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1481 adj_mode->crtc_clock *= 2;
1483 adj_mode->crtc_clock =
1484 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1489 static void vop_crtc_enable(struct drm_crtc *crtc)
1491 struct vop *vop = to_vop(crtc);
1492 const struct vop_data *vop_data = vop->data;
1493 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1494 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1495 u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1496 u16 hdisplay = adjusted_mode->crtc_hdisplay;
1497 u16 htotal = adjusted_mode->crtc_htotal;
1498 u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1499 u16 hact_end = hact_st + hdisplay;
1500 u16 vdisplay = adjusted_mode->crtc_vdisplay;
1501 u16 vtotal = adjusted_mode->crtc_vtotal;
1502 u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1503 u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1504 u16 vact_end = vact_st + vdisplay;
1509 val = BIT(DCLK_INVERT);
1510 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1511 0 : BIT(HSYNC_POSITIVE);
1512 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1513 0 : BIT(VSYNC_POSITIVE);
1514 VOP_CTRL_SET(vop, pin_pol, val);
1515 switch (s->output_type) {
1516 case DRM_MODE_CONNECTOR_LVDS:
1517 VOP_CTRL_SET(vop, rgb_en, 1);
1518 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1520 case DRM_MODE_CONNECTOR_eDP:
1521 VOP_CTRL_SET(vop, edp_en, 1);
1522 VOP_CTRL_SET(vop, edp_pin_pol, val);
1524 case DRM_MODE_CONNECTOR_HDMIA:
1525 VOP_CTRL_SET(vop, hdmi_en, 1);
1526 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1528 case DRM_MODE_CONNECTOR_DSI:
1529 VOP_CTRL_SET(vop, mipi_en, 1);
1530 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1532 case DRM_MODE_CONNECTOR_DisplayPort:
1533 val &= ~BIT(DCLK_INVERT);
1534 VOP_CTRL_SET(vop, dp_pin_pol, val);
1535 VOP_CTRL_SET(vop, dp_en, 1);
1538 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1541 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1542 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1543 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1545 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1546 switch (s->bus_format) {
1547 case MEDIA_BUS_FMT_RGB565_1X16:
1548 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1550 case MEDIA_BUS_FMT_RGB666_1X18:
1551 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1552 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1554 case MEDIA_BUS_FMT_YUV8_1X24:
1555 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1557 case MEDIA_BUS_FMT_YUV10_1X30:
1558 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1560 case MEDIA_BUS_FMT_RGB888_1X24:
1562 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1566 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1567 val |= PRE_DITHER_DOWN_EN(0);
1569 val |= PRE_DITHER_DOWN_EN(1);
1570 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1571 VOP_CTRL_SET(vop, dither_down, val);
1572 VOP_CTRL_SET(vop, dclk_ddr,
1573 s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1574 VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1575 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1576 VOP_CTRL_SET(vop, dsp_background,
1577 is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1579 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1580 val = hact_st << 16;
1582 VOP_CTRL_SET(vop, hact_st_end, val);
1583 VOP_CTRL_SET(vop, hpost_st_end, val);
1585 val = vact_st << 16;
1587 VOP_CTRL_SET(vop, vact_st_end, val);
1588 VOP_CTRL_SET(vop, vpost_st_end, val);
1589 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1590 u16 vact_st_f1 = vtotal + vact_st + 1;
1591 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1593 val = vact_st_f1 << 16 | vact_end_f1;
1594 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1595 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1597 val = vtotal << 16 | (vtotal + vsync_len);
1598 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1599 VOP_CTRL_SET(vop, dsp_interlace, 1);
1600 VOP_CTRL_SET(vop, p2i_en, 1);
1601 vtotal = vtotal + 1;
1603 VOP_CTRL_SET(vop, dsp_interlace, 0);
1604 VOP_CTRL_SET(vop, p2i_en, 0);
1606 VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1608 VOP_CTRL_SET(vop, core_dclk_div,
1609 !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1611 clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1615 * enable vop, all the register would take effect when vop exit standby
1617 VOP_CTRL_SET(vop, standby, 0);
1619 enable_irq(vop->irq);
1620 drm_crtc_vblank_on(crtc);
1623 static int vop_zpos_cmp(const void *a, const void *b)
1625 struct vop_zpos *pa = (struct vop_zpos *)a;
1626 struct vop_zpos *pb = (struct vop_zpos *)b;
1628 return pa->zpos - pb->zpos;
1631 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1632 struct drm_crtc_state *crtc_state)
1634 struct vop *vop = to_vop(crtc);
1635 const struct vop_data *vop_data = vop->data;
1636 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1637 struct drm_atomic_state *state = crtc_state->state;
1638 struct drm_plane *plane;
1639 struct drm_plane_state *pstate;
1640 struct vop_plane_state *plane_state;
1641 struct vop_win *win;
1647 for_each_plane_in_state(state, plane, pstate, i) {
1648 struct drm_framebuffer *fb = pstate->fb;
1649 struct drm_rect *src;
1651 win = to_vop_win(plane);
1652 plane_state = to_vop_plane_state(pstate);
1654 if (pstate->crtc != crtc || !fb)
1657 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1660 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1661 DRM_ERROR("not support afbdc\n");
1665 switch (plane_state->format) {
1666 case VOP_FMT_ARGB8888:
1667 afbdc_format = AFBDC_FMT_U8U8U8U8;
1669 case VOP_FMT_RGB888:
1670 afbdc_format = AFBDC_FMT_U8U8U8;
1672 case VOP_FMT_RGB565:
1673 afbdc_format = AFBDC_FMT_RGB565;
1680 DRM_ERROR("vop only support one afbc layer\n");
1684 src = &plane_state->src;
1685 if (src->x1 || src->y1 || fb->offsets[0]) {
1686 DRM_ERROR("win[%d] afbdc not support offset display\n",
1688 DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1689 src->x1, src->y1, fb->offsets[0]);
1692 s->afbdc_win_format = afbdc_format;
1693 s->afbdc_win_width = pstate->fb->width - 1;
1694 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1695 s->afbdc_win_id = win->win_id;
1696 s->afbdc_win_ptr = plane_state->yrgb_mst;
1703 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1704 struct drm_crtc_state *crtc_state)
1706 struct drm_atomic_state *state = crtc_state->state;
1707 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1708 struct vop *vop = to_vop(crtc);
1709 const struct vop_data *vop_data = vop->data;
1710 struct drm_plane *plane;
1711 struct drm_plane_state *pstate;
1712 struct vop_plane_state *plane_state;
1713 struct vop_zpos *pzpos;
1714 int dsp_layer_sel = 0;
1715 int i, j, cnt = 0, ret = 0;
1717 ret = vop_afbdc_atomic_check(crtc, crtc_state);
1721 ret = vop_csc_atomic_check(crtc, crtc_state);
1725 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1729 for (i = 0; i < vop_data->win_size; i++) {
1730 const struct vop_win_data *win_data = &vop_data->win[i];
1731 struct vop_win *win;
1736 for (j = 0; j < vop->num_wins; j++) {
1739 if (win->win_id == i && !win->area_id)
1742 if (WARN_ON(j >= vop->num_wins)) {
1744 goto err_free_pzpos;
1748 pstate = state->plane_states[drm_plane_index(plane)];
1750 * plane might not have changed, in which case take
1754 pstate = plane->state;
1755 plane_state = to_vop_plane_state(pstate);
1756 pzpos[cnt].zpos = plane_state->zpos;
1757 pzpos[cnt++].win_id = win->win_id;
1760 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1762 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1763 const struct vop_win_data *win_data = &vop_data->win[i];
1766 if (win_data->phy) {
1767 struct vop_zpos *zpos = &pzpos[cnt++];
1769 dsp_layer_sel |= zpos->win_id << shift;
1771 dsp_layer_sel |= i << shift;
1775 s->dsp_layer_sel = dsp_layer_sel;
1782 static void vop_post_config(struct drm_crtc *crtc)
1784 struct vop *vop = to_vop(crtc);
1785 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1786 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1787 u16 vtotal = mode->crtc_vtotal;
1788 u16 hdisplay = mode->crtc_hdisplay;
1789 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1790 u16 vdisplay = mode->crtc_vdisplay;
1791 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1792 u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1793 u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1794 u16 hact_end, vact_end;
1797 hact_st += hdisplay * (100 - s->left_margin) / 200;
1798 hact_end = hact_st + hsize;
1799 val = hact_st << 16;
1801 VOP_CTRL_SET(vop, hpost_st_end, val);
1802 vact_st += vdisplay * (100 - s->top_margin) / 200;
1803 vact_end = vact_st + vsize;
1804 val = vact_st << 16;
1806 VOP_CTRL_SET(vop, vpost_st_end, val);
1807 val = scl_cal_scale2(vdisplay, vsize) << 16;
1808 val |= scl_cal_scale2(hdisplay, hsize);
1809 VOP_CTRL_SET(vop, post_scl_factor, val);
1810 VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1811 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1812 u16 vact_st_f1 = vtotal + vact_st + 1;
1813 u16 vact_end_f1 = vact_st_f1 + vsize;
1815 val = vact_st_f1 << 16 | vact_end_f1;
1816 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1820 static void vop_cfg_update(struct drm_crtc *crtc,
1821 struct drm_crtc_state *old_crtc_state)
1823 struct rockchip_crtc_state *s =
1824 to_rockchip_crtc_state(crtc->state);
1825 struct vop *vop = to_vop(crtc);
1827 spin_lock(&vop->reg_lock);
1832 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1833 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1834 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1835 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1836 pic_size = (s->afbdc_win_width & 0xffff);
1837 pic_size |= s->afbdc_win_height << 16;
1838 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1841 VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1842 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1843 vop_post_config(crtc);
1845 spin_unlock(&vop->reg_lock);
1848 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1849 struct drm_crtc_state *old_crtc_state)
1851 struct vop *vop = to_vop(crtc);
1853 vop_cfg_update(crtc, old_crtc_state);
1855 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1856 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1859 if (need_wait_vblank) {
1862 disable_irq(vop->irq);
1863 drm_crtc_vblank_get(crtc);
1864 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1866 ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1867 vop, active, active,
1870 dev_err(vop->dev, "wait fs irq timeout\n");
1872 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1875 ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1876 vop, active, active,
1879 dev_err(vop->dev, "wait line flag timeout\n");
1881 enable_irq(vop->irq);
1883 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1885 dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1888 if (need_wait_vblank) {
1889 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1890 drm_crtc_vblank_put(crtc);
1893 vop->is_iommu_enabled = true;
1899 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1900 struct drm_crtc_state *old_crtc_state)
1902 struct vop *vop = to_vop(crtc);
1904 if (crtc->state->event) {
1905 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1907 vop->event = crtc->state->event;
1908 crtc->state->event = NULL;
1912 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1913 .enable = vop_crtc_enable,
1914 .disable = vop_crtc_disable,
1915 .mode_fixup = vop_crtc_mode_fixup,
1916 .atomic_check = vop_crtc_atomic_check,
1917 .atomic_flush = vop_crtc_atomic_flush,
1918 .atomic_begin = vop_crtc_atomic_begin,
1921 static void vop_crtc_destroy(struct drm_crtc *crtc)
1923 drm_crtc_cleanup(crtc);
1926 static void vop_crtc_reset(struct drm_crtc *crtc)
1928 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1931 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1935 s = kzalloc(sizeof(*s), GFP_KERNEL);
1938 crtc->state = &s->base;
1939 crtc->state->crtc = crtc;
1940 s->left_margin = 100;
1941 s->right_margin = 100;
1942 s->top_margin = 100;
1943 s->bottom_margin = 100;
1946 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1948 struct rockchip_crtc_state *rockchip_state, *old_state;
1950 old_state = to_rockchip_crtc_state(crtc->state);
1951 rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1952 if (!rockchip_state)
1955 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1956 return &rockchip_state->base;
1959 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1960 struct drm_crtc_state *state)
1962 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1964 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1968 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
1969 const struct drm_crtc_state *state,
1970 struct drm_property *property,
1973 struct drm_device *drm_dev = crtc->dev;
1974 struct drm_mode_config *mode_config = &drm_dev->mode_config;
1975 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1977 if (property == mode_config->tv_left_margin_property) {
1978 *val = s->left_margin;
1982 if (property == mode_config->tv_right_margin_property) {
1983 *val = s->right_margin;
1987 if (property == mode_config->tv_top_margin_property) {
1988 *val = s->top_margin;
1992 if (property == mode_config->tv_bottom_margin_property) {
1993 *val = s->bottom_margin;
1997 DRM_ERROR("failed to get vop crtc property\n");
2001 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2002 struct drm_crtc_state *state,
2003 struct drm_property *property,
2006 struct drm_device *drm_dev = crtc->dev;
2007 struct drm_mode_config *mode_config = &drm_dev->mode_config;
2008 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2010 if (property == mode_config->tv_left_margin_property) {
2011 s->left_margin = val;
2015 if (property == mode_config->tv_right_margin_property) {
2016 s->right_margin = val;
2020 if (property == mode_config->tv_top_margin_property) {
2021 s->top_margin = val;
2025 if (property == mode_config->tv_bottom_margin_property) {
2026 s->bottom_margin = val;
2030 DRM_ERROR("failed to set vop crtc property\n");
2034 static const struct drm_crtc_funcs vop_crtc_funcs = {
2035 .set_config = drm_atomic_helper_set_config,
2036 .page_flip = drm_atomic_helper_page_flip,
2037 .destroy = vop_crtc_destroy,
2038 .reset = vop_crtc_reset,
2039 .atomic_get_property = vop_crtc_atomic_get_property,
2040 .atomic_set_property = vop_crtc_atomic_set_property,
2041 .atomic_duplicate_state = vop_crtc_duplicate_state,
2042 .atomic_destroy_state = vop_crtc_destroy_state,
2045 static void vop_handle_vblank(struct vop *vop)
2047 struct drm_device *drm = vop->drm_dev;
2048 struct drm_crtc *crtc = &vop->crtc;
2049 unsigned long flags;
2051 if (!vop_is_cfg_done_complete(vop))
2055 spin_lock_irqsave(&drm->event_lock, flags);
2057 drm_crtc_send_vblank_event(crtc, vop->event);
2058 drm_crtc_vblank_put(crtc);
2061 spin_unlock_irqrestore(&drm->event_lock, flags);
2063 if (!completion_done(&vop->wait_update_complete))
2064 complete(&vop->wait_update_complete);
2067 static irqreturn_t vop_isr(int irq, void *data)
2069 struct vop *vop = data;
2070 struct drm_crtc *crtc = &vop->crtc;
2071 uint32_t active_irqs;
2072 unsigned long flags;
2076 * interrupt register has interrupt status, enable and clear bits, we
2077 * must hold irq_lock to avoid a race with enable/disable_vblank().
2079 spin_lock_irqsave(&vop->irq_lock, flags);
2081 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2082 /* Clear all active interrupt sources */
2084 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2086 spin_unlock_irqrestore(&vop->irq_lock, flags);
2088 /* This is expected for vop iommu irqs, since the irq is shared */
2092 if (active_irqs & DSP_HOLD_VALID_INTR) {
2093 complete(&vop->dsp_hold_completion);
2094 active_irqs &= ~DSP_HOLD_VALID_INTR;
2098 if (active_irqs & LINE_FLAG_INTR) {
2099 complete(&vop->line_flag_completion);
2100 active_irqs &= ~LINE_FLAG_INTR;
2104 if (active_irqs & FS_INTR) {
2105 drm_crtc_handle_vblank(crtc);
2106 vop_handle_vblank(vop);
2107 active_irqs &= ~FS_INTR;
2111 /* Unhandled irqs are spurious. */
2113 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2118 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2119 unsigned long possible_crtcs)
2121 struct drm_plane *share = NULL;
2122 unsigned int rotations = 0;
2123 struct drm_property *prop;
2124 uint64_t feature = 0;
2128 share = &win->parent->base;
2130 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2131 possible_crtcs, &vop_plane_funcs,
2132 win->data_formats, win->nformats, win->type);
2134 DRM_ERROR("failed to initialize plane\n");
2137 drm_plane_helper_add(&win->base, &plane_helper_funcs);
2138 drm_object_attach_property(&win->base.base,
2139 vop->plane_zpos_prop, win->win_id);
2141 if (VOP_WIN_SUPPORT(vop, win, xmirror))
2142 rotations |= BIT(DRM_REFLECT_X);
2144 if (VOP_WIN_SUPPORT(vop, win, ymirror))
2145 rotations |= BIT(DRM_REFLECT_Y);
2148 rotations |= BIT(DRM_ROTATE_0);
2149 prop = drm_mode_create_rotation_property(vop->drm_dev,
2152 DRM_ERROR("failed to create zpos property\n");
2155 drm_object_attach_property(&win->base.base, prop,
2157 win->rotation_prop = prop;
2160 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2161 if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2162 VOP_WIN_SUPPORT(vop, win, alpha_en))
2163 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2165 drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2171 static int vop_create_crtc(struct vop *vop)
2173 struct device *dev = vop->dev;
2174 const struct vop_data *vop_data = vop->data;
2175 struct drm_device *drm_dev = vop->drm_dev;
2176 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2177 struct drm_crtc *crtc = &vop->crtc;
2178 struct device_node *port;
2179 uint64_t feature = 0;
2184 * Create drm_plane for primary and cursor planes first, since we need
2185 * to pass them to drm_crtc_init_with_planes, which sets the
2186 * "possible_crtcs" to the newly initialized crtc.
2188 for (i = 0; i < vop->num_wins; i++) {
2189 struct vop_win *win = &vop->win[i];
2191 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2192 win->type != DRM_PLANE_TYPE_CURSOR)
2195 ret = vop_plane_init(vop, win, 0);
2197 goto err_cleanup_planes;
2200 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2202 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2207 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2208 &vop_crtc_funcs, NULL);
2210 goto err_cleanup_planes;
2212 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2215 * Create drm_planes for overlay windows with possible_crtcs restricted
2216 * to the newly created crtc.
2218 for (i = 0; i < vop->num_wins; i++) {
2219 struct vop_win *win = &vop->win[i];
2220 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2222 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2225 ret = vop_plane_init(vop, win, possible_crtcs);
2227 goto err_cleanup_crtc;
2230 port = of_get_child_by_name(dev->of_node, "port");
2232 DRM_ERROR("no port node found in %s\n",
2233 dev->of_node->full_name);
2235 goto err_cleanup_crtc;
2238 init_completion(&vop->dsp_hold_completion);
2239 init_completion(&vop->wait_update_complete);
2240 init_completion(&vop->line_flag_completion);
2242 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2244 ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2246 goto err_unregister_crtc_funcs;
2247 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2248 drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2250 VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2251 VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2252 VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2253 VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2254 #undef VOP_ATTACH_MODE_CONFIG_PROP
2256 if (vop_data->feature & VOP_FEATURE_AFBDC)
2257 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2258 drm_object_attach_property(&crtc->base, vop->feature_prop,
2263 err_unregister_crtc_funcs:
2264 rockchip_unregister_crtc_funcs(crtc);
2266 drm_crtc_cleanup(crtc);
2268 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2270 drm_plane_cleanup(plane);
2274 static void vop_destroy_crtc(struct vop *vop)
2276 struct drm_crtc *crtc = &vop->crtc;
2277 struct drm_device *drm_dev = vop->drm_dev;
2278 struct drm_plane *plane, *tmp;
2280 rockchip_unregister_crtc_funcs(crtc);
2281 of_node_put(crtc->port);
2284 * We need to cleanup the planes now. Why?
2286 * The planes are "&vop->win[i].base". That means the memory is
2287 * all part of the big "struct vop" chunk of memory. That memory
2288 * was devm allocated and associated with this component. We need to
2289 * free it ourselves before vop_unbind() finishes.
2291 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2293 vop_plane_destroy(plane);
2296 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2297 * references the CRTC.
2299 drm_crtc_cleanup(crtc);
2303 * Initialize the vop->win array elements.
2305 static int vop_win_init(struct vop *vop)
2307 const struct vop_data *vop_data = vop->data;
2309 unsigned int num_wins = 0;
2310 struct drm_property *prop;
2311 static const struct drm_prop_enum_list props[] = {
2312 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2313 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2315 static const struct drm_prop_enum_list crtc_props[] = {
2316 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2319 for (i = 0; i < vop_data->win_size; i++) {
2320 struct vop_win *vop_win = &vop->win[num_wins];
2321 const struct vop_win_data *win_data = &vop_data->win[i];
2326 vop_win->phy = win_data->phy;
2327 vop_win->csc = win_data->csc;
2328 vop_win->offset = win_data->base;
2329 vop_win->type = win_data->type;
2330 vop_win->data_formats = win_data->phy->data_formats;
2331 vop_win->nformats = win_data->phy->nformats;
2333 vop_win->win_id = i;
2334 vop_win->area_id = 0;
2337 for (j = 0; j < win_data->area_size; j++) {
2338 struct vop_win *vop_area = &vop->win[num_wins];
2339 const struct vop_win_phy *area = win_data->area[j];
2341 vop_area->parent = vop_win;
2342 vop_area->offset = vop_win->offset;
2343 vop_area->phy = area;
2344 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2345 vop_area->data_formats = vop_win->data_formats;
2346 vop_area->nformats = vop_win->nformats;
2347 vop_area->vop = vop;
2348 vop_area->win_id = i;
2349 vop_area->area_id = j;
2354 vop->num_wins = num_wins;
2356 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2357 "ZPOS", 0, vop->data->win_size);
2359 DRM_ERROR("failed to create zpos property\n");
2362 vop->plane_zpos_prop = prop;
2364 vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2365 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2366 props, ARRAY_SIZE(props),
2367 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2368 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2369 if (!vop->plane_feature_prop) {
2370 DRM_ERROR("failed to create feature property\n");
2374 vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2375 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2376 crtc_props, ARRAY_SIZE(crtc_props),
2377 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2378 if (!vop->feature_prop) {
2379 DRM_ERROR("failed to create vop feature property\n");
2387 * rockchip_drm_wait_line_flag - acqiure the give line flag event
2388 * @crtc: CRTC to enable line flag
2389 * @line_num: interested line number
2390 * @mstimeout: millisecond for timeout
2392 * Driver would hold here until the interested line flag interrupt have
2393 * happened or timeout to wait.
2396 * Zero on success, negative errno on failure.
2398 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2399 unsigned int mstimeout)
2401 struct vop *vop = to_vop(crtc);
2402 unsigned long jiffies_left;
2404 if (!crtc || !vop->is_enabled)
2407 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2410 if (vop_line_flag_irq_is_enabled(vop))
2413 reinit_completion(&vop->line_flag_completion);
2414 vop_line_flag_irq_enable(vop, line_num);
2416 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2417 msecs_to_jiffies(mstimeout));
2418 vop_line_flag_irq_disable(vop);
2420 if (jiffies_left == 0) {
2421 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2427 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2429 static int vop_bind(struct device *dev, struct device *master, void *data)
2431 struct platform_device *pdev = to_platform_device(dev);
2432 const struct vop_data *vop_data;
2433 struct drm_device *drm_dev = data;
2435 struct resource *res;
2440 vop_data = of_device_get_match_data(dev);
2444 for (i = 0; i < vop_data->win_size; i++) {
2445 const struct vop_win_data *win_data = &vop_data->win[i];
2447 num_wins += win_data->area_size + 1;
2450 /* Allocate vop struct and its vop_win array */
2451 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2452 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2457 vop->data = vop_data;
2458 vop->drm_dev = drm_dev;
2459 vop->num_wins = num_wins;
2460 dev_set_drvdata(dev, vop);
2462 ret = vop_win_init(vop);
2466 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2467 vop->len = resource_size(res);
2468 vop->regs = devm_ioremap_resource(dev, res);
2469 if (IS_ERR(vop->regs))
2470 return PTR_ERR(vop->regs);
2472 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2476 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2477 if (IS_ERR(vop->hclk)) {
2478 dev_err(vop->dev, "failed to get hclk source\n");
2479 return PTR_ERR(vop->hclk);
2481 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2482 if (IS_ERR(vop->aclk)) {
2483 dev_err(vop->dev, "failed to get aclk source\n");
2484 return PTR_ERR(vop->aclk);
2486 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2487 if (IS_ERR(vop->dclk)) {
2488 dev_err(vop->dev, "failed to get dclk source\n");
2489 return PTR_ERR(vop->dclk);
2492 irq = platform_get_irq(pdev, 0);
2494 dev_err(dev, "cannot find irq for vop\n");
2497 vop->irq = (unsigned int)irq;
2499 spin_lock_init(&vop->reg_lock);
2500 spin_lock_init(&vop->irq_lock);
2502 mutex_init(&vop->vsync_mutex);
2504 ret = devm_request_irq(dev, vop->irq, vop_isr,
2505 IRQF_SHARED, dev_name(dev), vop);
2509 /* IRQ is initially disabled; it gets enabled in power_on */
2510 disable_irq(vop->irq);
2512 ret = vop_create_crtc(vop);
2516 pm_runtime_enable(&pdev->dev);
2520 static void vop_unbind(struct device *dev, struct device *master, void *data)
2522 struct vop *vop = dev_get_drvdata(dev);
2524 pm_runtime_disable(dev);
2525 vop_destroy_crtc(vop);
2528 const struct component_ops vop_component_ops = {
2530 .unbind = vop_unbind,
2532 EXPORT_SYMBOL_GPL(vop_component_ops);