drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/devfreq.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/component.h>
  32
  33 #include <linux/reset.h>
  34 #include <linux/delay.h>
  35 #include <linux/sort.h>
  36 #include <uapi/drm/rockchip_drm.h>
  37
  38 #include "rockchip_drm_drv.h"
  39 #include "rockchip_drm_gem.h"
  40 #include "rockchip_drm_fb.h"
  41 #include "rockchip_drm_vop.h"
  42
  43 #define VOP_REG_SUPPORT(vop, reg) \
  44                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  45                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  46                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  47                 reg.mask))
  48
  49 #define VOP_WIN_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, win->phy->name)
  51
  52 #define VOP_CTRL_SUPPORT(vop, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  54
  55 #define VOP_INTR_SUPPORT(vop, name) \
  56                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  57
  58 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  59                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  60
  61 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  62         do { \
  63                 if (VOP_REG_SUPPORT(vop, reg)) \
  64                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  65                                   v, reg.write_mask, relaxed); \
  66                 else \
  67                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  68         } while(0)
  69
  70 #define REG_SET(x, name, off, reg, v, relaxed) \
  71                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  72 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  73                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  74
  75 #define VOP_WIN_SET(x, win, name, v) \
  76                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  77 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  78                 REG_SET(x, name, 0, win->ext->name, v, true)
  79 #define VOP_SCL_SET(x, win, name, v) \
  80                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  81 #define VOP_SCL_SET_EXT(x, win, name, v) \
  82                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  83
  84 #define VOP_CTRL_SET(x, name, v) \
  85                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  86
  87 #define VOP_INTR_GET(vop, name) \
  88                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  89
  90 #define VOP_INTR_SET(vop, name, v) \
  91                 REG_SET(vop, name, 0, vop->data->intr->name, \
  92                         v, false)
  93 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  94                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  95                              mask, v, false)
  96
  97 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  98         do { \
  99                 int i, reg = 0, mask = 0; \
 100                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 101                         if (vop->data->intr->intrs[i] & type) { \
 102                                 reg |= (v) << i; \
 103                                 mask |= 1 << i; \
 104                         } \
 105                 } \
 106                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 107         } while (0)
 108 #define VOP_INTR_GET_TYPE(vop, name, type) \
 109                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 110
 111 #define VOP_CTRL_GET(x, name) \
 112                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 113
 114 #define VOP_WIN_GET(x, win, name) \
 115                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 116
 117 #define VOP_WIN_NAME(win, name) \
 118                 (vop_get_win_phy(win, &win->phy->name)->name)
 119
 120 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 121                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 122
 123 #define to_vop(x) container_of(x, struct vop, crtc)
 124 #define to_vop_win(x) container_of(x, struct vop_win, base)
 125 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 126
 127 struct vop_zpos {
 128         int win_id;
 129         int zpos;
 130 };
 131
 132 struct vop_plane_state {
 133         struct drm_plane_state base;
 134         int format;
 135         int zpos;
 136         unsigned int logo_ymirror;
 137         struct drm_rect src;
 138         struct drm_rect dest;
 139         dma_addr_t yrgb_mst;
 140         dma_addr_t uv_mst;
 141         const uint32_t *y2r_table;
 142         const uint32_t *r2r_table;
 143         const uint32_t *r2y_table;
 144         bool enable;
 145 };
 146
 147 struct vop_win {
 148         struct vop_win *parent;
 149         struct drm_plane base;
 150
 151         int win_id;
 152         int area_id;
 153         uint32_t offset;
 154         enum drm_plane_type type;
 155         const struct vop_win_phy *phy;
 156         const struct vop_csc *csc;
 157         const uint32_t *data_formats;
 158         uint32_t nformats;
 159         struct vop *vop;
 160
 161         struct drm_property *rotation_prop;
 162         struct vop_plane_state state;
 163 };
 164
 165 struct vop {
 166         struct drm_crtc crtc;
 167         struct device *dev;
 168         struct drm_device *drm_dev;
 169         struct drm_property *plane_zpos_prop;
 170         struct drm_property *plane_feature_prop;
 171         struct drm_property *feature_prop;
 172         bool is_iommu_enabled;
 173         bool is_iommu_needed;
 174         bool is_enabled;
 175
 176         /* mutex vsync_ work */
 177         struct mutex vsync_mutex;
 178         bool vsync_work_pending;
 179         bool loader_protect;
 180         struct completion dsp_hold_completion;
 181         struct completion wait_update_complete;
 182         struct drm_pending_vblank_event *event;
 183
 184         struct completion line_flag_completion;
 185
 186         const struct vop_data *data;
 187         int num_wins;
 188
 189         uint32_t *regsbak;
 190         void __iomem *regs;
 191
 192         /* physical map length of vop register */
 193         uint32_t len;
 194
 195         void __iomem *lut_regs;
 196         u32 *lut;
 197         u32 lut_len;
 198         bool lut_active;
 199
 200         /* one time only one process allowed to config the register */
 201         spinlock_t reg_lock;
 202         /* lock vop irq reg */
 203         spinlock_t irq_lock;
 204         /* mutex vop enable and disable */
 205         struct mutex vop_lock;
 206
 207         unsigned int irq;
 208
 209         /* vop AHP clk */
 210         struct clk *hclk;
 211         /* vop dclk */
 212         struct clk *dclk;
 213         /* vop share memory frequency */
 214         struct clk *aclk;
 215
 216         /* vop dclk reset */
 217         struct reset_control *dclk_rst;
 218
 219         struct devfreq *devfreq;
 220         struct notifier_block dmc_nb;
 221
 222         struct vop_win win[];
 223 };
 224
 225 struct vop *dmc_vop;
 226
 227 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 228 {
 229         writel(v, vop->regs + offset);
 230         vop->regsbak[offset >> 2] = v;
 231 }
 232
 233 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 234 {
 235         return readl(vop->regs + offset);
 236 }
 237
 238 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 239                                     const struct vop_reg *reg)
 240 {
 241         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 242 }
 243
 244 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 245                                   uint32_t mask, uint32_t shift, uint32_t v,
 246                                   bool write_mask, bool relaxed)
 247 {
 248         if (!mask)
 249                 return;
 250
 251         if (write_mask) {
 252                 v = ((v & mask) << shift) | (mask << (shift + 16));
 253         } else {
 254                 uint32_t cached_val = vop->regsbak[offset >> 2];
 255
 256                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 257                 vop->regsbak[offset >> 2] = v;
 258         }
 259
 260         if (relaxed)
 261                 writel_relaxed(v, vop->regs + offset);
 262         else
 263                 writel(v, vop->regs + offset);
 264 }
 265
 266 static inline const struct vop_win_phy *
 267 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 268 {
 269         if (!reg->mask && win->parent)
 270                 return win->parent->phy;
 271
 272         return win->phy;
 273 }
 274
 275 static inline uint32_t vop_get_intr_type(struct vop *vop,
 276                                          const struct vop_reg *reg, int type)
 277 {
 278         uint32_t i, ret = 0;
 279         uint32_t regs = vop_read_reg(vop, 0, reg);
 280
 281         for (i = 0; i < vop->data->intr->nintrs; i++) {
 282                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 283                         ret |= vop->data->intr->intrs[i];
 284         }
 285
 286         return ret;
 287 }
 288
 289 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 290 {
 291         int i;
 292
 293         if (!table)
 294                 return;
 295
 296         for (i = 0; i < 8; i++)
 297                 vop_writel(vop, offset + i * 4, table[i]);
 298 }
 299
 300 static inline void vop_cfg_done(struct vop *vop)
 301 {
 302         VOP_CTRL_SET(vop, cfg_done, 1);
 303 }
 304
 305 static bool vop_is_allwin_disabled(struct vop *vop)
 306 {
 307         int i;
 308
 309         for (i = 0; i < vop->num_wins; i++) {
 310                 struct vop_win *win = &vop->win[i];
 311
 312                 if (VOP_WIN_GET(vop, win, enable) != 0)
 313                         return false;
 314         }
 315
 316         return true;
 317 }
 318
 319 static bool vop_is_cfg_done_complete(struct vop *vop)
 320 {
 321         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 322 }
 323
 324 static bool vop_fs_irq_is_active(struct vop *vop)
 325 {
 326         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 327 }
 328
 329 static bool vop_line_flag_is_active(struct vop *vop)
 330 {
 331         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 332 }
 333
 334 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 335 {
 336         writel(v, vop->lut_regs + offset);
 337 }
 338
 339 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 340 {
 341         return readl(vop->lut_regs + offset);
 342 }
 343
 344 static bool has_rb_swapped(uint32_t format)
 345 {
 346         switch (format) {
 347         case DRM_FORMAT_XBGR8888:
 348         case DRM_FORMAT_ABGR8888:
 349         case DRM_FORMAT_BGR888:
 350         case DRM_FORMAT_BGR565:
 351                 return true;
 352         default:
 353                 return false;
 354         }
 355 }
 356
 357 static enum vop_data_format vop_convert_format(uint32_t format)
 358 {
 359         switch (format) {
 360         case DRM_FORMAT_XRGB8888:
 361         case DRM_FORMAT_ARGB8888:
 362         case DRM_FORMAT_XBGR8888:
 363         case DRM_FORMAT_ABGR8888:
 364                 return VOP_FMT_ARGB8888;
 365         case DRM_FORMAT_RGB888:
 366         case DRM_FORMAT_BGR888:
 367                 return VOP_FMT_RGB888;
 368         case DRM_FORMAT_RGB565:
 369         case DRM_FORMAT_BGR565:
 370                 return VOP_FMT_RGB565;
 371         case DRM_FORMAT_NV12:
 372         case DRM_FORMAT_NV12_10:
 373                 return VOP_FMT_YUV420SP;
 374         case DRM_FORMAT_NV16:
 375         case DRM_FORMAT_NV16_10:
 376                 return VOP_FMT_YUV422SP;
 377         case DRM_FORMAT_NV24:
 378         case DRM_FORMAT_NV24_10:
 379                 return VOP_FMT_YUV444SP;
 380         default:
 381                 DRM_ERROR("unsupport format[%08x]\n", format);
 382                 return -EINVAL;
 383         }
 384 }
 385
 386 static bool is_yuv_output(uint32_t bus_format)
 387 {
 388         switch (bus_format) {
 389         case MEDIA_BUS_FMT_YUV8_1X24:
 390         case MEDIA_BUS_FMT_YUV10_1X30:
 391                 return true;
 392         default:
 393                 return false;
 394         }
 395 }
 396
 397 static bool is_yuv_support(uint32_t format)
 398 {
 399         switch (format) {
 400         case DRM_FORMAT_NV12:
 401         case DRM_FORMAT_NV12_10:
 402         case DRM_FORMAT_NV16:
 403         case DRM_FORMAT_NV16_10:
 404         case DRM_FORMAT_NV24:
 405         case DRM_FORMAT_NV24_10:
 406                 return true;
 407         default:
 408                 return false;
 409         }
 410 }
 411
 412 static bool is_yuv_10bit(uint32_t format)
 413 {
 414         switch (format) {
 415         case DRM_FORMAT_NV12_10:
 416         case DRM_FORMAT_NV16_10:
 417         case DRM_FORMAT_NV24_10:
 418                 return true;
 419         default:
 420                 return false;
 421         }
 422 }
 423
 424 static bool is_alpha_support(uint32_t format)
 425 {
 426         switch (format) {
 427         case DRM_FORMAT_ARGB8888:
 428         case DRM_FORMAT_ABGR8888:
 429                 return true;
 430         default:
 431                 return false;
 432         }
 433 }
 434
 435 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 436                                   uint32_t dst, bool is_horizontal,
 437                                   int vsu_mode, int *vskiplines)
 438 {
 439         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 440
 441         if (is_horizontal) {
 442                 if (mode == SCALE_UP)
 443                         val = GET_SCL_FT_BIC(src, dst);
 444                 else if (mode == SCALE_DOWN)
 445                         val = GET_SCL_FT_BILI_DN(src, dst);
 446         } else {
 447                 if (mode == SCALE_UP) {
 448                         if (vsu_mode == SCALE_UP_BIL)
 449                                 val = GET_SCL_FT_BILI_UP(src, dst);
 450                         else
 451                                 val = GET_SCL_FT_BIC(src, dst);
 452                 } else if (mode == SCALE_DOWN) {
 453                         if (vskiplines) {
 454                                 *vskiplines = scl_get_vskiplines(src, dst);
 455                                 val = scl_get_bili_dn_vskip(src, dst,
 456                                                             *vskiplines);
 457                         } else {
 458                                 val = GET_SCL_FT_BILI_DN(src, dst);
 459                         }
 460                 }
 461         }
 462
 463         return val;
 464 }
 465
 466 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 467                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 468                                 uint32_t dst_h, uint32_t pixel_format)
 469 {
 470         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 471         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 472         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 473         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 474         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 475         bool is_yuv = is_yuv_support(pixel_format);
 476         uint16_t cbcr_src_w = src_w / hsub;
 477         uint16_t cbcr_src_h = src_h / vsub;
 478         uint16_t vsu_mode;
 479         uint16_t lb_mode;
 480         uint32_t val;
 481         int vskiplines = 0;
 482
 483         if (!win->phy->scl)
 484                 return;
 485
 486         if (!win->phy->scl->ext) {
 487                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 488                             scl_cal_scale2(src_w, dst_w));
 489                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 490                             scl_cal_scale2(src_h, dst_h));
 491                 if (is_yuv) {
 492                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 493                                     scl_cal_scale2(cbcr_src_w, dst_w));
 494                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 495                                     scl_cal_scale2(cbcr_src_h, dst_h));
 496                 }
 497                 return;
 498         }
 499
 500         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 501         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 502
 503         if (is_yuv) {
 504                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 505                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 506                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 507                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 508                 else
 509                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 510         } else {
 511                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 512                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 513                 else
 514                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 515         }
 516
 517         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 518         if (lb_mode == LB_RGB_3840X2) {
 519                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 520                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 521                         return;
 522                 }
 523                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 524                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 525                         return;
 526                 }
 527                 vsu_mode = SCALE_UP_BIL;
 528         } else if (lb_mode == LB_RGB_2560X4) {
 529                 vsu_mode = SCALE_UP_BIL;
 530         } else {
 531                 vsu_mode = SCALE_UP_BIC;
 532         }
 533
 534         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 535                                 true, 0, NULL);
 536         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 537         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 538                                 false, vsu_mode, &vskiplines);
 539         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 540
 541         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 542         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 543
 544         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 545         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 546         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 547         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 548         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 549         if (is_yuv) {
 550                 vskiplines = 0;
 551
 552                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 553                                         dst_w, true, 0, NULL);
 554                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 555                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 556                                         dst_h, false, vsu_mode, &vskiplines);
 557                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 558
 559                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 560                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 561                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 562                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 563                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 564                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 565                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 566         }
 567 }
 568
 569 /*
 570  * rk3399 colorspace path:
 571  *      Input        Win csc                     Output
 572  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 573  *    RGB        --> R2Y                  __/
 574  *
 575  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 576  *    RGB        --> 709To2020->R2Y       __/
 577  *
 578  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 579  *    RGB        --> R2Y                  __/
 580  *
 581  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 582  *    RGB        --> 709To2020->R2Y       __/
 583  *
 584  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 585  *    RGB        --> R2Y                  __/
 586  *
 587  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 588  *    RGB        --> R2Y(601)             __/
 589  *
 590  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 591  *    RGB        --> bypass               __/
 592  *
 593  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 594  *
 595  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 596  *
 597  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 598  *
 599  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 600  */
 601 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 602                          bool is_input_yuv, bool is_output_yuv,
 603                          int input_csc, int output_csc,
 604                          const uint32_t **y2r_table,
 605                          const uint32_t **r2r_table,
 606                          const uint32_t **r2y_table)
 607 {
 608         *y2r_table = NULL;
 609         *r2r_table = NULL;
 610         *r2y_table = NULL;
 611
 612         if (is_output_yuv) {
 613                 if (output_csc == CSC_BT2020) {
 614                         if (is_input_yuv) {
 615                                 if (input_csc == CSC_BT2020)
 616                                         return 0;
 617                                 *y2r_table = csc_table->y2r_bt709;
 618                         }
 619                         if (input_csc != CSC_BT2020)
 620                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 621                         *r2y_table = csc_table->r2y_bt2020;
 622                 } else {
 623                         if (is_input_yuv && input_csc == CSC_BT2020)
 624                                 *y2r_table = csc_table->y2r_bt2020;
 625                         if (input_csc == CSC_BT2020)
 626                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 627                         if (!is_input_yuv || *y2r_table) {
 628                                 if (output_csc == CSC_BT709)
 629                                         *r2y_table = csc_table->r2y_bt709;
 630                                 else
 631                                         *r2y_table = csc_table->r2y_bt601;
 632                         }
 633                 }
 634         } else {
 635                 if (!is_input_yuv)
 636                         return 0;
 637
 638                 /*
 639                  * is possible use bt2020 on rgb mode?
 640                  */
 641                 if (WARN_ON(output_csc == CSC_BT2020))
 642                         return -EINVAL;
 643
 644                 if (input_csc == CSC_BT2020)
 645                         *y2r_table = csc_table->y2r_bt2020;
 646                 else if (input_csc == CSC_BT709)
 647                         *y2r_table = csc_table->y2r_bt709;
 648                 else
 649                         *y2r_table = csc_table->y2r_bt601;
 650
 651                 if (input_csc == CSC_BT2020)
 652                         /*
 653                          * We don't have bt601 to bt709 table, force use bt709.
 654                          */
 655                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 662                                 struct drm_crtc_state *crtc_state)
 663 {
 664         struct vop *vop = to_vop(crtc);
 665         struct drm_atomic_state *state = crtc_state->state;
 666         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 667         const struct vop_csc_table *csc_table = vop->data->csc_table;
 668         struct drm_plane_state *pstate;
 669         struct drm_plane *plane;
 670         bool is_input_yuv, is_output_yuv;
 671         int ret;
 672
 673         if (!csc_table)
 674                 return 0;
 675
 676         is_output_yuv = is_yuv_output(s->bus_format);
 677
 678         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 679                 struct vop_plane_state *vop_plane_state;
 680
 681                 pstate = drm_atomic_get_plane_state(state, plane);
 682                 if (IS_ERR(pstate))
 683                         return PTR_ERR(pstate);
 684                 vop_plane_state = to_vop_plane_state(pstate);
 685
 686                 if (!pstate->fb)
 687                         continue;
 688                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 689
 690                 /*
 691                  * TODO: force set input and output csc mode.
 692                  */
 693                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 694                                     CSC_BT709, CSC_BT709,
 695                                     &vop_plane_state->y2r_table,
 696                                     &vop_plane_state->r2r_table,
 697                                     &vop_plane_state->r2y_table);
 698                 if (ret)
 699                         return ret;
 700         }
 701
 702         return 0;
 703 }
 704
 705 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 706 {
 707         unsigned long flags;
 708
 709         spin_lock_irqsave(&vop->irq_lock, flags);
 710
 711         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 712         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 713
 714         spin_unlock_irqrestore(&vop->irq_lock, flags);
 715 }
 716
 717 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 718 {
 719         unsigned long flags;
 720
 721         spin_lock_irqsave(&vop->irq_lock, flags);
 722
 723         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 724
 725         spin_unlock_irqrestore(&vop->irq_lock, flags);
 726 }
 727
 728 /*
 729  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 730  *     the "FRAME_SYNC" interrupt.
 731  * (2) the active data region of each frame ends at dsp_vact_end
 732  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 733  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 734  *
 735  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 736  * Interrupts
 737  * LINE_FLAG -------------------------------+
 738  * FRAME_SYNC ----+                         |
 739  *                |                         |
 740  *                v                         v
 741  *                | Vsync | Vbp |  Vactive  | Vfp |
 742  *                        ^     ^           ^     ^
 743  *                        |     |           |     |
 744  *                        |     |           |     |
 745  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 746  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 747  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 748  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 749  */
 750 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 751 {
 752         uint32_t line_flag_irq;
 753         unsigned long flags;
 754
 755         spin_lock_irqsave(&vop->irq_lock, flags);
 756
 757         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 758
 759         spin_unlock_irqrestore(&vop->irq_lock, flags);
 760
 761         return !!line_flag_irq;
 762 }
 763
 764 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 765 {
 766         unsigned long flags;
 767
 768         if (WARN_ON(!vop->is_enabled))
 769                 return;
 770
 771         spin_lock_irqsave(&vop->irq_lock, flags);
 772
 773         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 774         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 775         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 776
 777         spin_unlock_irqrestore(&vop->irq_lock, flags);
 778 }
 779
 780 static void vop_line_flag_irq_disable(struct vop *vop)
 781 {
 782         unsigned long flags;
 783
 784         if (WARN_ON(!vop->is_enabled))
 785                 return;
 786
 787         spin_lock_irqsave(&vop->irq_lock, flags);
 788
 789         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 790
 791         spin_unlock_irqrestore(&vop->irq_lock, flags);
 792 }
 793
 794 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 795 {
 796         struct vop *vop = to_vop(crtc);
 797         int i, dle, lut_idx;
 798
 799         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 800                 return;
 801
 802         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 803                 return;
 804
 805         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 806                 spin_lock(&vop->reg_lock);
 807                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 808                 vop_cfg_done(vop);
 809                 spin_unlock(&vop->reg_lock);
 810
 811 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 812                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 813                                 dle, !dle, 5, 33333);
 814         } else {
 815                 lut_idx = CTRL_GET(lut_buffer_index);
 816         }
 817
 818         for (i = 0; i < vop->lut_len; i++)
 819                 vop_write_lut(vop, i << 2, vop->lut[i]);
 820
 821         spin_lock(&vop->reg_lock);
 822
 823         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 824         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 825         vop_cfg_done(vop);
 826         vop->lut_active = true;
 827
 828         spin_unlock(&vop->reg_lock);
 829
 830         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 831                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 832                                    dle, dle != lut_idx, 5, 33333);
 833                 /* FIXME:
 834                  * update_gamma value auto clean to 0 by HW, should not
 835                  * bakeup it.
 836                  */
 837                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 838         }
 839 #undef CTRL_GET
 840 }
 841
 842 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 843                                     u16 blue, int regno)
 844 {
 845         struct vop *vop = to_vop(crtc);
 846         u32 lut_len = vop->lut_len;
 847         u32 r, g, b;
 848
 849         if (regno >= lut_len || !vop->lut)
 850                 return;
 851
 852         r = red * (lut_len - 1) / 0xffff;
 853         g = green * (lut_len - 1) / 0xffff;
 854         b = blue * (lut_len - 1) / 0xffff;
 855         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 856 }
 857
 858 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 859                                     u16 *blue, int regno)
 860 {
 861         struct vop *vop = to_vop(crtc);
 862         u32 lut_len = vop->lut_len;
 863         u32 r, g, b;
 864
 865         if (regno >= lut_len || !vop->lut)
 866                 return;
 867
 868         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 869         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 870         b = vop->lut[regno] & (lut_len - 1);
 871         *red = r * 0xffff / (lut_len - 1);
 872         *green = g * 0xffff / (lut_len - 1);
 873         *blue = b * 0xffff / (lut_len - 1);
 874 }
 875
 876 static void vop_power_enable(struct drm_crtc *crtc)
 877 {
 878         struct vop *vop = to_vop(crtc);
 879         int ret;
 880
 881         ret = clk_prepare_enable(vop->hclk);
 882         if (ret < 0) {
 883                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 884                 return;
 885         }
 886
 887         ret = clk_prepare_enable(vop->dclk);
 888         if (ret < 0) {
 889                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 890                 goto err_disable_hclk;
 891         }
 892
 893         ret = clk_prepare_enable(vop->aclk);
 894         if (ret < 0) {
 895                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 896                 goto err_disable_dclk;
 897         }
 898
 899         ret = pm_runtime_get_sync(vop->dev);
 900         if (ret < 0) {
 901                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 902                 return;
 903         }
 904
 905         memcpy(vop->regsbak, vop->regs, vop->len);
 906
 907         vop->is_enabled = true;
 908
 909         return;
 910
 911 err_disable_dclk:
 912         clk_disable_unprepare(vop->dclk);
 913 err_disable_hclk:
 914         clk_disable_unprepare(vop->hclk);
 915 }
 916
 917 static void vop_initial(struct drm_crtc *crtc)
 918 {
 919         struct vop *vop = to_vop(crtc);
 920         int i;
 921
 922         vop_power_enable(crtc);
 923
 924         VOP_CTRL_SET(vop, global_regdone_en, 1);
 925         VOP_CTRL_SET(vop, dsp_blank, 0);
 926
 927         /*
 928          * restore the lut table.
 929          */
 930         if (vop->lut_active)
 931                 vop_crtc_load_lut(crtc);
 932
 933         /*
 934          * We need to make sure that all windows are disabled before resume
 935          * the crtc. Otherwise we might try to scan from a destroyed
 936          * buffer later.
 937          */
 938         for (i = 0; i < vop->num_wins; i++) {
 939                 struct vop_win *win = &vop->win[i];
 940                 int channel = i * 2 + 1;
 941
 942                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 943                 if (win->phy->scl && win->phy->scl->ext) {
 944                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 945                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 946                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 947                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 948                 }
 949                 VOP_WIN_SET(vop, win, enable, 0);
 950                 VOP_WIN_SET(vop, win, gate, 1);
 951         }
 952         VOP_CTRL_SET(vop, afbdc_en, 0);
 953 }
 954
 955 static void vop_crtc_disable(struct drm_crtc *crtc)
 956 {
 957         struct vop *vop = to_vop(crtc);
 958
 959         mutex_lock(&vop->vop_lock);
 960         drm_crtc_vblank_off(crtc);
 961
 962         /*
 963          * Vop standby will take effect at end of current frame,
 964          * if dsp hold valid irq happen, it means standby complete.
 965          *
 966          * we must wait standby complete when we want to disable aclk,
 967          * if not, memory bus maybe dead.
 968          */
 969         reinit_completion(&vop->dsp_hold_completion);
 970         vop_dsp_hold_valid_irq_enable(vop);
 971
 972         spin_lock(&vop->reg_lock);
 973
 974         VOP_CTRL_SET(vop, standby, 1);
 975
 976         spin_unlock(&vop->reg_lock);
 977
 978         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 979                                              msecs_to_jiffies(50)));
 980
 981         vop_dsp_hold_valid_irq_disable(vop);
 982
 983         disable_irq(vop->irq);
 984
 985         vop->is_enabled = false;
 986         if (vop->is_iommu_enabled) {
 987                 /*
 988                  * vop standby complete, so iommu detach is safe.
 989                  */
 990                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 991                 vop->is_iommu_enabled = false;
 992         }
 993
 994         pm_runtime_put(vop->dev);
 995         clk_disable_unprepare(vop->dclk);
 996         clk_disable_unprepare(vop->aclk);
 997         clk_disable_unprepare(vop->hclk);
 998         mutex_unlock(&vop->vop_lock);
 999 }
1000
1001 static void vop_plane_destroy(struct drm_plane *plane)
1002 {
1003         drm_plane_cleanup(plane);
1004 }
1005
1006 static int vop_plane_prepare_fb(struct drm_plane *plane,
1007                                 const struct drm_plane_state *new_state)
1008 {
1009         if (plane->state->fb)
1010                 drm_framebuffer_reference(plane->state->fb);
1011
1012         return 0;
1013 }
1014
1015 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1016                                  const struct drm_plane_state *old_state)
1017 {
1018         if (old_state->fb)
1019                 drm_framebuffer_unreference(old_state->fb);
1020 }
1021
1022 static int vop_plane_atomic_check(struct drm_plane *plane,
1023                            struct drm_plane_state *state)
1024 {
1025         struct drm_crtc *crtc = state->crtc;
1026         struct drm_framebuffer *fb = state->fb;
1027         struct vop_win *win = to_vop_win(plane);
1028         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1029         struct drm_crtc_state *crtc_state;
1030         const struct vop_data *vop_data;
1031         struct vop *vop;
1032         bool visible;
1033         int ret;
1034         struct drm_rect *dest = &vop_plane_state->dest;
1035         struct drm_rect *src = &vop_plane_state->src;
1036         struct drm_rect clip;
1037         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1038                                         DRM_PLANE_HELPER_NO_SCALING;
1039         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1040                                         DRM_PLANE_HELPER_NO_SCALING;
1041         unsigned long offset;
1042         dma_addr_t dma_addr;
1043         u16 vdisplay;
1044
1045         crtc = crtc ? crtc : plane->state->crtc;
1046         /*
1047          * Both crtc or plane->state->crtc can be null.
1048          */
1049         if (!crtc || !fb)
1050                 goto out_disable;
1051
1052         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1053         if (IS_ERR(crtc_state))
1054                 return PTR_ERR(crtc_state);
1055
1056         src->x1 = state->src_x;
1057         src->y1 = state->src_y;
1058         src->x2 = state->src_x + state->src_w;
1059         src->y2 = state->src_y + state->src_h;
1060         dest->x1 = state->crtc_x;
1061         dest->y1 = state->crtc_y;
1062         dest->x2 = state->crtc_x + state->crtc_w;
1063         dest->y2 = state->crtc_y + state->crtc_h;
1064
1065         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1066         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1067                 vdisplay *= 2;
1068
1069         clip.x1 = 0;
1070         clip.y1 = 0;
1071         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1072         clip.y2 = vdisplay;
1073
1074         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1075                                             src, dest, &clip,
1076                                             min_scale,
1077                                             max_scale,
1078                                             true, true, &visible);
1079         if (ret)
1080                 return ret;
1081
1082         if (!visible)
1083                 goto out_disable;
1084
1085         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1086         if (vop_plane_state->format < 0)
1087                 return vop_plane_state->format;
1088
1089         vop = to_vop(crtc);
1090         vop_data = vop->data;
1091
1092         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1093             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1094                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1095                           drm_rect_width(src) >> 16,
1096                           drm_rect_height(src) >> 16,
1097                           vop_data->max_input.width,
1098                           vop_data->max_input.height);
1099                 return -EINVAL;
1100         }
1101
1102         /*
1103          * Src.x1 can be odd when do clip, but yuv plane start point
1104          * need align with 2 pixel.
1105          */
1106         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1107                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1108                 return -EINVAL;
1109         }
1110
1111         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1112         if (state->rotation & BIT(DRM_REFLECT_Y) ||
1113             (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1114                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1115         else
1116                 offset += (src->y1 >> 16) * fb->pitches[0];
1117
1118         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1119         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1120         if (is_yuv_support(fb->pixel_format)) {
1121                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1122                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1123                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1124
1125                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1126                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1127
1128                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1129                 dma_addr += offset + fb->offsets[1];
1130                 vop_plane_state->uv_mst = dma_addr;
1131         }
1132
1133         vop_plane_state->enable = true;
1134
1135         return 0;
1136
1137 out_disable:
1138         vop_plane_state->enable = false;
1139         return 0;
1140 }
1141
1142 static void vop_plane_atomic_disable(struct drm_plane *plane,
1143                                      struct drm_plane_state *old_state)
1144 {
1145         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1146         struct vop_win *win = to_vop_win(plane);
1147         struct vop *vop = to_vop(old_state->crtc);
1148
1149         if (!old_state->crtc)
1150                 return;
1151
1152         spin_lock(&vop->reg_lock);
1153
1154         /*
1155          * FIXUP: some of the vop scale would be abnormal after windows power
1156          * on/off so deinit scale to scale_none mode.
1157          */
1158         if (win->phy->scl && win->phy->scl->ext) {
1159                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1160                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1161                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1162                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1163         }
1164         VOP_WIN_SET(vop, win, enable, 0);
1165
1166         spin_unlock(&vop->reg_lock);
1167
1168         vop_plane_state->enable = false;
1169 }
1170
1171 static void vop_plane_atomic_update(struct drm_plane *plane,
1172                 struct drm_plane_state *old_state)
1173 {
1174         struct drm_plane_state *state = plane->state;
1175         struct drm_crtc *crtc = state->crtc;
1176         struct vop_win *win = to_vop_win(plane);
1177         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1178         struct rockchip_crtc_state *s;
1179         struct vop *vop;
1180         struct drm_framebuffer *fb = state->fb;
1181         unsigned int actual_w, actual_h;
1182         unsigned int dsp_stx, dsp_sty;
1183         uint32_t act_info, dsp_info, dsp_st;
1184         struct drm_rect *src = &vop_plane_state->src;
1185         struct drm_rect *dest = &vop_plane_state->dest;
1186         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1187         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1188         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1189         int ymirror, xmirror;
1190         uint32_t val;
1191         bool rb_swap;
1192
1193         /*
1194          * can't update plane when vop is disabled.
1195          */
1196         if (!crtc)
1197                 return;
1198
1199         if (!vop_plane_state->enable) {
1200                 vop_plane_atomic_disable(plane, old_state);
1201                 return;
1202         }
1203
1204         actual_w = drm_rect_width(src) >> 16;
1205         actual_h = drm_rect_height(src) >> 16;
1206         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1207
1208         dsp_info = (drm_rect_height(dest) - 1) << 16;
1209         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1210
1211         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1212         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1213         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1214
1215         ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1216                   (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1217         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1218
1219         vop = to_vop(state->crtc);
1220         s = to_rockchip_crtc_state(crtc->state);
1221
1222         spin_lock(&vop->reg_lock);
1223
1224         VOP_WIN_SET(vop, win, xmirror, xmirror);
1225         VOP_WIN_SET(vop, win, ymirror, ymirror);
1226         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1227         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1228         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1229         if (is_yuv_support(fb->pixel_format)) {
1230                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1231                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1232         }
1233         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1234
1235         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1236                             drm_rect_width(dest), drm_rect_height(dest),
1237                             fb->pixel_format);
1238
1239         VOP_WIN_SET(vop, win, act_info, act_info);
1240         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1241         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1242
1243         rb_swap = has_rb_swapped(fb->pixel_format);
1244         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1245
1246         if (is_alpha_support(fb->pixel_format) &&
1247             (s->dsp_layer_sel & 0x3) != win->win_id) {
1248                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1249                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1250                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1251                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1252                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1253                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1254                         SRC_FACTOR_M0(ALPHA_ONE);
1255                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1256                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1257                 VOP_WIN_SET(vop, win, alpha_en, 1);
1258         } else {
1259                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1260                 VOP_WIN_SET(vop, win, alpha_en, 0);
1261         }
1262
1263         if (win->csc) {
1264                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1265                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1266                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1267                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1268                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1269                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1270         }
1271         VOP_WIN_SET(vop, win, enable, 1);
1272         spin_unlock(&vop->reg_lock);
1273         vop->is_iommu_needed = true;
1274 }
1275
1276 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1277         .prepare_fb = vop_plane_prepare_fb,
1278         .cleanup_fb = vop_plane_cleanup_fb,
1279         .atomic_check = vop_plane_atomic_check,
1280         .atomic_update = vop_plane_atomic_update,
1281         .atomic_disable = vop_plane_atomic_disable,
1282 };
1283
1284 void vop_atomic_plane_reset(struct drm_plane *plane)
1285 {
1286         struct vop_win *win = to_vop_win(plane);
1287         struct vop_plane_state *vop_plane_state =
1288                                         to_vop_plane_state(plane->state);
1289
1290         if (plane->state && plane->state->fb)
1291                 drm_framebuffer_unreference(plane->state->fb);
1292
1293         kfree(vop_plane_state);
1294         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1295         if (!vop_plane_state)
1296                 return;
1297
1298         vop_plane_state->zpos = win->win_id;
1299         plane->state = &vop_plane_state->base;
1300         plane->state->plane = plane;
1301 }
1302
1303 struct drm_plane_state *
1304 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1305 {
1306         struct vop_plane_state *old_vop_plane_state;
1307         struct vop_plane_state *vop_plane_state;
1308
1309         if (WARN_ON(!plane->state))
1310                 return NULL;
1311
1312         old_vop_plane_state = to_vop_plane_state(plane->state);
1313         vop_plane_state = kmemdup(old_vop_plane_state,
1314                                   sizeof(*vop_plane_state), GFP_KERNEL);
1315         if (!vop_plane_state)
1316                 return NULL;
1317
1318         __drm_atomic_helper_plane_duplicate_state(plane,
1319                                                   &vop_plane_state->base);
1320
1321         return &vop_plane_state->base;
1322 }
1323
1324 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1325                                            struct drm_plane_state *state)
1326 {
1327         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1328
1329         __drm_atomic_helper_plane_destroy_state(plane, state);
1330
1331         kfree(vop_state);
1332 }
1333
1334 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1335                                          struct drm_plane_state *state,
1336                                          struct drm_property *property,
1337                                          uint64_t val)
1338 {
1339         struct rockchip_drm_private *private = plane->dev->dev_private;
1340         struct vop_win *win = to_vop_win(plane);
1341         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1342
1343         if (property == win->vop->plane_zpos_prop) {
1344                 plane_state->zpos = val;
1345                 return 0;
1346         }
1347
1348         if (property == win->rotation_prop) {
1349                 state->rotation = val;
1350                 return 0;
1351         }
1352
1353         if (property == private->logo_ymirror_prop) {
1354                 WARN_ON(!rockchip_fb_is_logo(state->fb));
1355                 plane_state->logo_ymirror = val;
1356                 return 0;
1357         }
1358
1359         DRM_ERROR("failed to set vop plane property\n");
1360         return -EINVAL;
1361 }
1362
1363 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1364                                          const struct drm_plane_state *state,
1365                                          struct drm_property *property,
1366                                          uint64_t *val)
1367 {
1368         struct vop_win *win = to_vop_win(plane);
1369         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1370
1371         if (property == win->vop->plane_zpos_prop) {
1372                 *val = plane_state->zpos;
1373                 return 0;
1374         }
1375
1376         if (property == win->rotation_prop) {
1377                 *val = state->rotation;
1378                 return 0;
1379         }
1380
1381         DRM_ERROR("failed to get vop plane property\n");
1382         return -EINVAL;
1383 }
1384
1385 static const struct drm_plane_funcs vop_plane_funcs = {
1386         .update_plane   = drm_atomic_helper_update_plane,
1387         .disable_plane  = drm_atomic_helper_disable_plane,
1388         .destroy = vop_plane_destroy,
1389         .reset = vop_atomic_plane_reset,
1390         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1391         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1392         .atomic_set_property = vop_atomic_plane_set_property,
1393         .atomic_get_property = vop_atomic_plane_get_property,
1394 };
1395
1396 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1397 {
1398         struct vop *vop = to_vop(crtc);
1399         unsigned long flags;
1400
1401         if (!vop->is_enabled)
1402                 return -EPERM;
1403
1404         spin_lock_irqsave(&vop->irq_lock, flags);
1405
1406         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1407         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1408
1409         spin_unlock_irqrestore(&vop->irq_lock, flags);
1410
1411         return 0;
1412 }
1413
1414 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1415 {
1416         struct vop *vop = to_vop(crtc);
1417         unsigned long flags;
1418
1419         if (!vop->is_enabled)
1420                 return;
1421
1422         spin_lock_irqsave(&vop->irq_lock, flags);
1423
1424         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1425
1426         spin_unlock_irqrestore(&vop->irq_lock, flags);
1427 }
1428
1429 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1430 {
1431         struct vop *vop = to_vop(crtc);
1432
1433         reinit_completion(&vop->wait_update_complete);
1434         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete,
1435                                              msecs_to_jiffies(1000)));
1436 }
1437
1438 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1439                                            struct drm_file *file_priv)
1440 {
1441         struct drm_device *drm = crtc->dev;
1442         struct vop *vop = to_vop(crtc);
1443         struct drm_pending_vblank_event *e;
1444         unsigned long flags;
1445
1446         spin_lock_irqsave(&drm->event_lock, flags);
1447         e = vop->event;
1448         if (e && e->base.file_priv == file_priv) {
1449                 vop->event = NULL;
1450
1451                 e->base.destroy(&e->base);
1452                 file_priv->event_space += sizeof(e->event);
1453         }
1454         spin_unlock_irqrestore(&drm->event_lock, flags);
1455 }
1456
1457 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1458 {
1459         struct vop *vop = to_vop(crtc);
1460
1461         if (on == vop->loader_protect)
1462                 return 0;
1463
1464         if (on) {
1465                 vop_power_enable(crtc);
1466                 enable_irq(vop->irq);
1467                 drm_crtc_vblank_on(crtc);
1468                 vop->loader_protect = true;
1469         } else {
1470                 vop_crtc_disable(crtc);
1471
1472                 vop->loader_protect = false;
1473         }
1474
1475         return 0;
1476 }
1477
1478 #define DEBUG_PRINT(args...) \
1479                 do { \
1480                         if (s) \
1481                                 seq_printf(s, args); \
1482                         else \
1483                                 printk(args); \
1484                 } while (0)
1485
1486 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1487 {
1488         struct vop_win *win = to_vop_win(plane);
1489         struct drm_plane_state *state = plane->state;
1490         struct vop_plane_state *pstate = to_vop_plane_state(state);
1491         struct drm_rect *src, *dest;
1492         struct drm_framebuffer *fb = state->fb;
1493         int i;
1494
1495         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1496                     pstate->enable ? "ACTIVE" : "DISABLED");
1497         if (!fb)
1498                 return 0;
1499
1500         src = &pstate->src;
1501         dest = &pstate->dest;
1502
1503         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1504                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1505         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1506         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1507                     src->y1 >> 16, drm_rect_width(src) >> 16,
1508                     drm_rect_height(src) >> 16);
1509         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1510                     drm_rect_width(dest), drm_rect_height(dest));
1511
1512         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1513                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1514                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1515                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1516         }
1517
1518         return 0;
1519 }
1520
1521 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1522 {
1523         struct vop *vop = to_vop(crtc);
1524         struct drm_crtc_state *crtc_state = crtc->state;
1525         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1526         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1527         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1528         struct drm_plane *plane;
1529         int i;
1530
1531         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1532                     crtc_state->active ? "ACTIVE" : "DISABLED");
1533
1534         if (!crtc_state->active)
1535                 return 0;
1536
1537         DEBUG_PRINT("    Connector: %s\n",
1538                     drm_get_connector_name(state->output_type));
1539         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1540                     state->bus_format, state->output_mode);
1541         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1542                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1543                     drm_mode_vrefresh(mode));
1544         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1545                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1546         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1547                     mode->hsync_end, mode->htotal);
1548         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1549                     mode->vsync_end, mode->vtotal);
1550
1551         for (i = 0; i < vop->num_wins; i++) {
1552                 plane = &vop->win[i].base;
1553                 vop_plane_info_dump(s, plane);
1554         }
1555
1556         return 0;
1557 }
1558
1559 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1560 {
1561         struct vop *vop = to_vop(crtc);
1562         struct drm_crtc_state *crtc_state = crtc->state;
1563         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1564         int i;
1565
1566         if (!crtc_state->active)
1567                 return;
1568
1569         for (i = 0; i < dump_len; i += 4) {
1570                 if (i % 16 == 0)
1571                         DEBUG_PRINT("\n0x%08x: ", i);
1572                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1573         }
1574 }
1575
1576 #undef DEBUG_PRINT
1577
1578 static enum drm_mode_status
1579 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1580                     int output_type)
1581 {
1582         struct vop *vop = to_vop(crtc);
1583         const struct vop_data *vop_data = vop->data;
1584         int request_clock = mode->clock;
1585         int clock;
1586
1587         if (mode->hdisplay > vop_data->max_output.width)
1588                 return MODE_BAD_HVALUE;
1589         if (mode->vdisplay > vop_data->max_output.height)
1590                 return MODE_BAD_VVALUE;
1591
1592         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1593                 request_clock *= 2;
1594         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1595
1596         /*
1597          * Hdmi or DisplayPort request a Accurate clock.
1598          */
1599         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1600             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1601                 if (clock != request_clock)
1602                         return MODE_CLOCK_RANGE;
1603
1604         return MODE_OK;
1605 }
1606
1607 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1608         .loader_protect = vop_crtc_loader_protect,
1609         .enable_vblank = vop_crtc_enable_vblank,
1610         .disable_vblank = vop_crtc_disable_vblank,
1611         .wait_for_update = vop_crtc_wait_for_update,
1612         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1613         .debugfs_dump = vop_crtc_debugfs_dump,
1614         .regs_dump = vop_crtc_regs_dump,
1615         .mode_valid = vop_crtc_mode_valid,
1616 };
1617
1618 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1619                                 const struct drm_display_mode *mode,
1620                                 struct drm_display_mode *adj_mode)
1621 {
1622         struct vop *vop = to_vop(crtc);
1623         const struct vop_data *vop_data = vop->data;
1624
1625         if (mode->hdisplay > vop_data->max_output.width ||
1626             mode->vdisplay > vop_data->max_output.height)
1627                 return false;
1628
1629         drm_mode_set_crtcinfo(adj_mode,
1630                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1631
1632         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1633                 adj_mode->crtc_clock *= 2;
1634
1635         adj_mode->crtc_clock =
1636                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1637
1638         return true;
1639 }
1640
1641 static void vop_crtc_enable(struct drm_crtc *crtc)
1642 {
1643         struct vop *vop = to_vop(crtc);
1644         const struct vop_data *vop_data = vop->data;
1645         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1646         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1647         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1648         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1649         u16 htotal = adjusted_mode->crtc_htotal;
1650         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1651         u16 hact_end = hact_st + hdisplay;
1652         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1653         u16 vtotal = adjusted_mode->crtc_vtotal;
1654         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1655         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1656         u16 vact_end = vact_st + vdisplay;
1657         uint32_t val;
1658
1659         mutex_lock(&vop->vop_lock);
1660         vop_initial(crtc);
1661
1662         val = BIT(DCLK_INVERT);
1663         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1664                    0 : BIT(HSYNC_POSITIVE);
1665         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1666                    0 : BIT(VSYNC_POSITIVE);
1667         VOP_CTRL_SET(vop, pin_pol, val);
1668         switch (s->output_type) {
1669         case DRM_MODE_CONNECTOR_LVDS:
1670                 VOP_CTRL_SET(vop, rgb_en, 1);
1671                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1672                 break;
1673         case DRM_MODE_CONNECTOR_eDP:
1674                 VOP_CTRL_SET(vop, edp_en, 1);
1675                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1676                 break;
1677         case DRM_MODE_CONNECTOR_HDMIA:
1678                 VOP_CTRL_SET(vop, hdmi_en, 1);
1679                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1680                 break;
1681         case DRM_MODE_CONNECTOR_DSI:
1682                 VOP_CTRL_SET(vop, mipi_en, 1);
1683                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1684                 break;
1685         case DRM_MODE_CONNECTOR_DisplayPort:
1686                 val &= ~BIT(DCLK_INVERT);
1687                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1688                 VOP_CTRL_SET(vop, dp_en, 1);
1689                 break;
1690         default:
1691                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1692         }
1693
1694         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1695             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1696                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1697
1698         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1699         switch (s->bus_format) {
1700         case MEDIA_BUS_FMT_RGB565_1X16:
1701                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1702                 break;
1703         case MEDIA_BUS_FMT_RGB666_1X18:
1704         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1705                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1706                 break;
1707         case MEDIA_BUS_FMT_YUV8_1X24:
1708                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1709                 break;
1710         case MEDIA_BUS_FMT_YUV10_1X30:
1711                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1712                 break;
1713         case MEDIA_BUS_FMT_RGB888_1X24:
1714         default:
1715                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1716                 break;
1717         }
1718
1719         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1720                 val |= PRE_DITHER_DOWN_EN(0);
1721         else
1722                 val |= PRE_DITHER_DOWN_EN(1);
1723         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1724         VOP_CTRL_SET(vop, dither_down, val);
1725         VOP_CTRL_SET(vop, dclk_ddr,
1726                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1727         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1728         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1729         VOP_CTRL_SET(vop, dsp_background,
1730                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1731
1732         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1733         val = hact_st << 16;
1734         val |= hact_end;
1735         VOP_CTRL_SET(vop, hact_st_end, val);
1736         VOP_CTRL_SET(vop, hpost_st_end, val);
1737
1738         val = vact_st << 16;
1739         val |= vact_end;
1740         VOP_CTRL_SET(vop, vact_st_end, val);
1741         VOP_CTRL_SET(vop, vpost_st_end, val);
1742
1743         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1744         VOP_INTR_SET(vop, line_flag_num[1],
1745                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1746         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1747                 u16 vact_st_f1 = vtotal + vact_st + 1;
1748                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1749
1750                 val = vact_st_f1 << 16 | vact_end_f1;
1751                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1752                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1753
1754                 val = vtotal << 16 | (vtotal + vsync_len);
1755                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1756                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1757                 VOP_CTRL_SET(vop, p2i_en, 1);
1758                 vtotal += vtotal + 1;
1759         } else {
1760                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1761                 VOP_CTRL_SET(vop, p2i_en, 0);
1762         }
1763         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1764
1765         VOP_CTRL_SET(vop, core_dclk_div,
1766                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1767
1768         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1769
1770         vop_cfg_done(vop);
1771         /*
1772          * enable vop, all the register would take effect when vop exit standby
1773          */
1774         VOP_CTRL_SET(vop, standby, 0);
1775
1776         enable_irq(vop->irq);
1777         drm_crtc_vblank_on(crtc);
1778         mutex_unlock(&vop->vop_lock);
1779 }
1780
1781 static int vop_zpos_cmp(const void *a, const void *b)
1782 {
1783         struct vop_zpos *pa = (struct vop_zpos *)a;
1784         struct vop_zpos *pb = (struct vop_zpos *)b;
1785
1786         return pa->zpos - pb->zpos;
1787 }
1788
1789 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1790                                   struct drm_crtc_state *crtc_state)
1791 {
1792         struct vop *vop = to_vop(crtc);
1793         const struct vop_data *vop_data = vop->data;
1794         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1795         struct drm_atomic_state *state = crtc_state->state;
1796         struct drm_plane *plane;
1797         struct drm_plane_state *pstate;
1798         struct vop_plane_state *plane_state;
1799         struct vop_win *win;
1800         int afbdc_format;
1801         int i;
1802
1803         s->afbdc_en = 0;
1804
1805         for_each_plane_in_state(state, plane, pstate, i) {
1806                 struct drm_framebuffer *fb = pstate->fb;
1807                 struct drm_rect *src;
1808
1809                 win = to_vop_win(plane);
1810                 plane_state = to_vop_plane_state(pstate);
1811
1812                 if (pstate->crtc != crtc || !fb)
1813                         continue;
1814
1815                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1816                         continue;
1817
1818                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1819                         DRM_ERROR("not support afbdc\n");
1820                         return -EINVAL;
1821                 }
1822
1823                 switch (plane_state->format) {
1824                 case VOP_FMT_ARGB8888:
1825                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1826                         break;
1827                 case VOP_FMT_RGB888:
1828                         afbdc_format = AFBDC_FMT_U8U8U8;
1829                         break;
1830                 case VOP_FMT_RGB565:
1831                         afbdc_format = AFBDC_FMT_RGB565;
1832                         break;
1833                 default:
1834                         return -EINVAL;
1835                 }
1836
1837                 if (s->afbdc_en) {
1838                         DRM_ERROR("vop only support one afbc layer\n");
1839                         return -EINVAL;
1840                 }
1841
1842                 src = &plane_state->src;
1843                 if (src->x1 || src->y1 || fb->offsets[0]) {
1844                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1845                                   win->win_id);
1846                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1847                                   src->x1, src->y1, fb->offsets[0]);
1848                         return -EINVAL;
1849                 }
1850                 s->afbdc_win_format = afbdc_format;
1851                 s->afbdc_win_width = pstate->fb->width - 1;
1852                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1853                 s->afbdc_win_id = win->win_id;
1854                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1855                 s->afbdc_en = 1;
1856         }
1857
1858         return 0;
1859 }
1860
1861 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1862                                  struct drm_crtc_state *crtc_state)
1863 {
1864         struct drm_atomic_state *state = crtc_state->state;
1865         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1866         struct vop *vop = to_vop(crtc);
1867         const struct vop_data *vop_data = vop->data;
1868         struct drm_plane *plane;
1869         struct drm_plane_state *pstate;
1870         struct vop_plane_state *plane_state;
1871         struct vop_zpos *pzpos;
1872         int dsp_layer_sel = 0;
1873         int i, j, cnt = 0, ret = 0;
1874
1875         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1876         if (ret)
1877                 return ret;
1878
1879         ret = vop_csc_atomic_check(crtc, crtc_state);
1880         if (ret)
1881                 return ret;
1882
1883         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1884         if (!pzpos)
1885                 return -ENOMEM;
1886
1887         for (i = 0; i < vop_data->win_size; i++) {
1888                 const struct vop_win_data *win_data = &vop_data->win[i];
1889                 struct vop_win *win;
1890
1891                 if (!win_data->phy)
1892                         continue;
1893
1894                 for (j = 0; j < vop->num_wins; j++) {
1895                         win = &vop->win[j];
1896
1897                         if (win->win_id == i && !win->area_id)
1898                                 break;
1899                 }
1900                 if (WARN_ON(j >= vop->num_wins)) {
1901                         ret = -EINVAL;
1902                         goto err_free_pzpos;
1903                 }
1904
1905                 plane = &win->base;
1906                 pstate = state->plane_states[drm_plane_index(plane)];
1907                 /*
1908                  * plane might not have changed, in which case take
1909                  * current state:
1910                  */
1911                 if (!pstate)
1912                         pstate = plane->state;
1913                 plane_state = to_vop_plane_state(pstate);
1914                 pzpos[cnt].zpos = plane_state->zpos;
1915                 pzpos[cnt++].win_id = win->win_id;
1916         }
1917
1918         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1919
1920         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1921                 const struct vop_win_data *win_data = &vop_data->win[i];
1922                 int shift = i * 2;
1923
1924                 if (win_data->phy) {
1925                         struct vop_zpos *zpos = &pzpos[cnt++];
1926
1927                         dsp_layer_sel |= zpos->win_id << shift;
1928                 } else {
1929                         dsp_layer_sel |= i << shift;
1930                 }
1931         }
1932
1933         s->dsp_layer_sel = dsp_layer_sel;
1934
1935 err_free_pzpos:
1936         kfree(pzpos);
1937         return ret;
1938 }
1939
1940 static void vop_post_config(struct drm_crtc *crtc)
1941 {
1942         struct vop *vop = to_vop(crtc);
1943         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1944         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1945         u16 vtotal = mode->crtc_vtotal;
1946         u16 hdisplay = mode->crtc_hdisplay;
1947         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1948         u16 vdisplay = mode->crtc_vdisplay;
1949         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1950         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1951         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1952         u16 hact_end, vact_end;
1953         u32 val;
1954
1955         hact_st += hdisplay * (100 - s->left_margin) / 200;
1956         hact_end = hact_st + hsize;
1957         val = hact_st << 16;
1958         val |= hact_end;
1959         VOP_CTRL_SET(vop, hpost_st_end, val);
1960         vact_st += vdisplay * (100 - s->top_margin) / 200;
1961         vact_end = vact_st + vsize;
1962         val = vact_st << 16;
1963         val |= vact_end;
1964         VOP_CTRL_SET(vop, vpost_st_end, val);
1965         val = scl_cal_scale2(vdisplay, vsize) << 16;
1966         val |= scl_cal_scale2(hdisplay, hsize);
1967         VOP_CTRL_SET(vop, post_scl_factor, val);
1968         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1969         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1970                 u16 vact_st_f1 = vtotal + vact_st + 1;
1971                 u16 vact_end_f1 = vact_st_f1 + vsize;
1972
1973                 val = vact_st_f1 << 16 | vact_end_f1;
1974                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1975         }
1976 }
1977
1978 static void vop_cfg_update(struct drm_crtc *crtc,
1979                            struct drm_crtc_state *old_crtc_state)
1980 {
1981         struct rockchip_crtc_state *s =
1982                         to_rockchip_crtc_state(crtc->state);
1983         struct vop *vop = to_vop(crtc);
1984
1985         spin_lock(&vop->reg_lock);
1986
1987         if (s->afbdc_en) {
1988                 uint32_t pic_size;
1989
1990                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1991                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1992                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1993                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1994                 pic_size = (s->afbdc_win_width & 0xffff);
1995                 pic_size |= s->afbdc_win_height << 16;
1996                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1997         }
1998
1999         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2000         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2001         vop_post_config(crtc);
2002
2003         spin_unlock(&vop->reg_lock);
2004 }
2005
2006 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2007                                   struct drm_crtc_state *old_crtc_state)
2008 {
2009         struct vop *vop = to_vop(crtc);
2010
2011         vop_cfg_update(crtc, old_crtc_state);
2012
2013         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2014                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2015                 int ret;
2016
2017                 if (need_wait_vblank) {
2018                         bool active;
2019
2020                         disable_irq(vop->irq);
2021                         drm_crtc_vblank_get(crtc);
2022                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2023
2024                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2025                                                         vop, active, active,
2026                                                         0, 50 * 1000);
2027                         if (ret)
2028                                 dev_err(vop->dev, "wait fs irq timeout\n");
2029
2030                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2031                         vop_cfg_done(vop);
2032
2033                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2034                                                         vop, active, active,
2035                                                         0, 50 * 1000);
2036                         if (ret)
2037                                 dev_err(vop->dev, "wait line flag timeout\n");
2038
2039                         enable_irq(vop->irq);
2040                 }
2041                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2042                 if (ret)
2043                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2044                                 ret);
2045
2046                 if (need_wait_vblank) {
2047                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2048                         drm_crtc_vblank_put(crtc);
2049                 }
2050
2051                 vop->is_iommu_enabled = true;
2052         }
2053
2054         vop_cfg_done(vop);
2055 }
2056
2057 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2058                                   struct drm_crtc_state *old_crtc_state)
2059 {
2060         struct vop *vop = to_vop(crtc);
2061
2062         if (crtc->state->event) {
2063                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2064
2065                 vop->event = crtc->state->event;
2066                 crtc->state->event = NULL;
2067         }
2068 }
2069
2070 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2071         .load_lut = vop_crtc_load_lut,
2072         .enable = vop_crtc_enable,
2073         .disable = vop_crtc_disable,
2074         .mode_fixup = vop_crtc_mode_fixup,
2075         .atomic_check = vop_crtc_atomic_check,
2076         .atomic_flush = vop_crtc_atomic_flush,
2077         .atomic_begin = vop_crtc_atomic_begin,
2078 };
2079
2080 static void vop_crtc_destroy(struct drm_crtc *crtc)
2081 {
2082         drm_crtc_cleanup(crtc);
2083 }
2084
2085 static void vop_crtc_reset(struct drm_crtc *crtc)
2086 {
2087         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2088
2089         if (crtc->state) {
2090                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2091                 kfree(s);
2092         }
2093
2094         s = kzalloc(sizeof(*s), GFP_KERNEL);
2095         if (!s)
2096                 return;
2097         crtc->state = &s->base;
2098         crtc->state->crtc = crtc;
2099         s->left_margin = 100;
2100         s->right_margin = 100;
2101         s->top_margin = 100;
2102         s->bottom_margin = 100;
2103 }
2104
2105 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2106 {
2107         struct rockchip_crtc_state *rockchip_state, *old_state;
2108
2109         old_state = to_rockchip_crtc_state(crtc->state);
2110         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2111         if (!rockchip_state)
2112                 return NULL;
2113
2114         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2115         return &rockchip_state->base;
2116 }
2117
2118 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2119                                    struct drm_crtc_state *state)
2120 {
2121         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2122
2123         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2124         kfree(s);
2125 }
2126
2127 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2128                                         const struct drm_crtc_state *state,
2129                                         struct drm_property *property,
2130                                         uint64_t *val)
2131 {
2132         struct drm_device *drm_dev = crtc->dev;
2133         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2134         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2135
2136         if (property == mode_config->tv_left_margin_property) {
2137                 *val = s->left_margin;
2138                 return 0;
2139         }
2140
2141         if (property == mode_config->tv_right_margin_property) {
2142                 *val = s->right_margin;
2143                 return 0;
2144         }
2145
2146         if (property == mode_config->tv_top_margin_property) {
2147                 *val = s->top_margin;
2148                 return 0;
2149         }
2150
2151         if (property == mode_config->tv_bottom_margin_property) {
2152                 *val = s->bottom_margin;
2153                 return 0;
2154         }
2155
2156         DRM_ERROR("failed to get vop crtc property\n");
2157         return -EINVAL;
2158 }
2159
2160 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2161                                         struct drm_crtc_state *state,
2162                                         struct drm_property *property,
2163                                         uint64_t val)
2164 {
2165         struct drm_device *drm_dev = crtc->dev;
2166         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2167         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2168
2169         if (property == mode_config->tv_left_margin_property) {
2170                 s->left_margin = val;
2171                 return 0;
2172         }
2173
2174         if (property == mode_config->tv_right_margin_property) {
2175                 s->right_margin = val;
2176                 return 0;
2177         }
2178
2179         if (property == mode_config->tv_top_margin_property) {
2180                 s->top_margin = val;
2181                 return 0;
2182         }
2183
2184         if (property == mode_config->tv_bottom_margin_property) {
2185                 s->bottom_margin = val;
2186                 return 0;
2187         }
2188
2189         DRM_ERROR("failed to set vop crtc property\n");
2190         return -EINVAL;
2191 }
2192
2193 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2194                                u16 *blue, uint32_t start, uint32_t size)
2195 {
2196         struct vop *vop = to_vop(crtc);
2197         int end = min_t(u32, start + size, vop->lut_len);
2198         int i;
2199
2200         if (!vop->lut)
2201                 return;
2202
2203         for (i = start; i < end; i++)
2204                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2205                                                blue[i], i);
2206
2207         vop_crtc_load_lut(crtc);
2208 }
2209
2210 static const struct drm_crtc_funcs vop_crtc_funcs = {
2211         .gamma_set = vop_crtc_gamma_set,
2212         .set_config = drm_atomic_helper_set_config,
2213         .page_flip = drm_atomic_helper_page_flip,
2214         .destroy = vop_crtc_destroy,
2215         .reset = vop_crtc_reset,
2216         .atomic_get_property = vop_crtc_atomic_get_property,
2217         .atomic_set_property = vop_crtc_atomic_set_property,
2218         .atomic_duplicate_state = vop_crtc_duplicate_state,
2219         .atomic_destroy_state = vop_crtc_destroy_state,
2220 };
2221
2222 static void vop_handle_vblank(struct vop *vop)
2223 {
2224         struct drm_device *drm = vop->drm_dev;
2225         struct drm_crtc *crtc = &vop->crtc;
2226         unsigned long flags;
2227
2228         if (!vop_is_cfg_done_complete(vop))
2229                 return;
2230
2231         if (vop->event) {
2232                 spin_lock_irqsave(&drm->event_lock, flags);
2233
2234                 drm_crtc_send_vblank_event(crtc, vop->event);
2235                 drm_crtc_vblank_put(crtc);
2236                 vop->event = NULL;
2237
2238                 spin_unlock_irqrestore(&drm->event_lock, flags);
2239         }
2240         if (!completion_done(&vop->wait_update_complete))
2241                 complete(&vop->wait_update_complete);
2242 }
2243
2244 static irqreturn_t vop_isr(int irq, void *data)
2245 {
2246         struct vop *vop = data;
2247         struct drm_crtc *crtc = &vop->crtc;
2248         uint32_t active_irqs;
2249         unsigned long flags;
2250         int ret = IRQ_NONE;
2251
2252         /*
2253          * interrupt register has interrupt status, enable and clear bits, we
2254          * must hold irq_lock to avoid a race with enable/disable_vblank().
2255         */
2256         spin_lock_irqsave(&vop->irq_lock, flags);
2257
2258         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2259         /* Clear all active interrupt sources */
2260         if (active_irqs)
2261                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2262
2263         spin_unlock_irqrestore(&vop->irq_lock, flags);
2264
2265         /* This is expected for vop iommu irqs, since the irq is shared */
2266         if (!active_irqs)
2267                 return IRQ_NONE;
2268
2269         if (active_irqs & DSP_HOLD_VALID_INTR) {
2270                 complete(&vop->dsp_hold_completion);
2271                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2272                 ret = IRQ_HANDLED;
2273         }
2274
2275         if (active_irqs & LINE_FLAG_INTR) {
2276                 complete(&vop->line_flag_completion);
2277                 active_irqs &= ~LINE_FLAG_INTR;
2278                 ret = IRQ_HANDLED;
2279         }
2280
2281         if (active_irqs & FS_INTR) {
2282                 drm_crtc_handle_vblank(crtc);
2283                 vop_handle_vblank(vop);
2284                 active_irqs &= ~FS_INTR;
2285                 ret = IRQ_HANDLED;
2286         }
2287
2288         /* Unhandled irqs are spurious. */
2289         if (active_irqs)
2290                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2291
2292         return ret;
2293 }
2294
2295 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2296                           unsigned long possible_crtcs)
2297 {
2298         struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2299         struct drm_plane *share = NULL;
2300         unsigned int rotations = 0;
2301         struct drm_property *prop;
2302         uint64_t feature = 0;
2303         int ret;
2304
2305         if (win->parent)
2306                 share = &win->parent->base;
2307
2308         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2309                                    possible_crtcs, &vop_plane_funcs,
2310                                    win->data_formats, win->nformats, win->type);
2311         if (ret) {
2312                 DRM_ERROR("failed to initialize plane\n");
2313                 return ret;
2314         }
2315         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2316         drm_object_attach_property(&win->base.base,
2317                                    vop->plane_zpos_prop, win->win_id);
2318
2319         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2320                 rotations |= BIT(DRM_REFLECT_X);
2321
2322         if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2323                 rotations |= BIT(DRM_REFLECT_Y);
2324
2325                 prop = drm_property_create_bool(vop->drm_dev,
2326                                                 DRM_MODE_PROP_ATOMIC,
2327                                                 "LOGO_YMIRROR");
2328                 if (!prop)
2329                         return -ENOMEM;
2330                 private->logo_ymirror_prop = prop;
2331         }
2332
2333         if (rotations) {
2334                 rotations |= BIT(DRM_ROTATE_0);
2335                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2336                                                          rotations);
2337                 if (!prop) {
2338                         DRM_ERROR("failed to create zpos property\n");
2339                         return -EINVAL;
2340                 }
2341                 drm_object_attach_property(&win->base.base, prop,
2342                                            BIT(DRM_ROTATE_0));
2343                 win->rotation_prop = prop;
2344         }
2345         if (win->phy->scl)
2346                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2347         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2348             VOP_WIN_SUPPORT(vop, win, alpha_en))
2349                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2350
2351         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2352                                    feature);
2353
2354         return 0;
2355 }
2356
2357 static int vop_create_crtc(struct vop *vop)
2358 {
2359         struct device *dev = vop->dev;
2360         const struct vop_data *vop_data = vop->data;
2361         struct drm_device *drm_dev = vop->drm_dev;
2362         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2363         struct drm_crtc *crtc = &vop->crtc;
2364         struct device_node *port;
2365         uint64_t feature = 0;
2366         int ret;
2367         int i;
2368
2369         /*
2370          * Create drm_plane for primary and cursor planes first, since we need
2371          * to pass them to drm_crtc_init_with_planes, which sets the
2372          * "possible_crtcs" to the newly initialized crtc.
2373          */
2374         for (i = 0; i < vop->num_wins; i++) {
2375                 struct vop_win *win = &vop->win[i];
2376
2377                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2378                     win->type != DRM_PLANE_TYPE_CURSOR)
2379                         continue;
2380
2381                 ret = vop_plane_init(vop, win, 0);
2382                 if (ret)
2383                         goto err_cleanup_planes;
2384
2385                 plane = &win->base;
2386                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2387                         primary = plane;
2388                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2389                         cursor = plane;
2390
2391         }
2392
2393         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2394                                         &vop_crtc_funcs, NULL);
2395         if (ret)
2396                 goto err_cleanup_planes;
2397
2398         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2399
2400         /*
2401          * Create drm_planes for overlay windows with possible_crtcs restricted
2402          * to the newly created crtc.
2403          */
2404         for (i = 0; i < vop->num_wins; i++) {
2405                 struct vop_win *win = &vop->win[i];
2406                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2407
2408                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2409                         continue;
2410
2411                 ret = vop_plane_init(vop, win, possible_crtcs);
2412                 if (ret)
2413                         goto err_cleanup_crtc;
2414         }
2415
2416         port = of_get_child_by_name(dev->of_node, "port");
2417         if (!port) {
2418                 DRM_ERROR("no port node found in %s\n",
2419                           dev->of_node->full_name);
2420                 ret = -ENOENT;
2421                 goto err_cleanup_crtc;
2422         }
2423
2424         init_completion(&vop->dsp_hold_completion);
2425         init_completion(&vop->wait_update_complete);
2426         init_completion(&vop->line_flag_completion);
2427         crtc->port = port;
2428         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2429
2430         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2431         if (ret)
2432                 goto err_unregister_crtc_funcs;
2433 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2434         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2435
2436         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2437         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2438         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2439         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2440 #undef VOP_ATTACH_MODE_CONFIG_PROP
2441
2442         if (vop_data->feature & VOP_FEATURE_AFBDC)
2443                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2444         drm_object_attach_property(&crtc->base, vop->feature_prop,
2445                                    feature);
2446         if (vop->lut_regs) {
2447                 u16 *r_base, *g_base, *b_base;
2448                 u32 lut_len = vop->lut_len;
2449
2450                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2451                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2452                                               GFP_KERNEL);
2453                 if (!vop->lut)
2454                         return -ENOMEM;
2455
2456                 r_base = crtc->gamma_store;
2457                 g_base = r_base + crtc->gamma_size;
2458                 b_base = g_base + crtc->gamma_size;
2459
2460                 for (i = 0; i < lut_len; i++) {
2461                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2462                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2463                                                        &g_base[i], &b_base[i],
2464                                                        i);
2465                 }
2466         }
2467
2468         return 0;
2469
2470 err_unregister_crtc_funcs:
2471         rockchip_unregister_crtc_funcs(crtc);
2472 err_cleanup_crtc:
2473         drm_crtc_cleanup(crtc);
2474 err_cleanup_planes:
2475         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2476                                  head)
2477                 drm_plane_cleanup(plane);
2478         return ret;
2479 }
2480
2481 static void vop_destroy_crtc(struct vop *vop)
2482 {
2483         struct drm_crtc *crtc = &vop->crtc;
2484         struct drm_device *drm_dev = vop->drm_dev;
2485         struct drm_plane *plane, *tmp;
2486
2487         rockchip_unregister_crtc_funcs(crtc);
2488         of_node_put(crtc->port);
2489
2490         /*
2491          * We need to cleanup the planes now.  Why?
2492          *
2493          * The planes are "&vop->win[i].base".  That means the memory is
2494          * all part of the big "struct vop" chunk of memory.  That memory
2495          * was devm allocated and associated with this component.  We need to
2496          * free it ourselves before vop_unbind() finishes.
2497          */
2498         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2499                                  head)
2500                 vop_plane_destroy(plane);
2501
2502         /*
2503          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2504          * references the CRTC.
2505          */
2506         drm_crtc_cleanup(crtc);
2507 }
2508
2509 /*
2510  * Initialize the vop->win array elements.
2511  */
2512 static int vop_win_init(struct vop *vop)
2513 {
2514         const struct vop_data *vop_data = vop->data;
2515         unsigned int i, j;
2516         unsigned int num_wins = 0;
2517         struct drm_property *prop;
2518         static const struct drm_prop_enum_list props[] = {
2519                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2520                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2521         };
2522         static const struct drm_prop_enum_list crtc_props[] = {
2523                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2524         };
2525
2526         for (i = 0; i < vop_data->win_size; i++) {
2527                 struct vop_win *vop_win = &vop->win[num_wins];
2528                 const struct vop_win_data *win_data = &vop_data->win[i];
2529
2530                 if (!win_data->phy)
2531                         continue;
2532
2533                 vop_win->phy = win_data->phy;
2534                 vop_win->csc = win_data->csc;
2535                 vop_win->offset = win_data->base;
2536                 vop_win->type = win_data->type;
2537                 vop_win->data_formats = win_data->phy->data_formats;
2538                 vop_win->nformats = win_data->phy->nformats;
2539                 vop_win->vop = vop;
2540                 vop_win->win_id = i;
2541                 vop_win->area_id = 0;
2542                 num_wins++;
2543
2544                 for (j = 0; j < win_data->area_size; j++) {
2545                         struct vop_win *vop_area = &vop->win[num_wins];
2546                         const struct vop_win_phy *area = win_data->area[j];
2547
2548                         vop_area->parent = vop_win;
2549                         vop_area->offset = vop_win->offset;
2550                         vop_area->phy = area;
2551                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2552                         vop_area->data_formats = vop_win->data_formats;
2553                         vop_area->nformats = vop_win->nformats;
2554                         vop_area->vop = vop;
2555                         vop_area->win_id = i;
2556                         vop_area->area_id = j;
2557                         num_wins++;
2558                 }
2559         }
2560
2561         vop->num_wins = num_wins;
2562
2563         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2564                                          "ZPOS", 0, vop->data->win_size);
2565         if (!prop) {
2566                 DRM_ERROR("failed to create zpos property\n");
2567                 return -EINVAL;
2568         }
2569         vop->plane_zpos_prop = prop;
2570
2571         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2572                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2573                                 props, ARRAY_SIZE(props),
2574                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2575                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2576         if (!vop->plane_feature_prop) {
2577                 DRM_ERROR("failed to create feature property\n");
2578                 return -EINVAL;
2579         }
2580
2581         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2582                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2583                                 crtc_props, ARRAY_SIZE(crtc_props),
2584                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2585         if (!vop->feature_prop) {
2586                 DRM_ERROR("failed to create vop feature property\n");
2587                 return -EINVAL;
2588         }
2589
2590         return 0;
2591 }
2592
2593 /**
2594  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2595  * @crtc: CRTC to enable line flag
2596  * @line_num: interested line number
2597  * @mstimeout: millisecond for timeout
2598  *
2599  * Driver would hold here until the interested line flag interrupt have
2600  * happened or timeout to wait.
2601  *
2602  * Returns:
2603  * Zero on success, negative errno on failure.
2604  */
2605 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2606                                 unsigned int mstimeout)
2607 {
2608         struct vop *vop = to_vop(crtc);
2609         unsigned long jiffies_left;
2610         int ret = 0;
2611
2612         if (!crtc || !vop->is_enabled)
2613                 return -ENODEV;
2614
2615         mutex_lock(&vop->vop_lock);
2616
2617         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2618                 ret = -EINVAL;
2619                 goto out;
2620         }
2621
2622         if (vop_line_flag_irq_is_enabled(vop)) {
2623                 ret = -EBUSY;
2624                 goto out;
2625         }
2626
2627         reinit_completion(&vop->line_flag_completion);
2628         vop_line_flag_irq_enable(vop, line_num);
2629
2630         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2631                                                    msecs_to_jiffies(mstimeout));
2632         vop_line_flag_irq_disable(vop);
2633
2634         if (jiffies_left == 0) {
2635                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2636                 ret = -ETIMEDOUT;
2637                 goto out;
2638         }
2639
2640 out:
2641         mutex_unlock(&vop->vop_lock);
2642
2643         return ret;
2644 }
2645 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2646
2647 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
2648                              void *data)
2649 {
2650         if (event == DEVFREQ_PRECHANGE)
2651                 mutex_lock(&dmc_vop->vop_lock);
2652         else if (event == DEVFREQ_POSTCHANGE)
2653                 mutex_unlock(&dmc_vop->vop_lock);
2654
2655         return NOTIFY_OK;
2656 }
2657
2658 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
2659 {
2660         if (!dmc_vop)
2661                 return -ENOMEM;
2662
2663         dmc_vop->devfreq = devfreq;
2664         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
2665         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
2666                                   DEVFREQ_TRANSITION_NOTIFIER);
2667         return 0;
2668 }
2669 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
2670
2671 static int vop_bind(struct device *dev, struct device *master, void *data)
2672 {
2673         struct platform_device *pdev = to_platform_device(dev);
2674         const struct vop_data *vop_data;
2675         struct drm_device *drm_dev = data;
2676         struct vop *vop;
2677         struct resource *res;
2678         size_t alloc_size;
2679         int ret, irq, i;
2680         int num_wins = 0;
2681
2682         vop_data = of_device_get_match_data(dev);
2683         if (!vop_data)
2684                 return -ENODEV;
2685
2686         for (i = 0; i < vop_data->win_size; i++) {
2687                 const struct vop_win_data *win_data = &vop_data->win[i];
2688
2689                 num_wins += win_data->area_size + 1;
2690         }
2691
2692         /* Allocate vop struct and its vop_win array */
2693         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2694         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2695         if (!vop)
2696                 return -ENOMEM;
2697
2698         vop->dev = dev;
2699         vop->data = vop_data;
2700         vop->drm_dev = drm_dev;
2701         vop->num_wins = num_wins;
2702         dev_set_drvdata(dev, vop);
2703
2704         ret = vop_win_init(vop);
2705         if (ret)
2706                 return ret;
2707
2708         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2709         vop->len = resource_size(res);
2710         vop->regs = devm_ioremap_resource(dev, res);
2711         if (IS_ERR(vop->regs))
2712                 return PTR_ERR(vop->regs);
2713
2714         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2715         if (!vop->regsbak)
2716                 return -ENOMEM;
2717
2718         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2719         vop->lut_regs = devm_ioremap_resource(dev, res);
2720         if (IS_ERR(vop->lut_regs)) {
2721                 dev_warn(vop->dev, "failed to get vop lut registers\n");
2722                 vop->lut_regs = NULL;
2723         }
2724         if (vop->lut_regs) {
2725                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
2726                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
2727                         dev_err(vop->dev, "unsupport lut sizes %d\n",
2728                                 vop->lut_len);
2729                         return -EINVAL;
2730                 }
2731         }
2732
2733         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2734         if (IS_ERR(vop->hclk)) {
2735                 dev_err(vop->dev, "failed to get hclk source\n");
2736                 return PTR_ERR(vop->hclk);
2737         }
2738         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2739         if (IS_ERR(vop->aclk)) {
2740                 dev_err(vop->dev, "failed to get aclk source\n");
2741                 return PTR_ERR(vop->aclk);
2742         }
2743         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2744         if (IS_ERR(vop->dclk)) {
2745                 dev_err(vop->dev, "failed to get dclk source\n");
2746                 return PTR_ERR(vop->dclk);
2747         }
2748
2749         irq = platform_get_irq(pdev, 0);
2750         if (irq < 0) {
2751                 dev_err(dev, "cannot find irq for vop\n");
2752                 return irq;
2753         }
2754         vop->irq = (unsigned int)irq;
2755
2756         spin_lock_init(&vop->reg_lock);
2757         spin_lock_init(&vop->irq_lock);
2758         mutex_init(&vop->vop_lock);
2759
2760         mutex_init(&vop->vsync_mutex);
2761
2762         ret = devm_request_irq(dev, vop->irq, vop_isr,
2763                                IRQF_SHARED, dev_name(dev), vop);
2764         if (ret)
2765                 return ret;
2766
2767         /* IRQ is initially disabled; it gets enabled in power_on */
2768         disable_irq(vop->irq);
2769
2770         ret = vop_create_crtc(vop);
2771         if (ret)
2772                 return ret;
2773
2774         pm_runtime_enable(&pdev->dev);
2775
2776         dmc_vop = vop;
2777
2778         return 0;
2779 }
2780
2781 static void vop_unbind(struct device *dev, struct device *master, void *data)
2782 {
2783         struct vop *vop = dev_get_drvdata(dev);
2784
2785         pm_runtime_disable(dev);
2786         vop_destroy_crtc(vop);
2787 }
2788
2789 const struct component_ops vop_component_ops = {
2790         .bind = vop_bind,
2791         .unbind = vop_unbind,
2792 };
2793 EXPORT_SYMBOL_GPL(vop_component_ops);