2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
23 #include <linux/devfreq.h>
24 #include <linux/iopoll.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/iopoll.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/component.h>
35 #include <linux/reset.h>
36 #include <linux/delay.h>
37 #include <linux/sort.h>
38 #include <uapi/drm/rockchip_drm.h>
40 #include "rockchip_drm_drv.h"
41 #include "rockchip_drm_gem.h"
42 #include "rockchip_drm_fb.h"
43 #include "rockchip_drm_vop.h"
44 #include "rockchip_drm_backlight.h"
46 #define VOP_REG_SUPPORT(vop, reg) \
47 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
48 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
49 reg.end_minor >= VOP_MINOR(vop->data->version) && \
52 #define VOP_WIN_SUPPORT(vop, win, name) \
53 VOP_REG_SUPPORT(vop, win->phy->name)
55 #define VOP_CTRL_SUPPORT(vop, name) \
56 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
58 #define VOP_INTR_SUPPORT(vop, name) \
59 VOP_REG_SUPPORT(vop, vop->data->intr->name)
61 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
62 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
64 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
66 if (VOP_REG_SUPPORT(vop, reg)) \
67 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
68 v, reg.write_mask, relaxed); \
70 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
73 #define REG_SET(x, name, off, reg, v, relaxed) \
74 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
75 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
76 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
78 #define VOP_WIN_SET(x, win, name, v) \
79 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
80 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
81 REG_SET(x, name, 0, win->ext->name, v, true)
82 #define VOP_SCL_SET(x, win, name, v) \
83 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
84 #define VOP_SCL_SET_EXT(x, win, name, v) \
85 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
87 #define VOP_CTRL_SET(x, name, v) \
88 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
90 #define VOP_INTR_GET(vop, name) \
91 vop_read_reg(vop, 0, &vop->data->ctrl->name)
93 #define VOP_INTR_SET(vop, name, v) \
94 REG_SET(vop, name, 0, vop->data->intr->name, \
96 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
97 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
100 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
102 int i, reg = 0, mask = 0; \
103 for (i = 0; i < vop->data->intr->nintrs; i++) { \
104 if (vop->data->intr->intrs[i] & type) { \
109 VOP_INTR_SET_MASK(vop, name, mask, reg); \
111 #define VOP_INTR_GET_TYPE(vop, name, type) \
112 vop_get_intr_type(vop, &vop->data->intr->name, type)
114 #define VOP_CTRL_GET(x, name) \
115 vop_read_reg(x, 0, &vop->data->ctrl->name)
117 #define VOP_WIN_GET(x, win, name) \
118 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
120 #define VOP_WIN_NAME(win, name) \
121 (vop_get_win_phy(win, &win->phy->name)->name)
123 #define VOP_WIN_GET_YRGBADDR(vop, win) \
124 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
126 #define to_vop(x) container_of(x, struct vop, crtc)
127 #define to_vop_win(x) container_of(x, struct vop_win, base)
128 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
136 VOP_PENDING_FB_UNREF,
139 struct vop_plane_state {
140 struct drm_plane_state base;
143 unsigned int logo_ymirror;
145 struct drm_rect dest;
148 const uint32_t *y2r_table;
149 const uint32_t *r2r_table;
150 const uint32_t *r2y_table;
155 struct vop_win *parent;
156 struct drm_plane base;
161 enum drm_plane_type type;
162 const struct vop_win_phy *phy;
163 const struct vop_csc *csc;
164 const uint32_t *data_formats;
168 struct drm_property *rotation_prop;
169 struct vop_plane_state state;
173 struct drm_crtc crtc;
175 struct drm_device *drm_dev;
176 struct drm_property *plane_zpos_prop;
177 struct drm_property *plane_feature_prop;
178 struct drm_property *feature_prop;
179 bool is_iommu_enabled;
180 bool is_iommu_needed;
183 /* mutex vsync_ work */
184 struct mutex vsync_mutex;
185 bool vsync_work_pending;
187 struct completion dsp_hold_completion;
189 /* protected by dev->event_lock */
190 struct drm_pending_vblank_event *event;
192 struct drm_flip_work fb_unref_work;
193 unsigned long pending;
195 struct completion line_flag_completion;
197 const struct vop_data *data;
203 /* physical map length of vop register */
206 void __iomem *lut_regs;
210 void __iomem *cabc_lut_regs;
213 /* one time only one process allowed to config the register */
215 /* lock vop irq reg */
217 /* mutex vop enable and disable */
218 struct mutex vop_lock;
226 /* vop share memory frequency */
228 /* vop source handling, optional */
229 struct clk *dclk_source;
232 struct reset_control *dclk_rst;
234 struct devfreq *devfreq;
235 struct notifier_block dmc_nb;
237 struct rockchip_dclk_pll *pll;
239 struct vop_win win[];
244 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
246 writel(v, vop->regs + offset);
247 vop->regsbak[offset >> 2] = v;
250 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
252 return readl(vop->regs + offset);
255 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
256 const struct vop_reg *reg)
258 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
261 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
262 uint32_t mask, uint32_t shift, uint32_t v,
263 bool write_mask, bool relaxed)
269 v = ((v & mask) << shift) | (mask << (shift + 16));
271 uint32_t cached_val = vop->regsbak[offset >> 2];
273 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
274 vop->regsbak[offset >> 2] = v;
278 writel_relaxed(v, vop->regs + offset);
280 writel(v, vop->regs + offset);
283 static inline const struct vop_win_phy *
284 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
286 if (!reg->mask && win->parent)
287 return win->parent->phy;
292 static inline uint32_t vop_get_intr_type(struct vop *vop,
293 const struct vop_reg *reg, int type)
296 uint32_t regs = vop_read_reg(vop, 0, reg);
298 for (i = 0; i < vop->data->intr->nintrs; i++) {
299 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
300 ret |= vop->data->intr->intrs[i];
306 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
313 for (i = 0; i < 8; i++)
314 vop_writel(vop, offset + i * 4, table[i]);
317 static inline void vop_cfg_done(struct vop *vop)
319 VOP_CTRL_SET(vop, cfg_done, 1);
322 static bool vop_is_allwin_disabled(struct vop *vop)
326 for (i = 0; i < vop->num_wins; i++) {
327 struct vop_win *win = &vop->win[i];
329 if (VOP_WIN_GET(vop, win, enable) != 0)
336 static bool vop_fs_irq_is_active(struct vop *vop)
338 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
341 static bool vop_line_flag_is_active(struct vop *vop)
343 return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
346 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
348 writel(v, vop->lut_regs + offset);
351 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
353 return readl(vop->lut_regs + offset);
356 static inline void vop_write_cabc_lut(struct vop *vop, uint32_t offset, uint32_t v)
358 writel(v, vop->cabc_lut_regs + offset);
361 static bool has_rb_swapped(uint32_t format)
364 case DRM_FORMAT_XBGR8888:
365 case DRM_FORMAT_ABGR8888:
366 case DRM_FORMAT_BGR888:
367 case DRM_FORMAT_BGR565:
374 static enum vop_data_format vop_convert_format(uint32_t format)
377 case DRM_FORMAT_XRGB8888:
378 case DRM_FORMAT_ARGB8888:
379 case DRM_FORMAT_XBGR8888:
380 case DRM_FORMAT_ABGR8888:
381 return VOP_FMT_ARGB8888;
382 case DRM_FORMAT_RGB888:
383 case DRM_FORMAT_BGR888:
384 return VOP_FMT_RGB888;
385 case DRM_FORMAT_RGB565:
386 case DRM_FORMAT_BGR565:
387 return VOP_FMT_RGB565;
388 case DRM_FORMAT_NV12:
389 case DRM_FORMAT_NV12_10:
390 return VOP_FMT_YUV420SP;
391 case DRM_FORMAT_NV16:
392 case DRM_FORMAT_NV16_10:
393 return VOP_FMT_YUV422SP;
394 case DRM_FORMAT_NV24:
395 case DRM_FORMAT_NV24_10:
396 return VOP_FMT_YUV444SP;
398 DRM_ERROR("unsupport format[%08x]\n", format);
403 static bool is_yuv_output(uint32_t bus_format)
405 switch (bus_format) {
406 case MEDIA_BUS_FMT_YUV8_1X24:
407 case MEDIA_BUS_FMT_YUV10_1X30:
408 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
409 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
416 static bool is_yuv_support(uint32_t format)
419 case DRM_FORMAT_NV12:
420 case DRM_FORMAT_NV12_10:
421 case DRM_FORMAT_NV16:
422 case DRM_FORMAT_NV16_10:
423 case DRM_FORMAT_NV24:
424 case DRM_FORMAT_NV24_10:
431 static bool is_yuv_10bit(uint32_t format)
434 case DRM_FORMAT_NV12_10:
435 case DRM_FORMAT_NV16_10:
436 case DRM_FORMAT_NV24_10:
443 static bool is_alpha_support(uint32_t format)
446 case DRM_FORMAT_ARGB8888:
447 case DRM_FORMAT_ABGR8888:
454 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
455 uint32_t dst, bool is_horizontal,
456 int vsu_mode, int *vskiplines)
458 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
461 if (mode == SCALE_UP)
462 val = GET_SCL_FT_BIC(src, dst);
463 else if (mode == SCALE_DOWN)
464 val = GET_SCL_FT_BILI_DN(src, dst);
466 if (mode == SCALE_UP) {
467 if (vsu_mode == SCALE_UP_BIL)
468 val = GET_SCL_FT_BILI_UP(src, dst);
470 val = GET_SCL_FT_BIC(src, dst);
471 } else if (mode == SCALE_DOWN) {
473 *vskiplines = scl_get_vskiplines(src, dst);
474 val = scl_get_bili_dn_vskip(src, dst,
477 val = GET_SCL_FT_BILI_DN(src, dst);
485 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
486 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
487 uint32_t dst_h, uint32_t pixel_format)
489 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
490 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
491 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
492 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
493 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
494 bool is_yuv = is_yuv_support(pixel_format);
495 uint16_t cbcr_src_w = src_w / hsub;
496 uint16_t cbcr_src_h = src_h / vsub;
505 if (!win->phy->scl->ext) {
506 VOP_SCL_SET(vop, win, scale_yrgb_x,
507 scl_cal_scale2(src_w, dst_w));
508 VOP_SCL_SET(vop, win, scale_yrgb_y,
509 scl_cal_scale2(src_h, dst_h));
511 VOP_SCL_SET(vop, win, scale_cbcr_x,
512 scl_cal_scale2(cbcr_src_w, dst_w));
513 VOP_SCL_SET(vop, win, scale_cbcr_y,
514 scl_cal_scale2(cbcr_src_h, dst_h));
519 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
520 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
523 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
524 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
525 if (cbcr_hor_scl_mode == SCALE_DOWN)
526 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
528 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
530 if (yrgb_hor_scl_mode == SCALE_DOWN)
531 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
533 lb_mode = scl_vop_cal_lb_mode(src_w, false);
536 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
537 if (lb_mode == LB_RGB_3840X2) {
538 if (yrgb_ver_scl_mode != SCALE_NONE) {
539 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
542 if (cbcr_ver_scl_mode != SCALE_NONE) {
543 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
546 vsu_mode = SCALE_UP_BIL;
547 } else if (lb_mode == LB_RGB_2560X4) {
548 vsu_mode = SCALE_UP_BIL;
550 vsu_mode = SCALE_UP_BIC;
553 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
555 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
556 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
557 false, vsu_mode, &vskiplines);
558 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
560 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
561 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
563 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
564 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
565 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
566 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
567 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
571 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
572 dst_w, true, 0, NULL);
573 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
574 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
575 dst_h, false, vsu_mode, &vskiplines);
576 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
578 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
579 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
580 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
581 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
582 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
583 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
584 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
589 * rk3399 colorspace path:
590 * Input Win csc Output
591 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
594 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
595 * RGB --> 709To2020->R2Y __/
597 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
600 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
601 * RGB --> 709To2020->R2Y __/
603 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
606 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
607 * RGB --> R2Y(601) __/
609 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
612 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
614 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
616 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
618 * 11. RGB --> bypass --> RGB_OUTPUT(709)
620 static int vop_csc_setup(const struct vop_csc_table *csc_table,
621 bool is_input_yuv, bool is_output_yuv,
622 int input_csc, int output_csc,
623 const uint32_t **y2r_table,
624 const uint32_t **r2r_table,
625 const uint32_t **r2y_table)
632 if (output_csc == CSC_BT2020) {
634 if (input_csc == CSC_BT2020)
636 *y2r_table = csc_table->y2r_bt709;
638 if (input_csc != CSC_BT2020)
639 *r2r_table = csc_table->r2r_bt709_to_bt2020;
640 *r2y_table = csc_table->r2y_bt2020;
642 if (is_input_yuv && input_csc == CSC_BT2020)
643 *y2r_table = csc_table->y2r_bt2020;
644 if (input_csc == CSC_BT2020)
645 *r2r_table = csc_table->r2r_bt2020_to_bt709;
646 if (!is_input_yuv || *y2r_table) {
647 if (output_csc == CSC_BT709)
648 *r2y_table = csc_table->r2y_bt709;
650 *r2y_table = csc_table->r2y_bt601;
658 * is possible use bt2020 on rgb mode?
660 if (WARN_ON(output_csc == CSC_BT2020))
663 if (input_csc == CSC_BT2020)
664 *y2r_table = csc_table->y2r_bt2020;
665 else if (input_csc == CSC_BT709)
666 *y2r_table = csc_table->y2r_bt709;
668 *y2r_table = csc_table->y2r_bt601;
670 if (input_csc == CSC_BT2020)
672 * We don't have bt601 to bt709 table, force use bt709.
674 *r2r_table = csc_table->r2r_bt2020_to_bt709;
680 static int vop_csc_atomic_check(struct drm_crtc *crtc,
681 struct drm_crtc_state *crtc_state)
683 struct vop *vop = to_vop(crtc);
684 struct drm_atomic_state *state = crtc_state->state;
685 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
686 const struct vop_csc_table *csc_table = vop->data->csc_table;
687 struct drm_plane_state *pstate;
688 struct drm_plane *plane;
689 bool is_input_yuv, is_output_yuv;
695 is_output_yuv = is_yuv_output(s->bus_format);
697 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
698 struct vop_plane_state *vop_plane_state;
700 pstate = drm_atomic_get_plane_state(state, plane);
702 return PTR_ERR(pstate);
703 vop_plane_state = to_vop_plane_state(pstate);
707 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
710 * TODO: force set input and output csc mode.
712 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
713 CSC_BT709, CSC_BT709,
714 &vop_plane_state->y2r_table,
715 &vop_plane_state->r2r_table,
716 &vop_plane_state->r2y_table);
724 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
728 spin_lock_irqsave(&vop->irq_lock, flags);
730 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
731 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
733 spin_unlock_irqrestore(&vop->irq_lock, flags);
736 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
740 spin_lock_irqsave(&vop->irq_lock, flags);
742 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
744 spin_unlock_irqrestore(&vop->irq_lock, flags);
748 * (1) each frame starts at the start of the Vsync pulse which is signaled by
749 * the "FRAME_SYNC" interrupt.
750 * (2) the active data region of each frame ends at dsp_vact_end
751 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
752 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
754 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
756 * LINE_FLAG -------------------------------+
760 * | Vsync | Vbp | Vactive | Vfp |
764 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
765 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
766 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
767 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
769 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
771 uint32_t line_flag_irq;
774 spin_lock_irqsave(&vop->irq_lock, flags);
776 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
778 spin_unlock_irqrestore(&vop->irq_lock, flags);
780 return !!line_flag_irq;
783 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
787 if (WARN_ON(!vop->is_enabled))
790 spin_lock_irqsave(&vop->irq_lock, flags);
792 VOP_INTR_SET(vop, line_flag_num[0], line_num);
793 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
794 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
796 spin_unlock_irqrestore(&vop->irq_lock, flags);
799 static void vop_line_flag_irq_disable(struct vop *vop)
803 if (WARN_ON(!vop->is_enabled))
806 spin_lock_irqsave(&vop->irq_lock, flags);
808 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
810 spin_unlock_irqrestore(&vop->irq_lock, flags);
813 static void vop_crtc_load_lut(struct drm_crtc *crtc)
815 struct vop *vop = to_vop(crtc);
818 if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
821 if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
824 if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
825 spin_lock(&vop->reg_lock);
826 VOP_CTRL_SET(vop, dsp_lut_en, 0);
828 spin_unlock(&vop->reg_lock);
830 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
831 readx_poll_timeout(CTRL_GET, dsp_lut_en,
832 dle, !dle, 5, 33333);
834 lut_idx = CTRL_GET(lut_buffer_index);
837 for (i = 0; i < vop->lut_len; i++)
838 vop_write_lut(vop, i << 2, vop->lut[i]);
840 spin_lock(&vop->reg_lock);
842 VOP_CTRL_SET(vop, dsp_lut_en, 1);
843 VOP_CTRL_SET(vop, update_gamma_lut, 1);
845 vop->lut_active = true;
847 spin_unlock(&vop->reg_lock);
849 if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
850 readx_poll_timeout(CTRL_GET, lut_buffer_index,
851 dle, dle != lut_idx, 5, 33333);
853 * update_gamma value auto clean to 0 by HW, should not
856 VOP_CTRL_SET(vop, update_gamma_lut, 0);
861 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
864 struct vop *vop = to_vop(crtc);
865 u32 lut_len = vop->lut_len;
868 if (regno >= lut_len || !vop->lut)
871 r = red * (lut_len - 1) / 0xffff;
872 g = green * (lut_len - 1) / 0xffff;
873 b = blue * (lut_len - 1) / 0xffff;
874 vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
877 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
878 u16 *blue, int regno)
880 struct vop *vop = to_vop(crtc);
881 u32 lut_len = vop->lut_len;
884 if (regno >= lut_len || !vop->lut)
887 r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
888 g = (vop->lut[regno] / lut_len) & (lut_len - 1);
889 b = vop->lut[regno] & (lut_len - 1);
890 *red = r * 0xffff / (lut_len - 1);
891 *green = g * 0xffff / (lut_len - 1);
892 *blue = b * 0xffff / (lut_len - 1);
895 static void vop_power_enable(struct drm_crtc *crtc)
897 struct vop *vop = to_vop(crtc);
900 ret = clk_prepare_enable(vop->hclk);
902 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
906 ret = clk_prepare_enable(vop->dclk);
908 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
909 goto err_disable_hclk;
912 ret = clk_prepare_enable(vop->aclk);
914 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
915 goto err_disable_dclk;
918 ret = pm_runtime_get_sync(vop->dev);
920 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
924 memcpy(vop->regsbak, vop->regs, vop->len);
926 vop->is_enabled = true;
931 clk_disable_unprepare(vop->dclk);
933 clk_disable_unprepare(vop->hclk);
936 static void vop_initial(struct drm_crtc *crtc)
938 struct vop *vop = to_vop(crtc);
942 vop_power_enable(crtc);
944 VOP_CTRL_SET(vop, global_regdone_en, 1);
945 VOP_CTRL_SET(vop, dsp_blank, 0);
948 * restore the lut table.
951 vop_crtc_load_lut(crtc);
954 * We need to make sure that all windows are disabled before resume
955 * the crtc. Otherwise we might try to scan from a destroyed
958 for (i = 0; i < vop->num_wins; i++) {
959 struct vop_win *win = &vop->win[i];
960 int channel = i * 2 + 1;
962 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
963 if (win->phy->scl && win->phy->scl->ext) {
964 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
965 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
966 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
967 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
969 VOP_WIN_SET(vop, win, enable, 0);
970 VOP_WIN_SET(vop, win, gate, 1);
972 VOP_CTRL_SET(vop, afbdc_en, 0);
974 irqs = BUS_ERROR_INTR | WIN0_EMPTY_INTR | WIN1_EMPTY_INTR |
975 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | HWC_EMPTY_INTR |
977 VOP_INTR_SET_TYPE(vop, clear, irqs, 1);
978 VOP_INTR_SET_TYPE(vop, enable, irqs, 1);
981 static void vop_crtc_disable(struct drm_crtc *crtc)
983 struct vop *vop = to_vop(crtc);
985 mutex_lock(&vop->vop_lock);
986 drm_crtc_vblank_off(crtc);
989 * Vop standby will take effect at end of current frame,
990 * if dsp hold valid irq happen, it means standby complete.
992 * we must wait standby complete when we want to disable aclk,
993 * if not, memory bus maybe dead.
995 reinit_completion(&vop->dsp_hold_completion);
996 vop_dsp_hold_valid_irq_enable(vop);
998 spin_lock(&vop->reg_lock);
1000 VOP_CTRL_SET(vop, standby, 1);
1002 spin_unlock(&vop->reg_lock);
1004 WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
1005 msecs_to_jiffies(50)));
1007 vop_dsp_hold_valid_irq_disable(vop);
1009 disable_irq(vop->irq);
1011 vop->is_enabled = false;
1012 if (vop->is_iommu_enabled) {
1014 * vop standby complete, so iommu detach is safe.
1016 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
1017 vop->is_iommu_enabled = false;
1020 pm_runtime_put(vop->dev);
1021 clk_disable_unprepare(vop->dclk);
1022 clk_disable_unprepare(vop->aclk);
1023 clk_disable_unprepare(vop->hclk);
1024 mutex_unlock(&vop->vop_lock);
1027 static void vop_plane_destroy(struct drm_plane *plane)
1029 drm_plane_cleanup(plane);
1032 static int vop_plane_prepare_fb(struct drm_plane *plane,
1033 const struct drm_plane_state *new_state)
1035 if (plane->state->fb)
1036 drm_framebuffer_reference(plane->state->fb);
1041 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1042 const struct drm_plane_state *old_state)
1045 drm_framebuffer_unreference(old_state->fb);
1048 static int vop_plane_atomic_check(struct drm_plane *plane,
1049 struct drm_plane_state *state)
1051 struct drm_crtc *crtc = state->crtc;
1052 struct drm_framebuffer *fb = state->fb;
1053 struct vop_win *win = to_vop_win(plane);
1054 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1055 struct drm_crtc_state *crtc_state;
1056 const struct vop_data *vop_data;
1060 struct drm_rect *dest = &vop_plane_state->dest;
1061 struct drm_rect *src = &vop_plane_state->src;
1062 struct drm_rect clip;
1063 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1064 DRM_PLANE_HELPER_NO_SCALING;
1065 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1066 DRM_PLANE_HELPER_NO_SCALING;
1067 unsigned long offset;
1068 dma_addr_t dma_addr;
1071 crtc = crtc ? crtc : plane->state->crtc;
1073 * Both crtc or plane->state->crtc can be null.
1078 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1079 if (IS_ERR(crtc_state))
1080 return PTR_ERR(crtc_state);
1082 src->x1 = state->src_x;
1083 src->y1 = state->src_y;
1084 src->x2 = state->src_x + state->src_w;
1085 src->y2 = state->src_y + state->src_h;
1086 dest->x1 = state->crtc_x;
1087 dest->y1 = state->crtc_y;
1088 dest->x2 = state->crtc_x + state->crtc_w;
1089 dest->y2 = state->crtc_y + state->crtc_h;
1091 vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1092 if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1097 clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1100 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1104 true, true, &visible);
1111 vop_plane_state->format = vop_convert_format(fb->pixel_format);
1112 if (vop_plane_state->format < 0)
1113 return vop_plane_state->format;
1116 vop_data = vop->data;
1118 if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1119 drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1120 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1121 drm_rect_width(src) >> 16,
1122 drm_rect_height(src) >> 16,
1123 vop_data->max_input.width,
1124 vop_data->max_input.height);
1129 * Src.x1 can be odd when do clip, but yuv plane start point
1130 * need align with 2 pixel.
1132 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1133 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1137 offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1138 if (state->rotation & BIT(DRM_REFLECT_Y) ||
1139 (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1140 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1142 offset += (src->y1 >> 16) * fb->pitches[0];
1144 dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1145 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1146 if (is_yuv_support(fb->pixel_format)) {
1147 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1148 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1149 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1151 offset = (src->x1 >> 16) * bpp / hsub / 8;
1152 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1154 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1155 dma_addr += offset + fb->offsets[1];
1156 vop_plane_state->uv_mst = dma_addr;
1159 vop_plane_state->enable = true;
1164 vop_plane_state->enable = false;
1168 static void vop_plane_atomic_disable(struct drm_plane *plane,
1169 struct drm_plane_state *old_state)
1171 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1172 struct vop_win *win = to_vop_win(plane);
1173 struct vop *vop = to_vop(old_state->crtc);
1175 if (!old_state->crtc)
1178 spin_lock(&vop->reg_lock);
1181 * FIXUP: some of the vop scale would be abnormal after windows power
1182 * on/off so deinit scale to scale_none mode.
1184 if (win->phy->scl && win->phy->scl->ext) {
1185 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1186 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1187 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1188 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1190 VOP_WIN_SET(vop, win, enable, 0);
1192 spin_unlock(&vop->reg_lock);
1194 vop_plane_state->enable = false;
1197 static void vop_plane_atomic_update(struct drm_plane *plane,
1198 struct drm_plane_state *old_state)
1200 struct drm_plane_state *state = plane->state;
1201 struct drm_crtc *crtc = state->crtc;
1202 struct vop_win *win = to_vop_win(plane);
1203 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1204 struct rockchip_crtc_state *s;
1206 struct drm_framebuffer *fb = state->fb;
1207 unsigned int actual_w, actual_h;
1208 unsigned int dsp_stx, dsp_sty;
1209 uint32_t act_info, dsp_info, dsp_st;
1210 struct drm_rect *src = &vop_plane_state->src;
1211 struct drm_rect *dest = &vop_plane_state->dest;
1212 const uint32_t *y2r_table = vop_plane_state->y2r_table;
1213 const uint32_t *r2r_table = vop_plane_state->r2r_table;
1214 const uint32_t *r2y_table = vop_plane_state->r2y_table;
1215 int ymirror, xmirror;
1220 * can't update plane when vop is disabled.
1225 if (!vop_plane_state->enable) {
1226 vop_plane_atomic_disable(plane, old_state);
1230 actual_w = drm_rect_width(src) >> 16;
1231 actual_h = drm_rect_height(src) >> 16;
1232 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1234 dsp_info = (drm_rect_height(dest) - 1) << 16;
1235 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1237 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1238 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1239 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1241 ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1242 (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1243 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1245 vop = to_vop(state->crtc);
1246 s = to_rockchip_crtc_state(crtc->state);
1248 spin_lock(&vop->reg_lock);
1250 VOP_WIN_SET(vop, win, xmirror, xmirror);
1251 VOP_WIN_SET(vop, win, ymirror, ymirror);
1252 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1253 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1254 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1255 if (is_yuv_support(fb->pixel_format)) {
1256 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1257 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1259 VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1261 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1262 drm_rect_width(dest), drm_rect_height(dest),
1265 VOP_WIN_SET(vop, win, act_info, act_info);
1266 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1267 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1269 rb_swap = has_rb_swapped(fb->pixel_format);
1270 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1272 if (is_alpha_support(fb->pixel_format) &&
1273 (s->dsp_layer_sel & 0x3) != win->win_id) {
1274 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1275 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1276 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1277 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1278 SRC_BLEND_M0(ALPHA_PER_PIX) |
1279 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1280 SRC_FACTOR_M0(ALPHA_ONE);
1281 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1282 VOP_WIN_SET(vop, win, alpha_mode, 1);
1283 VOP_WIN_SET(vop, win, alpha_en, 1);
1285 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1286 VOP_WIN_SET(vop, win, alpha_en, 0);
1290 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1291 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1292 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1293 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1294 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1295 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1297 VOP_WIN_SET(vop, win, enable, 1);
1298 spin_unlock(&vop->reg_lock);
1299 vop->is_iommu_needed = true;
1302 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1303 .prepare_fb = vop_plane_prepare_fb,
1304 .cleanup_fb = vop_plane_cleanup_fb,
1305 .atomic_check = vop_plane_atomic_check,
1306 .atomic_update = vop_plane_atomic_update,
1307 .atomic_disable = vop_plane_atomic_disable,
1310 void vop_atomic_plane_reset(struct drm_plane *plane)
1312 struct vop_win *win = to_vop_win(plane);
1313 struct vop_plane_state *vop_plane_state =
1314 to_vop_plane_state(plane->state);
1316 if (plane->state && plane->state->fb)
1317 drm_framebuffer_unreference(plane->state->fb);
1319 kfree(vop_plane_state);
1320 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1321 if (!vop_plane_state)
1324 vop_plane_state->zpos = win->win_id;
1325 plane->state = &vop_plane_state->base;
1326 plane->state->plane = plane;
1329 struct drm_plane_state *
1330 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1332 struct vop_plane_state *old_vop_plane_state;
1333 struct vop_plane_state *vop_plane_state;
1335 if (WARN_ON(!plane->state))
1338 old_vop_plane_state = to_vop_plane_state(plane->state);
1339 vop_plane_state = kmemdup(old_vop_plane_state,
1340 sizeof(*vop_plane_state), GFP_KERNEL);
1341 if (!vop_plane_state)
1344 __drm_atomic_helper_plane_duplicate_state(plane,
1345 &vop_plane_state->base);
1347 return &vop_plane_state->base;
1350 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1351 struct drm_plane_state *state)
1353 struct vop_plane_state *vop_state = to_vop_plane_state(state);
1355 __drm_atomic_helper_plane_destroy_state(plane, state);
1360 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1361 struct drm_plane_state *state,
1362 struct drm_property *property,
1365 struct rockchip_drm_private *private = plane->dev->dev_private;
1366 struct vop_win *win = to_vop_win(plane);
1367 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1369 if (property == win->vop->plane_zpos_prop) {
1370 plane_state->zpos = val;
1374 if (property == win->rotation_prop) {
1375 state->rotation = val;
1379 if (property == private->logo_ymirror_prop) {
1380 WARN_ON(!rockchip_fb_is_logo(state->fb));
1381 plane_state->logo_ymirror = val;
1385 DRM_ERROR("failed to set vop plane property\n");
1389 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1390 const struct drm_plane_state *state,
1391 struct drm_property *property,
1394 struct vop_win *win = to_vop_win(plane);
1395 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1397 if (property == win->vop->plane_zpos_prop) {
1398 *val = plane_state->zpos;
1402 if (property == win->rotation_prop) {
1403 *val = state->rotation;
1407 DRM_ERROR("failed to get vop plane property\n");
1411 static const struct drm_plane_funcs vop_plane_funcs = {
1412 .update_plane = drm_atomic_helper_update_plane,
1413 .disable_plane = drm_atomic_helper_disable_plane,
1414 .destroy = vop_plane_destroy,
1415 .reset = vop_atomic_plane_reset,
1416 .set_property = drm_atomic_helper_plane_set_property,
1417 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1418 .atomic_destroy_state = vop_atomic_plane_destroy_state,
1419 .atomic_set_property = vop_atomic_plane_set_property,
1420 .atomic_get_property = vop_atomic_plane_get_property,
1423 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1425 struct vop *vop = to_vop(crtc);
1426 unsigned long flags;
1428 if (!vop->is_enabled)
1431 spin_lock_irqsave(&vop->irq_lock, flags);
1433 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1434 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1436 spin_unlock_irqrestore(&vop->irq_lock, flags);
1441 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1443 struct vop *vop = to_vop(crtc);
1444 unsigned long flags;
1446 if (!vop->is_enabled)
1449 spin_lock_irqsave(&vop->irq_lock, flags);
1451 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1453 spin_unlock_irqrestore(&vop->irq_lock, flags);
1456 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1457 struct drm_file *file_priv)
1459 struct drm_device *drm = crtc->dev;
1460 struct vop *vop = to_vop(crtc);
1461 struct drm_pending_vblank_event *e;
1462 unsigned long flags;
1464 spin_lock_irqsave(&drm->event_lock, flags);
1466 if (e && e->base.file_priv == file_priv) {
1469 e->base.destroy(&e->base);
1470 file_priv->event_space += sizeof(e->event);
1472 spin_unlock_irqrestore(&drm->event_lock, flags);
1475 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1477 struct rockchip_drm_private *private = crtc->dev->dev_private;
1478 struct vop *vop = to_vop(crtc);
1480 if (on == vop->loader_protect)
1484 if (vop->dclk_source) {
1487 parent = clk_get_parent(vop->dclk_source);
1489 if (clk_is_match(private->default_pll.pll, parent))
1490 vop->pll = &private->default_pll;
1491 else if (clk_is_match(private->hdmi_pll.pll, parent))
1492 vop->pll = &private->hdmi_pll;
1494 vop->pll->use_count++;
1498 vop_power_enable(crtc);
1499 enable_irq(vop->irq);
1500 drm_crtc_vblank_on(crtc);
1501 vop->loader_protect = true;
1503 vop_crtc_disable(crtc);
1505 if (vop->dclk_source && vop->pll) {
1506 vop->pll->use_count--;
1509 vop->loader_protect = false;
1515 #define DEBUG_PRINT(args...) \
1518 seq_printf(s, args); \
1523 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1525 struct vop_win *win = to_vop_win(plane);
1526 struct drm_plane_state *state = plane->state;
1527 struct vop_plane_state *pstate = to_vop_plane_state(state);
1528 struct drm_rect *src, *dest;
1529 struct drm_framebuffer *fb = state->fb;
1532 DEBUG_PRINT(" win%d-%d: %s\n", win->win_id, win->area_id,
1533 pstate->enable ? "ACTIVE" : "DISABLED");
1538 dest = &pstate->dest;
1540 DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1541 fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1542 DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1543 DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1544 src->y1 >> 16, drm_rect_width(src) >> 16,
1545 drm_rect_height(src) >> 16);
1546 DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1547 drm_rect_width(dest), drm_rect_height(dest));
1549 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1550 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1551 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1552 i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1558 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1560 struct vop *vop = to_vop(crtc);
1561 struct drm_crtc_state *crtc_state = crtc->state;
1562 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1563 struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1564 bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1565 struct drm_plane *plane;
1568 DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1569 crtc_state->active ? "ACTIVE" : "DISABLED");
1571 if (!crtc_state->active)
1574 DEBUG_PRINT(" Connector: %s\n",
1575 drm_get_connector_name(state->output_type));
1576 DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1577 state->bus_format, state->output_mode);
1578 DEBUG_PRINT(" Display mode: %dx%d%s%d\n",
1579 mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1580 drm_mode_vrefresh(mode));
1581 DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1582 mode->clock, mode->crtc_clock, mode->type, mode->flags);
1583 DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1584 mode->hsync_end, mode->htotal);
1585 DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1586 mode->vsync_end, mode->vtotal);
1588 for (i = 0; i < vop->num_wins; i++) {
1589 plane = &vop->win[i].base;
1590 vop_plane_info_dump(s, plane);
1596 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1598 struct vop *vop = to_vop(crtc);
1599 struct drm_crtc_state *crtc_state = crtc->state;
1600 int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1603 if (!crtc_state->active)
1606 for (i = 0; i < dump_len; i += 4) {
1608 DEBUG_PRINT("\n0x%08x: ", i);
1609 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1615 static enum drm_mode_status
1616 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1619 struct vop *vop = to_vop(crtc);
1620 const struct vop_data *vop_data = vop->data;
1621 int request_clock = mode->clock;
1624 if (mode->hdisplay > vop_data->max_output.width)
1625 return MODE_BAD_HVALUE;
1627 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
1628 VOP_MAJOR(vop->data->version) == 3 &&
1629 VOP_MINOR(vop->data->version) <= 2)
1632 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1634 clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1637 * Hdmi or DisplayPort request a Accurate clock.
1639 if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1640 output_type == DRM_MODE_CONNECTOR_DisplayPort)
1641 if (clock != request_clock)
1642 return MODE_CLOCK_RANGE;
1647 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1648 .loader_protect = vop_crtc_loader_protect,
1649 .enable_vblank = vop_crtc_enable_vblank,
1650 .disable_vblank = vop_crtc_disable_vblank,
1651 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1652 .debugfs_dump = vop_crtc_debugfs_dump,
1653 .regs_dump = vop_crtc_regs_dump,
1654 .mode_valid = vop_crtc_mode_valid,
1657 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1658 const struct drm_display_mode *mode,
1659 struct drm_display_mode *adj_mode)
1661 struct vop *vop = to_vop(crtc);
1662 const struct vop_data *vop_data = vop->data;
1664 if (mode->hdisplay > vop_data->max_output.width)
1667 drm_mode_set_crtcinfo(adj_mode,
1668 CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1670 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1671 adj_mode->crtc_clock *= 2;
1673 adj_mode->crtc_clock =
1674 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1679 static void vop_crtc_enable(struct drm_crtc *crtc)
1681 struct vop *vop = to_vop(crtc);
1682 const struct vop_data *vop_data = vop->data;
1683 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1684 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1685 u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1686 u16 hdisplay = adjusted_mode->crtc_hdisplay;
1687 u16 htotal = adjusted_mode->crtc_htotal;
1688 u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1689 u16 hact_end = hact_st + hdisplay;
1690 u16 vdisplay = adjusted_mode->crtc_vdisplay;
1691 u16 vtotal = adjusted_mode->crtc_vtotal;
1692 u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1693 u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1694 u16 vact_end = vact_st + vdisplay;
1697 mutex_lock(&vop->vop_lock);
1700 VOP_CTRL_SET(vop, dclk_pol, 1);
1701 val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1702 0 : BIT(HSYNC_POSITIVE);
1703 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1704 0 : BIT(VSYNC_POSITIVE);
1705 VOP_CTRL_SET(vop, pin_pol, val);
1707 if (vop->dclk_source && vop->pll && vop->pll->pll) {
1708 if (clk_set_parent(vop->dclk_source, vop->pll->pll))
1709 DRM_DEV_ERROR(vop->dev,
1710 "failed to set dclk's parents\n");
1713 switch (s->output_type) {
1714 case DRM_MODE_CONNECTOR_LVDS:
1715 VOP_CTRL_SET(vop, rgb_en, 1);
1716 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1717 VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
1718 VOP_CTRL_SET(vop, lvds_en, 1);
1719 VOP_CTRL_SET(vop, lvds_pin_pol, val);
1720 VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
1722 case DRM_MODE_CONNECTOR_eDP:
1723 VOP_CTRL_SET(vop, edp_en, 1);
1724 VOP_CTRL_SET(vop, edp_pin_pol, val);
1725 VOP_CTRL_SET(vop, edp_dclk_pol, 1);
1727 case DRM_MODE_CONNECTOR_HDMIA:
1728 VOP_CTRL_SET(vop, hdmi_en, 1);
1729 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1730 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
1732 case DRM_MODE_CONNECTOR_DSI:
1733 VOP_CTRL_SET(vop, mipi_en, 1);
1734 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1735 VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
1736 if (s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)
1737 VOP_CTRL_SET(vop, mipi_dual_channel_en, 1);
1739 VOP_CTRL_SET(vop, mipi_dual_channel_en, 0);
1741 case DRM_MODE_CONNECTOR_DisplayPort:
1742 VOP_CTRL_SET(vop, dp_dclk_pol, 0);
1743 VOP_CTRL_SET(vop, dp_pin_pol, val);
1744 VOP_CTRL_SET(vop, dp_en, 1);
1746 case DRM_MODE_CONNECTOR_TV:
1747 if (vdisplay == CVBS_PAL_VDISPLAY)
1748 VOP_CTRL_SET(vop, tve_sw_mode, 1);
1750 VOP_CTRL_SET(vop, tve_sw_mode, 0);
1752 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
1753 VOP_CTRL_SET(vop, tve_dclk_en, 1);
1754 /* use the same pol reg with hdmi */
1755 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1756 VOP_CTRL_SET(vop, sw_genlock, 1);
1757 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
1758 VOP_CTRL_SET(vop, dither_up, 1);
1761 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1764 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1765 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1766 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1768 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1769 switch (s->bus_format) {
1770 case MEDIA_BUS_FMT_RGB565_1X16:
1771 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1773 case MEDIA_BUS_FMT_RGB666_1X18:
1774 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1775 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1777 case MEDIA_BUS_FMT_YUV8_1X24:
1778 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1779 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1781 case MEDIA_BUS_FMT_YUV10_1X30:
1782 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1783 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1785 case MEDIA_BUS_FMT_RGB888_1X24:
1787 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1791 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1792 val |= PRE_DITHER_DOWN_EN(0);
1794 val |= PRE_DITHER_DOWN_EN(1);
1795 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1796 VOP_CTRL_SET(vop, dither_down, val);
1797 VOP_CTRL_SET(vop, dclk_ddr,
1798 s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1799 VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1800 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1803 * Background color is 10bit depth if vop version >= 3.5
1805 if (!is_yuv_output(s->bus_format))
1807 else if (VOP_MAJOR(vop->data->version) == 3 &&
1808 VOP_MINOR(vop->data->version) >= 5)
1812 VOP_CTRL_SET(vop, dsp_background, val);
1813 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1814 val = hact_st << 16;
1816 VOP_CTRL_SET(vop, hact_st_end, val);
1817 VOP_CTRL_SET(vop, hpost_st_end, val);
1819 val = vact_st << 16;
1821 VOP_CTRL_SET(vop, vact_st_end, val);
1822 VOP_CTRL_SET(vop, vpost_st_end, val);
1824 VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1825 VOP_INTR_SET(vop, line_flag_num[1],
1826 vact_end - us_to_vertical_line(adjusted_mode, 1000));
1827 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1828 u16 vact_st_f1 = vtotal + vact_st + 1;
1829 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1831 val = vact_st_f1 << 16 | vact_end_f1;
1832 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1833 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1835 val = vtotal << 16 | (vtotal + vsync_len);
1836 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1837 VOP_CTRL_SET(vop, dsp_interlace, 1);
1838 VOP_CTRL_SET(vop, p2i_en, 1);
1839 vtotal += vtotal + 1;
1841 VOP_CTRL_SET(vop, dsp_interlace, 0);
1842 VOP_CTRL_SET(vop, p2i_en, 0);
1844 VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1846 VOP_CTRL_SET(vop, core_dclk_div,
1847 !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1849 VOP_CTRL_SET(vop, cabc_total_num, hdisplay * vdisplay);
1850 VOP_CTRL_SET(vop, cabc_config_mode, STAGE_BY_STAGE);
1851 VOP_CTRL_SET(vop, cabc_stage_up_mode, MUL_MODE);
1852 VOP_CTRL_SET(vop, cabc_scale_cfg_value, 1);
1853 VOP_CTRL_SET(vop, cabc_scale_cfg_enable, 0);
1854 VOP_CTRL_SET(vop, cabc_global_dn_limit_en, 1);
1856 clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1860 * enable vop, all the register would take effect when vop exit standby
1862 VOP_CTRL_SET(vop, standby, 0);
1864 enable_irq(vop->irq);
1865 drm_crtc_vblank_on(crtc);
1866 mutex_unlock(&vop->vop_lock);
1869 static int vop_zpos_cmp(const void *a, const void *b)
1871 struct vop_zpos *pa = (struct vop_zpos *)a;
1872 struct vop_zpos *pb = (struct vop_zpos *)b;
1874 return pa->zpos - pb->zpos;
1877 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1878 struct drm_crtc_state *crtc_state)
1880 struct vop *vop = to_vop(crtc);
1881 const struct vop_data *vop_data = vop->data;
1882 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1883 struct drm_atomic_state *state = crtc_state->state;
1884 struct drm_plane *plane;
1885 struct drm_plane_state *pstate;
1886 struct vop_plane_state *plane_state;
1887 struct vop_win *win;
1893 for_each_plane_in_state(state, plane, pstate, i) {
1894 struct drm_framebuffer *fb = pstate->fb;
1895 struct drm_rect *src;
1897 win = to_vop_win(plane);
1898 plane_state = to_vop_plane_state(pstate);
1900 if (pstate->crtc != crtc || !fb)
1903 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1906 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1907 DRM_ERROR("not support afbdc\n");
1911 switch (plane_state->format) {
1912 case VOP_FMT_ARGB8888:
1913 afbdc_format = AFBDC_FMT_U8U8U8U8;
1915 case VOP_FMT_RGB888:
1916 afbdc_format = AFBDC_FMT_U8U8U8;
1918 case VOP_FMT_RGB565:
1919 afbdc_format = AFBDC_FMT_RGB565;
1926 DRM_ERROR("vop only support one afbc layer\n");
1930 src = &plane_state->src;
1931 if (src->x1 || src->y1 || fb->offsets[0]) {
1932 DRM_ERROR("win[%d] afbdc not support offset display\n",
1934 DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1935 src->x1, src->y1, fb->offsets[0]);
1938 s->afbdc_win_format = afbdc_format;
1939 s->afbdc_win_width = pstate->fb->width - 1;
1940 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1941 s->afbdc_win_id = win->win_id;
1942 s->afbdc_win_ptr = plane_state->yrgb_mst;
1949 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1950 struct drm_crtc_state *crtc_state)
1952 struct rockchip_drm_private *private = crtc->dev->dev_private;
1953 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1954 struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1955 struct vop *vop = to_vop(crtc);
1956 struct rockchip_dclk_pll *old_pll = vop->pll;
1958 if (!vop->dclk_source)
1961 if (crtc_state->active) {
1962 WARN_ON(vop->pll && !vop->pll->use_count);
1963 if (!vop->pll || vop->pll->use_count > 1 ||
1964 s->output_type != old_s->output_type) {
1966 vop->pll->use_count--;
1968 if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1969 !private->default_pll.use_count)
1970 vop->pll = &private->default_pll;
1972 vop->pll = &private->hdmi_pll;
1974 vop->pll->use_count++;
1976 } else if (vop->pll) {
1977 vop->pll->use_count--;
1980 if (vop->pll != old_pll)
1981 crtc_state->mode_changed = true;
1984 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1985 struct drm_crtc_state *crtc_state)
1987 struct drm_atomic_state *state = crtc_state->state;
1988 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1989 struct vop *vop = to_vop(crtc);
1990 const struct vop_data *vop_data = vop->data;
1991 struct drm_plane *plane;
1992 struct drm_plane_state *pstate;
1993 struct vop_plane_state *plane_state;
1994 struct vop_zpos *pzpos;
1995 int dsp_layer_sel = 0;
1996 int i, j, cnt = 0, ret = 0;
1998 ret = vop_afbdc_atomic_check(crtc, crtc_state);
2002 ret = vop_csc_atomic_check(crtc, crtc_state);
2006 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
2010 for (i = 0; i < vop_data->win_size; i++) {
2011 const struct vop_win_data *win_data = &vop_data->win[i];
2012 struct vop_win *win;
2017 for (j = 0; j < vop->num_wins; j++) {
2020 if (win->win_id == i && !win->area_id)
2023 if (WARN_ON(j >= vop->num_wins)) {
2025 goto err_free_pzpos;
2029 pstate = state->plane_states[drm_plane_index(plane)];
2031 * plane might not have changed, in which case take
2035 pstate = plane->state;
2036 plane_state = to_vop_plane_state(pstate);
2037 pzpos[cnt].zpos = plane_state->zpos;
2038 pzpos[cnt++].win_id = win->win_id;
2041 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
2043 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
2044 const struct vop_win_data *win_data = &vop_data->win[i];
2047 if (win_data->phy) {
2048 struct vop_zpos *zpos = &pzpos[cnt++];
2050 dsp_layer_sel |= zpos->win_id << shift;
2052 dsp_layer_sel |= i << shift;
2056 s->dsp_layer_sel = dsp_layer_sel;
2058 vop_dclk_source_generate(crtc, crtc_state);
2065 static void vop_post_config(struct drm_crtc *crtc)
2067 struct vop *vop = to_vop(crtc);
2068 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2069 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2070 u16 vtotal = mode->crtc_vtotal;
2071 u16 hdisplay = mode->crtc_hdisplay;
2072 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2073 u16 vdisplay = mode->crtc_vdisplay;
2074 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2075 u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
2076 u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
2077 u16 hact_end, vact_end;
2080 hact_st += hdisplay * (100 - s->left_margin) / 200;
2081 hact_end = hact_st + hsize;
2082 val = hact_st << 16;
2084 VOP_CTRL_SET(vop, hpost_st_end, val);
2085 vact_st += vdisplay * (100 - s->top_margin) / 200;
2086 vact_end = vact_st + vsize;
2087 val = vact_st << 16;
2089 VOP_CTRL_SET(vop, vpost_st_end, val);
2090 val = scl_cal_scale2(vdisplay, vsize) << 16;
2091 val |= scl_cal_scale2(hdisplay, hsize);
2092 VOP_CTRL_SET(vop, post_scl_factor, val);
2094 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0)
2095 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1)
2096 VOP_CTRL_SET(vop, post_scl_ctrl,
2097 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) ||
2098 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
2099 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2100 u16 vact_st_f1 = vtotal + vact_st + 1;
2101 u16 vact_end_f1 = vact_st_f1 + vsize;
2103 val = vact_st_f1 << 16 | vact_end_f1;
2104 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2108 static void vop_update_cabc_lut(struct drm_crtc *crtc,
2109 struct drm_crtc_state *old_crtc_state)
2111 struct rockchip_crtc_state *s =
2112 to_rockchip_crtc_state(crtc->state);
2113 struct rockchip_crtc_state *old_s =
2114 to_rockchip_crtc_state(old_crtc_state);
2115 struct drm_property_blob *cabc_lut = s->cabc_lut;
2116 struct drm_property_blob *old_cabc_lut = old_s->cabc_lut;
2117 struct vop *vop = to_vop(crtc);
2120 u32 lut_len = vop->cabc_lut_len;
2123 if (!cabc_lut && old_cabc_lut) {
2124 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2130 if (old_cabc_lut && old_cabc_lut->base.id == cabc_lut->base.id)
2133 lut = (u32 *)cabc_lut->data;
2134 lut_size = cabc_lut->length / sizeof(u32);
2135 if (WARN(lut_size != lut_len, "Unexpect cabc lut size not match\n"))
2138 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
2139 if (CTRL_GET(cabc_lut_en)) {
2140 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2142 readx_poll_timeout(CTRL_GET, cabc_lut_en, dle, !dle, 5, 33333);
2145 for (i = 0; i < lut_len; i++)
2146 vop_write_cabc_lut(vop, (i << 2), lut[i]);
2148 VOP_CTRL_SET(vop, cabc_lut_en, 1);
2151 static void vop_update_cabc(struct drm_crtc *crtc,
2152 struct drm_crtc_state *old_crtc_state)
2154 struct rockchip_crtc_state *s =
2155 to_rockchip_crtc_state(crtc->state);
2156 struct vop *vop = to_vop(crtc);
2157 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2158 int pixel_total = mode->hdisplay * mode->vdisplay;
2160 if (!vop->cabc_lut_regs)
2163 vop_update_cabc_lut(crtc, old_crtc_state);
2165 if (s->cabc_mode != ROCKCHIP_DRM_CABC_MODE_DISABLE) {
2166 VOP_CTRL_SET(vop, cabc_en, 1);
2167 VOP_CTRL_SET(vop, cabc_handle_en, 1);
2168 VOP_CTRL_SET(vop, cabc_stage_up, s->cabc_stage_up);
2169 VOP_CTRL_SET(vop, cabc_stage_down, s->cabc_stage_down);
2170 VOP_CTRL_SET(vop, cabc_global_dn, s->cabc_global_dn);
2171 VOP_CTRL_SET(vop, cabc_calc_pixel_num,
2172 s->cabc_calc_pixel_num * pixel_total / 1000);
2175 * There are some hardware issues on cabc disabling:
2176 * 1: if cabc auto gating enable, cabc disabling will cause
2178 * 2: cabc disabling always would make timing several
2179 * pixel cycle abnormal, cause some panel abnormal.
2181 * So just keep cabc enable, and make it no work with max
2182 * cabc_calc_pixel_num, it only has little power consume.
2184 VOP_CTRL_SET(vop, cabc_calc_pixel_num, pixel_total);
2188 static void vop_cfg_update(struct drm_crtc *crtc,
2189 struct drm_crtc_state *old_crtc_state)
2191 struct rockchip_crtc_state *s =
2192 to_rockchip_crtc_state(crtc->state);
2193 struct vop *vop = to_vop(crtc);
2195 spin_lock(&vop->reg_lock);
2200 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2201 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2202 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2203 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2204 pic_size = (s->afbdc_win_width & 0xffff);
2205 pic_size |= s->afbdc_win_height << 16;
2206 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2209 VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2210 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2211 vop_post_config(crtc);
2213 spin_unlock(&vop->reg_lock);
2216 static bool vop_fs_irq_is_pending(struct vop *vop)
2218 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
2221 static void vop_wait_for_irq_handler(struct vop *vop)
2227 * Spin until frame start interrupt status bit goes low, which means
2228 * that interrupt handler was invoked and cleared it. The timeout of
2229 * 10 msecs is really too long, but it is just a safety measure if
2230 * something goes really wrong. The wait will only happen in the very
2231 * unlikely case of a vblank happening exactly at the same time and
2232 * shouldn't exceed microseconds range.
2234 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
2235 !pending, 0, 10 * 1000);
2237 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
2239 synchronize_irq(vop->irq);
2242 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2243 struct drm_crtc_state *old_crtc_state)
2245 struct drm_atomic_state *old_state = old_crtc_state->state;
2246 struct drm_plane_state *old_plane_state;
2247 struct vop *vop = to_vop(crtc);
2248 struct drm_plane *plane;
2251 vop_cfg_update(crtc, old_crtc_state);
2253 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2254 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2257 if (need_wait_vblank) {
2260 disable_irq(vop->irq);
2261 drm_crtc_vblank_get(crtc);
2262 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2264 ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2265 vop, active, active,
2268 dev_err(vop->dev, "wait fs irq timeout\n");
2270 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2273 ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2274 vop, active, active,
2277 dev_err(vop->dev, "wait line flag timeout\n");
2279 enable_irq(vop->irq);
2281 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2283 dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2286 if (need_wait_vblank) {
2287 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2288 drm_crtc_vblank_put(crtc);
2291 vop->is_iommu_enabled = true;
2294 vop_update_cabc(crtc, old_crtc_state);
2299 * There is a (rather unlikely) possiblity that a vblank interrupt
2300 * fired before we set the cfg_done bit. To avoid spuriously
2301 * signalling flip completion we need to wait for it to finish.
2303 vop_wait_for_irq_handler(vop);
2305 spin_lock_irq(&crtc->dev->event_lock);
2306 if (crtc->state->event) {
2307 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2308 WARN_ON(vop->event);
2310 vop->event = crtc->state->event;
2311 crtc->state->event = NULL;
2313 spin_unlock_irq(&crtc->dev->event_lock);
2315 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
2316 if (!old_plane_state->fb)
2319 if (old_plane_state->fb == plane->state->fb)
2322 drm_framebuffer_reference(old_plane_state->fb);
2323 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
2324 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
2325 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2329 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2330 struct drm_crtc_state *old_crtc_state)
2334 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2335 .load_lut = vop_crtc_load_lut,
2336 .enable = vop_crtc_enable,
2337 .disable = vop_crtc_disable,
2338 .mode_fixup = vop_crtc_mode_fixup,
2339 .atomic_check = vop_crtc_atomic_check,
2340 .atomic_flush = vop_crtc_atomic_flush,
2341 .atomic_begin = vop_crtc_atomic_begin,
2344 static void vop_crtc_destroy(struct drm_crtc *crtc)
2346 drm_crtc_cleanup(crtc);
2349 static void vop_crtc_reset(struct drm_crtc *crtc)
2351 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2354 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2358 s = kzalloc(sizeof(*s), GFP_KERNEL);
2361 crtc->state = &s->base;
2362 crtc->state->crtc = crtc;
2364 s->left_margin = 100;
2365 s->right_margin = 100;
2366 s->top_margin = 100;
2367 s->bottom_margin = 100;
2370 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2372 struct rockchip_crtc_state *rockchip_state, *old_state;
2374 old_state = to_rockchip_crtc_state(crtc->state);
2375 rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2376 if (!rockchip_state)
2379 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2380 return &rockchip_state->base;
2383 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2384 struct drm_crtc_state *state)
2386 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2388 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2392 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2393 const struct drm_crtc_state *state,
2394 struct drm_property *property,
2397 struct drm_device *drm_dev = crtc->dev;
2398 struct rockchip_drm_private *private = drm_dev->dev_private;
2399 struct drm_mode_config *mode_config = &drm_dev->mode_config;
2400 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2402 if (property == mode_config->tv_left_margin_property) {
2403 *val = s->left_margin;
2407 if (property == mode_config->tv_right_margin_property) {
2408 *val = s->right_margin;
2412 if (property == mode_config->tv_top_margin_property) {
2413 *val = s->top_margin;
2417 if (property == mode_config->tv_bottom_margin_property) {
2418 *val = s->bottom_margin;
2422 if (property == private->cabc_mode_property) {
2423 *val = s->cabc_mode;
2427 if (property == private->cabc_stage_up_property) {
2428 *val = s->cabc_stage_up;
2432 if (property == private->cabc_stage_down_property) {
2433 *val = s->cabc_stage_down;
2437 if (property == private->cabc_global_dn_property) {
2438 *val = s->cabc_global_dn;
2442 if (property == private->cabc_calc_pixel_num_property) {
2443 *val = s->cabc_calc_pixel_num;
2447 if (property == private->cabc_lut_property) {
2448 *val = s->cabc_lut ? s->cabc_lut->base.id : 0;
2452 DRM_ERROR("failed to get vop crtc property\n");
2456 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2457 struct drm_crtc_state *state,
2458 struct drm_property *property,
2461 struct drm_device *drm_dev = crtc->dev;
2462 struct rockchip_drm_private *private = drm_dev->dev_private;
2463 struct drm_mode_config *mode_config = &drm_dev->mode_config;
2464 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2465 struct vop *vop = to_vop(crtc);
2467 if (property == mode_config->tv_left_margin_property) {
2468 s->left_margin = val;
2472 if (property == mode_config->tv_right_margin_property) {
2473 s->right_margin = val;
2477 if (property == mode_config->tv_top_margin_property) {
2478 s->top_margin = val;
2482 if (property == mode_config->tv_bottom_margin_property) {
2483 s->bottom_margin = val;
2487 if (property == private->cabc_mode_property) {
2490 * Pre-define lowpower and normal mode to make cabc
2493 if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_NORMAL) {
2494 s->cabc_stage_up = 257;
2495 s->cabc_stage_down = 255;
2496 s->cabc_global_dn = 192;
2497 s->cabc_calc_pixel_num = 995;
2498 } else if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_LOWPOWER) {
2499 s->cabc_stage_up = 260;
2500 s->cabc_stage_down = 252;
2501 s->cabc_global_dn = 180;
2502 s->cabc_calc_pixel_num = 992;
2507 if (property == private->cabc_stage_up_property) {
2508 s->cabc_stage_up = val;
2512 if (property == private->cabc_stage_down_property) {
2513 s->cabc_stage_down = val;
2517 if (property == private->cabc_calc_pixel_num_property) {
2518 s->cabc_calc_pixel_num = val;
2522 if (property == private->cabc_global_dn_property) {
2523 s->cabc_global_dn = val;
2527 if (property == private->cabc_lut_property) {
2529 ssize_t size = vop->cabc_lut_len * 4;
2531 return drm_atomic_replace_property_blob_from_id(crtc,
2538 DRM_ERROR("failed to set vop crtc property\n");
2542 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2543 u16 *blue, uint32_t start, uint32_t size)
2545 struct vop *vop = to_vop(crtc);
2546 int end = min_t(u32, start + size, vop->lut_len);
2552 for (i = start; i < end; i++)
2553 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2556 vop_crtc_load_lut(crtc);
2559 static const struct drm_crtc_funcs vop_crtc_funcs = {
2560 .gamma_set = vop_crtc_gamma_set,
2561 .set_config = drm_atomic_helper_set_config,
2562 .page_flip = drm_atomic_helper_page_flip,
2563 .destroy = vop_crtc_destroy,
2564 .reset = vop_crtc_reset,
2565 .set_property = drm_atomic_helper_crtc_set_property,
2566 .atomic_get_property = vop_crtc_atomic_get_property,
2567 .atomic_set_property = vop_crtc_atomic_set_property,
2568 .atomic_duplicate_state = vop_crtc_duplicate_state,
2569 .atomic_destroy_state = vop_crtc_destroy_state,
2572 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
2574 struct vop *vop = container_of(work, struct vop, fb_unref_work);
2575 struct drm_framebuffer *fb = val;
2577 drm_crtc_vblank_put(&vop->crtc);
2578 drm_framebuffer_unreference(fb);
2581 static void vop_handle_vblank(struct vop *vop)
2583 struct drm_device *drm = vop->drm_dev;
2584 struct drm_crtc *crtc = &vop->crtc;
2585 unsigned long flags;
2588 spin_lock_irqsave(&drm->event_lock, flags);
2590 drm_crtc_send_vblank_event(crtc, vop->event);
2591 drm_crtc_vblank_put(crtc);
2594 spin_unlock_irqrestore(&drm->event_lock, flags);
2597 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
2598 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2601 static irqreturn_t vop_isr(int irq, void *data)
2603 struct vop *vop = data;
2604 struct drm_crtc *crtc = &vop->crtc;
2605 uint32_t active_irqs;
2606 unsigned long flags;
2610 * interrupt register has interrupt status, enable and clear bits, we
2611 * must hold irq_lock to avoid a race with enable/disable_vblank().
2613 spin_lock_irqsave(&vop->irq_lock, flags);
2615 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2616 /* Clear all active interrupt sources */
2618 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2620 spin_unlock_irqrestore(&vop->irq_lock, flags);
2622 /* This is expected for vop iommu irqs, since the irq is shared */
2626 if (active_irqs & DSP_HOLD_VALID_INTR) {
2627 complete(&vop->dsp_hold_completion);
2628 active_irqs &= ~DSP_HOLD_VALID_INTR;
2632 if (active_irqs & LINE_FLAG_INTR) {
2633 complete(&vop->line_flag_completion);
2634 active_irqs &= ~LINE_FLAG_INTR;
2638 if (active_irqs & FS_INTR) {
2639 drm_crtc_handle_vblank(crtc);
2640 vop_handle_vblank(vop);
2641 active_irqs &= ~FS_INTR;
2645 #define ERROR_HANDLER(x) \
2647 if (active_irqs & x##_INTR) {\
2648 DRM_DEV_ERROR_RATELIMITED(vop->dev, #x " irq err\n"); \
2649 active_irqs &= ~x##_INTR; \
2650 ret = IRQ_HANDLED; \
2654 ERROR_HANDLER(BUS_ERROR);
2655 ERROR_HANDLER(WIN0_EMPTY);
2656 ERROR_HANDLER(WIN1_EMPTY);
2657 ERROR_HANDLER(WIN2_EMPTY);
2658 ERROR_HANDLER(WIN3_EMPTY);
2659 ERROR_HANDLER(HWC_EMPTY);
2660 ERROR_HANDLER(POST_BUF_EMPTY);
2662 /* Unhandled irqs are spurious. */
2664 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2669 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2670 unsigned long possible_crtcs)
2672 struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2673 struct drm_plane *share = NULL;
2674 unsigned int rotations = 0;
2675 struct drm_property *prop;
2676 uint64_t feature = 0;
2680 share = &win->parent->base;
2682 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2683 possible_crtcs, &vop_plane_funcs,
2684 win->data_formats, win->nformats, win->type);
2686 DRM_ERROR("failed to initialize plane\n");
2689 drm_plane_helper_add(&win->base, &plane_helper_funcs);
2690 drm_object_attach_property(&win->base.base,
2691 vop->plane_zpos_prop, win->win_id);
2693 if (VOP_WIN_SUPPORT(vop, win, xmirror))
2694 rotations |= BIT(DRM_REFLECT_X);
2696 if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2697 rotations |= BIT(DRM_REFLECT_Y);
2699 prop = drm_property_create_bool(vop->drm_dev,
2700 DRM_MODE_PROP_ATOMIC,
2704 private->logo_ymirror_prop = prop;
2708 rotations |= BIT(DRM_ROTATE_0);
2709 prop = drm_mode_create_rotation_property(vop->drm_dev,
2712 DRM_ERROR("failed to create zpos property\n");
2715 drm_object_attach_property(&win->base.base, prop,
2717 win->rotation_prop = prop;
2720 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2721 if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2722 VOP_WIN_SUPPORT(vop, win, alpha_en))
2723 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2725 drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2731 static int vop_create_crtc(struct vop *vop)
2733 struct device *dev = vop->dev;
2734 const struct vop_data *vop_data = vop->data;
2735 struct drm_device *drm_dev = vop->drm_dev;
2736 struct rockchip_drm_private *private = drm_dev->dev_private;
2737 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2738 struct drm_crtc *crtc = &vop->crtc;
2739 struct device_node *port;
2740 uint64_t feature = 0;
2745 * Create drm_plane for primary and cursor planes first, since we need
2746 * to pass them to drm_crtc_init_with_planes, which sets the
2747 * "possible_crtcs" to the newly initialized crtc.
2749 for (i = 0; i < vop->num_wins; i++) {
2750 struct vop_win *win = &vop->win[i];
2752 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2753 win->type != DRM_PLANE_TYPE_CURSOR)
2756 ret = vop_plane_init(vop, win, 0);
2758 goto err_cleanup_planes;
2761 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2763 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2768 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2769 &vop_crtc_funcs, NULL);
2771 goto err_cleanup_planes;
2773 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2776 * Create drm_planes for overlay windows with possible_crtcs restricted
2777 * to the newly created crtc.
2779 for (i = 0; i < vop->num_wins; i++) {
2780 struct vop_win *win = &vop->win[i];
2781 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2783 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2786 ret = vop_plane_init(vop, win, possible_crtcs);
2788 goto err_cleanup_crtc;
2791 port = of_get_child_by_name(dev->of_node, "port");
2793 DRM_ERROR("no port node found in %s\n",
2794 dev->of_node->full_name);
2796 goto err_cleanup_crtc;
2799 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
2800 vop_fb_unref_worker);
2802 init_completion(&vop->dsp_hold_completion);
2803 init_completion(&vop->line_flag_completion);
2805 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2807 ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2809 goto err_unregister_crtc_funcs;
2810 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2811 drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2813 VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2814 VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2815 VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2816 VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2818 #undef VOP_ATTACH_MODE_CONFIG_PROP
2820 drm_object_attach_property(&crtc->base, private->cabc_lut_property, 0);
2821 drm_object_attach_property(&crtc->base, private->cabc_mode_property, 0);
2822 drm_object_attach_property(&crtc->base, private->cabc_stage_up_property, 0);
2823 drm_object_attach_property(&crtc->base, private->cabc_stage_down_property, 0);
2824 drm_object_attach_property(&crtc->base, private->cabc_global_dn_property, 0);
2825 drm_object_attach_property(&crtc->base, private->cabc_calc_pixel_num_property, 0);
2827 if (vop_data->feature & VOP_FEATURE_AFBDC)
2828 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2829 drm_object_attach_property(&crtc->base, vop->feature_prop,
2831 if (vop->lut_regs) {
2832 u16 *r_base, *g_base, *b_base;
2833 u32 lut_len = vop->lut_len;
2835 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2836 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2841 r_base = crtc->gamma_store;
2842 g_base = r_base + crtc->gamma_size;
2843 b_base = g_base + crtc->gamma_size;
2845 for (i = 0; i < lut_len; i++) {
2846 vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2847 rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2848 &g_base[i], &b_base[i],
2855 err_unregister_crtc_funcs:
2856 rockchip_unregister_crtc_funcs(crtc);
2858 drm_crtc_cleanup(crtc);
2860 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2862 drm_plane_cleanup(plane);
2866 static void vop_destroy_crtc(struct vop *vop)
2868 struct drm_crtc *crtc = &vop->crtc;
2869 struct drm_device *drm_dev = vop->drm_dev;
2870 struct drm_plane *plane, *tmp;
2872 rockchip_unregister_crtc_funcs(crtc);
2873 of_node_put(crtc->port);
2876 * We need to cleanup the planes now. Why?
2878 * The planes are "&vop->win[i].base". That means the memory is
2879 * all part of the big "struct vop" chunk of memory. That memory
2880 * was devm allocated and associated with this component. We need to
2881 * free it ourselves before vop_unbind() finishes.
2883 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2885 vop_plane_destroy(plane);
2888 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2889 * references the CRTC.
2891 drm_crtc_cleanup(crtc);
2892 drm_flip_work_cleanup(&vop->fb_unref_work);
2896 * Initialize the vop->win array elements.
2898 static int vop_win_init(struct vop *vop)
2900 const struct vop_data *vop_data = vop->data;
2902 unsigned int num_wins = 0;
2903 struct drm_property *prop;
2904 static const struct drm_prop_enum_list props[] = {
2905 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2906 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2908 static const struct drm_prop_enum_list crtc_props[] = {
2909 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2912 for (i = 0; i < vop_data->win_size; i++) {
2913 struct vop_win *vop_win = &vop->win[num_wins];
2914 const struct vop_win_data *win_data = &vop_data->win[i];
2919 vop_win->phy = win_data->phy;
2920 vop_win->csc = win_data->csc;
2921 vop_win->offset = win_data->base;
2922 vop_win->type = win_data->type;
2923 vop_win->data_formats = win_data->phy->data_formats;
2924 vop_win->nformats = win_data->phy->nformats;
2926 vop_win->win_id = i;
2927 vop_win->area_id = 0;
2930 for (j = 0; j < win_data->area_size; j++) {
2931 struct vop_win *vop_area = &vop->win[num_wins];
2932 const struct vop_win_phy *area = win_data->area[j];
2934 vop_area->parent = vop_win;
2935 vop_area->offset = vop_win->offset;
2936 vop_area->phy = area;
2937 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2938 vop_area->data_formats = vop_win->data_formats;
2939 vop_area->nformats = vop_win->nformats;
2940 vop_area->vop = vop;
2941 vop_area->win_id = i;
2942 vop_area->area_id = j;
2947 vop->num_wins = num_wins;
2949 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2950 "ZPOS", 0, vop->data->win_size);
2952 DRM_ERROR("failed to create zpos property\n");
2955 vop->plane_zpos_prop = prop;
2957 vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2958 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2959 props, ARRAY_SIZE(props),
2960 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2961 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2962 if (!vop->plane_feature_prop) {
2963 DRM_ERROR("failed to create feature property\n");
2967 vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2968 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2969 crtc_props, ARRAY_SIZE(crtc_props),
2970 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2971 if (!vop->feature_prop) {
2972 DRM_ERROR("failed to create vop feature property\n");
2980 * rockchip_drm_wait_line_flag - acqiure the give line flag event
2981 * @crtc: CRTC to enable line flag
2982 * @line_num: interested line number
2983 * @mstimeout: millisecond for timeout
2985 * Driver would hold here until the interested line flag interrupt have
2986 * happened or timeout to wait.
2989 * Zero on success, negative errno on failure.
2991 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2992 unsigned int mstimeout)
2994 struct vop *vop = to_vop(crtc);
2995 unsigned long jiffies_left;
2998 if (!crtc || !vop->is_enabled)
3001 mutex_lock(&vop->vop_lock);
3003 if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
3008 if (vop_line_flag_irq_is_enabled(vop)) {
3013 reinit_completion(&vop->line_flag_completion);
3014 vop_line_flag_irq_enable(vop, line_num);
3016 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
3017 msecs_to_jiffies(mstimeout));
3018 vop_line_flag_irq_disable(vop);
3020 if (jiffies_left == 0) {
3021 dev_err(vop->dev, "Timeout waiting for IRQ\n");
3027 mutex_unlock(&vop->vop_lock);
3031 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
3033 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
3036 if (event == DEVFREQ_PRECHANGE)
3037 mutex_lock(&dmc_vop->vop_lock);
3038 else if (event == DEVFREQ_POSTCHANGE)
3039 mutex_unlock(&dmc_vop->vop_lock);
3044 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
3049 dmc_vop->devfreq = devfreq;
3050 dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
3051 devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
3052 DEVFREQ_TRANSITION_NOTIFIER);
3055 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
3057 static void vop_backlight_config_done(struct device *dev, bool async)
3059 struct vop *vop = dev_get_drvdata(dev);
3061 if (vop && vop->is_enabled) {
3066 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
3067 readx_poll_timeout(CTRL_GET, cfg_done,
3068 dle, !dle, 5, 33333);
3074 static const struct rockchip_sub_backlight_ops rockchip_sub_backlight_ops = {
3075 .config_done = vop_backlight_config_done,
3078 static int vop_bind(struct device *dev, struct device *master, void *data)
3080 struct platform_device *pdev = to_platform_device(dev);
3081 const struct vop_data *vop_data;
3082 struct drm_device *drm_dev = data;
3084 struct resource *res;
3089 vop_data = of_device_get_match_data(dev);
3093 for (i = 0; i < vop_data->win_size; i++) {
3094 const struct vop_win_data *win_data = &vop_data->win[i];
3096 num_wins += win_data->area_size + 1;
3099 /* Allocate vop struct and its vop_win array */
3100 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
3101 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3106 vop->data = vop_data;
3107 vop->drm_dev = drm_dev;
3108 vop->num_wins = num_wins;
3109 dev_set_drvdata(dev, vop);
3111 ret = vop_win_init(vop);
3115 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3117 dev_warn(vop->dev, "failed to get vop register byname\n");
3118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3120 vop->regs = devm_ioremap_resource(dev, res);
3121 if (IS_ERR(vop->regs))
3122 return PTR_ERR(vop->regs);
3123 vop->len = resource_size(res);
3125 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
3129 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
3130 vop->lut_regs = devm_ioremap_resource(dev, res);
3131 if (IS_ERR(vop->lut_regs)) {
3132 dev_warn(vop->dev, "failed to get vop lut registers\n");
3133 vop->lut_regs = NULL;
3135 if (vop->lut_regs) {
3136 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
3137 if (vop->lut_len != 256 && vop->lut_len != 1024) {
3138 dev_err(vop->dev, "unsupport lut sizes %d\n",
3144 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cabc_lut");
3145 vop->cabc_lut_regs = devm_ioremap_resource(dev, res);
3146 if (IS_ERR(vop->cabc_lut_regs)) {
3147 dev_warn(vop->dev, "failed to get vop cabc lut registers\n");
3148 vop->cabc_lut_regs = NULL;
3151 if (vop->cabc_lut_regs) {
3152 vop->cabc_lut_len = resource_size(res) >> 2;
3153 if (vop->cabc_lut_len != 128) {
3154 dev_err(vop->dev, "unsupport cabc lut sizes %d\n",
3160 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
3161 if (IS_ERR(vop->hclk)) {
3162 dev_err(vop->dev, "failed to get hclk source\n");
3163 return PTR_ERR(vop->hclk);
3165 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
3166 if (IS_ERR(vop->aclk)) {
3167 dev_err(vop->dev, "failed to get aclk source\n");
3168 return PTR_ERR(vop->aclk);
3170 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
3171 if (IS_ERR(vop->dclk)) {
3172 dev_err(vop->dev, "failed to get dclk source\n");
3173 return PTR_ERR(vop->dclk);
3176 vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
3177 if (PTR_ERR(vop->dclk_source) == -ENOENT) {
3178 vop->dclk_source = NULL;
3179 } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
3180 return -EPROBE_DEFER;
3181 } else if (IS_ERR(vop->dclk_source)) {
3182 dev_err(vop->dev, "failed to get dclk source parent\n");
3183 return PTR_ERR(vop->dclk_source);
3186 irq = platform_get_irq(pdev, 0);
3188 dev_err(dev, "cannot find irq for vop\n");
3191 vop->irq = (unsigned int)irq;
3193 spin_lock_init(&vop->reg_lock);
3194 spin_lock_init(&vop->irq_lock);
3195 mutex_init(&vop->vop_lock);
3197 mutex_init(&vop->vsync_mutex);
3199 ret = devm_request_irq(dev, vop->irq, vop_isr,
3200 IRQF_SHARED, dev_name(dev), vop);
3204 /* IRQ is initially disabled; it gets enabled in power_on */
3205 disable_irq(vop->irq);
3207 ret = vop_create_crtc(vop);
3211 pm_runtime_enable(&pdev->dev);
3213 of_rockchip_drm_sub_backlight_register(dev, &vop->crtc,
3214 &rockchip_sub_backlight_ops);
3221 static void vop_unbind(struct device *dev, struct device *master, void *data)
3223 struct vop *vop = dev_get_drvdata(dev);
3225 pm_runtime_disable(dev);
3226 vop_destroy_crtc(vop);
3229 const struct component_ops vop_component_ops = {
3231 .unbind = vop_unbind,
3233 EXPORT_SYMBOL_GPL(vop_component_ops);