2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
23 #include <linux/devfreq.h>
24 #include <linux/iopoll.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/iopoll.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/component.h>
35 #include <linux/reset.h>
36 #include <linux/delay.h>
37 #include <linux/sort.h>
38 #include <uapi/drm/rockchip_drm.h>
40 #include "rockchip_drm_drv.h"
41 #include "rockchip_drm_gem.h"
42 #include "rockchip_drm_fb.h"
43 #include "rockchip_drm_vop.h"
44 #include "rockchip_drm_backlight.h"
48 #define VOP_REG_SUPPORT(vop, reg) \
49 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
50 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
51 reg.end_minor >= VOP_MINOR(vop->data->version) && \
54 #define VOP_WIN_SUPPORT(vop, win, name) \
55 VOP_REG_SUPPORT(vop, win->phy->name)
57 #define VOP_CTRL_SUPPORT(vop, name) \
58 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
60 #define VOP_INTR_SUPPORT(vop, name) \
61 VOP_REG_SUPPORT(vop, vop->data->intr->name)
63 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
64 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
66 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
68 if (VOP_REG_SUPPORT(vop, reg)) \
69 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
70 v, reg.write_mask, relaxed); \
72 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
75 #define REG_SET(x, name, off, reg, v, relaxed) \
76 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
77 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
78 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
80 #define VOP_WIN_SET(x, win, name, v) \
81 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
82 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
83 REG_SET(x, name, 0, win->ext->name, v, true)
84 #define VOP_SCL_SET(x, win, name, v) \
85 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
86 #define VOP_SCL_SET_EXT(x, win, name, v) \
87 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
89 #define VOP_CTRL_SET(x, name, v) \
90 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
92 #define VOP_INTR_GET(vop, name) \
93 vop_read_reg(vop, 0, &vop->data->ctrl->name)
95 #define VOP_INTR_SET(vop, name, v) \
96 REG_SET(vop, name, 0, vop->data->intr->name, \
98 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
99 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
102 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
104 int i, reg = 0, mask = 0; \
105 for (i = 0; i < vop->data->intr->nintrs; i++) { \
106 if (vop->data->intr->intrs[i] & type) { \
111 VOP_INTR_SET_MASK(vop, name, mask, reg); \
113 #define VOP_INTR_GET_TYPE(vop, name, type) \
114 vop_get_intr_type(vop, &vop->data->intr->name, type)
116 #define VOP_CTRL_GET(x, name) \
117 vop_read_reg(x, 0, &vop->data->ctrl->name)
119 #define VOP_WIN_GET(x, win, name) \
120 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
122 #define VOP_WIN_NAME(win, name) \
123 (vop_get_win_phy(win, &win->phy->name)->name)
125 #define VOP_WIN_GET_YRGBADDR(vop, win) \
126 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
128 #define to_vop(x) container_of(x, struct vop, crtc)
129 #define to_vop_win(x) container_of(x, struct vop_win, base)
130 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
138 VOP_PENDING_FB_UNREF,
141 struct vop_plane_state {
142 struct drm_plane_state base;
145 unsigned int logo_ymirror;
147 struct drm_rect dest;
150 const uint32_t *y2r_table;
151 const uint32_t *r2r_table;
152 const uint32_t *r2y_table;
157 struct vop_win *parent;
158 struct drm_plane base;
163 enum drm_plane_type type;
164 const struct vop_win_phy *phy;
165 const struct vop_csc *csc;
166 const uint32_t *data_formats;
170 struct drm_property *rotation_prop;
171 struct vop_plane_state state;
175 struct drm_crtc crtc;
177 struct drm_device *drm_dev;
178 struct drm_property *plane_zpos_prop;
179 struct drm_property *plane_feature_prop;
180 struct drm_property *feature_prop;
181 bool is_iommu_enabled;
182 bool is_iommu_needed;
185 /* mutex vsync_ work */
186 struct mutex vsync_mutex;
187 bool vsync_work_pending;
189 struct completion dsp_hold_completion;
191 /* protected by dev->event_lock */
192 struct drm_pending_vblank_event *event;
194 struct drm_flip_work fb_unref_work;
195 unsigned long pending;
197 struct completion line_flag_completion;
199 const struct vop_data *data;
205 /* physical map length of vop register */
208 void __iomem *lut_regs;
212 void __iomem *cabc_lut_regs;
215 /* one time only one process allowed to config the register */
217 /* lock vop irq reg */
219 /* mutex vop enable and disable */
220 struct mutex vop_lock;
228 /* vop share memory frequency */
230 /* vop source handling, optional */
231 struct clk *dclk_source;
234 struct reset_control *dclk_rst;
236 struct notifier_block dmc_nb;
238 struct rockchip_dclk_pll *pll;
240 struct vop_win win[];
243 static struct vop *dmc_vop[MAX_VOPS];
244 static struct devfreq *devfreq_vop;
245 static DEFINE_MUTEX(register_devfreq_lock);
247 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
249 writel(v, vop->regs + offset);
250 vop->regsbak[offset >> 2] = v;
253 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
255 return readl(vop->regs + offset);
258 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
259 const struct vop_reg *reg)
261 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
264 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
265 uint32_t mask, uint32_t shift, uint32_t v,
266 bool write_mask, bool relaxed)
272 v = ((v & mask) << shift) | (mask << (shift + 16));
274 uint32_t cached_val = vop->regsbak[offset >> 2];
276 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
277 vop->regsbak[offset >> 2] = v;
281 writel_relaxed(v, vop->regs + offset);
283 writel(v, vop->regs + offset);
286 static inline const struct vop_win_phy *
287 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
289 if (!reg->mask && win->parent)
290 return win->parent->phy;
295 static inline uint32_t vop_get_intr_type(struct vop *vop,
296 const struct vop_reg *reg, int type)
299 uint32_t regs = vop_read_reg(vop, 0, reg);
301 for (i = 0; i < vop->data->intr->nintrs; i++) {
302 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
303 ret |= vop->data->intr->intrs[i];
309 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
316 for (i = 0; i < 8; i++)
317 vop_writel(vop, offset + i * 4, table[i]);
320 static inline void vop_cfg_done(struct vop *vop)
322 VOP_CTRL_SET(vop, cfg_done, 1);
325 static bool vop_is_allwin_disabled(struct vop *vop)
329 for (i = 0; i < vop->num_wins; i++) {
330 struct vop_win *win = &vop->win[i];
332 if (VOP_WIN_GET(vop, win, enable) != 0)
339 static bool vop_fs_irq_is_active(struct vop *vop)
341 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
344 static bool vop_line_flag_is_active(struct vop *vop)
346 return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
349 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
351 writel(v, vop->lut_regs + offset);
354 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
356 return readl(vop->lut_regs + offset);
359 static inline void vop_write_cabc_lut(struct vop *vop, uint32_t offset, uint32_t v)
361 writel(v, vop->cabc_lut_regs + offset);
364 static bool has_rb_swapped(uint32_t format)
367 case DRM_FORMAT_XBGR8888:
368 case DRM_FORMAT_ABGR8888:
369 case DRM_FORMAT_BGR888:
370 case DRM_FORMAT_BGR565:
377 static enum vop_data_format vop_convert_format(uint32_t format)
380 case DRM_FORMAT_XRGB8888:
381 case DRM_FORMAT_ARGB8888:
382 case DRM_FORMAT_XBGR8888:
383 case DRM_FORMAT_ABGR8888:
384 return VOP_FMT_ARGB8888;
385 case DRM_FORMAT_RGB888:
386 case DRM_FORMAT_BGR888:
387 return VOP_FMT_RGB888;
388 case DRM_FORMAT_RGB565:
389 case DRM_FORMAT_BGR565:
390 return VOP_FMT_RGB565;
391 case DRM_FORMAT_NV12:
392 case DRM_FORMAT_NV12_10:
393 return VOP_FMT_YUV420SP;
394 case DRM_FORMAT_NV16:
395 case DRM_FORMAT_NV16_10:
396 return VOP_FMT_YUV422SP;
397 case DRM_FORMAT_NV24:
398 case DRM_FORMAT_NV24_10:
399 return VOP_FMT_YUV444SP;
401 DRM_ERROR("unsupport format[%08x]\n", format);
406 static bool is_yuv_output(uint32_t bus_format)
408 switch (bus_format) {
409 case MEDIA_BUS_FMT_YUV8_1X24:
410 case MEDIA_BUS_FMT_YUV10_1X30:
411 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
412 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
419 static bool is_yuv_support(uint32_t format)
422 case DRM_FORMAT_NV12:
423 case DRM_FORMAT_NV12_10:
424 case DRM_FORMAT_NV16:
425 case DRM_FORMAT_NV16_10:
426 case DRM_FORMAT_NV24:
427 case DRM_FORMAT_NV24_10:
434 static bool is_yuv_10bit(uint32_t format)
437 case DRM_FORMAT_NV12_10:
438 case DRM_FORMAT_NV16_10:
439 case DRM_FORMAT_NV24_10:
446 static bool is_alpha_support(uint32_t format)
449 case DRM_FORMAT_ARGB8888:
450 case DRM_FORMAT_ABGR8888:
457 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
458 uint32_t dst, bool is_horizontal,
459 int vsu_mode, int *vskiplines)
461 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
464 if (mode == SCALE_UP)
465 val = GET_SCL_FT_BIC(src, dst);
466 else if (mode == SCALE_DOWN)
467 val = GET_SCL_FT_BILI_DN(src, dst);
469 if (mode == SCALE_UP) {
470 if (vsu_mode == SCALE_UP_BIL)
471 val = GET_SCL_FT_BILI_UP(src, dst);
473 val = GET_SCL_FT_BIC(src, dst);
474 } else if (mode == SCALE_DOWN) {
476 *vskiplines = scl_get_vskiplines(src, dst);
477 val = scl_get_bili_dn_vskip(src, dst,
480 val = GET_SCL_FT_BILI_DN(src, dst);
488 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
489 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
490 uint32_t dst_h, uint32_t pixel_format)
492 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
493 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
494 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
495 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
496 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
497 bool is_yuv = is_yuv_support(pixel_format);
498 uint16_t cbcr_src_w = src_w / hsub;
499 uint16_t cbcr_src_h = src_h / vsub;
508 if (!win->phy->scl->ext) {
509 VOP_SCL_SET(vop, win, scale_yrgb_x,
510 scl_cal_scale2(src_w, dst_w));
511 VOP_SCL_SET(vop, win, scale_yrgb_y,
512 scl_cal_scale2(src_h, dst_h));
514 VOP_SCL_SET(vop, win, scale_cbcr_x,
515 scl_cal_scale2(cbcr_src_w, dst_w));
516 VOP_SCL_SET(vop, win, scale_cbcr_y,
517 scl_cal_scale2(cbcr_src_h, dst_h));
522 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
523 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
526 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
527 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
528 if (cbcr_hor_scl_mode == SCALE_DOWN)
529 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
531 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
533 if (yrgb_hor_scl_mode == SCALE_DOWN)
534 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
536 lb_mode = scl_vop_cal_lb_mode(src_w, false);
539 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
540 if (lb_mode == LB_RGB_3840X2) {
541 if (yrgb_ver_scl_mode != SCALE_NONE) {
542 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
545 if (cbcr_ver_scl_mode != SCALE_NONE) {
546 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
549 vsu_mode = SCALE_UP_BIL;
550 } else if (lb_mode == LB_RGB_2560X4) {
551 vsu_mode = SCALE_UP_BIL;
553 vsu_mode = SCALE_UP_BIC;
556 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
558 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
559 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
560 false, vsu_mode, &vskiplines);
561 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
563 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
564 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
566 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
567 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
568 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
569 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
570 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
574 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
575 dst_w, true, 0, NULL);
576 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
577 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
578 dst_h, false, vsu_mode, &vskiplines);
579 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
581 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
582 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
583 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
584 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
585 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
586 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
587 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
592 * rk3399 colorspace path:
593 * Input Win csc Output
594 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
597 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
598 * RGB --> 709To2020->R2Y __/
600 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
603 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
604 * RGB --> 709To2020->R2Y __/
606 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
609 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
610 * RGB --> R2Y(601) __/
612 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
615 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
617 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
619 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
621 * 11. RGB --> bypass --> RGB_OUTPUT(709)
623 static int vop_csc_setup(const struct vop_csc_table *csc_table,
624 bool is_input_yuv, bool is_output_yuv,
625 int input_csc, int output_csc,
626 const uint32_t **y2r_table,
627 const uint32_t **r2r_table,
628 const uint32_t **r2y_table)
635 if (output_csc == CSC_BT2020) {
637 if (input_csc == CSC_BT2020)
639 *y2r_table = csc_table->y2r_bt709;
641 if (input_csc != CSC_BT2020)
642 *r2r_table = csc_table->r2r_bt709_to_bt2020;
643 *r2y_table = csc_table->r2y_bt2020;
645 if (is_input_yuv && input_csc == CSC_BT2020)
646 *y2r_table = csc_table->y2r_bt2020;
647 if (input_csc == CSC_BT2020)
648 *r2r_table = csc_table->r2r_bt2020_to_bt709;
649 if (!is_input_yuv || *y2r_table) {
650 if (output_csc == CSC_BT709)
651 *r2y_table = csc_table->r2y_bt709;
653 *r2y_table = csc_table->r2y_bt601;
661 * is possible use bt2020 on rgb mode?
663 if (WARN_ON(output_csc == CSC_BT2020))
666 if (input_csc == CSC_BT2020)
667 *y2r_table = csc_table->y2r_bt2020;
668 else if (input_csc == CSC_BT709)
669 *y2r_table = csc_table->y2r_bt709;
671 *y2r_table = csc_table->y2r_bt601;
673 if (input_csc == CSC_BT2020)
675 * We don't have bt601 to bt709 table, force use bt709.
677 *r2r_table = csc_table->r2r_bt2020_to_bt709;
683 static int vop_csc_atomic_check(struct drm_crtc *crtc,
684 struct drm_crtc_state *crtc_state)
686 struct vop *vop = to_vop(crtc);
687 struct drm_atomic_state *state = crtc_state->state;
688 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
689 const struct vop_csc_table *csc_table = vop->data->csc_table;
690 struct drm_plane_state *pstate;
691 struct drm_plane *plane;
692 bool is_input_yuv, is_output_yuv;
698 is_output_yuv = is_yuv_output(s->bus_format);
700 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
701 struct vop_plane_state *vop_plane_state;
703 pstate = drm_atomic_get_plane_state(state, plane);
705 return PTR_ERR(pstate);
706 vop_plane_state = to_vop_plane_state(pstate);
710 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
713 * TODO: force set input and output csc mode.
715 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
716 CSC_BT709, CSC_BT709,
717 &vop_plane_state->y2r_table,
718 &vop_plane_state->r2r_table,
719 &vop_plane_state->r2y_table);
727 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
731 spin_lock_irqsave(&vop->irq_lock, flags);
733 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
734 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
736 spin_unlock_irqrestore(&vop->irq_lock, flags);
739 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
743 spin_lock_irqsave(&vop->irq_lock, flags);
745 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
747 spin_unlock_irqrestore(&vop->irq_lock, flags);
751 * (1) each frame starts at the start of the Vsync pulse which is signaled by
752 * the "FRAME_SYNC" interrupt.
753 * (2) the active data region of each frame ends at dsp_vact_end
754 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
755 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
757 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
759 * LINE_FLAG -------------------------------+
763 * | Vsync | Vbp | Vactive | Vfp |
767 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
768 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
769 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
770 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
772 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
774 uint32_t line_flag_irq;
777 spin_lock_irqsave(&vop->irq_lock, flags);
779 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
781 spin_unlock_irqrestore(&vop->irq_lock, flags);
783 return !!line_flag_irq;
786 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
790 if (WARN_ON(!vop->is_enabled))
793 spin_lock_irqsave(&vop->irq_lock, flags);
795 VOP_INTR_SET(vop, line_flag_num[0], line_num);
796 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
797 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
799 spin_unlock_irqrestore(&vop->irq_lock, flags);
802 static void vop_line_flag_irq_disable(struct vop *vop)
806 if (WARN_ON(!vop->is_enabled))
809 spin_lock_irqsave(&vop->irq_lock, flags);
811 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
813 spin_unlock_irqrestore(&vop->irq_lock, flags);
816 static void vop_crtc_load_lut(struct drm_crtc *crtc)
818 struct vop *vop = to_vop(crtc);
821 if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
824 if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
827 if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
828 spin_lock(&vop->reg_lock);
829 VOP_CTRL_SET(vop, dsp_lut_en, 0);
831 spin_unlock(&vop->reg_lock);
833 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
834 readx_poll_timeout(CTRL_GET, dsp_lut_en,
835 dle, !dle, 5, 33333);
837 lut_idx = CTRL_GET(lut_buffer_index);
840 for (i = 0; i < vop->lut_len; i++)
841 vop_write_lut(vop, i << 2, vop->lut[i]);
843 spin_lock(&vop->reg_lock);
845 VOP_CTRL_SET(vop, dsp_lut_en, 1);
846 VOP_CTRL_SET(vop, update_gamma_lut, 1);
848 vop->lut_active = true;
850 spin_unlock(&vop->reg_lock);
852 if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
853 readx_poll_timeout(CTRL_GET, lut_buffer_index,
854 dle, dle != lut_idx, 5, 33333);
856 * update_gamma value auto clean to 0 by HW, should not
859 VOP_CTRL_SET(vop, update_gamma_lut, 0);
864 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
867 struct vop *vop = to_vop(crtc);
868 u32 lut_len = vop->lut_len;
871 if (regno >= lut_len || !vop->lut)
874 r = red * (lut_len - 1) / 0xffff;
875 g = green * (lut_len - 1) / 0xffff;
876 b = blue * (lut_len - 1) / 0xffff;
877 vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
880 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
881 u16 *blue, int regno)
883 struct vop *vop = to_vop(crtc);
884 u32 lut_len = vop->lut_len;
887 if (regno >= lut_len || !vop->lut)
890 r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
891 g = (vop->lut[regno] / lut_len) & (lut_len - 1);
892 b = vop->lut[regno] & (lut_len - 1);
893 *red = r * 0xffff / (lut_len - 1);
894 *green = g * 0xffff / (lut_len - 1);
895 *blue = b * 0xffff / (lut_len - 1);
898 static void vop_power_enable(struct drm_crtc *crtc)
900 struct vop *vop = to_vop(crtc);
903 ret = clk_prepare_enable(vop->hclk);
905 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
909 ret = clk_prepare_enable(vop->dclk);
911 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
912 goto err_disable_hclk;
915 ret = clk_prepare_enable(vop->aclk);
917 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
918 goto err_disable_dclk;
921 ret = pm_runtime_get_sync(vop->dev);
923 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
927 memcpy(vop->regsbak, vop->regs, vop->len);
929 vop->is_enabled = true;
934 clk_disable_unprepare(vop->dclk);
936 clk_disable_unprepare(vop->hclk);
939 static void vop_initial(struct drm_crtc *crtc)
941 struct vop *vop = to_vop(crtc);
945 vop_power_enable(crtc);
947 VOP_CTRL_SET(vop, global_regdone_en, 1);
948 VOP_CTRL_SET(vop, dsp_blank, 0);
951 * restore the lut table.
954 vop_crtc_load_lut(crtc);
957 * We need to make sure that all windows are disabled before resume
958 * the crtc. Otherwise we might try to scan from a destroyed
961 for (i = 0; i < vop->num_wins; i++) {
962 struct vop_win *win = &vop->win[i];
963 int channel = i * 2 + 1;
965 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
966 if (win->phy->scl && win->phy->scl->ext) {
967 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
968 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
969 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
970 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
972 VOP_WIN_SET(vop, win, enable, 0);
973 VOP_WIN_SET(vop, win, gate, 1);
975 VOP_CTRL_SET(vop, afbdc_en, 0);
977 irqs = BUS_ERROR_INTR | WIN0_EMPTY_INTR | WIN1_EMPTY_INTR |
978 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | HWC_EMPTY_INTR |
980 VOP_INTR_SET_TYPE(vop, clear, irqs, 1);
981 VOP_INTR_SET_TYPE(vop, enable, irqs, 1);
984 static void vop_crtc_disable(struct drm_crtc *crtc)
986 struct vop *vop = to_vop(crtc);
988 mutex_lock(&vop->vop_lock);
989 drm_crtc_vblank_off(crtc);
992 * Vop standby will take effect at end of current frame,
993 * if dsp hold valid irq happen, it means standby complete.
995 * we must wait standby complete when we want to disable aclk,
996 * if not, memory bus maybe dead.
998 reinit_completion(&vop->dsp_hold_completion);
999 vop_dsp_hold_valid_irq_enable(vop);
1001 spin_lock(&vop->reg_lock);
1003 VOP_CTRL_SET(vop, standby, 1);
1005 spin_unlock(&vop->reg_lock);
1007 WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
1008 msecs_to_jiffies(50)));
1010 vop_dsp_hold_valid_irq_disable(vop);
1012 disable_irq(vop->irq);
1014 vop->is_enabled = false;
1015 if (vop->is_iommu_enabled) {
1017 * vop standby complete, so iommu detach is safe.
1019 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
1020 vop->is_iommu_enabled = false;
1023 pm_runtime_put(vop->dev);
1024 clk_disable_unprepare(vop->dclk);
1025 clk_disable_unprepare(vop->aclk);
1026 clk_disable_unprepare(vop->hclk);
1027 mutex_unlock(&vop->vop_lock);
1030 static void vop_plane_destroy(struct drm_plane *plane)
1032 drm_plane_cleanup(plane);
1035 static int vop_plane_prepare_fb(struct drm_plane *plane,
1036 const struct drm_plane_state *new_state)
1038 if (plane->state->fb)
1039 drm_framebuffer_reference(plane->state->fb);
1044 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1045 const struct drm_plane_state *old_state)
1048 drm_framebuffer_unreference(old_state->fb);
1051 static int vop_plane_atomic_check(struct drm_plane *plane,
1052 struct drm_plane_state *state)
1054 struct drm_crtc *crtc = state->crtc;
1055 struct drm_framebuffer *fb = state->fb;
1056 struct vop_win *win = to_vop_win(plane);
1057 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1058 struct drm_crtc_state *crtc_state;
1059 const struct vop_data *vop_data;
1063 struct drm_rect *dest = &vop_plane_state->dest;
1064 struct drm_rect *src = &vop_plane_state->src;
1065 struct drm_rect clip;
1066 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1067 DRM_PLANE_HELPER_NO_SCALING;
1068 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1069 DRM_PLANE_HELPER_NO_SCALING;
1070 unsigned long offset;
1071 dma_addr_t dma_addr;
1074 crtc = crtc ? crtc : plane->state->crtc;
1076 * Both crtc or plane->state->crtc can be null.
1081 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1082 if (IS_ERR(crtc_state))
1083 return PTR_ERR(crtc_state);
1085 src->x1 = state->src_x;
1086 src->y1 = state->src_y;
1087 src->x2 = state->src_x + state->src_w;
1088 src->y2 = state->src_y + state->src_h;
1089 dest->x1 = state->crtc_x;
1090 dest->y1 = state->crtc_y;
1091 dest->x2 = state->crtc_x + state->crtc_w;
1092 dest->y2 = state->crtc_y + state->crtc_h;
1094 vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1095 if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1100 clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1103 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1107 true, true, &visible);
1114 vop_plane_state->format = vop_convert_format(fb->pixel_format);
1115 if (vop_plane_state->format < 0)
1116 return vop_plane_state->format;
1119 vop_data = vop->data;
1121 if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1122 drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1123 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1124 drm_rect_width(src) >> 16,
1125 drm_rect_height(src) >> 16,
1126 vop_data->max_input.width,
1127 vop_data->max_input.height);
1132 * Src.x1 can be odd when do clip, but yuv plane start point
1133 * need align with 2 pixel.
1135 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1136 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1140 offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1141 if (state->rotation & BIT(DRM_REFLECT_Y) ||
1142 (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1143 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1145 offset += (src->y1 >> 16) * fb->pitches[0];
1147 dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1148 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1149 if (is_yuv_support(fb->pixel_format)) {
1150 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1151 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1152 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1154 offset = (src->x1 >> 16) * bpp / hsub / 8;
1155 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1157 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1158 dma_addr += offset + fb->offsets[1];
1159 vop_plane_state->uv_mst = dma_addr;
1162 vop_plane_state->enable = true;
1167 vop_plane_state->enable = false;
1171 static void vop_plane_atomic_disable(struct drm_plane *plane,
1172 struct drm_plane_state *old_state)
1174 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1175 struct vop_win *win = to_vop_win(plane);
1176 struct vop *vop = to_vop(old_state->crtc);
1178 if (!old_state->crtc)
1181 spin_lock(&vop->reg_lock);
1184 * FIXUP: some of the vop scale would be abnormal after windows power
1185 * on/off so deinit scale to scale_none mode.
1187 if (win->phy->scl && win->phy->scl->ext) {
1188 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1189 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1190 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1191 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1193 VOP_WIN_SET(vop, win, enable, 0);
1195 spin_unlock(&vop->reg_lock);
1197 vop_plane_state->enable = false;
1200 static void vop_plane_atomic_update(struct drm_plane *plane,
1201 struct drm_plane_state *old_state)
1203 struct drm_plane_state *state = plane->state;
1204 struct drm_crtc *crtc = state->crtc;
1205 struct vop_win *win = to_vop_win(plane);
1206 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1207 struct rockchip_crtc_state *s;
1209 struct drm_framebuffer *fb = state->fb;
1210 unsigned int actual_w, actual_h;
1211 unsigned int dsp_stx, dsp_sty;
1212 uint32_t act_info, dsp_info, dsp_st;
1213 struct drm_rect *src = &vop_plane_state->src;
1214 struct drm_rect *dest = &vop_plane_state->dest;
1215 const uint32_t *y2r_table = vop_plane_state->y2r_table;
1216 const uint32_t *r2r_table = vop_plane_state->r2r_table;
1217 const uint32_t *r2y_table = vop_plane_state->r2y_table;
1218 int ymirror, xmirror;
1223 * can't update plane when vop is disabled.
1228 if (!vop_plane_state->enable) {
1229 vop_plane_atomic_disable(plane, old_state);
1233 actual_w = drm_rect_width(src) >> 16;
1234 actual_h = drm_rect_height(src) >> 16;
1235 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1237 dsp_info = (drm_rect_height(dest) - 1) << 16;
1238 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1240 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1241 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1242 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1244 ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1245 (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1246 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1248 vop = to_vop(state->crtc);
1249 s = to_rockchip_crtc_state(crtc->state);
1251 spin_lock(&vop->reg_lock);
1253 VOP_WIN_SET(vop, win, xmirror, xmirror);
1254 VOP_WIN_SET(vop, win, ymirror, ymirror);
1255 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1256 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1257 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1258 if (is_yuv_support(fb->pixel_format)) {
1259 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1260 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1262 VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1264 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1265 drm_rect_width(dest), drm_rect_height(dest),
1268 VOP_WIN_SET(vop, win, act_info, act_info);
1269 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1270 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1272 rb_swap = has_rb_swapped(fb->pixel_format);
1273 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1275 if (is_alpha_support(fb->pixel_format) &&
1276 (s->dsp_layer_sel & 0x3) != win->win_id) {
1277 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1278 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1279 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1280 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1281 SRC_BLEND_M0(ALPHA_PER_PIX) |
1282 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1283 SRC_FACTOR_M0(ALPHA_ONE);
1284 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1285 VOP_WIN_SET(vop, win, alpha_mode, 1);
1286 VOP_WIN_SET(vop, win, alpha_en, 1);
1288 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1289 VOP_WIN_SET(vop, win, alpha_en, 0);
1293 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1294 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1295 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1296 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1297 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1298 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1300 VOP_WIN_SET(vop, win, enable, 1);
1301 spin_unlock(&vop->reg_lock);
1302 vop->is_iommu_needed = true;
1305 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1306 .prepare_fb = vop_plane_prepare_fb,
1307 .cleanup_fb = vop_plane_cleanup_fb,
1308 .atomic_check = vop_plane_atomic_check,
1309 .atomic_update = vop_plane_atomic_update,
1310 .atomic_disable = vop_plane_atomic_disable,
1313 void vop_atomic_plane_reset(struct drm_plane *plane)
1315 struct vop_win *win = to_vop_win(plane);
1316 struct vop_plane_state *vop_plane_state =
1317 to_vop_plane_state(plane->state);
1319 if (plane->state && plane->state->fb)
1320 drm_framebuffer_unreference(plane->state->fb);
1322 kfree(vop_plane_state);
1323 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1324 if (!vop_plane_state)
1327 vop_plane_state->zpos = win->win_id;
1328 plane->state = &vop_plane_state->base;
1329 plane->state->plane = plane;
1332 struct drm_plane_state *
1333 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1335 struct vop_plane_state *old_vop_plane_state;
1336 struct vop_plane_state *vop_plane_state;
1338 if (WARN_ON(!plane->state))
1341 old_vop_plane_state = to_vop_plane_state(plane->state);
1342 vop_plane_state = kmemdup(old_vop_plane_state,
1343 sizeof(*vop_plane_state), GFP_KERNEL);
1344 if (!vop_plane_state)
1347 __drm_atomic_helper_plane_duplicate_state(plane,
1348 &vop_plane_state->base);
1350 return &vop_plane_state->base;
1353 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1354 struct drm_plane_state *state)
1356 struct vop_plane_state *vop_state = to_vop_plane_state(state);
1358 __drm_atomic_helper_plane_destroy_state(plane, state);
1363 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1364 struct drm_plane_state *state,
1365 struct drm_property *property,
1368 struct rockchip_drm_private *private = plane->dev->dev_private;
1369 struct vop_win *win = to_vop_win(plane);
1370 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1372 if (property == win->vop->plane_zpos_prop) {
1373 plane_state->zpos = val;
1377 if (property == win->rotation_prop) {
1378 state->rotation = val;
1382 if (property == private->logo_ymirror_prop) {
1383 WARN_ON(!rockchip_fb_is_logo(state->fb));
1384 plane_state->logo_ymirror = val;
1388 DRM_ERROR("failed to set vop plane property\n");
1392 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1393 const struct drm_plane_state *state,
1394 struct drm_property *property,
1397 struct vop_win *win = to_vop_win(plane);
1398 struct vop_plane_state *plane_state = to_vop_plane_state(state);
1400 if (property == win->vop->plane_zpos_prop) {
1401 *val = plane_state->zpos;
1405 if (property == win->rotation_prop) {
1406 *val = state->rotation;
1410 DRM_ERROR("failed to get vop plane property\n");
1414 static const struct drm_plane_funcs vop_plane_funcs = {
1415 .update_plane = drm_atomic_helper_update_plane,
1416 .disable_plane = drm_atomic_helper_disable_plane,
1417 .destroy = vop_plane_destroy,
1418 .reset = vop_atomic_plane_reset,
1419 .set_property = drm_atomic_helper_plane_set_property,
1420 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1421 .atomic_destroy_state = vop_atomic_plane_destroy_state,
1422 .atomic_set_property = vop_atomic_plane_set_property,
1423 .atomic_get_property = vop_atomic_plane_get_property,
1426 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1428 struct vop *vop = to_vop(crtc);
1429 unsigned long flags;
1431 if (!vop->is_enabled)
1434 spin_lock_irqsave(&vop->irq_lock, flags);
1436 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1437 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1439 spin_unlock_irqrestore(&vop->irq_lock, flags);
1444 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1446 struct vop *vop = to_vop(crtc);
1447 unsigned long flags;
1449 if (!vop->is_enabled)
1452 spin_lock_irqsave(&vop->irq_lock, flags);
1454 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1456 spin_unlock_irqrestore(&vop->irq_lock, flags);
1459 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1460 struct drm_file *file_priv)
1462 struct drm_device *drm = crtc->dev;
1463 struct vop *vop = to_vop(crtc);
1464 struct drm_pending_vblank_event *e;
1465 unsigned long flags;
1467 spin_lock_irqsave(&drm->event_lock, flags);
1469 if (e && e->base.file_priv == file_priv) {
1472 e->base.destroy(&e->base);
1473 file_priv->event_space += sizeof(e->event);
1475 spin_unlock_irqrestore(&drm->event_lock, flags);
1478 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1480 struct rockchip_drm_private *private = crtc->dev->dev_private;
1481 struct vop *vop = to_vop(crtc);
1483 if (on == vop->loader_protect)
1487 if (vop->dclk_source) {
1490 parent = clk_get_parent(vop->dclk_source);
1492 if (clk_is_match(private->default_pll.pll, parent))
1493 vop->pll = &private->default_pll;
1494 else if (clk_is_match(private->hdmi_pll.pll, parent))
1495 vop->pll = &private->hdmi_pll;
1497 vop->pll->use_count++;
1501 vop_power_enable(crtc);
1502 enable_irq(vop->irq);
1503 drm_crtc_vblank_on(crtc);
1504 vop->loader_protect = true;
1506 vop_crtc_disable(crtc);
1508 if (vop->dclk_source && vop->pll) {
1509 vop->pll->use_count--;
1512 vop->loader_protect = false;
1518 #define DEBUG_PRINT(args...) \
1521 seq_printf(s, args); \
1526 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1528 struct vop_win *win = to_vop_win(plane);
1529 struct drm_plane_state *state = plane->state;
1530 struct vop_plane_state *pstate = to_vop_plane_state(state);
1531 struct drm_rect *src, *dest;
1532 struct drm_framebuffer *fb = state->fb;
1535 DEBUG_PRINT(" win%d-%d: %s\n", win->win_id, win->area_id,
1536 pstate->enable ? "ACTIVE" : "DISABLED");
1541 dest = &pstate->dest;
1543 DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1544 fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1545 DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1546 DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1547 src->y1 >> 16, drm_rect_width(src) >> 16,
1548 drm_rect_height(src) >> 16);
1549 DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1550 drm_rect_width(dest), drm_rect_height(dest));
1552 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1553 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1554 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1555 i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1561 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1563 struct vop *vop = to_vop(crtc);
1564 struct drm_crtc_state *crtc_state = crtc->state;
1565 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1566 struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1567 bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1568 struct drm_plane *plane;
1571 DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1572 crtc_state->active ? "ACTIVE" : "DISABLED");
1574 if (!crtc_state->active)
1577 DEBUG_PRINT(" Connector: %s\n",
1578 drm_get_connector_name(state->output_type));
1579 DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1580 state->bus_format, state->output_mode);
1581 DEBUG_PRINT(" Display mode: %dx%d%s%d\n",
1582 mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1583 drm_mode_vrefresh(mode));
1584 DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1585 mode->clock, mode->crtc_clock, mode->type, mode->flags);
1586 DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1587 mode->hsync_end, mode->htotal);
1588 DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1589 mode->vsync_end, mode->vtotal);
1591 for (i = 0; i < vop->num_wins; i++) {
1592 plane = &vop->win[i].base;
1593 vop_plane_info_dump(s, plane);
1599 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1601 struct vop *vop = to_vop(crtc);
1602 struct drm_crtc_state *crtc_state = crtc->state;
1603 int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1606 if (!crtc_state->active)
1609 for (i = 0; i < dump_len; i += 4) {
1611 DEBUG_PRINT("\n0x%08x: ", i);
1612 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1618 static enum drm_mode_status
1619 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1622 struct vop *vop = to_vop(crtc);
1623 const struct vop_data *vop_data = vop->data;
1624 int request_clock = mode->clock;
1627 if (mode->hdisplay > vop_data->max_output.width)
1628 return MODE_BAD_HVALUE;
1630 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
1631 VOP_MAJOR(vop->data->version) == 3 &&
1632 VOP_MINOR(vop->data->version) <= 2)
1635 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1637 clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1640 * Hdmi or DisplayPort request a Accurate clock.
1642 if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1643 output_type == DRM_MODE_CONNECTOR_DisplayPort)
1644 if (clock != request_clock)
1645 return MODE_CLOCK_RANGE;
1650 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1651 .loader_protect = vop_crtc_loader_protect,
1652 .enable_vblank = vop_crtc_enable_vblank,
1653 .disable_vblank = vop_crtc_disable_vblank,
1654 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1655 .debugfs_dump = vop_crtc_debugfs_dump,
1656 .regs_dump = vop_crtc_regs_dump,
1657 .mode_valid = vop_crtc_mode_valid,
1660 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1661 const struct drm_display_mode *mode,
1662 struct drm_display_mode *adj_mode)
1664 struct vop *vop = to_vop(crtc);
1665 const struct vop_data *vop_data = vop->data;
1667 if (mode->hdisplay > vop_data->max_output.width)
1670 drm_mode_set_crtcinfo(adj_mode,
1671 CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1673 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1674 adj_mode->crtc_clock *= 2;
1676 adj_mode->crtc_clock =
1677 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1682 static void vop_crtc_enable(struct drm_crtc *crtc)
1684 struct vop *vop = to_vop(crtc);
1685 const struct vop_data *vop_data = vop->data;
1686 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1687 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1688 u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1689 u16 hdisplay = adjusted_mode->crtc_hdisplay;
1690 u16 htotal = adjusted_mode->crtc_htotal;
1691 u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1692 u16 hact_end = hact_st + hdisplay;
1693 u16 vdisplay = adjusted_mode->crtc_vdisplay;
1694 u16 vtotal = adjusted_mode->crtc_vtotal;
1695 u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1696 u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1697 u16 vact_end = vact_st + vdisplay;
1700 mutex_lock(&vop->vop_lock);
1703 VOP_CTRL_SET(vop, dclk_pol, 1);
1704 val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1705 0 : BIT(HSYNC_POSITIVE);
1706 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1707 0 : BIT(VSYNC_POSITIVE);
1708 VOP_CTRL_SET(vop, pin_pol, val);
1710 if (vop->dclk_source && vop->pll && vop->pll->pll) {
1711 if (clk_set_parent(vop->dclk_source, vop->pll->pll))
1712 DRM_DEV_ERROR(vop->dev,
1713 "failed to set dclk's parents\n");
1716 switch (s->output_type) {
1717 case DRM_MODE_CONNECTOR_LVDS:
1718 VOP_CTRL_SET(vop, rgb_en, 1);
1719 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1720 VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
1721 VOP_CTRL_SET(vop, lvds_en, 1);
1722 VOP_CTRL_SET(vop, lvds_pin_pol, val);
1723 VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
1725 case DRM_MODE_CONNECTOR_eDP:
1726 VOP_CTRL_SET(vop, edp_en, 1);
1727 VOP_CTRL_SET(vop, edp_pin_pol, val);
1728 VOP_CTRL_SET(vop, edp_dclk_pol, 1);
1730 case DRM_MODE_CONNECTOR_HDMIA:
1731 VOP_CTRL_SET(vop, hdmi_en, 1);
1732 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1733 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
1735 case DRM_MODE_CONNECTOR_DSI:
1736 VOP_CTRL_SET(vop, mipi_en, 1);
1737 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1738 VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
1739 VOP_CTRL_SET(vop, mipi_dual_channel_en,
1740 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL));
1741 VOP_CTRL_SET(vop, data01_swap,
1742 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_LINK));
1744 case DRM_MODE_CONNECTOR_DisplayPort:
1745 VOP_CTRL_SET(vop, dp_dclk_pol, 0);
1746 VOP_CTRL_SET(vop, dp_pin_pol, val);
1747 VOP_CTRL_SET(vop, dp_en, 1);
1749 case DRM_MODE_CONNECTOR_TV:
1750 if (vdisplay == CVBS_PAL_VDISPLAY)
1751 VOP_CTRL_SET(vop, tve_sw_mode, 1);
1753 VOP_CTRL_SET(vop, tve_sw_mode, 0);
1755 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
1756 VOP_CTRL_SET(vop, tve_dclk_en, 1);
1757 /* use the same pol reg with hdmi */
1758 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1759 VOP_CTRL_SET(vop, sw_genlock, 1);
1760 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
1761 VOP_CTRL_SET(vop, dither_up, 1);
1764 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1767 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1768 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1769 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1771 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1772 switch (s->bus_format) {
1773 case MEDIA_BUS_FMT_RGB565_1X16:
1774 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1776 case MEDIA_BUS_FMT_RGB666_1X18:
1777 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1778 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1780 case MEDIA_BUS_FMT_YUV8_1X24:
1781 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1782 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1784 case MEDIA_BUS_FMT_YUV10_1X30:
1785 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1786 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1788 case MEDIA_BUS_FMT_RGB888_1X24:
1790 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1794 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1795 val |= PRE_DITHER_DOWN_EN(0);
1797 val |= PRE_DITHER_DOWN_EN(1);
1798 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1799 VOP_CTRL_SET(vop, dither_down, val);
1800 VOP_CTRL_SET(vop, dclk_ddr,
1801 s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1802 VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1803 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1806 * Background color is 10bit depth if vop version >= 3.5
1808 if (!is_yuv_output(s->bus_format))
1810 else if (VOP_MAJOR(vop->data->version) == 3 &&
1811 VOP_MINOR(vop->data->version) >= 5)
1815 VOP_CTRL_SET(vop, dsp_background, val);
1816 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1817 val = hact_st << 16;
1819 VOP_CTRL_SET(vop, hact_st_end, val);
1820 VOP_CTRL_SET(vop, hpost_st_end, val);
1822 val = vact_st << 16;
1824 VOP_CTRL_SET(vop, vact_st_end, val);
1825 VOP_CTRL_SET(vop, vpost_st_end, val);
1827 VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1828 VOP_INTR_SET(vop, line_flag_num[1],
1829 vact_end - us_to_vertical_line(adjusted_mode, 1000));
1830 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1831 u16 vact_st_f1 = vtotal + vact_st + 1;
1832 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1834 val = vact_st_f1 << 16 | vact_end_f1;
1835 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1836 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1838 val = vtotal << 16 | (vtotal + vsync_len);
1839 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1840 VOP_CTRL_SET(vop, dsp_interlace, 1);
1841 VOP_CTRL_SET(vop, p2i_en, 1);
1842 vtotal += vtotal + 1;
1844 VOP_CTRL_SET(vop, dsp_interlace, 0);
1845 VOP_CTRL_SET(vop, p2i_en, 0);
1847 VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1849 VOP_CTRL_SET(vop, core_dclk_div,
1850 !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1852 VOP_CTRL_SET(vop, cabc_total_num, hdisplay * vdisplay);
1853 VOP_CTRL_SET(vop, cabc_config_mode, STAGE_BY_STAGE);
1854 VOP_CTRL_SET(vop, cabc_stage_up_mode, MUL_MODE);
1855 VOP_CTRL_SET(vop, cabc_scale_cfg_value, 1);
1856 VOP_CTRL_SET(vop, cabc_scale_cfg_enable, 0);
1857 VOP_CTRL_SET(vop, cabc_global_dn_limit_en, 1);
1859 clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1863 * enable vop, all the register would take effect when vop exit standby
1865 VOP_CTRL_SET(vop, standby, 0);
1867 enable_irq(vop->irq);
1868 drm_crtc_vblank_on(crtc);
1869 mutex_unlock(&vop->vop_lock);
1872 static int vop_zpos_cmp(const void *a, const void *b)
1874 struct vop_zpos *pa = (struct vop_zpos *)a;
1875 struct vop_zpos *pb = (struct vop_zpos *)b;
1877 return pa->zpos - pb->zpos;
1880 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1881 struct drm_crtc_state *crtc_state)
1883 struct vop *vop = to_vop(crtc);
1884 const struct vop_data *vop_data = vop->data;
1885 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1886 struct drm_atomic_state *state = crtc_state->state;
1887 struct drm_plane *plane;
1888 struct drm_plane_state *pstate;
1889 struct vop_plane_state *plane_state;
1890 struct vop_win *win;
1896 for_each_plane_in_state(state, plane, pstate, i) {
1897 struct drm_framebuffer *fb = pstate->fb;
1898 struct drm_rect *src;
1900 win = to_vop_win(plane);
1901 plane_state = to_vop_plane_state(pstate);
1903 if (pstate->crtc != crtc || !fb)
1906 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1909 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1910 DRM_ERROR("not support afbdc\n");
1914 switch (plane_state->format) {
1915 case VOP_FMT_ARGB8888:
1916 afbdc_format = AFBDC_FMT_U8U8U8U8;
1918 case VOP_FMT_RGB888:
1919 afbdc_format = AFBDC_FMT_U8U8U8;
1921 case VOP_FMT_RGB565:
1922 afbdc_format = AFBDC_FMT_RGB565;
1929 DRM_ERROR("vop only support one afbc layer\n");
1933 src = &plane_state->src;
1934 if (src->x1 || src->y1 || fb->offsets[0]) {
1935 DRM_ERROR("win[%d] afbdc not support offset display\n",
1937 DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1938 src->x1, src->y1, fb->offsets[0]);
1941 s->afbdc_win_format = afbdc_format;
1942 s->afbdc_win_width = pstate->fb->width - 1;
1943 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1944 s->afbdc_win_id = win->win_id;
1945 s->afbdc_win_ptr = plane_state->yrgb_mst;
1952 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1953 struct drm_crtc_state *crtc_state)
1955 struct rockchip_drm_private *private = crtc->dev->dev_private;
1956 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1957 struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1958 struct vop *vop = to_vop(crtc);
1959 struct rockchip_dclk_pll *old_pll = vop->pll;
1961 if (!vop->dclk_source)
1964 if (crtc_state->active) {
1965 WARN_ON(vop->pll && !vop->pll->use_count);
1966 if (!vop->pll || vop->pll->use_count > 1 ||
1967 s->output_type != old_s->output_type) {
1969 vop->pll->use_count--;
1971 if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1972 !private->default_pll.use_count)
1973 vop->pll = &private->default_pll;
1975 vop->pll = &private->hdmi_pll;
1977 vop->pll->use_count++;
1979 } else if (vop->pll) {
1980 vop->pll->use_count--;
1983 if (vop->pll != old_pll)
1984 crtc_state->mode_changed = true;
1987 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1988 struct drm_crtc_state *crtc_state)
1990 struct drm_atomic_state *state = crtc_state->state;
1991 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1992 struct vop *vop = to_vop(crtc);
1993 const struct vop_data *vop_data = vop->data;
1994 struct drm_plane *plane;
1995 struct drm_plane_state *pstate;
1996 struct vop_plane_state *plane_state;
1997 struct vop_zpos *pzpos;
1998 int dsp_layer_sel = 0;
1999 int i, j, cnt = 0, ret = 0;
2001 ret = vop_afbdc_atomic_check(crtc, crtc_state);
2005 ret = vop_csc_atomic_check(crtc, crtc_state);
2009 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
2013 for (i = 0; i < vop_data->win_size; i++) {
2014 const struct vop_win_data *win_data = &vop_data->win[i];
2015 struct vop_win *win;
2020 for (j = 0; j < vop->num_wins; j++) {
2023 if (win->win_id == i && !win->area_id)
2026 if (WARN_ON(j >= vop->num_wins)) {
2028 goto err_free_pzpos;
2032 pstate = state->plane_states[drm_plane_index(plane)];
2034 * plane might not have changed, in which case take
2038 pstate = plane->state;
2039 plane_state = to_vop_plane_state(pstate);
2040 pzpos[cnt].zpos = plane_state->zpos;
2041 pzpos[cnt++].win_id = win->win_id;
2044 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
2046 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
2047 const struct vop_win_data *win_data = &vop_data->win[i];
2050 if (win_data->phy) {
2051 struct vop_zpos *zpos = &pzpos[cnt++];
2053 dsp_layer_sel |= zpos->win_id << shift;
2055 dsp_layer_sel |= i << shift;
2059 s->dsp_layer_sel = dsp_layer_sel;
2061 vop_dclk_source_generate(crtc, crtc_state);
2068 static void vop_post_config(struct drm_crtc *crtc)
2070 struct vop *vop = to_vop(crtc);
2071 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2072 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2073 u16 vtotal = mode->crtc_vtotal;
2074 u16 hdisplay = mode->crtc_hdisplay;
2075 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2076 u16 vdisplay = mode->crtc_vdisplay;
2077 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2078 u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
2079 u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
2080 u16 hact_end, vact_end;
2083 hact_st += hdisplay * (100 - s->left_margin) / 200;
2084 hact_end = hact_st + hsize;
2085 val = hact_st << 16;
2087 VOP_CTRL_SET(vop, hpost_st_end, val);
2088 vact_st += vdisplay * (100 - s->top_margin) / 200;
2089 vact_end = vact_st + vsize;
2090 val = vact_st << 16;
2092 VOP_CTRL_SET(vop, vpost_st_end, val);
2093 val = scl_cal_scale2(vdisplay, vsize) << 16;
2094 val |= scl_cal_scale2(hdisplay, hsize);
2095 VOP_CTRL_SET(vop, post_scl_factor, val);
2097 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0)
2098 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1)
2099 VOP_CTRL_SET(vop, post_scl_ctrl,
2100 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) |
2101 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
2102 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2103 u16 vact_st_f1 = vtotal + vact_st + 1;
2104 u16 vact_end_f1 = vact_st_f1 + vsize;
2106 val = vact_st_f1 << 16 | vact_end_f1;
2107 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2111 static void vop_update_cabc_lut(struct drm_crtc *crtc,
2112 struct drm_crtc_state *old_crtc_state)
2114 struct rockchip_crtc_state *s =
2115 to_rockchip_crtc_state(crtc->state);
2116 struct rockchip_crtc_state *old_s =
2117 to_rockchip_crtc_state(old_crtc_state);
2118 struct drm_property_blob *cabc_lut = s->cabc_lut;
2119 struct drm_property_blob *old_cabc_lut = old_s->cabc_lut;
2120 struct vop *vop = to_vop(crtc);
2123 u32 lut_len = vop->cabc_lut_len;
2126 if (!cabc_lut && old_cabc_lut) {
2127 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2133 if (old_cabc_lut && old_cabc_lut->base.id == cabc_lut->base.id)
2136 lut = (u32 *)cabc_lut->data;
2137 lut_size = cabc_lut->length / sizeof(u32);
2138 if (WARN(lut_size != lut_len, "Unexpect cabc lut size not match\n"))
2141 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
2142 if (CTRL_GET(cabc_lut_en)) {
2143 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2145 readx_poll_timeout(CTRL_GET, cabc_lut_en, dle, !dle, 5, 33333);
2148 for (i = 0; i < lut_len; i++)
2149 vop_write_cabc_lut(vop, (i << 2), lut[i]);
2151 VOP_CTRL_SET(vop, cabc_lut_en, 1);
2154 static void vop_update_cabc(struct drm_crtc *crtc,
2155 struct drm_crtc_state *old_crtc_state)
2157 struct rockchip_crtc_state *s =
2158 to_rockchip_crtc_state(crtc->state);
2159 struct vop *vop = to_vop(crtc);
2160 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2161 int pixel_total = mode->hdisplay * mode->vdisplay;
2163 if (!vop->cabc_lut_regs)
2166 vop_update_cabc_lut(crtc, old_crtc_state);
2168 if (s->cabc_mode != ROCKCHIP_DRM_CABC_MODE_DISABLE) {
2169 VOP_CTRL_SET(vop, cabc_en, 1);
2170 VOP_CTRL_SET(vop, cabc_handle_en, 1);
2171 VOP_CTRL_SET(vop, cabc_stage_up, s->cabc_stage_up);
2172 VOP_CTRL_SET(vop, cabc_stage_down, s->cabc_stage_down);
2173 VOP_CTRL_SET(vop, cabc_global_dn, s->cabc_global_dn);
2174 VOP_CTRL_SET(vop, cabc_calc_pixel_num,
2175 s->cabc_calc_pixel_num * pixel_total / 1000);
2178 * There are some hardware issues on cabc disabling:
2179 * 1: if cabc auto gating enable, cabc disabling will cause
2181 * 2: cabc disabling always would make timing several
2182 * pixel cycle abnormal, cause some panel abnormal.
2184 * So just keep cabc enable, and make it no work with max
2185 * cabc_calc_pixel_num, it only has little power consume.
2187 VOP_CTRL_SET(vop, cabc_calc_pixel_num, pixel_total);
2191 static void vop_cfg_update(struct drm_crtc *crtc,
2192 struct drm_crtc_state *old_crtc_state)
2194 struct rockchip_crtc_state *s =
2195 to_rockchip_crtc_state(crtc->state);
2196 struct vop *vop = to_vop(crtc);
2198 spin_lock(&vop->reg_lock);
2203 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2204 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2205 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2206 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2207 pic_size = (s->afbdc_win_width & 0xffff);
2208 pic_size |= s->afbdc_win_height << 16;
2209 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2212 VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2213 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2214 vop_post_config(crtc);
2216 spin_unlock(&vop->reg_lock);
2219 static bool vop_fs_irq_is_pending(struct vop *vop)
2221 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
2224 static void vop_wait_for_irq_handler(struct vop *vop)
2230 * Spin until frame start interrupt status bit goes low, which means
2231 * that interrupt handler was invoked and cleared it. The timeout of
2232 * 10 msecs is really too long, but it is just a safety measure if
2233 * something goes really wrong. The wait will only happen in the very
2234 * unlikely case of a vblank happening exactly at the same time and
2235 * shouldn't exceed microseconds range.
2237 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
2238 !pending, 0, 10 * 1000);
2240 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
2242 synchronize_irq(vop->irq);
2245 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2246 struct drm_crtc_state *old_crtc_state)
2248 struct drm_atomic_state *old_state = old_crtc_state->state;
2249 struct drm_plane_state *old_plane_state;
2250 struct vop *vop = to_vop(crtc);
2251 struct drm_plane *plane;
2254 vop_cfg_update(crtc, old_crtc_state);
2256 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2257 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2260 if (need_wait_vblank) {
2263 disable_irq(vop->irq);
2264 drm_crtc_vblank_get(crtc);
2265 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2267 ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2268 vop, active, active,
2271 dev_err(vop->dev, "wait fs irq timeout\n");
2273 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2276 ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2277 vop, active, active,
2280 dev_err(vop->dev, "wait line flag timeout\n");
2282 enable_irq(vop->irq);
2284 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2286 dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2289 if (need_wait_vblank) {
2290 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2291 drm_crtc_vblank_put(crtc);
2294 vop->is_iommu_enabled = true;
2297 vop_update_cabc(crtc, old_crtc_state);
2302 * There is a (rather unlikely) possiblity that a vblank interrupt
2303 * fired before we set the cfg_done bit. To avoid spuriously
2304 * signalling flip completion we need to wait for it to finish.
2306 vop_wait_for_irq_handler(vop);
2308 spin_lock_irq(&crtc->dev->event_lock);
2309 if (crtc->state->event) {
2310 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2311 WARN_ON(vop->event);
2313 vop->event = crtc->state->event;
2314 crtc->state->event = NULL;
2316 spin_unlock_irq(&crtc->dev->event_lock);
2318 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
2319 if (!old_plane_state->fb)
2322 if (old_plane_state->fb == plane->state->fb)
2325 drm_framebuffer_reference(old_plane_state->fb);
2326 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2327 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
2328 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
2332 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2333 struct drm_crtc_state *old_crtc_state)
2337 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2338 .load_lut = vop_crtc_load_lut,
2339 .enable = vop_crtc_enable,
2340 .disable = vop_crtc_disable,
2341 .mode_fixup = vop_crtc_mode_fixup,
2342 .atomic_check = vop_crtc_atomic_check,
2343 .atomic_flush = vop_crtc_atomic_flush,
2344 .atomic_begin = vop_crtc_atomic_begin,
2347 static void vop_crtc_destroy(struct drm_crtc *crtc)
2349 drm_crtc_cleanup(crtc);
2352 static void vop_crtc_reset(struct drm_crtc *crtc)
2354 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2357 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2361 s = kzalloc(sizeof(*s), GFP_KERNEL);
2364 crtc->state = &s->base;
2365 crtc->state->crtc = crtc;
2367 s->left_margin = 100;
2368 s->right_margin = 100;
2369 s->top_margin = 100;
2370 s->bottom_margin = 100;
2373 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2375 struct rockchip_crtc_state *rockchip_state, *old_state;
2377 old_state = to_rockchip_crtc_state(crtc->state);
2378 rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2379 if (!rockchip_state)
2382 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2383 return &rockchip_state->base;
2386 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2387 struct drm_crtc_state *state)
2389 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2391 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2395 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2396 const struct drm_crtc_state *state,
2397 struct drm_property *property,
2400 struct drm_device *drm_dev = crtc->dev;
2401 struct rockchip_drm_private *private = drm_dev->dev_private;
2402 struct drm_mode_config *mode_config = &drm_dev->mode_config;
2403 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2405 if (property == mode_config->tv_left_margin_property) {
2406 *val = s->left_margin;
2410 if (property == mode_config->tv_right_margin_property) {
2411 *val = s->right_margin;
2415 if (property == mode_config->tv_top_margin_property) {
2416 *val = s->top_margin;
2420 if (property == mode_config->tv_bottom_margin_property) {
2421 *val = s->bottom_margin;
2425 if (property == private->cabc_mode_property) {
2426 *val = s->cabc_mode;
2430 if (property == private->cabc_stage_up_property) {
2431 *val = s->cabc_stage_up;
2435 if (property == private->cabc_stage_down_property) {
2436 *val = s->cabc_stage_down;
2440 if (property == private->cabc_global_dn_property) {
2441 *val = s->cabc_global_dn;
2445 if (property == private->cabc_calc_pixel_num_property) {
2446 *val = s->cabc_calc_pixel_num;
2450 if (property == private->cabc_lut_property) {
2451 *val = s->cabc_lut ? s->cabc_lut->base.id : 0;
2455 DRM_ERROR("failed to get vop crtc property\n");
2459 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2460 struct drm_crtc_state *state,
2461 struct drm_property *property,
2464 struct drm_device *drm_dev = crtc->dev;
2465 struct rockchip_drm_private *private = drm_dev->dev_private;
2466 struct drm_mode_config *mode_config = &drm_dev->mode_config;
2467 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2468 struct vop *vop = to_vop(crtc);
2470 if (property == mode_config->tv_left_margin_property) {
2471 s->left_margin = val;
2475 if (property == mode_config->tv_right_margin_property) {
2476 s->right_margin = val;
2480 if (property == mode_config->tv_top_margin_property) {
2481 s->top_margin = val;
2485 if (property == mode_config->tv_bottom_margin_property) {
2486 s->bottom_margin = val;
2490 if (property == private->cabc_mode_property) {
2493 * Pre-define lowpower and normal mode to make cabc
2496 if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_NORMAL) {
2497 s->cabc_stage_up = 257;
2498 s->cabc_stage_down = 255;
2499 s->cabc_global_dn = 192;
2500 s->cabc_calc_pixel_num = 995;
2501 } else if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_LOWPOWER) {
2502 s->cabc_stage_up = 260;
2503 s->cabc_stage_down = 252;
2504 s->cabc_global_dn = 180;
2505 s->cabc_calc_pixel_num = 992;
2510 if (property == private->cabc_stage_up_property) {
2511 s->cabc_stage_up = val;
2515 if (property == private->cabc_stage_down_property) {
2516 s->cabc_stage_down = val;
2520 if (property == private->cabc_calc_pixel_num_property) {
2521 s->cabc_calc_pixel_num = val;
2525 if (property == private->cabc_global_dn_property) {
2526 s->cabc_global_dn = val;
2530 if (property == private->cabc_lut_property) {
2532 ssize_t size = vop->cabc_lut_len * 4;
2534 return drm_atomic_replace_property_blob_from_id(crtc,
2541 DRM_ERROR("failed to set vop crtc property\n");
2545 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2546 u16 *blue, uint32_t start, uint32_t size)
2548 struct vop *vop = to_vop(crtc);
2549 int end = min_t(u32, start + size, vop->lut_len);
2555 for (i = start; i < end; i++)
2556 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2559 vop_crtc_load_lut(crtc);
2562 static const struct drm_crtc_funcs vop_crtc_funcs = {
2563 .gamma_set = vop_crtc_gamma_set,
2564 .set_config = drm_atomic_helper_set_config,
2565 .page_flip = drm_atomic_helper_page_flip,
2566 .destroy = vop_crtc_destroy,
2567 .reset = vop_crtc_reset,
2568 .set_property = drm_atomic_helper_crtc_set_property,
2569 .atomic_get_property = vop_crtc_atomic_get_property,
2570 .atomic_set_property = vop_crtc_atomic_set_property,
2571 .atomic_duplicate_state = vop_crtc_duplicate_state,
2572 .atomic_destroy_state = vop_crtc_destroy_state,
2575 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
2577 struct vop *vop = container_of(work, struct vop, fb_unref_work);
2578 struct drm_framebuffer *fb = val;
2580 drm_crtc_vblank_put(&vop->crtc);
2581 drm_framebuffer_unreference(fb);
2584 static void vop_handle_vblank(struct vop *vop)
2586 struct drm_device *drm = vop->drm_dev;
2587 struct drm_crtc *crtc = &vop->crtc;
2588 unsigned long flags;
2591 spin_lock_irqsave(&drm->event_lock, flags);
2593 drm_crtc_send_vblank_event(crtc, vop->event);
2594 drm_crtc_vblank_put(crtc);
2597 spin_unlock_irqrestore(&drm->event_lock, flags);
2600 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
2601 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2604 static irqreturn_t vop_isr(int irq, void *data)
2606 struct vop *vop = data;
2607 struct drm_crtc *crtc = &vop->crtc;
2608 uint32_t active_irqs;
2609 unsigned long flags;
2613 * interrupt register has interrupt status, enable and clear bits, we
2614 * must hold irq_lock to avoid a race with enable/disable_vblank().
2616 spin_lock_irqsave(&vop->irq_lock, flags);
2618 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2619 /* Clear all active interrupt sources */
2621 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2623 spin_unlock_irqrestore(&vop->irq_lock, flags);
2625 /* This is expected for vop iommu irqs, since the irq is shared */
2629 if (active_irqs & DSP_HOLD_VALID_INTR) {
2630 complete(&vop->dsp_hold_completion);
2631 active_irqs &= ~DSP_HOLD_VALID_INTR;
2635 if (active_irqs & LINE_FLAG_INTR) {
2636 complete(&vop->line_flag_completion);
2637 active_irqs &= ~LINE_FLAG_INTR;
2641 if (active_irqs & FS_INTR) {
2642 drm_crtc_handle_vblank(crtc);
2643 vop_handle_vblank(vop);
2644 active_irqs &= ~FS_INTR;
2648 #define ERROR_HANDLER(x) \
2650 if (active_irqs & x##_INTR) {\
2651 DRM_DEV_ERROR_RATELIMITED(vop->dev, #x " irq err\n"); \
2652 active_irqs &= ~x##_INTR; \
2653 ret = IRQ_HANDLED; \
2657 ERROR_HANDLER(BUS_ERROR);
2658 ERROR_HANDLER(WIN0_EMPTY);
2659 ERROR_HANDLER(WIN1_EMPTY);
2660 ERROR_HANDLER(WIN2_EMPTY);
2661 ERROR_HANDLER(WIN3_EMPTY);
2662 ERROR_HANDLER(HWC_EMPTY);
2663 ERROR_HANDLER(POST_BUF_EMPTY);
2665 /* Unhandled irqs are spurious. */
2667 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2672 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2673 unsigned long possible_crtcs)
2675 struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2676 struct drm_plane *share = NULL;
2677 unsigned int rotations = 0;
2678 struct drm_property *prop;
2679 uint64_t feature = 0;
2683 share = &win->parent->base;
2685 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2686 possible_crtcs, &vop_plane_funcs,
2687 win->data_formats, win->nformats, win->type);
2689 DRM_ERROR("failed to initialize plane\n");
2692 drm_plane_helper_add(&win->base, &plane_helper_funcs);
2693 drm_object_attach_property(&win->base.base,
2694 vop->plane_zpos_prop, win->win_id);
2696 if (VOP_WIN_SUPPORT(vop, win, xmirror))
2697 rotations |= BIT(DRM_REFLECT_X);
2699 if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2700 rotations |= BIT(DRM_REFLECT_Y);
2702 prop = drm_property_create_bool(vop->drm_dev,
2703 DRM_MODE_PROP_ATOMIC,
2707 private->logo_ymirror_prop = prop;
2711 rotations |= BIT(DRM_ROTATE_0);
2712 prop = drm_mode_create_rotation_property(vop->drm_dev,
2715 DRM_ERROR("failed to create zpos property\n");
2718 drm_object_attach_property(&win->base.base, prop,
2720 win->rotation_prop = prop;
2723 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2724 if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2725 VOP_WIN_SUPPORT(vop, win, alpha_en))
2726 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2728 drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2734 static int vop_create_crtc(struct vop *vop)
2736 struct device *dev = vop->dev;
2737 const struct vop_data *vop_data = vop->data;
2738 struct drm_device *drm_dev = vop->drm_dev;
2739 struct rockchip_drm_private *private = drm_dev->dev_private;
2740 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2741 struct drm_crtc *crtc = &vop->crtc;
2742 struct device_node *port;
2743 uint64_t feature = 0;
2748 * Create drm_plane for primary and cursor planes first, since we need
2749 * to pass them to drm_crtc_init_with_planes, which sets the
2750 * "possible_crtcs" to the newly initialized crtc.
2752 for (i = 0; i < vop->num_wins; i++) {
2753 struct vop_win *win = &vop->win[i];
2755 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2756 win->type != DRM_PLANE_TYPE_CURSOR)
2759 ret = vop_plane_init(vop, win, 0);
2761 goto err_cleanup_planes;
2764 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2766 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2771 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2772 &vop_crtc_funcs, NULL);
2774 goto err_cleanup_planes;
2776 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2779 * Create drm_planes for overlay windows with possible_crtcs restricted
2780 * to the newly created crtc.
2782 for (i = 0; i < vop->num_wins; i++) {
2783 struct vop_win *win = &vop->win[i];
2784 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2786 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2789 ret = vop_plane_init(vop, win, possible_crtcs);
2791 goto err_cleanup_crtc;
2794 port = of_get_child_by_name(dev->of_node, "port");
2796 DRM_ERROR("no port node found in %s\n",
2797 dev->of_node->full_name);
2799 goto err_cleanup_crtc;
2802 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
2803 vop_fb_unref_worker);
2805 init_completion(&vop->dsp_hold_completion);
2806 init_completion(&vop->line_flag_completion);
2808 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2810 ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2812 goto err_unregister_crtc_funcs;
2813 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2814 drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2816 VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2817 VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2818 VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2819 VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2821 #undef VOP_ATTACH_MODE_CONFIG_PROP
2823 drm_object_attach_property(&crtc->base, private->cabc_lut_property, 0);
2824 drm_object_attach_property(&crtc->base, private->cabc_mode_property, 0);
2825 drm_object_attach_property(&crtc->base, private->cabc_stage_up_property, 0);
2826 drm_object_attach_property(&crtc->base, private->cabc_stage_down_property, 0);
2827 drm_object_attach_property(&crtc->base, private->cabc_global_dn_property, 0);
2828 drm_object_attach_property(&crtc->base, private->cabc_calc_pixel_num_property, 0);
2830 if (vop_data->feature & VOP_FEATURE_AFBDC)
2831 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2832 drm_object_attach_property(&crtc->base, vop->feature_prop,
2834 if (vop->lut_regs) {
2835 u16 *r_base, *g_base, *b_base;
2836 u32 lut_len = vop->lut_len;
2838 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2839 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2844 r_base = crtc->gamma_store;
2845 g_base = r_base + crtc->gamma_size;
2846 b_base = g_base + crtc->gamma_size;
2848 for (i = 0; i < lut_len; i++) {
2849 vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2850 rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2851 &g_base[i], &b_base[i],
2858 err_unregister_crtc_funcs:
2859 rockchip_unregister_crtc_funcs(crtc);
2861 drm_crtc_cleanup(crtc);
2863 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2865 drm_plane_cleanup(plane);
2869 static void vop_destroy_crtc(struct vop *vop)
2871 struct drm_crtc *crtc = &vop->crtc;
2872 struct drm_device *drm_dev = vop->drm_dev;
2873 struct drm_plane *plane, *tmp;
2875 rockchip_unregister_crtc_funcs(crtc);
2876 of_node_put(crtc->port);
2879 * We need to cleanup the planes now. Why?
2881 * The planes are "&vop->win[i].base". That means the memory is
2882 * all part of the big "struct vop" chunk of memory. That memory
2883 * was devm allocated and associated with this component. We need to
2884 * free it ourselves before vop_unbind() finishes.
2886 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2888 vop_plane_destroy(plane);
2891 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2892 * references the CRTC.
2894 drm_crtc_cleanup(crtc);
2895 drm_flip_work_cleanup(&vop->fb_unref_work);
2899 * Initialize the vop->win array elements.
2901 static int vop_win_init(struct vop *vop)
2903 const struct vop_data *vop_data = vop->data;
2905 unsigned int num_wins = 0;
2906 struct drm_property *prop;
2907 static const struct drm_prop_enum_list props[] = {
2908 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2909 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2911 static const struct drm_prop_enum_list crtc_props[] = {
2912 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2915 for (i = 0; i < vop_data->win_size; i++) {
2916 struct vop_win *vop_win = &vop->win[num_wins];
2917 const struct vop_win_data *win_data = &vop_data->win[i];
2922 vop_win->phy = win_data->phy;
2923 vop_win->csc = win_data->csc;
2924 vop_win->offset = win_data->base;
2925 vop_win->type = win_data->type;
2926 vop_win->data_formats = win_data->phy->data_formats;
2927 vop_win->nformats = win_data->phy->nformats;
2929 vop_win->win_id = i;
2930 vop_win->area_id = 0;
2933 for (j = 0; j < win_data->area_size; j++) {
2934 struct vop_win *vop_area = &vop->win[num_wins];
2935 const struct vop_win_phy *area = win_data->area[j];
2937 vop_area->parent = vop_win;
2938 vop_area->offset = vop_win->offset;
2939 vop_area->phy = area;
2940 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2941 vop_area->data_formats = vop_win->data_formats;
2942 vop_area->nformats = vop_win->nformats;
2943 vop_area->vop = vop;
2944 vop_area->win_id = i;
2945 vop_area->area_id = j;
2950 vop->num_wins = num_wins;
2952 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2953 "ZPOS", 0, vop->data->win_size);
2955 DRM_ERROR("failed to create zpos property\n");
2958 vop->plane_zpos_prop = prop;
2960 vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2961 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2962 props, ARRAY_SIZE(props),
2963 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2964 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2965 if (!vop->plane_feature_prop) {
2966 DRM_ERROR("failed to create feature property\n");
2970 vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2971 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2972 crtc_props, ARRAY_SIZE(crtc_props),
2973 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2974 if (!vop->feature_prop) {
2975 DRM_ERROR("failed to create vop feature property\n");
2983 * rockchip_drm_wait_line_flag - acqiure the give line flag event
2984 * @crtc: CRTC to enable line flag
2985 * @line_num: interested line number
2986 * @mstimeout: millisecond for timeout
2988 * Driver would hold here until the interested line flag interrupt have
2989 * happened or timeout to wait.
2992 * Zero on success, negative errno on failure.
2994 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2995 unsigned int mstimeout)
2997 struct vop *vop = to_vop(crtc);
2998 unsigned long jiffies_left;
3001 if (!crtc || !vop->is_enabled)
3004 mutex_lock(&vop->vop_lock);
3006 if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
3011 if (vop_line_flag_irq_is_enabled(vop)) {
3016 reinit_completion(&vop->line_flag_completion);
3017 vop_line_flag_irq_enable(vop, line_num);
3019 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
3020 msecs_to_jiffies(mstimeout));
3021 vop_line_flag_irq_disable(vop);
3023 if (jiffies_left == 0) {
3024 dev_err(vop->dev, "Timeout waiting for IRQ\n");
3030 mutex_unlock(&vop->vop_lock);
3034 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
3036 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
3039 struct vop *vop = container_of(nb, struct vop, dmc_nb);
3041 if (event == DEVFREQ_PRECHANGE)
3042 mutex_lock(&vop->vop_lock);
3043 else if (event == DEVFREQ_POSTCHANGE)
3044 mutex_unlock(&vop->vop_lock);
3049 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
3053 mutex_lock(®ister_devfreq_lock);
3055 devfreq_vop = devfreq;
3057 for (i = 0; i < ARRAY_SIZE(dmc_vop); i++) {
3060 dmc_vop[i]->dmc_nb.notifier_call = dmc_notifier_call;
3061 devfreq_register_notifier(devfreq_vop, &dmc_vop[i]->dmc_nb,
3062 DEVFREQ_TRANSITION_NOTIFIER);
3066 mutex_unlock(®ister_devfreq_lock);
3073 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
3075 static void vop_backlight_config_done(struct device *dev, bool async)
3077 struct vop *vop = dev_get_drvdata(dev);
3079 if (vop && vop->is_enabled) {
3084 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
3085 readx_poll_timeout(CTRL_GET, cfg_done,
3086 dle, !dle, 5, 33333);
3092 static const struct rockchip_sub_backlight_ops rockchip_sub_backlight_ops = {
3093 .config_done = vop_backlight_config_done,
3096 static int vop_bind(struct device *dev, struct device *master, void *data)
3098 struct platform_device *pdev = to_platform_device(dev);
3099 const struct vop_data *vop_data;
3100 struct drm_device *drm_dev = data;
3102 struct resource *res;
3107 vop_data = of_device_get_match_data(dev);
3111 for (i = 0; i < vop_data->win_size; i++) {
3112 const struct vop_win_data *win_data = &vop_data->win[i];
3114 num_wins += win_data->area_size + 1;
3117 /* Allocate vop struct and its vop_win array */
3118 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
3119 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3124 vop->data = vop_data;
3125 vop->drm_dev = drm_dev;
3126 vop->num_wins = num_wins;
3127 dev_set_drvdata(dev, vop);
3129 ret = vop_win_init(vop);
3133 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3135 dev_warn(vop->dev, "failed to get vop register byname\n");
3136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3138 vop->regs = devm_ioremap_resource(dev, res);
3139 if (IS_ERR(vop->regs))
3140 return PTR_ERR(vop->regs);
3141 vop->len = resource_size(res);
3143 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
3147 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
3148 vop->lut_regs = devm_ioremap_resource(dev, res);
3149 if (IS_ERR(vop->lut_regs)) {
3150 dev_warn(vop->dev, "failed to get vop lut registers\n");
3151 vop->lut_regs = NULL;
3153 if (vop->lut_regs) {
3154 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
3155 if (vop->lut_len != 256 && vop->lut_len != 1024) {
3156 dev_err(vop->dev, "unsupport lut sizes %d\n",
3162 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cabc_lut");
3163 vop->cabc_lut_regs = devm_ioremap_resource(dev, res);
3164 if (IS_ERR(vop->cabc_lut_regs)) {
3165 dev_warn(vop->dev, "failed to get vop cabc lut registers\n");
3166 vop->cabc_lut_regs = NULL;
3169 if (vop->cabc_lut_regs) {
3170 vop->cabc_lut_len = resource_size(res) >> 2;
3171 if (vop->cabc_lut_len != 128) {
3172 dev_err(vop->dev, "unsupport cabc lut sizes %d\n",
3178 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
3179 if (IS_ERR(vop->hclk)) {
3180 dev_err(vop->dev, "failed to get hclk source\n");
3181 return PTR_ERR(vop->hclk);
3183 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
3184 if (IS_ERR(vop->aclk)) {
3185 dev_err(vop->dev, "failed to get aclk source\n");
3186 return PTR_ERR(vop->aclk);
3188 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
3189 if (IS_ERR(vop->dclk)) {
3190 dev_err(vop->dev, "failed to get dclk source\n");
3191 return PTR_ERR(vop->dclk);
3194 vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
3195 if (PTR_ERR(vop->dclk_source) == -ENOENT) {
3196 vop->dclk_source = NULL;
3197 } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
3198 return -EPROBE_DEFER;
3199 } else if (IS_ERR(vop->dclk_source)) {
3200 dev_err(vop->dev, "failed to get dclk source parent\n");
3201 return PTR_ERR(vop->dclk_source);
3204 irq = platform_get_irq(pdev, 0);
3206 dev_err(dev, "cannot find irq for vop\n");
3209 vop->irq = (unsigned int)irq;
3211 spin_lock_init(&vop->reg_lock);
3212 spin_lock_init(&vop->irq_lock);
3213 mutex_init(&vop->vop_lock);
3215 mutex_init(&vop->vsync_mutex);
3217 ret = devm_request_irq(dev, vop->irq, vop_isr,
3218 IRQF_SHARED, dev_name(dev), vop);
3222 /* IRQ is initially disabled; it gets enabled in power_on */
3223 disable_irq(vop->irq);
3225 ret = vop_create_crtc(vop);
3229 pm_runtime_enable(&pdev->dev);
3231 of_rockchip_drm_sub_backlight_register(dev, &vop->crtc,
3232 &rockchip_sub_backlight_ops);
3234 mutex_lock(®ister_devfreq_lock);
3236 for (i = 0; i < ARRAY_SIZE(dmc_vop); i++) {
3240 vop->dmc_nb.notifier_call = dmc_notifier_call;
3241 devfreq_register_notifier(devfreq_vop,
3243 DEVFREQ_TRANSITION_NOTIFIER);
3249 mutex_unlock(®ister_devfreq_lock);
3254 static void vop_unbind(struct device *dev, struct device *master, void *data)
3256 struct vop *vop = dev_get_drvdata(dev);
3259 mutex_lock(®ister_devfreq_lock);
3261 for (i = 0; i < ARRAY_SIZE(dmc_vop); i++) {
3262 if (dmc_vop[i] != vop)
3268 devfreq_unregister_notifier(devfreq_vop,
3270 DEVFREQ_TRANSITION_NOTIFIER);
3274 mutex_unlock(®ister_devfreq_lock);
3276 pm_runtime_disable(dev);
3277 vop_destroy_crtc(vop);
3280 const struct component_ops vop_component_ops = {
3282 .unbind = vop_unbind,
3284 EXPORT_SYMBOL_GPL(vop_component_ops);