drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22
  23 #include <linux/devfreq.h>
  24 #include <linux/iopoll.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/iopoll.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/component.h>
  34
  35 #include <linux/reset.h>
  36 #include <linux/delay.h>
  37 #include <linux/sort.h>
  38 #include <uapi/drm/rockchip_drm.h>
  39
  40 #include "rockchip_drm_drv.h"
  41 #include "rockchip_drm_gem.h"
  42 #include "rockchip_drm_fb.h"
  43 #include "rockchip_drm_vop.h"
  44 #include "rockchip_drm_backlight.h"
  45
  46 #define VOP_REG_SUPPORT(vop, reg) \
  47                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  48                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  49                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  50                 reg.mask))
  51
  52 #define VOP_WIN_SUPPORT(vop, win, name) \
  53                 VOP_REG_SUPPORT(vop, win->phy->name)
  54
  55 #define VOP_CTRL_SUPPORT(vop, name) \
  56                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  57
  58 #define VOP_INTR_SUPPORT(vop, name) \
  59                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  60
  61 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  62                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  63
  64 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  65         do { \
  66                 if (VOP_REG_SUPPORT(vop, reg)) \
  67                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  68                                   v, reg.write_mask, relaxed); \
  69                 else \
  70                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  71         } while(0)
  72
  73 #define REG_SET(x, name, off, reg, v, relaxed) \
  74                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  75 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  76                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  77
  78 #define VOP_WIN_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  80 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  81                 REG_SET(x, name, 0, win->ext->name, v, true)
  82 #define VOP_SCL_SET(x, win, name, v) \
  83                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  84 #define VOP_SCL_SET_EXT(x, win, name, v) \
  85                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  86
  87 #define VOP_CTRL_SET(x, name, v) \
  88                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  89
  90 #define VOP_INTR_GET(vop, name) \
  91                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  92
  93 #define VOP_INTR_SET(vop, name, v) \
  94                 REG_SET(vop, name, 0, vop->data->intr->name, \
  95                         v, false)
  96 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  97                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  98                              mask, v, false)
  99
 100 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
 101         do { \
 102                 int i, reg = 0, mask = 0; \
 103                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 104                         if (vop->data->intr->intrs[i] & type) { \
 105                                 reg |= (v) << i; \
 106                                 mask |= 1 << i; \
 107                         } \
 108                 } \
 109                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 110         } while (0)
 111 #define VOP_INTR_GET_TYPE(vop, name, type) \
 112                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 113
 114 #define VOP_CTRL_GET(x, name) \
 115                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 116
 117 #define VOP_WIN_GET(x, win, name) \
 118                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 119
 120 #define VOP_WIN_NAME(win, name) \
 121                 (vop_get_win_phy(win, &win->phy->name)->name)
 122
 123 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 124                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 125
 126 #define to_vop(x) container_of(x, struct vop, crtc)
 127 #define to_vop_win(x) container_of(x, struct vop_win, base)
 128 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 129
 130 struct vop_zpos {
 131         int win_id;
 132         int zpos;
 133 };
 134
 135 enum vop_pending {
 136         VOP_PENDING_FB_UNREF,
 137 };
 138
 139 struct vop_plane_state {
 140         struct drm_plane_state base;
 141         int format;
 142         int zpos;
 143         unsigned int logo_ymirror;
 144         struct drm_rect src;
 145         struct drm_rect dest;
 146         dma_addr_t yrgb_mst;
 147         dma_addr_t uv_mst;
 148         const uint32_t *y2r_table;
 149         const uint32_t *r2r_table;
 150         const uint32_t *r2y_table;
 151         bool enable;
 152 };
 153
 154 struct vop_win {
 155         struct vop_win *parent;
 156         struct drm_plane base;
 157
 158         int win_id;
 159         int area_id;
 160         uint32_t offset;
 161         enum drm_plane_type type;
 162         const struct vop_win_phy *phy;
 163         const struct vop_csc *csc;
 164         const uint32_t *data_formats;
 165         uint32_t nformats;
 166         struct vop *vop;
 167
 168         struct drm_property *rotation_prop;
 169         struct vop_plane_state state;
 170 };
 171
 172 struct vop {
 173         struct drm_crtc crtc;
 174         struct device *dev;
 175         struct drm_device *drm_dev;
 176         struct drm_property *plane_zpos_prop;
 177         struct drm_property *plane_feature_prop;
 178         struct drm_property *feature_prop;
 179         bool is_iommu_enabled;
 180         bool is_iommu_needed;
 181         bool is_enabled;
 182
 183         /* mutex vsync_ work */
 184         struct mutex vsync_mutex;
 185         bool vsync_work_pending;
 186         bool loader_protect;
 187         struct completion dsp_hold_completion;
 188
 189         /* protected by dev->event_lock */
 190         struct drm_pending_vblank_event *event;
 191
 192         struct drm_flip_work fb_unref_work;
 193         unsigned long pending;
 194
 195         struct completion line_flag_completion;
 196
 197         const struct vop_data *data;
 198         int num_wins;
 199
 200         uint32_t *regsbak;
 201         void __iomem *regs;
 202
 203         /* physical map length of vop register */
 204         uint32_t len;
 205
 206         void __iomem *lut_regs;
 207         u32 *lut;
 208         u32 lut_len;
 209         bool lut_active;
 210         void __iomem *cabc_lut_regs;
 211         u32 cabc_lut_len;
 212
 213         /* one time only one process allowed to config the register */
 214         spinlock_t reg_lock;
 215         /* lock vop irq reg */
 216         spinlock_t irq_lock;
 217         /* mutex vop enable and disable */
 218         struct mutex vop_lock;
 219
 220         unsigned int irq;
 221
 222         /* vop AHP clk */
 223         struct clk *hclk;
 224         /* vop dclk */
 225         struct clk *dclk;
 226         /* vop share memory frequency */
 227         struct clk *aclk;
 228         /* vop source handling, optional */
 229         struct clk *dclk_source;
 230
 231         /* vop dclk reset */
 232         struct reset_control *dclk_rst;
 233
 234         struct devfreq *devfreq;
 235         struct notifier_block dmc_nb;
 236
 237         struct vop_win win[];
 238 };
 239
 240 struct vop *dmc_vop;
 241
 242 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 243 {
 244         writel(v, vop->regs + offset);
 245         vop->regsbak[offset >> 2] = v;
 246 }
 247
 248 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 249 {
 250         return readl(vop->regs + offset);
 251 }
 252
 253 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 254                                     const struct vop_reg *reg)
 255 {
 256         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 257 }
 258
 259 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 260                                   uint32_t mask, uint32_t shift, uint32_t v,
 261                                   bool write_mask, bool relaxed)
 262 {
 263         if (!mask)
 264                 return;
 265
 266         if (write_mask) {
 267                 v = ((v & mask) << shift) | (mask << (shift + 16));
 268         } else {
 269                 uint32_t cached_val = vop->regsbak[offset >> 2];
 270
 271                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 272                 vop->regsbak[offset >> 2] = v;
 273         }
 274
 275         if (relaxed)
 276                 writel_relaxed(v, vop->regs + offset);
 277         else
 278                 writel(v, vop->regs + offset);
 279 }
 280
 281 static inline const struct vop_win_phy *
 282 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 283 {
 284         if (!reg->mask && win->parent)
 285                 return win->parent->phy;
 286
 287         return win->phy;
 288 }
 289
 290 static inline uint32_t vop_get_intr_type(struct vop *vop,
 291                                          const struct vop_reg *reg, int type)
 292 {
 293         uint32_t i, ret = 0;
 294         uint32_t regs = vop_read_reg(vop, 0, reg);
 295
 296         for (i = 0; i < vop->data->intr->nintrs; i++) {
 297                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 298                         ret |= vop->data->intr->intrs[i];
 299         }
 300
 301         return ret;
 302 }
 303
 304 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 305 {
 306         int i;
 307
 308         if (!table)
 309                 return;
 310
 311         for (i = 0; i < 8; i++)
 312                 vop_writel(vop, offset + i * 4, table[i]);
 313 }
 314
 315 static inline void vop_cfg_done(struct vop *vop)
 316 {
 317         VOP_CTRL_SET(vop, cfg_done, 1);
 318 }
 319
 320 static bool vop_is_allwin_disabled(struct vop *vop)
 321 {
 322         int i;
 323
 324         for (i = 0; i < vop->num_wins; i++) {
 325                 struct vop_win *win = &vop->win[i];
 326
 327                 if (VOP_WIN_GET(vop, win, enable) != 0)
 328                         return false;
 329         }
 330
 331         return true;
 332 }
 333
 334 static bool vop_is_cfg_done_complete(struct vop *vop)
 335 {
 336         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 337 }
 338
 339 static bool vop_fs_irq_is_active(struct vop *vop)
 340 {
 341         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 342 }
 343
 344 static bool vop_line_flag_is_active(struct vop *vop)
 345 {
 346         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 347 }
 348
 349 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 350 {
 351         writel(v, vop->lut_regs + offset);
 352 }
 353
 354 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 355 {
 356         return readl(vop->lut_regs + offset);
 357 }
 358
 359 static inline void vop_write_cabc_lut(struct vop *vop, uint32_t offset, uint32_t v)
 360 {
 361         writel(v, vop->cabc_lut_regs + offset);
 362 }
 363
 364 static bool has_rb_swapped(uint32_t format)
 365 {
 366         switch (format) {
 367         case DRM_FORMAT_XBGR8888:
 368         case DRM_FORMAT_ABGR8888:
 369         case DRM_FORMAT_BGR888:
 370         case DRM_FORMAT_BGR565:
 371                 return true;
 372         default:
 373                 return false;
 374         }
 375 }
 376
 377 static enum vop_data_format vop_convert_format(uint32_t format)
 378 {
 379         switch (format) {
 380         case DRM_FORMAT_XRGB8888:
 381         case DRM_FORMAT_ARGB8888:
 382         case DRM_FORMAT_XBGR8888:
 383         case DRM_FORMAT_ABGR8888:
 384                 return VOP_FMT_ARGB8888;
 385         case DRM_FORMAT_RGB888:
 386         case DRM_FORMAT_BGR888:
 387                 return VOP_FMT_RGB888;
 388         case DRM_FORMAT_RGB565:
 389         case DRM_FORMAT_BGR565:
 390                 return VOP_FMT_RGB565;
 391         case DRM_FORMAT_NV12:
 392         case DRM_FORMAT_NV12_10:
 393                 return VOP_FMT_YUV420SP;
 394         case DRM_FORMAT_NV16:
 395         case DRM_FORMAT_NV16_10:
 396                 return VOP_FMT_YUV422SP;
 397         case DRM_FORMAT_NV24:
 398         case DRM_FORMAT_NV24_10:
 399                 return VOP_FMT_YUV444SP;
 400         default:
 401                 DRM_ERROR("unsupport format[%08x]\n", format);
 402                 return -EINVAL;
 403         }
 404 }
 405
 406 static bool is_yuv_output(uint32_t bus_format)
 407 {
 408         switch (bus_format) {
 409         case MEDIA_BUS_FMT_YUV8_1X24:
 410         case MEDIA_BUS_FMT_YUV10_1X30:
 411         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 412         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 413                 return true;
 414         default:
 415                 return false;
 416         }
 417 }
 418
 419 static bool is_yuv_support(uint32_t format)
 420 {
 421         switch (format) {
 422         case DRM_FORMAT_NV12:
 423         case DRM_FORMAT_NV12_10:
 424         case DRM_FORMAT_NV16:
 425         case DRM_FORMAT_NV16_10:
 426         case DRM_FORMAT_NV24:
 427         case DRM_FORMAT_NV24_10:
 428                 return true;
 429         default:
 430                 return false;
 431         }
 432 }
 433
 434 static bool is_yuv_10bit(uint32_t format)
 435 {
 436         switch (format) {
 437         case DRM_FORMAT_NV12_10:
 438         case DRM_FORMAT_NV16_10:
 439         case DRM_FORMAT_NV24_10:
 440                 return true;
 441         default:
 442                 return false;
 443         }
 444 }
 445
 446 static bool is_alpha_support(uint32_t format)
 447 {
 448         switch (format) {
 449         case DRM_FORMAT_ARGB8888:
 450         case DRM_FORMAT_ABGR8888:
 451                 return true;
 452         default:
 453                 return false;
 454         }
 455 }
 456
 457 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 458                                   uint32_t dst, bool is_horizontal,
 459                                   int vsu_mode, int *vskiplines)
 460 {
 461         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 462
 463         if (is_horizontal) {
 464                 if (mode == SCALE_UP)
 465                         val = GET_SCL_FT_BIC(src, dst);
 466                 else if (mode == SCALE_DOWN)
 467                         val = GET_SCL_FT_BILI_DN(src, dst);
 468         } else {
 469                 if (mode == SCALE_UP) {
 470                         if (vsu_mode == SCALE_UP_BIL)
 471                                 val = GET_SCL_FT_BILI_UP(src, dst);
 472                         else
 473                                 val = GET_SCL_FT_BIC(src, dst);
 474                 } else if (mode == SCALE_DOWN) {
 475                         if (vskiplines) {
 476                                 *vskiplines = scl_get_vskiplines(src, dst);
 477                                 val = scl_get_bili_dn_vskip(src, dst,
 478                                                             *vskiplines);
 479                         } else {
 480                                 val = GET_SCL_FT_BILI_DN(src, dst);
 481                         }
 482                 }
 483         }
 484
 485         return val;
 486 }
 487
 488 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 489                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 490                                 uint32_t dst_h, uint32_t pixel_format)
 491 {
 492         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 493         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 494         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 495         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 496         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 497         bool is_yuv = is_yuv_support(pixel_format);
 498         uint16_t cbcr_src_w = src_w / hsub;
 499         uint16_t cbcr_src_h = src_h / vsub;
 500         uint16_t vsu_mode;
 501         uint16_t lb_mode;
 502         uint32_t val;
 503         int vskiplines = 0;
 504
 505         if (!win->phy->scl)
 506                 return;
 507
 508         if (!win->phy->scl->ext) {
 509                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 510                             scl_cal_scale2(src_w, dst_w));
 511                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 512                             scl_cal_scale2(src_h, dst_h));
 513                 if (is_yuv) {
 514                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 515                                     scl_cal_scale2(cbcr_src_w, dst_w));
 516                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 517                                     scl_cal_scale2(cbcr_src_h, dst_h));
 518                 }
 519                 return;
 520         }
 521
 522         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 523         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 524
 525         if (is_yuv) {
 526                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 527                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 528                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 529                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 530                 else
 531                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 532         } else {
 533                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 534                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 535                 else
 536                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 537         }
 538
 539         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 540         if (lb_mode == LB_RGB_3840X2) {
 541                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 542                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 543                         return;
 544                 }
 545                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 546                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 547                         return;
 548                 }
 549                 vsu_mode = SCALE_UP_BIL;
 550         } else if (lb_mode == LB_RGB_2560X4) {
 551                 vsu_mode = SCALE_UP_BIL;
 552         } else {
 553                 vsu_mode = SCALE_UP_BIC;
 554         }
 555
 556         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 557                                 true, 0, NULL);
 558         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 559         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 560                                 false, vsu_mode, &vskiplines);
 561         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 562
 563         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 564         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 565
 566         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 567         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 568         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 569         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 570         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 571         if (is_yuv) {
 572                 vskiplines = 0;
 573
 574                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 575                                         dst_w, true, 0, NULL);
 576                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 577                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 578                                         dst_h, false, vsu_mode, &vskiplines);
 579                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 580
 581                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 582                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 583                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 584                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 585                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 586                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 587                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 588         }
 589 }
 590
 591 /*
 592  * rk3399 colorspace path:
 593  *      Input        Win csc                     Output
 594  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 595  *    RGB        --> R2Y                  __/
 596  *
 597  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 598  *    RGB        --> 709To2020->R2Y       __/
 599  *
 600  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 601  *    RGB        --> R2Y                  __/
 602  *
 603  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 604  *    RGB        --> 709To2020->R2Y       __/
 605  *
 606  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 607  *    RGB        --> R2Y                  __/
 608  *
 609  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 610  *    RGB        --> R2Y(601)             __/
 611  *
 612  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 613  *    RGB        --> bypass               __/
 614  *
 615  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 616  *
 617  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 618  *
 619  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 620  *
 621  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 622  */
 623 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 624                          bool is_input_yuv, bool is_output_yuv,
 625                          int input_csc, int output_csc,
 626                          const uint32_t **y2r_table,
 627                          const uint32_t **r2r_table,
 628                          const uint32_t **r2y_table)
 629 {
 630         *y2r_table = NULL;
 631         *r2r_table = NULL;
 632         *r2y_table = NULL;
 633
 634         if (is_output_yuv) {
 635                 if (output_csc == CSC_BT2020) {
 636                         if (is_input_yuv) {
 637                                 if (input_csc == CSC_BT2020)
 638                                         return 0;
 639                                 *y2r_table = csc_table->y2r_bt709;
 640                         }
 641                         if (input_csc != CSC_BT2020)
 642                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 643                         *r2y_table = csc_table->r2y_bt2020;
 644                 } else {
 645                         if (is_input_yuv && input_csc == CSC_BT2020)
 646                                 *y2r_table = csc_table->y2r_bt2020;
 647                         if (input_csc == CSC_BT2020)
 648                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 649                         if (!is_input_yuv || *y2r_table) {
 650                                 if (output_csc == CSC_BT709)
 651                                         *r2y_table = csc_table->r2y_bt709;
 652                                 else
 653                                         *r2y_table = csc_table->r2y_bt601;
 654                         }
 655                 }
 656         } else {
 657                 if (!is_input_yuv)
 658                         return 0;
 659
 660                 /*
 661                  * is possible use bt2020 on rgb mode?
 662                  */
 663                 if (WARN_ON(output_csc == CSC_BT2020))
 664                         return -EINVAL;
 665
 666                 if (input_csc == CSC_BT2020)
 667                         *y2r_table = csc_table->y2r_bt2020;
 668                 else if (input_csc == CSC_BT709)
 669                         *y2r_table = csc_table->y2r_bt709;
 670                 else
 671                         *y2r_table = csc_table->y2r_bt601;
 672
 673                 if (input_csc == CSC_BT2020)
 674                         /*
 675                          * We don't have bt601 to bt709 table, force use bt709.
 676                          */
 677                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 684                                 struct drm_crtc_state *crtc_state)
 685 {
 686         struct vop *vop = to_vop(crtc);
 687         struct drm_atomic_state *state = crtc_state->state;
 688         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 689         const struct vop_csc_table *csc_table = vop->data->csc_table;
 690         struct drm_plane_state *pstate;
 691         struct drm_plane *plane;
 692         bool is_input_yuv, is_output_yuv;
 693         int ret;
 694
 695         if (!csc_table)
 696                 return 0;
 697
 698         is_output_yuv = is_yuv_output(s->bus_format);
 699
 700         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 701                 struct vop_plane_state *vop_plane_state;
 702
 703                 pstate = drm_atomic_get_plane_state(state, plane);
 704                 if (IS_ERR(pstate))
 705                         return PTR_ERR(pstate);
 706                 vop_plane_state = to_vop_plane_state(pstate);
 707
 708                 if (!pstate->fb)
 709                         continue;
 710                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 711
 712                 /*
 713                  * TODO: force set input and output csc mode.
 714                  */
 715                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 716                                     CSC_BT709, CSC_BT709,
 717                                     &vop_plane_state->y2r_table,
 718                                     &vop_plane_state->r2r_table,
 719                                     &vop_plane_state->r2y_table);
 720                 if (ret)
 721                         return ret;
 722         }
 723
 724         return 0;
 725 }
 726
 727 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 728 {
 729         unsigned long flags;
 730
 731         spin_lock_irqsave(&vop->irq_lock, flags);
 732
 733         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 734         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 735
 736         spin_unlock_irqrestore(&vop->irq_lock, flags);
 737 }
 738
 739 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 740 {
 741         unsigned long flags;
 742
 743         spin_lock_irqsave(&vop->irq_lock, flags);
 744
 745         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 746
 747         spin_unlock_irqrestore(&vop->irq_lock, flags);
 748 }
 749
 750 /*
 751  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 752  *     the "FRAME_SYNC" interrupt.
 753  * (2) the active data region of each frame ends at dsp_vact_end
 754  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 755  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 756  *
 757  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 758  * Interrupts
 759  * LINE_FLAG -------------------------------+
 760  * FRAME_SYNC ----+                         |
 761  *                |                         |
 762  *                v                         v
 763  *                | Vsync | Vbp |  Vactive  | Vfp |
 764  *                        ^     ^           ^     ^
 765  *                        |     |           |     |
 766  *                        |     |           |     |
 767  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 768  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 769  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 770  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 771  */
 772 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 773 {
 774         uint32_t line_flag_irq;
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&vop->irq_lock, flags);
 778
 779         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 780
 781         spin_unlock_irqrestore(&vop->irq_lock, flags);
 782
 783         return !!line_flag_irq;
 784 }
 785
 786 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 787 {
 788         unsigned long flags;
 789
 790         if (WARN_ON(!vop->is_enabled))
 791                 return;
 792
 793         spin_lock_irqsave(&vop->irq_lock, flags);
 794
 795         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 796         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 797         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 798
 799         spin_unlock_irqrestore(&vop->irq_lock, flags);
 800 }
 801
 802 static void vop_line_flag_irq_disable(struct vop *vop)
 803 {
 804         unsigned long flags;
 805
 806         if (WARN_ON(!vop->is_enabled))
 807                 return;
 808
 809         spin_lock_irqsave(&vop->irq_lock, flags);
 810
 811         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 812
 813         spin_unlock_irqrestore(&vop->irq_lock, flags);
 814 }
 815
 816 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 817 {
 818         struct vop *vop = to_vop(crtc);
 819         int i, dle, lut_idx;
 820
 821         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 822                 return;
 823
 824         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 825                 return;
 826
 827         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 828                 spin_lock(&vop->reg_lock);
 829                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 830                 vop_cfg_done(vop);
 831                 spin_unlock(&vop->reg_lock);
 832
 833 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 834                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 835                                 dle, !dle, 5, 33333);
 836         } else {
 837                 lut_idx = CTRL_GET(lut_buffer_index);
 838         }
 839
 840         for (i = 0; i < vop->lut_len; i++)
 841                 vop_write_lut(vop, i << 2, vop->lut[i]);
 842
 843         spin_lock(&vop->reg_lock);
 844
 845         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 846         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 847         vop_cfg_done(vop);
 848         vop->lut_active = true;
 849
 850         spin_unlock(&vop->reg_lock);
 851
 852         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 853                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 854                                    dle, dle != lut_idx, 5, 33333);
 855                 /* FIXME:
 856                  * update_gamma value auto clean to 0 by HW, should not
 857                  * bakeup it.
 858                  */
 859                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 860         }
 861 #undef CTRL_GET
 862 }
 863
 864 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 865                                     u16 blue, int regno)
 866 {
 867         struct vop *vop = to_vop(crtc);
 868         u32 lut_len = vop->lut_len;
 869         u32 r, g, b;
 870
 871         if (regno >= lut_len || !vop->lut)
 872                 return;
 873
 874         r = red * (lut_len - 1) / 0xffff;
 875         g = green * (lut_len - 1) / 0xffff;
 876         b = blue * (lut_len - 1) / 0xffff;
 877         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 878 }
 879
 880 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 881                                     u16 *blue, int regno)
 882 {
 883         struct vop *vop = to_vop(crtc);
 884         u32 lut_len = vop->lut_len;
 885         u32 r, g, b;
 886
 887         if (regno >= lut_len || !vop->lut)
 888                 return;
 889
 890         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 891         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 892         b = vop->lut[regno] & (lut_len - 1);
 893         *red = r * 0xffff / (lut_len - 1);
 894         *green = g * 0xffff / (lut_len - 1);
 895         *blue = b * 0xffff / (lut_len - 1);
 896 }
 897
 898 static void vop_power_enable(struct drm_crtc *crtc)
 899 {
 900         struct vop *vop = to_vop(crtc);
 901         int ret;
 902
 903         ret = clk_prepare_enable(vop->hclk);
 904         if (ret < 0) {
 905                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 906                 return;
 907         }
 908
 909         ret = clk_prepare_enable(vop->dclk);
 910         if (ret < 0) {
 911                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 912                 goto err_disable_hclk;
 913         }
 914
 915         ret = clk_prepare_enable(vop->aclk);
 916         if (ret < 0) {
 917                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 918                 goto err_disable_dclk;
 919         }
 920
 921         ret = pm_runtime_get_sync(vop->dev);
 922         if (ret < 0) {
 923                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 924                 return;
 925         }
 926
 927         memcpy(vop->regsbak, vop->regs, vop->len);
 928
 929         vop->is_enabled = true;
 930
 931         return;
 932
 933 err_disable_dclk:
 934         clk_disable_unprepare(vop->dclk);
 935 err_disable_hclk:
 936         clk_disable_unprepare(vop->hclk);
 937 }
 938
 939 static void vop_initial(struct drm_crtc *crtc)
 940 {
 941         struct vop *vop = to_vop(crtc);
 942         uint32_t irqs;
 943         int i;
 944
 945         vop_power_enable(crtc);
 946
 947         VOP_CTRL_SET(vop, global_regdone_en, 1);
 948         VOP_CTRL_SET(vop, dsp_blank, 0);
 949
 950         /*
 951          * restore the lut table.
 952          */
 953         if (vop->lut_active)
 954                 vop_crtc_load_lut(crtc);
 955
 956         /*
 957          * We need to make sure that all windows are disabled before resume
 958          * the crtc. Otherwise we might try to scan from a destroyed
 959          * buffer later.
 960          */
 961         for (i = 0; i < vop->num_wins; i++) {
 962                 struct vop_win *win = &vop->win[i];
 963                 int channel = i * 2 + 1;
 964
 965                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 966                 if (win->phy->scl && win->phy->scl->ext) {
 967                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 968                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 969                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 970                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 971                 }
 972                 VOP_WIN_SET(vop, win, enable, 0);
 973                 VOP_WIN_SET(vop, win, gate, 1);
 974         }
 975         VOP_CTRL_SET(vop, afbdc_en, 0);
 976
 977         irqs = BUS_ERROR_INTR | WIN0_EMPTY_INTR | WIN1_EMPTY_INTR |
 978                 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | HWC_EMPTY_INTR |
 979                 POST_BUF_EMPTY_INTR;
 980         VOP_INTR_SET_TYPE(vop, clear, irqs, 1);
 981         VOP_INTR_SET_TYPE(vop, enable, irqs, 1);
 982 }
 983
 984 static void vop_crtc_disable(struct drm_crtc *crtc)
 985 {
 986         struct vop *vop = to_vop(crtc);
 987
 988         mutex_lock(&vop->vop_lock);
 989         drm_crtc_vblank_off(crtc);
 990
 991         /*
 992          * Vop standby will take effect at end of current frame,
 993          * if dsp hold valid irq happen, it means standby complete.
 994          *
 995          * we must wait standby complete when we want to disable aclk,
 996          * if not, memory bus maybe dead.
 997          */
 998         reinit_completion(&vop->dsp_hold_completion);
 999         vop_dsp_hold_valid_irq_enable(vop);
1000
1001         spin_lock(&vop->reg_lock);
1002
1003         VOP_CTRL_SET(vop, standby, 1);
1004
1005         spin_unlock(&vop->reg_lock);
1006
1007         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
1008                                              msecs_to_jiffies(50)));
1009
1010         vop_dsp_hold_valid_irq_disable(vop);
1011
1012         disable_irq(vop->irq);
1013
1014         vop->is_enabled = false;
1015         if (vop->is_iommu_enabled) {
1016                 /*
1017                  * vop standby complete, so iommu detach is safe.
1018                  */
1019                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
1020                 vop->is_iommu_enabled = false;
1021         }
1022
1023         pm_runtime_put(vop->dev);
1024         clk_disable_unprepare(vop->dclk);
1025         clk_disable_unprepare(vop->aclk);
1026         clk_disable_unprepare(vop->hclk);
1027         mutex_unlock(&vop->vop_lock);
1028 }
1029
1030 static void vop_plane_destroy(struct drm_plane *plane)
1031 {
1032         drm_plane_cleanup(plane);
1033 }
1034
1035 static int vop_plane_prepare_fb(struct drm_plane *plane,
1036                                 const struct drm_plane_state *new_state)
1037 {
1038         if (plane->state->fb)
1039                 drm_framebuffer_reference(plane->state->fb);
1040
1041         return 0;
1042 }
1043
1044 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1045                                  const struct drm_plane_state *old_state)
1046 {
1047         if (old_state->fb)
1048                 drm_framebuffer_unreference(old_state->fb);
1049 }
1050
1051 static int vop_plane_atomic_check(struct drm_plane *plane,
1052                            struct drm_plane_state *state)
1053 {
1054         struct drm_crtc *crtc = state->crtc;
1055         struct drm_framebuffer *fb = state->fb;
1056         struct vop_win *win = to_vop_win(plane);
1057         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1058         struct drm_crtc_state *crtc_state;
1059         const struct vop_data *vop_data;
1060         struct vop *vop;
1061         bool visible;
1062         int ret;
1063         struct drm_rect *dest = &vop_plane_state->dest;
1064         struct drm_rect *src = &vop_plane_state->src;
1065         struct drm_rect clip;
1066         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1067                                         DRM_PLANE_HELPER_NO_SCALING;
1068         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1069                                         DRM_PLANE_HELPER_NO_SCALING;
1070         unsigned long offset;
1071         dma_addr_t dma_addr;
1072         u16 vdisplay;
1073
1074         crtc = crtc ? crtc : plane->state->crtc;
1075         /*
1076          * Both crtc or plane->state->crtc can be null.
1077          */
1078         if (!crtc || !fb)
1079                 goto out_disable;
1080
1081         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1082         if (IS_ERR(crtc_state))
1083                 return PTR_ERR(crtc_state);
1084
1085         src->x1 = state->src_x;
1086         src->y1 = state->src_y;
1087         src->x2 = state->src_x + state->src_w;
1088         src->y2 = state->src_y + state->src_h;
1089         dest->x1 = state->crtc_x;
1090         dest->y1 = state->crtc_y;
1091         dest->x2 = state->crtc_x + state->crtc_w;
1092         dest->y2 = state->crtc_y + state->crtc_h;
1093
1094         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1095         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1096                 vdisplay *= 2;
1097
1098         clip.x1 = 0;
1099         clip.y1 = 0;
1100         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1101         clip.y2 = vdisplay;
1102
1103         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1104                                             src, dest, &clip,
1105                                             min_scale,
1106                                             max_scale,
1107                                             true, true, &visible);
1108         if (ret)
1109                 return ret;
1110
1111         if (!visible)
1112                 goto out_disable;
1113
1114         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1115         if (vop_plane_state->format < 0)
1116                 return vop_plane_state->format;
1117
1118         vop = to_vop(crtc);
1119         vop_data = vop->data;
1120
1121         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1122             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1123                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1124                           drm_rect_width(src) >> 16,
1125                           drm_rect_height(src) >> 16,
1126                           vop_data->max_input.width,
1127                           vop_data->max_input.height);
1128                 return -EINVAL;
1129         }
1130
1131         /*
1132          * Src.x1 can be odd when do clip, but yuv plane start point
1133          * need align with 2 pixel.
1134          */
1135         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1136                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1137                 return -EINVAL;
1138         }
1139
1140         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1141         if (state->rotation & BIT(DRM_REFLECT_Y) ||
1142             (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1143                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1144         else
1145                 offset += (src->y1 >> 16) * fb->pitches[0];
1146
1147         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1148         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1149         if (is_yuv_support(fb->pixel_format)) {
1150                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1151                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1152                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1153
1154                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1155                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1156
1157                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1158                 dma_addr += offset + fb->offsets[1];
1159                 vop_plane_state->uv_mst = dma_addr;
1160         }
1161
1162         vop_plane_state->enable = true;
1163
1164         return 0;
1165
1166 out_disable:
1167         vop_plane_state->enable = false;
1168         return 0;
1169 }
1170
1171 static void vop_plane_atomic_disable(struct drm_plane *plane,
1172                                      struct drm_plane_state *old_state)
1173 {
1174         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1175         struct vop_win *win = to_vop_win(plane);
1176         struct vop *vop = to_vop(old_state->crtc);
1177
1178         if (!old_state->crtc)
1179                 return;
1180
1181         spin_lock(&vop->reg_lock);
1182
1183         /*
1184          * FIXUP: some of the vop scale would be abnormal after windows power
1185          * on/off so deinit scale to scale_none mode.
1186          */
1187         if (win->phy->scl && win->phy->scl->ext) {
1188                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1189                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1190                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1191                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1192         }
1193         VOP_WIN_SET(vop, win, enable, 0);
1194
1195         spin_unlock(&vop->reg_lock);
1196
1197         vop_plane_state->enable = false;
1198 }
1199
1200 static void vop_plane_atomic_update(struct drm_plane *plane,
1201                 struct drm_plane_state *old_state)
1202 {
1203         struct drm_plane_state *state = plane->state;
1204         struct drm_crtc *crtc = state->crtc;
1205         struct vop_win *win = to_vop_win(plane);
1206         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1207         struct rockchip_crtc_state *s;
1208         struct vop *vop;
1209         struct drm_framebuffer *fb = state->fb;
1210         unsigned int actual_w, actual_h;
1211         unsigned int dsp_stx, dsp_sty;
1212         uint32_t act_info, dsp_info, dsp_st;
1213         struct drm_rect *src = &vop_plane_state->src;
1214         struct drm_rect *dest = &vop_plane_state->dest;
1215         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1216         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1217         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1218         int ymirror, xmirror;
1219         uint32_t val;
1220         bool rb_swap;
1221
1222         /*
1223          * can't update plane when vop is disabled.
1224          */
1225         if (!crtc)
1226                 return;
1227
1228         if (!vop_plane_state->enable) {
1229                 vop_plane_atomic_disable(plane, old_state);
1230                 return;
1231         }
1232
1233         actual_w = drm_rect_width(src) >> 16;
1234         actual_h = drm_rect_height(src) >> 16;
1235         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1236
1237         dsp_info = (drm_rect_height(dest) - 1) << 16;
1238         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1239
1240         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1241         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1242         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1243
1244         ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1245                   (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1246         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1247
1248         vop = to_vop(state->crtc);
1249         s = to_rockchip_crtc_state(crtc->state);
1250
1251         spin_lock(&vop->reg_lock);
1252
1253         VOP_WIN_SET(vop, win, xmirror, xmirror);
1254         VOP_WIN_SET(vop, win, ymirror, ymirror);
1255         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1256         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1257         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1258         if (is_yuv_support(fb->pixel_format)) {
1259                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1260                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1261         }
1262         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1263
1264         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1265                             drm_rect_width(dest), drm_rect_height(dest),
1266                             fb->pixel_format);
1267
1268         VOP_WIN_SET(vop, win, act_info, act_info);
1269         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1270         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1271
1272         rb_swap = has_rb_swapped(fb->pixel_format);
1273         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1274
1275         if (is_alpha_support(fb->pixel_format) &&
1276             (s->dsp_layer_sel & 0x3) != win->win_id) {
1277                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1278                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1279                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1280                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1281                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1282                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1283                         SRC_FACTOR_M0(ALPHA_ONE);
1284                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1285                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1286                 VOP_WIN_SET(vop, win, alpha_en, 1);
1287         } else {
1288                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1289                 VOP_WIN_SET(vop, win, alpha_en, 0);
1290         }
1291
1292         if (win->csc) {
1293                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1294                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1295                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1296                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1297                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1298                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1299         }
1300         VOP_WIN_SET(vop, win, enable, 1);
1301         spin_unlock(&vop->reg_lock);
1302         vop->is_iommu_needed = true;
1303 }
1304
1305 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1306         .prepare_fb = vop_plane_prepare_fb,
1307         .cleanup_fb = vop_plane_cleanup_fb,
1308         .atomic_check = vop_plane_atomic_check,
1309         .atomic_update = vop_plane_atomic_update,
1310         .atomic_disable = vop_plane_atomic_disable,
1311 };
1312
1313 void vop_atomic_plane_reset(struct drm_plane *plane)
1314 {
1315         struct vop_win *win = to_vop_win(plane);
1316         struct vop_plane_state *vop_plane_state =
1317                                         to_vop_plane_state(plane->state);
1318
1319         if (plane->state && plane->state->fb)
1320                 drm_framebuffer_unreference(plane->state->fb);
1321
1322         kfree(vop_plane_state);
1323         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1324         if (!vop_plane_state)
1325                 return;
1326
1327         vop_plane_state->zpos = win->win_id;
1328         plane->state = &vop_plane_state->base;
1329         plane->state->plane = plane;
1330 }
1331
1332 struct drm_plane_state *
1333 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1334 {
1335         struct vop_plane_state *old_vop_plane_state;
1336         struct vop_plane_state *vop_plane_state;
1337
1338         if (WARN_ON(!plane->state))
1339                 return NULL;
1340
1341         old_vop_plane_state = to_vop_plane_state(plane->state);
1342         vop_plane_state = kmemdup(old_vop_plane_state,
1343                                   sizeof(*vop_plane_state), GFP_KERNEL);
1344         if (!vop_plane_state)
1345                 return NULL;
1346
1347         __drm_atomic_helper_plane_duplicate_state(plane,
1348                                                   &vop_plane_state->base);
1349
1350         return &vop_plane_state->base;
1351 }
1352
1353 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1354                                            struct drm_plane_state *state)
1355 {
1356         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1357
1358         __drm_atomic_helper_plane_destroy_state(plane, state);
1359
1360         kfree(vop_state);
1361 }
1362
1363 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1364                                          struct drm_plane_state *state,
1365                                          struct drm_property *property,
1366                                          uint64_t val)
1367 {
1368         struct rockchip_drm_private *private = plane->dev->dev_private;
1369         struct vop_win *win = to_vop_win(plane);
1370         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1371
1372         if (property == win->vop->plane_zpos_prop) {
1373                 plane_state->zpos = val;
1374                 return 0;
1375         }
1376
1377         if (property == win->rotation_prop) {
1378                 state->rotation = val;
1379                 return 0;
1380         }
1381
1382         if (property == private->logo_ymirror_prop) {
1383                 WARN_ON(!rockchip_fb_is_logo(state->fb));
1384                 plane_state->logo_ymirror = val;
1385                 return 0;
1386         }
1387
1388         DRM_ERROR("failed to set vop plane property\n");
1389         return -EINVAL;
1390 }
1391
1392 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1393                                          const struct drm_plane_state *state,
1394                                          struct drm_property *property,
1395                                          uint64_t *val)
1396 {
1397         struct vop_win *win = to_vop_win(plane);
1398         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1399
1400         if (property == win->vop->plane_zpos_prop) {
1401                 *val = plane_state->zpos;
1402                 return 0;
1403         }
1404
1405         if (property == win->rotation_prop) {
1406                 *val = state->rotation;
1407                 return 0;
1408         }
1409
1410         DRM_ERROR("failed to get vop plane property\n");
1411         return -EINVAL;
1412 }
1413
1414 static const struct drm_plane_funcs vop_plane_funcs = {
1415         .update_plane   = drm_atomic_helper_update_plane,
1416         .disable_plane  = drm_atomic_helper_disable_plane,
1417         .destroy = vop_plane_destroy,
1418         .reset = vop_atomic_plane_reset,
1419         .set_property = drm_atomic_helper_plane_set_property,
1420         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1421         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1422         .atomic_set_property = vop_atomic_plane_set_property,
1423         .atomic_get_property = vop_atomic_plane_get_property,
1424 };
1425
1426 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1427 {
1428         struct vop *vop = to_vop(crtc);
1429         unsigned long flags;
1430
1431         if (!vop->is_enabled)
1432                 return -EPERM;
1433
1434         spin_lock_irqsave(&vop->irq_lock, flags);
1435
1436         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1437         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1438
1439         spin_unlock_irqrestore(&vop->irq_lock, flags);
1440
1441         return 0;
1442 }
1443
1444 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1445 {
1446         struct vop *vop = to_vop(crtc);
1447         unsigned long flags;
1448
1449         if (!vop->is_enabled)
1450                 return;
1451
1452         spin_lock_irqsave(&vop->irq_lock, flags);
1453
1454         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1455
1456         spin_unlock_irqrestore(&vop->irq_lock, flags);
1457 }
1458
1459 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1460                                            struct drm_file *file_priv)
1461 {
1462         struct drm_device *drm = crtc->dev;
1463         struct vop *vop = to_vop(crtc);
1464         struct drm_pending_vblank_event *e;
1465         unsigned long flags;
1466
1467         spin_lock_irqsave(&drm->event_lock, flags);
1468         e = vop->event;
1469         if (e && e->base.file_priv == file_priv) {
1470                 vop->event = NULL;
1471
1472                 e->base.destroy(&e->base);
1473                 file_priv->event_space += sizeof(e->event);
1474         }
1475         spin_unlock_irqrestore(&drm->event_lock, flags);
1476 }
1477
1478 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1479 {
1480         struct vop *vop = to_vop(crtc);
1481
1482         if (on == vop->loader_protect)
1483                 return 0;
1484
1485         if (on) {
1486                 vop_power_enable(crtc);
1487                 enable_irq(vop->irq);
1488                 drm_crtc_vblank_on(crtc);
1489                 vop->loader_protect = true;
1490         } else {
1491                 vop_crtc_disable(crtc);
1492
1493                 vop->loader_protect = false;
1494         }
1495
1496         return 0;
1497 }
1498
1499 #define DEBUG_PRINT(args...) \
1500                 do { \
1501                         if (s) \
1502                                 seq_printf(s, args); \
1503                         else \
1504                                 printk(args); \
1505                 } while (0)
1506
1507 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1508 {
1509         struct vop_win *win = to_vop_win(plane);
1510         struct drm_plane_state *state = plane->state;
1511         struct vop_plane_state *pstate = to_vop_plane_state(state);
1512         struct drm_rect *src, *dest;
1513         struct drm_framebuffer *fb = state->fb;
1514         int i;
1515
1516         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1517                     pstate->enable ? "ACTIVE" : "DISABLED");
1518         if (!fb)
1519                 return 0;
1520
1521         src = &pstate->src;
1522         dest = &pstate->dest;
1523
1524         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1525                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1526         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1527         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1528                     src->y1 >> 16, drm_rect_width(src) >> 16,
1529                     drm_rect_height(src) >> 16);
1530         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1531                     drm_rect_width(dest), drm_rect_height(dest));
1532
1533         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1534                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1535                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1536                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1543 {
1544         struct vop *vop = to_vop(crtc);
1545         struct drm_crtc_state *crtc_state = crtc->state;
1546         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1547         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1548         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1549         struct drm_plane *plane;
1550         int i;
1551
1552         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1553                     crtc_state->active ? "ACTIVE" : "DISABLED");
1554
1555         if (!crtc_state->active)
1556                 return 0;
1557
1558         DEBUG_PRINT("    Connector: %s\n",
1559                     drm_get_connector_name(state->output_type));
1560         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1561                     state->bus_format, state->output_mode);
1562         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1563                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1564                     drm_mode_vrefresh(mode));
1565         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1566                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1567         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1568                     mode->hsync_end, mode->htotal);
1569         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1570                     mode->vsync_end, mode->vtotal);
1571
1572         for (i = 0; i < vop->num_wins; i++) {
1573                 plane = &vop->win[i].base;
1574                 vop_plane_info_dump(s, plane);
1575         }
1576
1577         return 0;
1578 }
1579
1580 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1581 {
1582         struct vop *vop = to_vop(crtc);
1583         struct drm_crtc_state *crtc_state = crtc->state;
1584         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1585         int i;
1586
1587         if (!crtc_state->active)
1588                 return;
1589
1590         for (i = 0; i < dump_len; i += 4) {
1591                 if (i % 16 == 0)
1592                         DEBUG_PRINT("\n0x%08x: ", i);
1593                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1594         }
1595 }
1596
1597 #undef DEBUG_PRINT
1598
1599 static enum drm_mode_status
1600 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1601                     int output_type)
1602 {
1603         struct vop *vop = to_vop(crtc);
1604         const struct vop_data *vop_data = vop->data;
1605         int request_clock = mode->clock;
1606         int clock;
1607
1608         if (mode->hdisplay > vop_data->max_output.width)
1609                 return MODE_BAD_HVALUE;
1610
1611         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
1612             VOP_MAJOR(vop->data->version) == 3 &&
1613             VOP_MINOR(vop->data->version) <= 2)
1614                 return MODE_BAD;
1615
1616         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1617                 request_clock *= 2;
1618         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1619
1620         /*
1621          * Hdmi or DisplayPort request a Accurate clock.
1622          */
1623         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1624             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1625                 if (clock != request_clock)
1626                         return MODE_CLOCK_RANGE;
1627
1628         return MODE_OK;
1629 }
1630
1631 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1632         .loader_protect = vop_crtc_loader_protect,
1633         .enable_vblank = vop_crtc_enable_vblank,
1634         .disable_vblank = vop_crtc_disable_vblank,
1635         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1636         .debugfs_dump = vop_crtc_debugfs_dump,
1637         .regs_dump = vop_crtc_regs_dump,
1638         .mode_valid = vop_crtc_mode_valid,
1639 };
1640
1641 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1642                                 const struct drm_display_mode *mode,
1643                                 struct drm_display_mode *adj_mode)
1644 {
1645         struct vop *vop = to_vop(crtc);
1646         const struct vop_data *vop_data = vop->data;
1647
1648         if (mode->hdisplay > vop_data->max_output.width)
1649                 return false;
1650
1651         drm_mode_set_crtcinfo(adj_mode,
1652                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1653
1654         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1655                 adj_mode->crtc_clock *= 2;
1656
1657         adj_mode->crtc_clock =
1658                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1659
1660         return true;
1661 }
1662
1663 static void vop_crtc_enable(struct drm_crtc *crtc)
1664 {
1665         struct vop *vop = to_vop(crtc);
1666         const struct vop_data *vop_data = vop->data;
1667         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1668         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1669         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1670         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1671         u16 htotal = adjusted_mode->crtc_htotal;
1672         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1673         u16 hact_end = hact_st + hdisplay;
1674         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1675         u16 vtotal = adjusted_mode->crtc_vtotal;
1676         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1677         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1678         u16 vact_end = vact_st + vdisplay;
1679         uint32_t val;
1680
1681         mutex_lock(&vop->vop_lock);
1682         vop_initial(crtc);
1683
1684         VOP_CTRL_SET(vop, dclk_pol, 1);
1685         val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1686                    0 : BIT(HSYNC_POSITIVE);
1687         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1688                    0 : BIT(VSYNC_POSITIVE);
1689         VOP_CTRL_SET(vop, pin_pol, val);
1690
1691         if (vop->dclk_source && s->pll && s->pll->pll) {
1692                 if (clk_set_parent(vop->dclk_source, s->pll->pll))
1693                         DRM_DEV_ERROR(vop->dev,
1694                                       "failed to set dclk's parents\n");
1695         }
1696
1697         switch (s->output_type) {
1698         case DRM_MODE_CONNECTOR_LVDS:
1699                 VOP_CTRL_SET(vop, rgb_en, 1);
1700                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1701                 VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
1702                 VOP_CTRL_SET(vop, lvds_en, 1);
1703                 VOP_CTRL_SET(vop, lvds_pin_pol, val);
1704                 VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
1705                 break;
1706         case DRM_MODE_CONNECTOR_eDP:
1707                 VOP_CTRL_SET(vop, edp_en, 1);
1708                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1709                 VOP_CTRL_SET(vop, edp_dclk_pol, 1);
1710                 break;
1711         case DRM_MODE_CONNECTOR_HDMIA:
1712                 VOP_CTRL_SET(vop, hdmi_en, 1);
1713                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1714                 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
1715                 break;
1716         case DRM_MODE_CONNECTOR_DSI:
1717                 VOP_CTRL_SET(vop, mipi_en, 1);
1718                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1719                 VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
1720                 break;
1721         case DRM_MODE_CONNECTOR_DisplayPort:
1722                 VOP_CTRL_SET(vop, dp_dclk_pol, 0);
1723                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1724                 VOP_CTRL_SET(vop, dp_en, 1);
1725                 break;
1726         case DRM_MODE_CONNECTOR_TV:
1727                 if (vdisplay == CVBS_PAL_VDISPLAY)
1728                         VOP_CTRL_SET(vop, tve_sw_mode, 1);
1729                 else
1730                         VOP_CTRL_SET(vop, tve_sw_mode, 0);
1731
1732                 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
1733                 VOP_CTRL_SET(vop, tve_dclk_en, 1);
1734                 /* use the same pol reg with hdmi */
1735                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1736                 VOP_CTRL_SET(vop, sw_genlock, 1);
1737                 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
1738                 VOP_CTRL_SET(vop, dither_up, 1);
1739                 break;
1740         default:
1741                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1742         }
1743
1744         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1745             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1746                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1747
1748         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1749         switch (s->bus_format) {
1750         case MEDIA_BUS_FMT_RGB565_1X16:
1751                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1752                 break;
1753         case MEDIA_BUS_FMT_RGB666_1X18:
1754         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1755                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1756                 break;
1757         case MEDIA_BUS_FMT_YUV8_1X24:
1758         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1759                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1760                 break;
1761         case MEDIA_BUS_FMT_YUV10_1X30:
1762         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1763                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1764                 break;
1765         case MEDIA_BUS_FMT_RGB888_1X24:
1766         default:
1767                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1768                 break;
1769         }
1770
1771         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1772                 val |= PRE_DITHER_DOWN_EN(0);
1773         else
1774                 val |= PRE_DITHER_DOWN_EN(1);
1775         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1776         VOP_CTRL_SET(vop, dither_down, val);
1777         VOP_CTRL_SET(vop, dclk_ddr,
1778                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1779         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1780         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1781
1782         /*
1783          * Background color is 10bit depth if vop version >= 3.5
1784          */
1785         if (!is_yuv_output(s->bus_format))
1786                 val = 0;
1787         else if (VOP_MAJOR(vop->data->version) == 3 &&
1788                  VOP_MINOR(vop->data->version) >= 5)
1789                 val = 0x20010200;
1790         else
1791                 val = 0x801080;
1792         VOP_CTRL_SET(vop, dsp_background, val);
1793         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1794         val = hact_st << 16;
1795         val |= hact_end;
1796         VOP_CTRL_SET(vop, hact_st_end, val);
1797         VOP_CTRL_SET(vop, hpost_st_end, val);
1798
1799         val = vact_st << 16;
1800         val |= vact_end;
1801         VOP_CTRL_SET(vop, vact_st_end, val);
1802         VOP_CTRL_SET(vop, vpost_st_end, val);
1803
1804         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1805         VOP_INTR_SET(vop, line_flag_num[1],
1806                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1807         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1808                 u16 vact_st_f1 = vtotal + vact_st + 1;
1809                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1810
1811                 val = vact_st_f1 << 16 | vact_end_f1;
1812                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1813                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1814
1815                 val = vtotal << 16 | (vtotal + vsync_len);
1816                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1817                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1818                 VOP_CTRL_SET(vop, p2i_en, 1);
1819                 vtotal += vtotal + 1;
1820         } else {
1821                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1822                 VOP_CTRL_SET(vop, p2i_en, 0);
1823         }
1824         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1825
1826         VOP_CTRL_SET(vop, core_dclk_div,
1827                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1828
1829         VOP_CTRL_SET(vop, cabc_total_num, hdisplay * vdisplay);
1830         VOP_CTRL_SET(vop, cabc_config_mode, STAGE_BY_STAGE);
1831         VOP_CTRL_SET(vop, cabc_stage_up_mode, MUL_MODE);
1832         VOP_CTRL_SET(vop, cabc_scale_cfg_value, 1);
1833         VOP_CTRL_SET(vop, cabc_scale_cfg_enable, 0);
1834         VOP_CTRL_SET(vop, cabc_global_dn_limit_en, 1);
1835
1836         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1837
1838         vop_cfg_done(vop);
1839         /*
1840          * enable vop, all the register would take effect when vop exit standby
1841          */
1842         VOP_CTRL_SET(vop, standby, 0);
1843
1844         enable_irq(vop->irq);
1845         drm_crtc_vblank_on(crtc);
1846         mutex_unlock(&vop->vop_lock);
1847 }
1848
1849 static int vop_zpos_cmp(const void *a, const void *b)
1850 {
1851         struct vop_zpos *pa = (struct vop_zpos *)a;
1852         struct vop_zpos *pb = (struct vop_zpos *)b;
1853
1854         return pa->zpos - pb->zpos;
1855 }
1856
1857 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1858                                   struct drm_crtc_state *crtc_state)
1859 {
1860         struct vop *vop = to_vop(crtc);
1861         const struct vop_data *vop_data = vop->data;
1862         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1863         struct drm_atomic_state *state = crtc_state->state;
1864         struct drm_plane *plane;
1865         struct drm_plane_state *pstate;
1866         struct vop_plane_state *plane_state;
1867         struct vop_win *win;
1868         int afbdc_format;
1869         int i;
1870
1871         s->afbdc_en = 0;
1872
1873         for_each_plane_in_state(state, plane, pstate, i) {
1874                 struct drm_framebuffer *fb = pstate->fb;
1875                 struct drm_rect *src;
1876
1877                 win = to_vop_win(plane);
1878                 plane_state = to_vop_plane_state(pstate);
1879
1880                 if (pstate->crtc != crtc || !fb)
1881                         continue;
1882
1883                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1884                         continue;
1885
1886                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1887                         DRM_ERROR("not support afbdc\n");
1888                         return -EINVAL;
1889                 }
1890
1891                 switch (plane_state->format) {
1892                 case VOP_FMT_ARGB8888:
1893                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1894                         break;
1895                 case VOP_FMT_RGB888:
1896                         afbdc_format = AFBDC_FMT_U8U8U8;
1897                         break;
1898                 case VOP_FMT_RGB565:
1899                         afbdc_format = AFBDC_FMT_RGB565;
1900                         break;
1901                 default:
1902                         return -EINVAL;
1903                 }
1904
1905                 if (s->afbdc_en) {
1906                         DRM_ERROR("vop only support one afbc layer\n");
1907                         return -EINVAL;
1908                 }
1909
1910                 src = &plane_state->src;
1911                 if (src->x1 || src->y1 || fb->offsets[0]) {
1912                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1913                                   win->win_id);
1914                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1915                                   src->x1, src->y1, fb->offsets[0]);
1916                         return -EINVAL;
1917                 }
1918                 s->afbdc_win_format = afbdc_format;
1919                 s->afbdc_win_width = pstate->fb->width - 1;
1920                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1921                 s->afbdc_win_id = win->win_id;
1922                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1923                 s->afbdc_en = 1;
1924         }
1925
1926         return 0;
1927 }
1928
1929 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1930                                      struct drm_crtc_state *crtc_state)
1931 {
1932         struct rockchip_drm_private *private = crtc->dev->dev_private;
1933         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1934         struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1935         struct vop *vop = to_vop(crtc);
1936
1937         if (!vop->dclk_source)
1938                 return;
1939
1940         if (crtc_state->active) {
1941                 WARN_ON(s->pll && !s->pll->use_count);
1942                 if (!s->pll || s->pll->use_count > 1 ||
1943                     s->output_type != old_s->output_type) {
1944                         if (s->pll)
1945                                 s->pll->use_count--;
1946
1947                         if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1948                             !private->default_pll.use_count)
1949                                 s->pll = &private->default_pll;
1950                         else
1951                                 s->pll = &private->hdmi_pll;
1952
1953                         s->pll->use_count++;
1954                 }
1955         } else if (s->pll) {
1956                 s->pll->use_count--;
1957                 s->pll = NULL;
1958         }
1959         if (s->pll && s->pll != old_s->pll)
1960                 crtc_state->mode_changed = true;
1961 }
1962
1963 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1964                                  struct drm_crtc_state *crtc_state)
1965 {
1966         struct drm_atomic_state *state = crtc_state->state;
1967         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1968         struct vop *vop = to_vop(crtc);
1969         const struct vop_data *vop_data = vop->data;
1970         struct drm_plane *plane;
1971         struct drm_plane_state *pstate;
1972         struct vop_plane_state *plane_state;
1973         struct vop_zpos *pzpos;
1974         int dsp_layer_sel = 0;
1975         int i, j, cnt = 0, ret = 0;
1976
1977         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1978         if (ret)
1979                 return ret;
1980
1981         ret = vop_csc_atomic_check(crtc, crtc_state);
1982         if (ret)
1983                 return ret;
1984
1985         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1986         if (!pzpos)
1987                 return -ENOMEM;
1988
1989         for (i = 0; i < vop_data->win_size; i++) {
1990                 const struct vop_win_data *win_data = &vop_data->win[i];
1991                 struct vop_win *win;
1992
1993                 if (!win_data->phy)
1994                         continue;
1995
1996                 for (j = 0; j < vop->num_wins; j++) {
1997                         win = &vop->win[j];
1998
1999                         if (win->win_id == i && !win->area_id)
2000                                 break;
2001                 }
2002                 if (WARN_ON(j >= vop->num_wins)) {
2003                         ret = -EINVAL;
2004                         goto err_free_pzpos;
2005                 }
2006
2007                 plane = &win->base;
2008                 pstate = state->plane_states[drm_plane_index(plane)];
2009                 /*
2010                  * plane might not have changed, in which case take
2011                  * current state:
2012                  */
2013                 if (!pstate)
2014                         pstate = plane->state;
2015                 plane_state = to_vop_plane_state(pstate);
2016                 pzpos[cnt].zpos = plane_state->zpos;
2017                 pzpos[cnt++].win_id = win->win_id;
2018         }
2019
2020         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
2021
2022         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
2023                 const struct vop_win_data *win_data = &vop_data->win[i];
2024                 int shift = i * 2;
2025
2026                 if (win_data->phy) {
2027                         struct vop_zpos *zpos = &pzpos[cnt++];
2028
2029                         dsp_layer_sel |= zpos->win_id << shift;
2030                 } else {
2031                         dsp_layer_sel |= i << shift;
2032                 }
2033         }
2034
2035         s->dsp_layer_sel = dsp_layer_sel;
2036
2037         vop_dclk_source_generate(crtc, crtc_state);
2038
2039 err_free_pzpos:
2040         kfree(pzpos);
2041         return ret;
2042 }
2043
2044 static void vop_post_config(struct drm_crtc *crtc)
2045 {
2046         struct vop *vop = to_vop(crtc);
2047         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2048         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2049         u16 vtotal = mode->crtc_vtotal;
2050         u16 hdisplay = mode->crtc_hdisplay;
2051         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2052         u16 vdisplay = mode->crtc_vdisplay;
2053         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2054         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
2055         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
2056         u16 hact_end, vact_end;
2057         u32 val;
2058
2059         hact_st += hdisplay * (100 - s->left_margin) / 200;
2060         hact_end = hact_st + hsize;
2061         val = hact_st << 16;
2062         val |= hact_end;
2063         VOP_CTRL_SET(vop, hpost_st_end, val);
2064         vact_st += vdisplay * (100 - s->top_margin) / 200;
2065         vact_end = vact_st + vsize;
2066         val = vact_st << 16;
2067         val |= vact_end;
2068         VOP_CTRL_SET(vop, vpost_st_end, val);
2069         val = scl_cal_scale2(vdisplay, vsize) << 16;
2070         val |= scl_cal_scale2(hdisplay, hsize);
2071         VOP_CTRL_SET(vop, post_scl_factor, val);
2072
2073 #define POST_HORIZONTAL_SCALEDOWN_EN(x)         ((x) << 0)
2074 #define POST_VERTICAL_SCALEDOWN_EN(x)           ((x) << 1)
2075         VOP_CTRL_SET(vop, post_scl_ctrl,
2076                      POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) ||
2077                      POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
2078         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2079                 u16 vact_st_f1 = vtotal + vact_st + 1;
2080                 u16 vact_end_f1 = vact_st_f1 + vsize;
2081
2082                 val = vact_st_f1 << 16 | vact_end_f1;
2083                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2084         }
2085 }
2086
2087 static void vop_update_cabc_lut(struct drm_crtc *crtc,
2088                             struct drm_crtc_state *old_crtc_state)
2089 {
2090         struct rockchip_crtc_state *s =
2091                         to_rockchip_crtc_state(crtc->state);
2092         struct rockchip_crtc_state *old_s =
2093                         to_rockchip_crtc_state(old_crtc_state);
2094         struct drm_property_blob *cabc_lut = s->cabc_lut;
2095         struct drm_property_blob *old_cabc_lut = old_s->cabc_lut;
2096         struct vop *vop = to_vop(crtc);
2097         int lut_size;
2098         u32 *lut;
2099         u32 lut_len = vop->cabc_lut_len;
2100         int i, dle;
2101
2102         if (!cabc_lut && old_cabc_lut) {
2103                 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2104                 return;
2105         }
2106         if (!cabc_lut)
2107                 return;
2108
2109         if (old_cabc_lut && old_cabc_lut->base.id == cabc_lut->base.id)
2110                 return;
2111
2112         lut = (u32 *)cabc_lut->data;
2113         lut_size = cabc_lut->length / sizeof(u32);
2114         if (WARN(lut_size != lut_len, "Unexpect cabc lut size not match\n"))
2115                 return;
2116
2117 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
2118         if (CTRL_GET(cabc_lut_en)) {
2119                 VOP_CTRL_SET(vop, cabc_lut_en, 0);
2120                 vop_cfg_done(vop);
2121                 readx_poll_timeout(CTRL_GET, cabc_lut_en, dle, !dle, 5, 33333);
2122         }
2123
2124         for (i = 0; i < lut_len; i++)
2125                 vop_write_cabc_lut(vop, (i << 2), lut[i]);
2126 #undef CTRL_GET
2127         VOP_CTRL_SET(vop, cabc_lut_en, 1);
2128 }
2129
2130 static void vop_update_cabc(struct drm_crtc *crtc,
2131                             struct drm_crtc_state *old_crtc_state)
2132 {
2133         struct rockchip_crtc_state *s =
2134                         to_rockchip_crtc_state(crtc->state);
2135         struct vop *vop = to_vop(crtc);
2136         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2137         int pixel_total = mode->hdisplay * mode->vdisplay;
2138
2139         if (!vop->cabc_lut_regs)
2140                 return;
2141
2142         vop_update_cabc_lut(crtc, old_crtc_state);
2143
2144         if (s->cabc_mode != ROCKCHIP_DRM_CABC_MODE_DISABLE) {
2145                 VOP_CTRL_SET(vop, cabc_en, 1);
2146                 VOP_CTRL_SET(vop, cabc_handle_en, 1);
2147                 VOP_CTRL_SET(vop, cabc_stage_up, s->cabc_stage_up);
2148                 VOP_CTRL_SET(vop, cabc_stage_down, s->cabc_stage_down);
2149                 VOP_CTRL_SET(vop, cabc_global_dn, s->cabc_global_dn);
2150                 VOP_CTRL_SET(vop, cabc_calc_pixel_num,
2151                              s->cabc_calc_pixel_num * pixel_total / 1000);
2152         } else {
2153                 /*
2154                  * There are some hardware issues on cabc disabling:
2155                  *   1: if cabc auto gating enable, cabc disabling will cause
2156                  *      vop die
2157                  *   2: cabc disabling always would make timing several
2158                  *      pixel cycle abnormal, cause some panel abnormal.
2159                  *
2160                  * So just keep cabc enable, and make it no work with max
2161                  * cabc_calc_pixel_num, it only has little power consume.
2162                  */
2163                 VOP_CTRL_SET(vop, cabc_calc_pixel_num, pixel_total);
2164         }
2165 }
2166
2167 static void vop_cfg_update(struct drm_crtc *crtc,
2168                            struct drm_crtc_state *old_crtc_state)
2169 {
2170         struct rockchip_crtc_state *s =
2171                         to_rockchip_crtc_state(crtc->state);
2172         struct vop *vop = to_vop(crtc);
2173
2174         spin_lock(&vop->reg_lock);
2175
2176         if (s->afbdc_en) {
2177                 uint32_t pic_size;
2178
2179                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2180                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2181                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2182                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2183                 pic_size = (s->afbdc_win_width & 0xffff);
2184                 pic_size |= s->afbdc_win_height << 16;
2185                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2186         }
2187
2188         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2189         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2190         vop_post_config(crtc);
2191
2192         spin_unlock(&vop->reg_lock);
2193 }
2194
2195 static bool vop_fs_irq_is_pending(struct vop *vop)
2196 {
2197         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
2198 }
2199
2200 static void vop_wait_for_irq_handler(struct vop *vop)
2201 {
2202         bool pending;
2203         int ret;
2204
2205         /*
2206          * Spin until frame start interrupt status bit goes low, which means
2207          * that interrupt handler was invoked and cleared it. The timeout of
2208          * 10 msecs is really too long, but it is just a safety measure if
2209          * something goes really wrong. The wait will only happen in the very
2210          * unlikely case of a vblank happening exactly at the same time and
2211          * shouldn't exceed microseconds range.
2212          */
2213         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
2214                                         !pending, 0, 10 * 1000);
2215         if (ret)
2216                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
2217
2218         synchronize_irq(vop->irq);
2219 }
2220
2221 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2222                                   struct drm_crtc_state *old_crtc_state)
2223 {
2224         struct drm_atomic_state *old_state = old_crtc_state->state;
2225         struct drm_plane_state *old_plane_state;
2226         struct vop *vop = to_vop(crtc);
2227         struct drm_plane *plane;
2228         int i;
2229
2230         vop_cfg_update(crtc, old_crtc_state);
2231
2232         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2233                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2234                 int ret;
2235
2236                 if (need_wait_vblank) {
2237                         bool active;
2238
2239                         disable_irq(vop->irq);
2240                         drm_crtc_vblank_get(crtc);
2241                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2242
2243                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2244                                                         vop, active, active,
2245                                                         0, 50 * 1000);
2246                         if (ret)
2247                                 dev_err(vop->dev, "wait fs irq timeout\n");
2248
2249                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2250                         vop_cfg_done(vop);
2251
2252                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2253                                                         vop, active, active,
2254                                                         0, 50 * 1000);
2255                         if (ret)
2256                                 dev_err(vop->dev, "wait line flag timeout\n");
2257
2258                         enable_irq(vop->irq);
2259                 }
2260                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2261                 if (ret)
2262                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2263                                 ret);
2264
2265                 if (need_wait_vblank) {
2266                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2267                         drm_crtc_vblank_put(crtc);
2268                 }
2269
2270                 vop->is_iommu_enabled = true;
2271         }
2272
2273         vop_update_cabc(crtc, old_crtc_state);
2274
2275         vop_cfg_done(vop);
2276
2277         /*
2278          * There is a (rather unlikely) possiblity that a vblank interrupt
2279          * fired before we set the cfg_done bit. To avoid spuriously
2280          * signalling flip completion we need to wait for it to finish.
2281          */
2282         vop_wait_for_irq_handler(vop);
2283
2284         for_each_plane_in_state(old_state, plane, old_plane_state, i) {
2285                 if (!old_plane_state->fb)
2286                         continue;
2287
2288                 if (old_plane_state->fb == plane->state->fb)
2289                         continue;
2290
2291                 drm_framebuffer_reference(old_plane_state->fb);
2292                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
2293                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
2294                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2295         }
2296 }
2297
2298 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2299                                   struct drm_crtc_state *old_crtc_state)
2300 {
2301         struct vop *vop = to_vop(crtc);
2302
2303         if (crtc->state->event) {
2304                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2305
2306                 vop->event = crtc->state->event;
2307                 crtc->state->event = NULL;
2308         }
2309 }
2310
2311 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2312         .load_lut = vop_crtc_load_lut,
2313         .enable = vop_crtc_enable,
2314         .disable = vop_crtc_disable,
2315         .mode_fixup = vop_crtc_mode_fixup,
2316         .atomic_check = vop_crtc_atomic_check,
2317         .atomic_flush = vop_crtc_atomic_flush,
2318         .atomic_begin = vop_crtc_atomic_begin,
2319 };
2320
2321 static void vop_crtc_destroy(struct drm_crtc *crtc)
2322 {
2323         drm_crtc_cleanup(crtc);
2324 }
2325
2326 static void vop_crtc_reset(struct drm_crtc *crtc)
2327 {
2328         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2329         struct rockchip_drm_private *private = crtc->dev->dev_private;
2330         struct vop *vop = to_vop(crtc);
2331
2332         if (crtc->state) {
2333                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2334                 kfree(s);
2335         }
2336
2337         s = kzalloc(sizeof(*s), GFP_KERNEL);
2338         if (!s)
2339                 return;
2340         crtc->state = &s->base;
2341         crtc->state->crtc = crtc;
2342
2343         if (vop->dclk_source) {
2344                 struct clk *parent;
2345
2346                 parent = clk_get_parent(vop->dclk_source);
2347                 if (parent) {
2348                         if (clk_is_match(private->default_pll.pll, parent))
2349                                 s->pll = &private->default_pll;
2350                         else if (clk_is_match(private->hdmi_pll.pll, parent))
2351                                 s->pll = &private->hdmi_pll;
2352                         if (s->pll)
2353                                 s->pll->use_count++;
2354                 }
2355         }
2356         s->left_margin = 100;
2357         s->right_margin = 100;
2358         s->top_margin = 100;
2359         s->bottom_margin = 100;
2360 }
2361
2362 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2363 {
2364         struct rockchip_crtc_state *rockchip_state, *old_state;
2365
2366         old_state = to_rockchip_crtc_state(crtc->state);
2367         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2368         if (!rockchip_state)
2369                 return NULL;
2370
2371         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2372         return &rockchip_state->base;
2373 }
2374
2375 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2376                                    struct drm_crtc_state *state)
2377 {
2378         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2379
2380         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2381         kfree(s);
2382 }
2383
2384 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2385                                         const struct drm_crtc_state *state,
2386                                         struct drm_property *property,
2387                                         uint64_t *val)
2388 {
2389         struct drm_device *drm_dev = crtc->dev;
2390         struct rockchip_drm_private *private = drm_dev->dev_private;
2391         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2392         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2393
2394         if (property == mode_config->tv_left_margin_property) {
2395                 *val = s->left_margin;
2396                 return 0;
2397         }
2398
2399         if (property == mode_config->tv_right_margin_property) {
2400                 *val = s->right_margin;
2401                 return 0;
2402         }
2403
2404         if (property == mode_config->tv_top_margin_property) {
2405                 *val = s->top_margin;
2406                 return 0;
2407         }
2408
2409         if (property == mode_config->tv_bottom_margin_property) {
2410                 *val = s->bottom_margin;
2411                 return 0;
2412         }
2413
2414         if (property == private->cabc_mode_property) {
2415                 *val = s->cabc_mode;
2416                 return 0;
2417         }
2418
2419         if (property == private->cabc_stage_up_property) {
2420                 *val = s->cabc_stage_up;
2421                 return 0;
2422         }
2423
2424         if (property == private->cabc_stage_down_property) {
2425                 *val = s->cabc_stage_down;
2426                 return 0;
2427         }
2428
2429         if (property == private->cabc_global_dn_property) {
2430                 *val = s->cabc_global_dn;
2431                 return 0;
2432         }
2433
2434         if (property == private->cabc_calc_pixel_num_property) {
2435                 *val = s->cabc_calc_pixel_num;
2436                 return 0;
2437         }
2438
2439         if (property == private->cabc_lut_property) {
2440                 *val = s->cabc_lut ? s->cabc_lut->base.id : 0;
2441                 return 0;
2442         }
2443
2444         DRM_ERROR("failed to get vop crtc property\n");
2445         return -EINVAL;
2446 }
2447
2448 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2449                                         struct drm_crtc_state *state,
2450                                         struct drm_property *property,
2451                                         uint64_t val)
2452 {
2453         struct drm_device *drm_dev = crtc->dev;
2454         struct rockchip_drm_private *private = drm_dev->dev_private;
2455         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2456         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2457         struct vop *vop = to_vop(crtc);
2458
2459         if (property == mode_config->tv_left_margin_property) {
2460                 s->left_margin = val;
2461                 return 0;
2462         }
2463
2464         if (property == mode_config->tv_right_margin_property) {
2465                 s->right_margin = val;
2466                 return 0;
2467         }
2468
2469         if (property == mode_config->tv_top_margin_property) {
2470                 s->top_margin = val;
2471                 return 0;
2472         }
2473
2474         if (property == mode_config->tv_bottom_margin_property) {
2475                 s->bottom_margin = val;
2476                 return 0;
2477         }
2478
2479         if (property == private->cabc_mode_property) {
2480                 s->cabc_mode = val;
2481                 /*
2482                  * Pre-define lowpower and normal mode to make cabc
2483                  * easier to use.
2484                  */
2485                 if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_NORMAL) {
2486                         s->cabc_stage_up = 257;
2487                         s->cabc_stage_down = 255;
2488                         s->cabc_global_dn = 192;
2489                         s->cabc_calc_pixel_num = 995;
2490                 } else if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_LOWPOWER) {
2491                         s->cabc_stage_up = 260;
2492                         s->cabc_stage_down = 252;
2493                         s->cabc_global_dn = 180;
2494                         s->cabc_calc_pixel_num = 992;
2495                 }
2496                 return 0;
2497         }
2498
2499         if (property == private->cabc_stage_up_property) {
2500                 s->cabc_stage_up = val;
2501                 return 0;
2502         }
2503
2504         if (property == private->cabc_stage_down_property) {
2505                 s->cabc_stage_down = val;
2506                 return 0;
2507         }
2508
2509         if (property == private->cabc_calc_pixel_num_property) {
2510                 s->cabc_calc_pixel_num = val;
2511                 return 0;
2512         }
2513
2514         if (property == private->cabc_global_dn_property) {
2515                 s->cabc_global_dn = val;
2516                 return 0;
2517         }
2518
2519         if (property == private->cabc_lut_property) {
2520                 bool replaced;
2521                 ssize_t size = vop->cabc_lut_len * 4;
2522
2523                 return drm_atomic_replace_property_blob_from_id(crtc,
2524                                                                 &s->cabc_lut,
2525                                                                 val,
2526                                                                 size,
2527                                                                 &replaced);
2528         }
2529
2530         DRM_ERROR("failed to set vop crtc property\n");
2531         return -EINVAL;
2532 }
2533
2534 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2535                                u16 *blue, uint32_t start, uint32_t size)
2536 {
2537         struct vop *vop = to_vop(crtc);
2538         int end = min_t(u32, start + size, vop->lut_len);
2539         int i;
2540
2541         if (!vop->lut)
2542                 return;
2543
2544         for (i = start; i < end; i++)
2545                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2546                                                blue[i], i);
2547
2548         vop_crtc_load_lut(crtc);
2549 }
2550
2551 static const struct drm_crtc_funcs vop_crtc_funcs = {
2552         .gamma_set = vop_crtc_gamma_set,
2553         .set_config = drm_atomic_helper_set_config,
2554         .page_flip = drm_atomic_helper_page_flip,
2555         .destroy = vop_crtc_destroy,
2556         .reset = vop_crtc_reset,
2557         .set_property = drm_atomic_helper_crtc_set_property,
2558         .atomic_get_property = vop_crtc_atomic_get_property,
2559         .atomic_set_property = vop_crtc_atomic_set_property,
2560         .atomic_duplicate_state = vop_crtc_duplicate_state,
2561         .atomic_destroy_state = vop_crtc_destroy_state,
2562 };
2563
2564 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
2565 {
2566         struct vop *vop = container_of(work, struct vop, fb_unref_work);
2567         struct drm_framebuffer *fb = val;
2568
2569         drm_crtc_vblank_put(&vop->crtc);
2570         drm_framebuffer_unreference(fb);
2571 }
2572
2573 static void vop_handle_vblank(struct vop *vop)
2574 {
2575         struct drm_device *drm = vop->drm_dev;
2576         struct drm_crtc *crtc = &vop->crtc;
2577         unsigned long flags;
2578
2579         if (!vop_is_cfg_done_complete(vop))
2580                 return;
2581
2582         if (vop->event) {
2583                 spin_lock_irqsave(&drm->event_lock, flags);
2584
2585                 drm_crtc_send_vblank_event(crtc, vop->event);
2586                 drm_crtc_vblank_put(crtc);
2587                 vop->event = NULL;
2588
2589                 spin_unlock_irqrestore(&drm->event_lock, flags);
2590         }
2591
2592         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
2593                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
2594 }
2595
2596 static irqreturn_t vop_isr(int irq, void *data)
2597 {
2598         struct vop *vop = data;
2599         struct drm_crtc *crtc = &vop->crtc;
2600         uint32_t active_irqs;
2601         unsigned long flags;
2602         int ret = IRQ_NONE;
2603
2604         /*
2605          * interrupt register has interrupt status, enable and clear bits, we
2606          * must hold irq_lock to avoid a race with enable/disable_vblank().
2607         */
2608         spin_lock_irqsave(&vop->irq_lock, flags);
2609
2610         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2611         /* Clear all active interrupt sources */
2612         if (active_irqs)
2613                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2614
2615         spin_unlock_irqrestore(&vop->irq_lock, flags);
2616
2617         /* This is expected for vop iommu irqs, since the irq is shared */
2618         if (!active_irqs)
2619                 return IRQ_NONE;
2620
2621         if (active_irqs & DSP_HOLD_VALID_INTR) {
2622                 complete(&vop->dsp_hold_completion);
2623                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2624                 ret = IRQ_HANDLED;
2625         }
2626
2627         if (active_irqs & LINE_FLAG_INTR) {
2628                 complete(&vop->line_flag_completion);
2629                 active_irqs &= ~LINE_FLAG_INTR;
2630                 ret = IRQ_HANDLED;
2631         }
2632
2633         if (active_irqs & FS_INTR) {
2634                 drm_crtc_handle_vblank(crtc);
2635                 vop_handle_vblank(vop);
2636                 active_irqs &= ~FS_INTR;
2637                 ret = IRQ_HANDLED;
2638         }
2639
2640 #define ERROR_HANDLER(x) \
2641         do { \
2642                 if (active_irqs & x##_INTR) {\
2643                         DRM_DEV_ERROR_RATELIMITED(vop->dev, #x " irq err\n"); \
2644                         active_irqs &= ~x##_INTR; \
2645                         ret = IRQ_HANDLED; \
2646                 } \
2647         } while (0)
2648
2649         ERROR_HANDLER(BUS_ERROR);
2650         ERROR_HANDLER(WIN0_EMPTY);
2651         ERROR_HANDLER(WIN1_EMPTY);
2652         ERROR_HANDLER(WIN2_EMPTY);
2653         ERROR_HANDLER(WIN3_EMPTY);
2654         ERROR_HANDLER(HWC_EMPTY);
2655         ERROR_HANDLER(POST_BUF_EMPTY);
2656
2657         /* Unhandled irqs are spurious. */
2658         if (active_irqs)
2659                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2660
2661         return ret;
2662 }
2663
2664 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2665                           unsigned long possible_crtcs)
2666 {
2667         struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2668         struct drm_plane *share = NULL;
2669         unsigned int rotations = 0;
2670         struct drm_property *prop;
2671         uint64_t feature = 0;
2672         int ret;
2673
2674         if (win->parent)
2675                 share = &win->parent->base;
2676
2677         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2678                                    possible_crtcs, &vop_plane_funcs,
2679                                    win->data_formats, win->nformats, win->type);
2680         if (ret) {
2681                 DRM_ERROR("failed to initialize plane\n");
2682                 return ret;
2683         }
2684         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2685         drm_object_attach_property(&win->base.base,
2686                                    vop->plane_zpos_prop, win->win_id);
2687
2688         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2689                 rotations |= BIT(DRM_REFLECT_X);
2690
2691         if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2692                 rotations |= BIT(DRM_REFLECT_Y);
2693
2694                 prop = drm_property_create_bool(vop->drm_dev,
2695                                                 DRM_MODE_PROP_ATOMIC,
2696                                                 "LOGO_YMIRROR");
2697                 if (!prop)
2698                         return -ENOMEM;
2699                 private->logo_ymirror_prop = prop;
2700         }
2701
2702         if (rotations) {
2703                 rotations |= BIT(DRM_ROTATE_0);
2704                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2705                                                          rotations);
2706                 if (!prop) {
2707                         DRM_ERROR("failed to create zpos property\n");
2708                         return -EINVAL;
2709                 }
2710                 drm_object_attach_property(&win->base.base, prop,
2711                                            BIT(DRM_ROTATE_0));
2712                 win->rotation_prop = prop;
2713         }
2714         if (win->phy->scl)
2715                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2716         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2717             VOP_WIN_SUPPORT(vop, win, alpha_en))
2718                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2719
2720         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2721                                    feature);
2722
2723         return 0;
2724 }
2725
2726 static int vop_create_crtc(struct vop *vop)
2727 {
2728         struct device *dev = vop->dev;
2729         const struct vop_data *vop_data = vop->data;
2730         struct drm_device *drm_dev = vop->drm_dev;
2731         struct rockchip_drm_private *private = drm_dev->dev_private;
2732         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2733         struct drm_crtc *crtc = &vop->crtc;
2734         struct device_node *port;
2735         uint64_t feature = 0;
2736         int ret;
2737         int i;
2738
2739         /*
2740          * Create drm_plane for primary and cursor planes first, since we need
2741          * to pass them to drm_crtc_init_with_planes, which sets the
2742          * "possible_crtcs" to the newly initialized crtc.
2743          */
2744         for (i = 0; i < vop->num_wins; i++) {
2745                 struct vop_win *win = &vop->win[i];
2746
2747                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2748                     win->type != DRM_PLANE_TYPE_CURSOR)
2749                         continue;
2750
2751                 ret = vop_plane_init(vop, win, 0);
2752                 if (ret)
2753                         goto err_cleanup_planes;
2754
2755                 plane = &win->base;
2756                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2757                         primary = plane;
2758                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2759                         cursor = plane;
2760
2761         }
2762
2763         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2764                                         &vop_crtc_funcs, NULL);
2765         if (ret)
2766                 goto err_cleanup_planes;
2767
2768         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2769
2770         /*
2771          * Create drm_planes for overlay windows with possible_crtcs restricted
2772          * to the newly created crtc.
2773          */
2774         for (i = 0; i < vop->num_wins; i++) {
2775                 struct vop_win *win = &vop->win[i];
2776                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2777
2778                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2779                         continue;
2780
2781                 ret = vop_plane_init(vop, win, possible_crtcs);
2782                 if (ret)
2783                         goto err_cleanup_crtc;
2784         }
2785
2786         port = of_get_child_by_name(dev->of_node, "port");
2787         if (!port) {
2788                 DRM_ERROR("no port node found in %s\n",
2789                           dev->of_node->full_name);
2790                 ret = -ENOENT;
2791                 goto err_cleanup_crtc;
2792         }
2793
2794         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
2795                            vop_fb_unref_worker);
2796
2797         init_completion(&vop->dsp_hold_completion);
2798         init_completion(&vop->line_flag_completion);
2799         crtc->port = port;
2800         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2801
2802         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2803         if (ret)
2804                 goto err_unregister_crtc_funcs;
2805 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2806         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2807
2808         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2809         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2810         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2811         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2812
2813 #undef VOP_ATTACH_MODE_CONFIG_PROP
2814
2815         drm_object_attach_property(&crtc->base, private->cabc_lut_property, 0);
2816         drm_object_attach_property(&crtc->base, private->cabc_mode_property, 0);
2817         drm_object_attach_property(&crtc->base, private->cabc_stage_up_property, 0);
2818         drm_object_attach_property(&crtc->base, private->cabc_stage_down_property, 0);
2819         drm_object_attach_property(&crtc->base, private->cabc_global_dn_property, 0);
2820         drm_object_attach_property(&crtc->base, private->cabc_calc_pixel_num_property, 0);
2821
2822         if (vop_data->feature & VOP_FEATURE_AFBDC)
2823                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2824         drm_object_attach_property(&crtc->base, vop->feature_prop,
2825                                    feature);
2826         if (vop->lut_regs) {
2827                 u16 *r_base, *g_base, *b_base;
2828                 u32 lut_len = vop->lut_len;
2829
2830                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2831                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2832                                               GFP_KERNEL);
2833                 if (!vop->lut)
2834                         return -ENOMEM;
2835
2836                 r_base = crtc->gamma_store;
2837                 g_base = r_base + crtc->gamma_size;
2838                 b_base = g_base + crtc->gamma_size;
2839
2840                 for (i = 0; i < lut_len; i++) {
2841                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2842                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2843                                                        &g_base[i], &b_base[i],
2844                                                        i);
2845                 }
2846         }
2847
2848         return 0;
2849
2850 err_unregister_crtc_funcs:
2851         rockchip_unregister_crtc_funcs(crtc);
2852 err_cleanup_crtc:
2853         drm_crtc_cleanup(crtc);
2854 err_cleanup_planes:
2855         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2856                                  head)
2857                 drm_plane_cleanup(plane);
2858         return ret;
2859 }
2860
2861 static void vop_destroy_crtc(struct vop *vop)
2862 {
2863         struct drm_crtc *crtc = &vop->crtc;
2864         struct drm_device *drm_dev = vop->drm_dev;
2865         struct drm_plane *plane, *tmp;
2866
2867         rockchip_unregister_crtc_funcs(crtc);
2868         of_node_put(crtc->port);
2869
2870         /*
2871          * We need to cleanup the planes now.  Why?
2872          *
2873          * The planes are "&vop->win[i].base".  That means the memory is
2874          * all part of the big "struct vop" chunk of memory.  That memory
2875          * was devm allocated and associated with this component.  We need to
2876          * free it ourselves before vop_unbind() finishes.
2877          */
2878         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2879                                  head)
2880                 vop_plane_destroy(plane);
2881
2882         /*
2883          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2884          * references the CRTC.
2885          */
2886         drm_crtc_cleanup(crtc);
2887         drm_flip_work_cleanup(&vop->fb_unref_work);
2888 }
2889
2890 /*
2891  * Initialize the vop->win array elements.
2892  */
2893 static int vop_win_init(struct vop *vop)
2894 {
2895         const struct vop_data *vop_data = vop->data;
2896         unsigned int i, j;
2897         unsigned int num_wins = 0;
2898         struct drm_property *prop;
2899         static const struct drm_prop_enum_list props[] = {
2900                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2901                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2902         };
2903         static const struct drm_prop_enum_list crtc_props[] = {
2904                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2905         };
2906
2907         for (i = 0; i < vop_data->win_size; i++) {
2908                 struct vop_win *vop_win = &vop->win[num_wins];
2909                 const struct vop_win_data *win_data = &vop_data->win[i];
2910
2911                 if (!win_data->phy)
2912                         continue;
2913
2914                 vop_win->phy = win_data->phy;
2915                 vop_win->csc = win_data->csc;
2916                 vop_win->offset = win_data->base;
2917                 vop_win->type = win_data->type;
2918                 vop_win->data_formats = win_data->phy->data_formats;
2919                 vop_win->nformats = win_data->phy->nformats;
2920                 vop_win->vop = vop;
2921                 vop_win->win_id = i;
2922                 vop_win->area_id = 0;
2923                 num_wins++;
2924
2925                 for (j = 0; j < win_data->area_size; j++) {
2926                         struct vop_win *vop_area = &vop->win[num_wins];
2927                         const struct vop_win_phy *area = win_data->area[j];
2928
2929                         vop_area->parent = vop_win;
2930                         vop_area->offset = vop_win->offset;
2931                         vop_area->phy = area;
2932                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2933                         vop_area->data_formats = vop_win->data_formats;
2934                         vop_area->nformats = vop_win->nformats;
2935                         vop_area->vop = vop;
2936                         vop_area->win_id = i;
2937                         vop_area->area_id = j;
2938                         num_wins++;
2939                 }
2940         }
2941
2942         vop->num_wins = num_wins;
2943
2944         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2945                                          "ZPOS", 0, vop->data->win_size);
2946         if (!prop) {
2947                 DRM_ERROR("failed to create zpos property\n");
2948                 return -EINVAL;
2949         }
2950         vop->plane_zpos_prop = prop;
2951
2952         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2953                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2954                                 props, ARRAY_SIZE(props),
2955                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2956                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2957         if (!vop->plane_feature_prop) {
2958                 DRM_ERROR("failed to create feature property\n");
2959                 return -EINVAL;
2960         }
2961
2962         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2963                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2964                                 crtc_props, ARRAY_SIZE(crtc_props),
2965                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2966         if (!vop->feature_prop) {
2967                 DRM_ERROR("failed to create vop feature property\n");
2968                 return -EINVAL;
2969         }
2970
2971         return 0;
2972 }
2973
2974 /**
2975  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2976  * @crtc: CRTC to enable line flag
2977  * @line_num: interested line number
2978  * @mstimeout: millisecond for timeout
2979  *
2980  * Driver would hold here until the interested line flag interrupt have
2981  * happened or timeout to wait.
2982  *
2983  * Returns:
2984  * Zero on success, negative errno on failure.
2985  */
2986 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2987                                 unsigned int mstimeout)
2988 {
2989         struct vop *vop = to_vop(crtc);
2990         unsigned long jiffies_left;
2991         int ret = 0;
2992
2993         if (!crtc || !vop->is_enabled)
2994                 return -ENODEV;
2995
2996         mutex_lock(&vop->vop_lock);
2997
2998         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2999                 ret = -EINVAL;
3000                 goto out;
3001         }
3002
3003         if (vop_line_flag_irq_is_enabled(vop)) {
3004                 ret = -EBUSY;
3005                 goto out;
3006         }
3007
3008         reinit_completion(&vop->line_flag_completion);
3009         vop_line_flag_irq_enable(vop, line_num);
3010
3011         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
3012                                                    msecs_to_jiffies(mstimeout));
3013         vop_line_flag_irq_disable(vop);
3014
3015         if (jiffies_left == 0) {
3016                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
3017                 ret = -ETIMEDOUT;
3018                 goto out;
3019         }
3020
3021 out:
3022         mutex_unlock(&vop->vop_lock);
3023
3024         return ret;
3025 }
3026 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
3027
3028 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
3029                              void *data)
3030 {
3031         if (event == DEVFREQ_PRECHANGE)
3032                 mutex_lock(&dmc_vop->vop_lock);
3033         else if (event == DEVFREQ_POSTCHANGE)
3034                 mutex_unlock(&dmc_vop->vop_lock);
3035
3036         return NOTIFY_OK;
3037 }
3038
3039 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
3040 {
3041         if (!dmc_vop)
3042                 return -ENOMEM;
3043
3044         dmc_vop->devfreq = devfreq;
3045         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
3046         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
3047                                   DEVFREQ_TRANSITION_NOTIFIER);
3048         return 0;
3049 }
3050 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
3051
3052 static void vop_backlight_config_done(struct device *dev, bool async)
3053 {
3054         struct vop *vop = dev_get_drvdata(dev);
3055
3056         if (vop && vop->is_enabled) {
3057                 int dle;
3058
3059                 vop_cfg_done(vop);
3060                 if (!async) {
3061                         #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
3062                         readx_poll_timeout(CTRL_GET, cfg_done,
3063                                            dle, !dle, 5, 33333);
3064                         #undef CTRL_GET
3065                 }
3066         }
3067 }
3068
3069 static const struct rockchip_sub_backlight_ops rockchip_sub_backlight_ops = {
3070         .config_done = vop_backlight_config_done,
3071 };
3072
3073 static int vop_bind(struct device *dev, struct device *master, void *data)
3074 {
3075         struct platform_device *pdev = to_platform_device(dev);
3076         const struct vop_data *vop_data;
3077         struct drm_device *drm_dev = data;
3078         struct vop *vop;
3079         struct resource *res;
3080         size_t alloc_size;
3081         int ret, irq, i;
3082         int num_wins = 0;
3083
3084         vop_data = of_device_get_match_data(dev);
3085         if (!vop_data)
3086                 return -ENODEV;
3087
3088         for (i = 0; i < vop_data->win_size; i++) {
3089                 const struct vop_win_data *win_data = &vop_data->win[i];
3090
3091                 num_wins += win_data->area_size + 1;
3092         }
3093
3094         /* Allocate vop struct and its vop_win array */
3095         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
3096         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3097         if (!vop)
3098                 return -ENOMEM;
3099
3100         vop->dev = dev;
3101         vop->data = vop_data;
3102         vop->drm_dev = drm_dev;
3103         vop->num_wins = num_wins;
3104         dev_set_drvdata(dev, vop);
3105
3106         ret = vop_win_init(vop);
3107         if (ret)
3108                 return ret;
3109
3110         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3111         if (!res) {
3112                 dev_warn(vop->dev, "failed to get vop register byname\n");
3113                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3114         }
3115         vop->regs = devm_ioremap_resource(dev, res);
3116         if (IS_ERR(vop->regs))
3117                 return PTR_ERR(vop->regs);
3118         vop->len = resource_size(res);
3119
3120         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
3121         if (!vop->regsbak)
3122                 return -ENOMEM;
3123
3124         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
3125         vop->lut_regs = devm_ioremap_resource(dev, res);
3126         if (IS_ERR(vop->lut_regs)) {
3127                 dev_warn(vop->dev, "failed to get vop lut registers\n");
3128                 vop->lut_regs = NULL;
3129         }
3130         if (vop->lut_regs) {
3131                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
3132                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
3133                         dev_err(vop->dev, "unsupport lut sizes %d\n",
3134                                 vop->lut_len);
3135                         return -EINVAL;
3136                 }
3137         }
3138
3139         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cabc_lut");
3140         vop->cabc_lut_regs = devm_ioremap_resource(dev, res);
3141         if (IS_ERR(vop->cabc_lut_regs)) {
3142                 dev_warn(vop->dev, "failed to get vop cabc lut registers\n");
3143                 vop->cabc_lut_regs = NULL;
3144         }
3145
3146         if (vop->cabc_lut_regs) {
3147                 vop->cabc_lut_len = resource_size(res) >> 2;
3148                 if (vop->cabc_lut_len != 128) {
3149                         dev_err(vop->dev, "unsupport cabc lut sizes %d\n",
3150                                 vop->cabc_lut_len);
3151                         return -EINVAL;
3152                 }
3153         }
3154
3155         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
3156         if (IS_ERR(vop->hclk)) {
3157                 dev_err(vop->dev, "failed to get hclk source\n");
3158                 return PTR_ERR(vop->hclk);
3159         }
3160         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
3161         if (IS_ERR(vop->aclk)) {
3162                 dev_err(vop->dev, "failed to get aclk source\n");
3163                 return PTR_ERR(vop->aclk);
3164         }
3165         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
3166         if (IS_ERR(vop->dclk)) {
3167                 dev_err(vop->dev, "failed to get dclk source\n");
3168                 return PTR_ERR(vop->dclk);
3169         }
3170
3171         vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
3172         if (PTR_ERR(vop->dclk_source) == -ENOENT) {
3173                 vop->dclk_source = NULL;
3174         } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
3175                 return -EPROBE_DEFER;
3176         } else if (IS_ERR(vop->dclk_source)) {
3177                 dev_err(vop->dev, "failed to get dclk source parent\n");
3178                 return PTR_ERR(vop->dclk_source);
3179         }
3180
3181         irq = platform_get_irq(pdev, 0);
3182         if (irq < 0) {
3183                 dev_err(dev, "cannot find irq for vop\n");
3184                 return irq;
3185         }
3186         vop->irq = (unsigned int)irq;
3187
3188         spin_lock_init(&vop->reg_lock);
3189         spin_lock_init(&vop->irq_lock);
3190         mutex_init(&vop->vop_lock);
3191
3192         mutex_init(&vop->vsync_mutex);
3193
3194         ret = devm_request_irq(dev, vop->irq, vop_isr,
3195                                IRQF_SHARED, dev_name(dev), vop);
3196         if (ret)
3197                 return ret;
3198
3199         /* IRQ is initially disabled; it gets enabled in power_on */
3200         disable_irq(vop->irq);
3201
3202         ret = vop_create_crtc(vop);
3203         if (ret)
3204                 return ret;
3205
3206         pm_runtime_enable(&pdev->dev);
3207
3208         of_rockchip_drm_sub_backlight_register(dev, &vop->crtc,
3209                                                &rockchip_sub_backlight_ops);
3210
3211         dmc_vop = vop;
3212
3213         return 0;
3214 }
3215
3216 static void vop_unbind(struct device *dev, struct device *master, void *data)
3217 {
3218         struct vop *vop = dev_get_drvdata(dev);
3219
3220         pm_runtime_disable(dev);
3221         vop_destroy_crtc(vop);
3222 }
3223
3224 const struct component_ops vop_component_ops = {
3225         .bind = vop_bind,
3226         .unbind = vop_unbind,
3227 };
3228 EXPORT_SYMBOL_GPL(vop_component_ops);