2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
33 #include <linux/sort.h>
34 #include <uapi/drm/rockchip_drm.h>
36 #include "rockchip_drm_drv.h"
37 #include "rockchip_drm_gem.h"
38 #include "rockchip_drm_fb.h"
39 #include "rockchip_drm_vop.h"
41 #define VOP_REG_SUPPORT(vop, reg) \
42 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
43 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
44 reg.end_minor >= VOP_MINOR(vop->data->version) && \
47 #define VOP_WIN_SUPPORT(vop, win, name) \
48 VOP_REG_SUPPORT(vop, win->phy->name)
50 #define VOP_CTRL_SUPPORT(vop, win, name) \
51 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
53 #define VOP_INTR_SUPPORT(vop, win, name) \
54 VOP_REG_SUPPORT(vop, vop->data->intr->name)
56 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
57 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
59 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
61 if (VOP_REG_SUPPORT(vop, reg)) \
62 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
63 v, reg.write_mask, relaxed); \
65 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
68 #define REG_SET(x, name, off, reg, v, relaxed) \
69 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
70 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
71 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
73 #define VOP_WIN_SET(x, win, name, v) \
74 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
75 #define VOP_SCL_SET(x, win, name, v) \
76 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
77 #define VOP_SCL_SET_EXT(x, win, name, v) \
78 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
80 #define VOP_CTRL_SET(x, name, v) \
81 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
83 #define VOP_INTR_GET(vop, name) \
84 vop_read_reg(vop, 0, &vop->data->ctrl->name)
86 #define VOP_INTR_SET(vop, name, mask, v) \
87 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
90 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
92 int i, reg = 0, mask = 0; \
93 for (i = 0; i < vop->data->intr->nintrs; i++) { \
94 if (vop->data->intr->intrs[i] & type) { \
99 VOP_INTR_SET(vop, name, mask, reg); \
101 #define VOP_INTR_GET_TYPE(vop, name, type) \
102 vop_get_intr_type(vop, &vop->data->intr->name, type)
104 #define VOP_CTRL_GET(x, name) \
105 vop_read_reg(x, 0, &vop->data->ctrl->name)
107 #define VOP_WIN_GET(x, win, name) \
108 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
110 #define VOP_WIN_NAME(win, name) \
111 (vop_get_win_phy(win, &win->phy->name)->name)
113 #define VOP_WIN_GET_YRGBADDR(vop, win) \
114 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
116 #define to_vop(x) container_of(x, struct vop, crtc)
117 #define to_vop_win(x) container_of(x, struct vop_win, base)
118 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
125 struct vop_plane_state {
126 struct drm_plane_state base;
130 struct drm_rect dest;
137 struct vop_win *parent;
138 struct drm_plane base;
143 enum drm_plane_type type;
144 const struct vop_win_phy *phy;
145 const uint32_t *data_formats;
149 struct drm_property *rotation_prop;
150 struct vop_plane_state state;
154 struct drm_crtc crtc;
156 struct drm_device *drm_dev;
157 struct drm_property *plane_zpos_prop;
158 struct drm_property *plane_feature_prop;
159 bool is_iommu_enabled;
160 bool is_iommu_needed;
163 /* mutex vsync_ work */
164 struct mutex vsync_mutex;
165 bool vsync_work_pending;
166 struct completion dsp_hold_completion;
167 struct completion wait_update_complete;
168 struct drm_pending_vblank_event *event;
170 const struct vop_data *data;
176 /* physical map length of vop register */
179 /* one time only one process allowed to config the register */
181 /* lock vop irq reg */
190 /* vop share memory frequency */
194 struct reset_control *dclk_rst;
196 struct vop_win win[];
199 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
201 writel(v, vop->regs + offset);
202 vop->regsbak[offset >> 2] = v;
205 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
207 return readl(vop->regs + offset);
210 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
211 const struct vop_reg *reg)
213 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
216 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
217 uint32_t mask, uint32_t shift, uint32_t v,
218 bool write_mask, bool relaxed)
224 v = ((v & mask) << shift) | (mask << (shift + 16));
226 uint32_t cached_val = vop->regsbak[offset >> 2];
228 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
229 vop->regsbak[offset >> 2] = v;
233 writel_relaxed(v, vop->regs + offset);
235 writel(v, vop->regs + offset);
238 static inline const struct vop_win_phy *
239 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
241 if (!reg->mask && win->parent)
242 return win->parent->phy;
247 static inline uint32_t vop_get_intr_type(struct vop *vop,
248 const struct vop_reg *reg, int type)
251 uint32_t regs = vop_read_reg(vop, 0, reg);
253 for (i = 0; i < vop->data->intr->nintrs; i++) {
254 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
255 ret |= vop->data->intr->intrs[i];
261 static inline void vop_cfg_done(struct vop *vop)
263 VOP_CTRL_SET(vop, cfg_done, 1);
266 static bool vop_is_allwin_disabled(struct vop *vop)
270 for (i = 0; i < vop->num_wins; i++) {
271 struct vop_win *win = &vop->win[i];
273 if (VOP_WIN_GET(vop, win, enable) != 0)
280 static bool vop_is_cfg_done_complete(struct vop *vop)
282 return VOP_CTRL_GET(vop, cfg_done) ? false : true;
285 static bool has_rb_swapped(uint32_t format)
288 case DRM_FORMAT_XBGR8888:
289 case DRM_FORMAT_ABGR8888:
290 case DRM_FORMAT_BGR888:
291 case DRM_FORMAT_BGR565:
298 static enum vop_data_format vop_convert_format(uint32_t format)
301 case DRM_FORMAT_XRGB8888:
302 case DRM_FORMAT_ARGB8888:
303 case DRM_FORMAT_XBGR8888:
304 case DRM_FORMAT_ABGR8888:
305 return VOP_FMT_ARGB8888;
306 case DRM_FORMAT_RGB888:
307 case DRM_FORMAT_BGR888:
308 return VOP_FMT_RGB888;
309 case DRM_FORMAT_RGB565:
310 case DRM_FORMAT_BGR565:
311 return VOP_FMT_RGB565;
312 case DRM_FORMAT_NV12:
313 return VOP_FMT_YUV420SP;
314 case DRM_FORMAT_NV16:
315 return VOP_FMT_YUV422SP;
316 case DRM_FORMAT_NV24:
317 return VOP_FMT_YUV444SP;
319 DRM_ERROR("unsupport format[%08x]\n", format);
324 static bool is_yuv_support(uint32_t format)
327 case DRM_FORMAT_NV12:
328 case DRM_FORMAT_NV16:
329 case DRM_FORMAT_NV24:
336 static bool is_alpha_support(uint32_t format)
339 case DRM_FORMAT_ARGB8888:
340 case DRM_FORMAT_ABGR8888:
347 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
348 uint32_t dst, bool is_horizontal,
349 int vsu_mode, int *vskiplines)
351 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
354 if (mode == SCALE_UP)
355 val = GET_SCL_FT_BIC(src, dst);
356 else if (mode == SCALE_DOWN)
357 val = GET_SCL_FT_BILI_DN(src, dst);
359 if (mode == SCALE_UP) {
360 if (vsu_mode == SCALE_UP_BIL)
361 val = GET_SCL_FT_BILI_UP(src, dst);
363 val = GET_SCL_FT_BIC(src, dst);
364 } else if (mode == SCALE_DOWN) {
366 *vskiplines = scl_get_vskiplines(src, dst);
367 val = scl_get_bili_dn_vskip(src, dst,
370 val = GET_SCL_FT_BILI_DN(src, dst);
378 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
379 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
380 uint32_t dst_h, uint32_t pixel_format)
382 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
383 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
384 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
385 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
386 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
387 bool is_yuv = is_yuv_support(pixel_format);
388 uint16_t cbcr_src_w = src_w / hsub;
389 uint16_t cbcr_src_h = src_h / vsub;
399 DRM_ERROR("Maximum destination width (3840) exceeded\n");
403 if (!win->phy->scl->ext) {
404 VOP_SCL_SET(vop, win, scale_yrgb_x,
405 scl_cal_scale2(src_w, dst_w));
406 VOP_SCL_SET(vop, win, scale_yrgb_y,
407 scl_cal_scale2(src_h, dst_h));
409 VOP_SCL_SET(vop, win, scale_cbcr_x,
410 scl_cal_scale2(cbcr_src_w, dst_w));
411 VOP_SCL_SET(vop, win, scale_cbcr_y,
412 scl_cal_scale2(cbcr_src_h, dst_h));
417 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
418 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
421 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
422 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
423 if (cbcr_hor_scl_mode == SCALE_DOWN)
424 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
426 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
428 if (yrgb_hor_scl_mode == SCALE_DOWN)
429 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
431 lb_mode = scl_vop_cal_lb_mode(src_w, false);
434 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
435 if (lb_mode == LB_RGB_3840X2) {
436 if (yrgb_ver_scl_mode != SCALE_NONE) {
437 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
440 if (cbcr_ver_scl_mode != SCALE_NONE) {
441 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
444 vsu_mode = SCALE_UP_BIL;
445 } else if (lb_mode == LB_RGB_2560X4) {
446 vsu_mode = SCALE_UP_BIL;
448 vsu_mode = SCALE_UP_BIC;
451 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
453 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
454 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
455 false, vsu_mode, &vskiplines);
456 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
458 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
459 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
461 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
462 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
463 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
464 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
465 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
469 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
470 dst_w, true, 0, NULL);
471 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
472 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
473 dst_h, false, vsu_mode, &vskiplines);
474 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
476 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
477 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
478 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
479 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
480 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
481 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
482 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
486 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
490 spin_lock_irqsave(&vop->irq_lock, flags);
492 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
494 spin_unlock_irqrestore(&vop->irq_lock, flags);
497 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
501 spin_lock_irqsave(&vop->irq_lock, flags);
503 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
505 spin_unlock_irqrestore(&vop->irq_lock, flags);
508 static void vop_enable(struct drm_crtc *crtc)
510 struct vop *vop = to_vop(crtc);
513 ret = clk_prepare_enable(vop->hclk);
515 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
519 ret = clk_prepare_enable(vop->dclk);
521 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
522 goto err_disable_hclk;
525 ret = clk_prepare_enable(vop->aclk);
527 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
528 goto err_disable_dclk;
531 ret = pm_runtime_get_sync(vop->dev);
533 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
537 memcpy(vop->regsbak, vop->regs, vop->len);
539 VOP_CTRL_SET(vop, global_regdone_en, 1);
540 VOP_CTRL_SET(vop, dsp_blank, 0);
542 for (i = 0; i < vop->num_wins; i++) {
543 struct vop_win *win = &vop->win[i];
545 VOP_WIN_SET(vop, win, gate, 1);
547 vop->is_enabled = true;
549 spin_lock(&vop->reg_lock);
551 VOP_CTRL_SET(vop, standby, 0);
553 spin_unlock(&vop->reg_lock);
555 enable_irq(vop->irq);
557 drm_crtc_vblank_on(crtc);
562 clk_disable_unprepare(vop->dclk);
564 clk_disable_unprepare(vop->hclk);
567 static void vop_crtc_disable(struct drm_crtc *crtc)
569 struct vop *vop = to_vop(crtc);
573 * We need to make sure that all windows are disabled before we
574 * disable that crtc. Otherwise we might try to scan from a destroyed
577 for (i = 0; i < vop->num_wins; i++) {
578 struct vop_win *win = &vop->win[i];
580 spin_lock(&vop->reg_lock);
581 VOP_WIN_SET(vop, win, enable, 0);
582 spin_unlock(&vop->reg_lock);
586 drm_crtc_vblank_off(crtc);
589 * Vop standby will take effect at end of current frame,
590 * if dsp hold valid irq happen, it means standby complete.
592 * we must wait standby complete when we want to disable aclk,
593 * if not, memory bus maybe dead.
595 reinit_completion(&vop->dsp_hold_completion);
596 vop_dsp_hold_valid_irq_enable(vop);
598 spin_lock(&vop->reg_lock);
600 VOP_CTRL_SET(vop, standby, 1);
602 spin_unlock(&vop->reg_lock);
604 wait_for_completion(&vop->dsp_hold_completion);
606 vop_dsp_hold_valid_irq_disable(vop);
608 disable_irq(vop->irq);
610 vop->is_enabled = false;
611 if (vop->is_iommu_enabled) {
613 * vop standby complete, so iommu detach is safe.
615 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
616 vop->is_iommu_enabled = false;
619 pm_runtime_put(vop->dev);
620 clk_disable_unprepare(vop->dclk);
621 clk_disable_unprepare(vop->aclk);
622 clk_disable_unprepare(vop->hclk);
625 static void vop_plane_destroy(struct drm_plane *plane)
627 drm_plane_cleanup(plane);
630 static int vop_plane_prepare_fb(struct drm_plane *plane,
631 const struct drm_plane_state *new_state)
633 if (plane->state->fb)
634 drm_framebuffer_reference(plane->state->fb);
639 static void vop_plane_cleanup_fb(struct drm_plane *plane,
640 const struct drm_plane_state *old_state)
643 drm_framebuffer_unreference(old_state->fb);
646 static int vop_plane_atomic_check(struct drm_plane *plane,
647 struct drm_plane_state *state)
649 struct drm_crtc *crtc = state->crtc;
650 struct drm_framebuffer *fb = state->fb;
651 struct vop_win *win = to_vop_win(plane);
652 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
653 struct drm_crtc_state *crtc_state;
656 struct drm_rect *dest = &vop_plane_state->dest;
657 struct drm_rect *src = &vop_plane_state->src;
658 struct drm_rect clip;
659 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
660 DRM_PLANE_HELPER_NO_SCALING;
661 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
662 DRM_PLANE_HELPER_NO_SCALING;
663 unsigned long offset;
666 crtc = crtc ? crtc : plane->state->crtc;
668 * Both crtc or plane->state->crtc can be null.
673 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
674 if (IS_ERR(crtc_state))
675 return PTR_ERR(crtc_state);
677 src->x1 = state->src_x;
678 src->y1 = state->src_y;
679 src->x2 = state->src_x + state->src_w;
680 src->y2 = state->src_y + state->src_h;
681 dest->x1 = state->crtc_x;
682 dest->y1 = state->crtc_y;
683 dest->x2 = state->crtc_x + state->crtc_w;
684 dest->y2 = state->crtc_y + state->crtc_h;
688 clip.x2 = crtc_state->mode.hdisplay;
689 clip.y2 = crtc_state->mode.vdisplay;
691 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
695 true, true, &visible);
702 vop_plane_state->format = vop_convert_format(fb->pixel_format);
703 if (vop_plane_state->format < 0)
704 return vop_plane_state->format;
707 * Src.x1 can be odd when do clip, but yuv plane start point
708 * need align with 2 pixel.
710 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
713 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
714 if (state->rotation & BIT(DRM_REFLECT_Y))
715 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
717 offset += (src->y1 >> 16) * fb->pitches[0];
719 dma_addr = rockchip_fb_get_dma_addr(fb, 0);
720 vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
721 if (is_yuv_support(fb->pixel_format)) {
722 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
723 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
724 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
726 offset = (src->x1 >> 16) * bpp / hsub;
727 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
729 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
730 dma_addr += offset + fb->offsets[1];
731 vop_plane_state->uv_mst = dma_addr;
734 vop_plane_state->enable = true;
739 vop_plane_state->enable = false;
743 static void vop_plane_atomic_disable(struct drm_plane *plane,
744 struct drm_plane_state *old_state)
746 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
747 struct vop_win *win = to_vop_win(plane);
748 struct vop *vop = to_vop(old_state->crtc);
750 if (!old_state->crtc)
753 spin_lock(&vop->reg_lock);
755 VOP_WIN_SET(vop, win, enable, 0);
757 spin_unlock(&vop->reg_lock);
759 vop_plane_state->enable = false;
762 static void vop_plane_atomic_update(struct drm_plane *plane,
763 struct drm_plane_state *old_state)
765 struct drm_plane_state *state = plane->state;
766 struct drm_crtc *crtc = state->crtc;
767 struct vop_win *win = to_vop_win(plane);
768 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
769 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
770 struct vop *vop = to_vop(state->crtc);
771 struct drm_framebuffer *fb = state->fb;
772 unsigned int actual_w, actual_h;
773 unsigned int dsp_stx, dsp_sty;
774 uint32_t act_info, dsp_info, dsp_st;
775 struct drm_rect *src = &vop_plane_state->src;
776 struct drm_rect *dest = &vop_plane_state->dest;
777 int ymirror, xmirror;
782 * can't update plane when vop is disabled.
787 if (!vop_plane_state->enable) {
788 vop_plane_atomic_disable(plane, old_state);
792 actual_w = drm_rect_width(src) >> 16;
793 actual_h = drm_rect_height(src) >> 16;
794 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
796 dsp_info = (drm_rect_height(dest) - 1) << 16;
797 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
799 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
800 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
801 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
803 ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
804 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
806 spin_lock(&vop->reg_lock);
808 VOP_WIN_SET(vop, win, xmirror, xmirror);
809 VOP_WIN_SET(vop, win, ymirror, ymirror);
810 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
811 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
812 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
813 if (is_yuv_support(fb->pixel_format)) {
814 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
815 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
818 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
819 drm_rect_width(dest), drm_rect_height(dest),
822 VOP_WIN_SET(vop, win, act_info, act_info);
823 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
824 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
826 rb_swap = has_rb_swapped(fb->pixel_format);
827 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
829 if (is_alpha_support(fb->pixel_format) &&
830 (s->dsp_layer_sel & 0x3) != win->win_id) {
831 VOP_WIN_SET(vop, win, dst_alpha_ctl,
832 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
833 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
834 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
835 SRC_BLEND_M0(ALPHA_PER_PIX) |
836 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
837 SRC_FACTOR_M0(ALPHA_ONE);
838 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
839 VOP_WIN_SET(vop, win, alpha_mode, 1);
840 VOP_WIN_SET(vop, win, alpha_en, 1);
842 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
843 VOP_WIN_SET(vop, win, alpha_en, 0);
846 VOP_WIN_SET(vop, win, enable, 1);
847 spin_unlock(&vop->reg_lock);
848 vop->is_iommu_needed = true;
851 static const struct drm_plane_helper_funcs plane_helper_funcs = {
852 .prepare_fb = vop_plane_prepare_fb,
853 .cleanup_fb = vop_plane_cleanup_fb,
854 .atomic_check = vop_plane_atomic_check,
855 .atomic_update = vop_plane_atomic_update,
856 .atomic_disable = vop_plane_atomic_disable,
859 void vop_atomic_plane_reset(struct drm_plane *plane)
861 struct vop_win *win = to_vop_win(plane);
862 struct vop_plane_state *vop_plane_state =
863 to_vop_plane_state(plane->state);
865 if (plane->state && plane->state->fb)
866 drm_framebuffer_unreference(plane->state->fb);
868 kfree(vop_plane_state);
869 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
870 if (!vop_plane_state)
873 vop_plane_state->zpos = win->win_id;
874 plane->state = &vop_plane_state->base;
875 plane->state->plane = plane;
878 struct drm_plane_state *
879 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
881 struct vop_plane_state *old_vop_plane_state;
882 struct vop_plane_state *vop_plane_state;
884 if (WARN_ON(!plane->state))
887 old_vop_plane_state = to_vop_plane_state(plane->state);
888 vop_plane_state = kmemdup(old_vop_plane_state,
889 sizeof(*vop_plane_state), GFP_KERNEL);
890 if (!vop_plane_state)
893 __drm_atomic_helper_plane_duplicate_state(plane,
894 &vop_plane_state->base);
896 return &vop_plane_state->base;
899 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
900 struct drm_plane_state *state)
902 struct vop_plane_state *vop_state = to_vop_plane_state(state);
904 __drm_atomic_helper_plane_destroy_state(plane, state);
909 static int vop_atomic_plane_set_property(struct drm_plane *plane,
910 struct drm_plane_state *state,
911 struct drm_property *property,
914 struct vop_win *win = to_vop_win(plane);
915 struct vop_plane_state *plane_state = to_vop_plane_state(state);
917 if (property == win->vop->plane_zpos_prop) {
918 plane_state->zpos = val;
922 if (property == win->rotation_prop) {
923 state->rotation = val;
927 DRM_ERROR("failed to set vop plane property\n");
931 static int vop_atomic_plane_get_property(struct drm_plane *plane,
932 const struct drm_plane_state *state,
933 struct drm_property *property,
936 struct vop_win *win = to_vop_win(plane);
937 struct vop_plane_state *plane_state = to_vop_plane_state(state);
939 if (property == win->vop->plane_zpos_prop) {
940 *val = plane_state->zpos;
944 if (property == win->rotation_prop) {
945 *val = state->rotation;
949 DRM_ERROR("failed to get vop plane property\n");
953 static const struct drm_plane_funcs vop_plane_funcs = {
954 .update_plane = drm_atomic_helper_update_plane,
955 .disable_plane = drm_atomic_helper_disable_plane,
956 .destroy = vop_plane_destroy,
957 .reset = vop_atomic_plane_reset,
958 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
959 .atomic_destroy_state = vop_atomic_plane_destroy_state,
960 .atomic_set_property = vop_atomic_plane_set_property,
961 .atomic_get_property = vop_atomic_plane_get_property,
964 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
966 struct vop *vop = to_vop(crtc);
969 if (!vop->is_enabled)
972 spin_lock_irqsave(&vop->irq_lock, flags);
974 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
976 spin_unlock_irqrestore(&vop->irq_lock, flags);
981 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
983 struct vop *vop = to_vop(crtc);
986 if (!vop->is_enabled)
989 spin_lock_irqsave(&vop->irq_lock, flags);
991 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
993 spin_unlock_irqrestore(&vop->irq_lock, flags);
996 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
998 struct vop *vop = to_vop(crtc);
1000 reinit_completion(&vop->wait_update_complete);
1001 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1004 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1005 struct drm_file *file_priv)
1007 struct drm_device *drm = crtc->dev;
1008 struct vop *vop = to_vop(crtc);
1009 struct drm_pending_vblank_event *e;
1010 unsigned long flags;
1012 spin_lock_irqsave(&drm->event_lock, flags);
1014 if (e && e->base.file_priv == file_priv) {
1017 e->base.destroy(&e->base);
1018 file_priv->event_space += sizeof(e->event);
1020 spin_unlock_irqrestore(&drm->event_lock, flags);
1023 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1024 .enable_vblank = vop_crtc_enable_vblank,
1025 .disable_vblank = vop_crtc_disable_vblank,
1026 .wait_for_update = vop_crtc_wait_for_update,
1027 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1030 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1031 const struct drm_display_mode *mode,
1032 struct drm_display_mode *adjusted_mode)
1034 struct vop *vop = to_vop(crtc);
1036 adjusted_mode->clock =
1037 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1042 static void vop_crtc_enable(struct drm_crtc *crtc)
1044 struct vop *vop = to_vop(crtc);
1045 const struct vop_data *vop_data = vop->data;
1046 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1047 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1048 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1049 u16 hdisplay = adjusted_mode->hdisplay;
1050 u16 htotal = adjusted_mode->htotal;
1051 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1052 u16 hact_end = hact_st + hdisplay;
1053 u16 vdisplay = adjusted_mode->vdisplay;
1054 u16 vtotal = adjusted_mode->vtotal;
1055 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1056 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1057 u16 vact_end = vact_st + vdisplay;
1062 * If dclk rate is zero, mean that scanout is stop,
1063 * we don't need wait any more.
1065 if (clk_get_rate(vop->dclk)) {
1067 * Rk3288 vop timing register is immediately, when configure
1068 * display timing on display time, may cause tearing.
1070 * Vop standby will take effect at end of current frame,
1071 * if dsp hold valid irq happen, it means standby complete.
1074 * standby and wait complete --> |----
1077 * |---> dsp hold irq
1078 * configure display timing --> |
1080 * | new frame start.
1083 reinit_completion(&vop->dsp_hold_completion);
1084 vop_dsp_hold_valid_irq_enable(vop);
1086 spin_lock(&vop->reg_lock);
1088 VOP_CTRL_SET(vop, standby, 1);
1090 spin_unlock(&vop->reg_lock);
1092 wait_for_completion(&vop->dsp_hold_completion);
1094 vop_dsp_hold_valid_irq_disable(vop);
1098 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1099 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1100 VOP_CTRL_SET(vop, pin_pol, val);
1101 switch (s->output_type) {
1102 case DRM_MODE_CONNECTOR_LVDS:
1103 VOP_CTRL_SET(vop, rgb_en, 1);
1104 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1106 case DRM_MODE_CONNECTOR_eDP:
1107 VOP_CTRL_SET(vop, edp_en, 1);
1108 VOP_CTRL_SET(vop, edp_pin_pol, val);
1110 case DRM_MODE_CONNECTOR_HDMIA:
1111 VOP_CTRL_SET(vop, hdmi_en, 1);
1112 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1114 case DRM_MODE_CONNECTOR_DSI:
1115 VOP_CTRL_SET(vop, mipi_en, 1);
1116 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1119 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1122 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1123 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1124 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1126 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1128 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1129 val = hact_st << 16;
1131 VOP_CTRL_SET(vop, hact_st_end, val);
1132 VOP_CTRL_SET(vop, hpost_st_end, val);
1134 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1135 val = vact_st << 16;
1137 VOP_CTRL_SET(vop, vact_st_end, val);
1138 VOP_CTRL_SET(vop, vpost_st_end, val);
1140 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1142 VOP_CTRL_SET(vop, standby, 0);
1145 static int vop_zpos_cmp(const void *a, const void *b)
1147 struct vop_zpos *pa = (struct vop_zpos *)a;
1148 struct vop_zpos *pb = (struct vop_zpos *)b;
1150 return pa->zpos - pb->zpos;
1153 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1154 struct drm_crtc_state *crtc_state)
1156 struct drm_atomic_state *state = crtc_state->state;
1157 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1158 struct vop *vop = to_vop(crtc);
1159 const struct vop_data *vop_data = vop->data;
1160 struct drm_plane *plane;
1161 struct drm_plane_state *pstate;
1162 struct vop_plane_state *plane_state;
1163 struct vop_zpos *pzpos;
1164 int dsp_layer_sel = 0;
1165 int i, j, cnt = 0, ret = 0;
1167 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1171 for (i = 0; i < vop_data->win_size; i++) {
1172 const struct vop_win_data *win_data = &vop_data->win[i];
1173 struct vop_win *win;
1178 for (j = 0; j < vop->num_wins; j++) {
1181 if (win->win_id == i && !win->area_id)
1184 if (WARN_ON(j >= vop->num_wins)) {
1186 goto err_free_pzpos;
1190 pstate = state->plane_states[drm_plane_index(plane)];
1192 * plane might not have changed, in which case take
1196 pstate = plane->state;
1197 plane_state = to_vop_plane_state(pstate);
1198 pzpos[cnt].zpos = plane_state->zpos;
1199 pzpos[cnt++].win_id = win->win_id;
1202 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1204 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1205 const struct vop_win_data *win_data = &vop_data->win[i];
1208 if (win_data->phy) {
1209 struct vop_zpos *zpos = &pzpos[cnt++];
1211 dsp_layer_sel |= zpos->win_id << shift;
1213 dsp_layer_sel |= i << shift;
1217 s->dsp_layer_sel = dsp_layer_sel;
1224 static void vop_cfg_update(struct drm_crtc *crtc,
1225 struct drm_crtc_state *old_crtc_state)
1227 struct rockchip_crtc_state *s =
1228 to_rockchip_crtc_state(crtc->state);
1229 struct vop *vop = to_vop(crtc);
1231 spin_lock(&vop->reg_lock);
1233 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1236 spin_unlock(&vop->reg_lock);
1239 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1240 struct drm_crtc_state *old_crtc_state)
1242 struct vop *vop = to_vop(crtc);
1244 if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1246 if (!vop_is_allwin_disabled(vop)) {
1247 vop_cfg_update(crtc, old_crtc_state);
1248 while(!vop_is_cfg_done_complete(vop));
1250 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1252 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
1254 vop->is_iommu_enabled = true;
1257 vop_cfg_update(crtc, old_crtc_state);
1260 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1261 struct drm_crtc_state *old_crtc_state)
1263 struct vop *vop = to_vop(crtc);
1265 if (crtc->state->event) {
1266 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1268 vop->event = crtc->state->event;
1269 crtc->state->event = NULL;
1273 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1274 .enable = vop_crtc_enable,
1275 .disable = vop_crtc_disable,
1276 .mode_fixup = vop_crtc_mode_fixup,
1277 .atomic_check = vop_crtc_atomic_check,
1278 .atomic_flush = vop_crtc_atomic_flush,
1279 .atomic_begin = vop_crtc_atomic_begin,
1282 static void vop_crtc_destroy(struct drm_crtc *crtc)
1284 drm_crtc_cleanup(crtc);
1287 static void vop_crtc_reset(struct drm_crtc *crtc)
1290 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1293 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1295 crtc->state->crtc = crtc;
1298 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1300 struct rockchip_crtc_state *rockchip_state;
1302 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1303 if (!rockchip_state)
1306 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1307 return &rockchip_state->base;
1310 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1311 struct drm_crtc_state *state)
1313 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1315 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1319 static const struct drm_crtc_funcs vop_crtc_funcs = {
1320 .set_config = drm_atomic_helper_set_config,
1321 .page_flip = drm_atomic_helper_page_flip,
1322 .destroy = vop_crtc_destroy,
1323 .reset = vop_crtc_reset,
1324 .atomic_duplicate_state = vop_crtc_duplicate_state,
1325 .atomic_destroy_state = vop_crtc_destroy_state,
1328 static void vop_handle_vblank(struct vop *vop)
1330 struct drm_device *drm = vop->drm_dev;
1331 struct drm_crtc *crtc = &vop->crtc;
1332 unsigned long flags;
1334 if (!vop_is_cfg_done_complete(vop))
1338 spin_lock_irqsave(&drm->event_lock, flags);
1340 drm_crtc_send_vblank_event(crtc, vop->event);
1341 drm_crtc_vblank_put(crtc);
1344 spin_unlock_irqrestore(&drm->event_lock, flags);
1346 if (!completion_done(&vop->wait_update_complete))
1347 complete(&vop->wait_update_complete);
1350 static irqreturn_t vop_isr(int irq, void *data)
1352 struct vop *vop = data;
1353 struct drm_crtc *crtc = &vop->crtc;
1354 uint32_t active_irqs;
1355 unsigned long flags;
1359 * interrupt register has interrupt status, enable and clear bits, we
1360 * must hold irq_lock to avoid a race with enable/disable_vblank().
1362 spin_lock_irqsave(&vop->irq_lock, flags);
1364 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1365 /* Clear all active interrupt sources */
1367 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1369 spin_unlock_irqrestore(&vop->irq_lock, flags);
1371 /* This is expected for vop iommu irqs, since the irq is shared */
1375 if (active_irqs & DSP_HOLD_VALID_INTR) {
1376 complete(&vop->dsp_hold_completion);
1377 active_irqs &= ~DSP_HOLD_VALID_INTR;
1381 if (active_irqs & FS_INTR) {
1382 drm_crtc_handle_vblank(crtc);
1383 vop_handle_vblank(vop);
1384 active_irqs &= ~FS_INTR;
1388 /* Unhandled irqs are spurious. */
1390 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1395 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1396 unsigned long possible_crtcs)
1398 struct drm_plane *share = NULL;
1399 unsigned int rotations = 0;
1400 struct drm_property *prop;
1401 uint64_t feature = 0;
1405 share = &win->parent->base;
1407 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1408 possible_crtcs, &vop_plane_funcs,
1409 win->data_formats, win->nformats, win->type);
1411 DRM_ERROR("failed to initialize plane\n");
1414 drm_plane_helper_add(&win->base, &plane_helper_funcs);
1415 drm_object_attach_property(&win->base.base,
1416 vop->plane_zpos_prop, win->win_id);
1418 if (VOP_WIN_SUPPORT(vop, win, xmirror))
1419 rotations |= BIT(DRM_REFLECT_X);
1421 if (VOP_WIN_SUPPORT(vop, win, ymirror))
1422 rotations |= BIT(DRM_REFLECT_Y);
1425 rotations |= BIT(DRM_ROTATE_0);
1426 prop = drm_mode_create_rotation_property(vop->drm_dev,
1429 DRM_ERROR("failed to create zpos property\n");
1432 drm_object_attach_property(&win->base.base, prop,
1434 win->rotation_prop = prop;
1437 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
1438 if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
1439 VOP_WIN_SUPPORT(vop, win, alpha_en))
1440 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
1442 drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
1448 static int vop_create_crtc(struct vop *vop)
1450 struct device *dev = vop->dev;
1451 struct drm_device *drm_dev = vop->drm_dev;
1452 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1453 struct drm_crtc *crtc = &vop->crtc;
1454 struct device_node *port;
1459 * Create drm_plane for primary and cursor planes first, since we need
1460 * to pass them to drm_crtc_init_with_planes, which sets the
1461 * "possible_crtcs" to the newly initialized crtc.
1463 for (i = 0; i < vop->num_wins; i++) {
1464 struct vop_win *win = &vop->win[i];
1466 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1467 win->type != DRM_PLANE_TYPE_CURSOR)
1470 ret = vop_plane_init(vop, win, 0);
1472 goto err_cleanup_planes;
1475 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1477 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1482 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1483 &vop_crtc_funcs, NULL);
1485 goto err_cleanup_planes;
1487 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1490 * Create drm_planes for overlay windows with possible_crtcs restricted
1491 * to the newly created crtc.
1493 for (i = 0; i < vop->num_wins; i++) {
1494 struct vop_win *win = &vop->win[i];
1495 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1497 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1500 ret = vop_plane_init(vop, win, possible_crtcs);
1502 goto err_cleanup_crtc;
1505 port = of_get_child_by_name(dev->of_node, "port");
1507 DRM_ERROR("no port node found in %s\n",
1508 dev->of_node->full_name);
1510 goto err_cleanup_crtc;
1513 init_completion(&vop->dsp_hold_completion);
1514 init_completion(&vop->wait_update_complete);
1516 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1521 drm_crtc_cleanup(crtc);
1523 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1525 drm_plane_cleanup(plane);
1529 static void vop_destroy_crtc(struct vop *vop)
1531 struct drm_crtc *crtc = &vop->crtc;
1532 struct drm_device *drm_dev = vop->drm_dev;
1533 struct drm_plane *plane, *tmp;
1535 rockchip_unregister_crtc_funcs(crtc);
1536 of_node_put(crtc->port);
1539 * We need to cleanup the planes now. Why?
1541 * The planes are "&vop->win[i].base". That means the memory is
1542 * all part of the big "struct vop" chunk of memory. That memory
1543 * was devm allocated and associated with this component. We need to
1544 * free it ourselves before vop_unbind() finishes.
1546 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1548 vop_plane_destroy(plane);
1551 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1552 * references the CRTC.
1554 drm_crtc_cleanup(crtc);
1558 * Initialize the vop->win array elements.
1560 static int vop_win_init(struct vop *vop)
1562 const struct vop_data *vop_data = vop->data;
1564 unsigned int num_wins = 0;
1565 struct drm_property *prop;
1566 static const struct drm_prop_enum_list props[] = {
1567 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
1568 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
1571 for (i = 0; i < vop_data->win_size; i++) {
1572 struct vop_win *vop_win = &vop->win[num_wins];
1573 const struct vop_win_data *win_data = &vop_data->win[i];
1578 vop_win->phy = win_data->phy;
1579 vop_win->offset = win_data->base;
1580 vop_win->type = win_data->type;
1581 vop_win->data_formats = win_data->phy->data_formats;
1582 vop_win->nformats = win_data->phy->nformats;
1584 vop_win->win_id = i;
1585 vop_win->area_id = 0;
1588 for (j = 0; j < win_data->area_size; j++) {
1589 struct vop_win *vop_area = &vop->win[num_wins];
1590 const struct vop_win_phy *area = win_data->area[j];
1592 vop_area->parent = vop_win;
1593 vop_area->offset = vop_win->offset;
1594 vop_area->phy = area;
1595 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1596 vop_area->data_formats = vop_win->data_formats;
1597 vop_area->nformats = vop_win->nformats;
1598 vop_area->vop = vop;
1599 vop_area->win_id = i;
1600 vop_area->area_id = j;
1605 vop->num_wins = num_wins;
1607 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1608 "ZPOS", 0, vop->data->win_size);
1610 DRM_ERROR("failed to create zpos property\n");
1613 vop->plane_zpos_prop = prop;
1615 vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
1616 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
1617 props, ARRAY_SIZE(props),
1618 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
1619 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
1620 if (!vop->plane_feature_prop) {
1621 DRM_ERROR("failed to create feature property\n");
1628 static int vop_bind(struct device *dev, struct device *master, void *data)
1630 struct platform_device *pdev = to_platform_device(dev);
1631 const struct vop_data *vop_data;
1632 struct drm_device *drm_dev = data;
1634 struct resource *res;
1639 vop_data = of_device_get_match_data(dev);
1643 for (i = 0; i < vop_data->win_size; i++) {
1644 const struct vop_win_data *win_data = &vop_data->win[i];
1646 num_wins += win_data->area_size + 1;
1649 /* Allocate vop struct and its vop_win array */
1650 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1651 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1656 vop->data = vop_data;
1657 vop->drm_dev = drm_dev;
1658 vop->num_wins = num_wins;
1659 dev_set_drvdata(dev, vop);
1661 ret = vop_win_init(vop);
1665 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1666 vop->len = resource_size(res);
1667 vop->regs = devm_ioremap_resource(dev, res);
1668 if (IS_ERR(vop->regs))
1669 return PTR_ERR(vop->regs);
1671 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1675 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1676 if (IS_ERR(vop->hclk)) {
1677 dev_err(vop->dev, "failed to get hclk source\n");
1678 return PTR_ERR(vop->hclk);
1680 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1681 if (IS_ERR(vop->aclk)) {
1682 dev_err(vop->dev, "failed to get aclk source\n");
1683 return PTR_ERR(vop->aclk);
1685 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1686 if (IS_ERR(vop->dclk)) {
1687 dev_err(vop->dev, "failed to get dclk source\n");
1688 return PTR_ERR(vop->dclk);
1691 irq = platform_get_irq(pdev, 0);
1693 dev_err(dev, "cannot find irq for vop\n");
1696 vop->irq = (unsigned int)irq;
1698 spin_lock_init(&vop->reg_lock);
1699 spin_lock_init(&vop->irq_lock);
1701 mutex_init(&vop->vsync_mutex);
1703 ret = devm_request_irq(dev, vop->irq, vop_isr,
1704 IRQF_SHARED, dev_name(dev), vop);
1708 /* IRQ is initially disabled; it gets enabled in power_on */
1709 disable_irq(vop->irq);
1711 ret = vop_create_crtc(vop);
1715 pm_runtime_enable(&pdev->dev);
1719 static void vop_unbind(struct device *dev, struct device *master, void *data)
1721 struct vop *vop = dev_get_drvdata(dev);
1723 pm_runtime_disable(dev);
1724 vop_destroy_crtc(vop);
1727 const struct component_ops vop_component_ops = {
1729 .unbind = vop_unbind,
1731 EXPORT_SYMBOL_GPL(vop_component_ops);