drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34
  35 #include "rockchip_drm_drv.h"
  36 #include "rockchip_drm_gem.h"
  37 #include "rockchip_drm_fb.h"
  38 #include "rockchip_drm_vop.h"
  39
  40 #define VOP_REG_SUPPORT(vop, reg) \
  41                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  42                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  43                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  44                 reg.mask))
  45
  46 #define VOP_WIN_SUPPORT(vop, win, name) \
  47                 VOP_REG_SUPPORT(vop, win->phy->name)
  48
  49 #define VOP_CTRL_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  51
  52 #define VOP_INTR_SUPPORT(vop, win, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  54
  55 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  56                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  57
  58 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  59         do { \
  60                 if (VOP_REG_SUPPORT(vop, reg)) \
  61                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  62                                   v, reg.write_mask, relaxed); \
  63                 else \
  64                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  65         } while(0)
  66
  67 #define REG_SET(x, name, off, reg, v, relaxed) \
  68                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  69 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  71
  72 #define VOP_WIN_SET(x, win, name, v) \
  73                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  74 #define VOP_SCL_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  76 #define VOP_SCL_SET_EXT(x, win, name, v) \
  77                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  78
  79 #define VOP_CTRL_SET(x, name, v) \
  80                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  81
  82 #define VOP_INTR_GET(vop, name) \
  83                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  84
  85 #define VOP_INTR_SET(vop, name, mask, v) \
  86                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  87                              mask, v, false)
  88
  89 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  90         do { \
  91                 int i, reg = 0, mask = 0; \
  92                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  93                         if (vop->data->intr->intrs[i] & type) { \
  94                                 reg |= (v) << i; \
  95                                 mask |= 1 << i; \
  96                         } \
  97                 } \
  98                 VOP_INTR_SET(vop, name, mask, reg); \
  99         } while (0)
 100 #define VOP_INTR_GET_TYPE(vop, name, type) \
 101                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 102
 103 #define VOP_CTRL_GET(x, name) \
 104                 vop_read_reg(x, 0, vop->data->ctrl->name)
 105
 106 #define VOP_WIN_GET(x, win, name) \
 107                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 108
 109 #define VOP_WIN_NAME(win, name) \
 110                 (vop_get_win_phy(win, &win->phy->name)->name)
 111
 112 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 113                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 114
 115 #define to_vop(x) container_of(x, struct vop, crtc)
 116 #define to_vop_win(x) container_of(x, struct vop_win, base)
 117 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 118
 119 struct vop_zpos {
 120         int win_id;
 121         int zpos;
 122 };
 123
 124 struct vop_plane_state {
 125         struct drm_plane_state base;
 126         int format;
 127         int zpos;
 128         struct drm_rect src;
 129         struct drm_rect dest;
 130         dma_addr_t yrgb_mst;
 131         bool enable;
 132 };
 133
 134 struct vop_win {
 135         struct vop_win *parent;
 136         struct drm_plane base;
 137
 138         int win_id;
 139         int area_id;
 140         uint32_t offset;
 141         enum drm_plane_type type;
 142         const struct vop_win_phy *phy;
 143         const uint32_t *data_formats;
 144         uint32_t nformats;
 145         struct vop *vop;
 146
 147         struct drm_property *rotation_prop;
 148         struct vop_plane_state state;
 149 };
 150
 151 struct vop {
 152         struct drm_crtc crtc;
 153         struct device *dev;
 154         struct drm_device *drm_dev;
 155         struct drm_property *plane_zpos_prop;
 156
 157         /* mutex vsync_ work */
 158         struct mutex vsync_mutex;
 159         bool vsync_work_pending;
 160         struct completion dsp_hold_completion;
 161         struct completion wait_update_complete;
 162         struct drm_pending_vblank_event *event;
 163
 164         const struct vop_data *data;
 165         int num_wins;
 166
 167         uint32_t *regsbak;
 168         void __iomem *regs;
 169
 170         /* physical map length of vop register */
 171         uint32_t len;
 172
 173         /* one time only one process allowed to config the register */
 174         spinlock_t reg_lock;
 175         /* lock vop irq reg */
 176         spinlock_t irq_lock;
 177
 178         unsigned int irq;
 179
 180         /* vop AHP clk */
 181         struct clk *hclk;
 182         /* vop dclk */
 183         struct clk *dclk;
 184         /* vop share memory frequency */
 185         struct clk *aclk;
 186
 187         /* vop dclk reset */
 188         struct reset_control *dclk_rst;
 189
 190         struct vop_win win[];
 191 };
 192
 193 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 194 {
 195         writel(v, vop->regs + offset);
 196         vop->regsbak[offset >> 2] = v;
 197 }
 198
 199 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 200 {
 201         return readl(vop->regs + offset);
 202 }
 203
 204 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 205                                     const struct vop_reg *reg)
 206 {
 207         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 208 }
 209
 210 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 211                                   uint32_t mask, uint32_t shift, uint32_t v,
 212                                   bool write_mask, bool relaxed)
 213 {
 214         if (!mask)
 215                 return;
 216
 217         if (write_mask) {
 218                 v = ((v & mask) << shift) | (mask << (shift + 16));
 219         } else {
 220                 uint32_t cached_val = vop->regsbak[offset >> 2];
 221
 222                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 223                 vop->regsbak[offset >> 2] = v;
 224         }
 225
 226         if (relaxed)
 227                 writel_relaxed(v, vop->regs + offset);
 228         else
 229                 writel(v, vop->regs + offset);
 230 }
 231
 232 static inline const struct vop_win_phy *
 233 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 234 {
 235         if (!reg->mask && win->parent)
 236                 return win->parent->phy;
 237
 238         return win->phy;
 239 }
 240
 241 static inline uint32_t vop_get_intr_type(struct vop *vop,
 242                                          const struct vop_reg *reg, int type)
 243 {
 244         uint32_t i, ret = 0;
 245         uint32_t regs = vop_read_reg(vop, 0, reg);
 246
 247         for (i = 0; i < vop->data->intr->nintrs; i++) {
 248                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 249                         ret |= vop->data->intr->intrs[i];
 250         }
 251
 252         return ret;
 253 }
 254
 255 static inline void vop_cfg_done(struct vop *vop)
 256 {
 257         VOP_CTRL_SET(vop, cfg_done, 1);
 258 }
 259
 260 static bool has_rb_swapped(uint32_t format)
 261 {
 262         switch (format) {
 263         case DRM_FORMAT_XBGR8888:
 264         case DRM_FORMAT_ABGR8888:
 265         case DRM_FORMAT_BGR888:
 266         case DRM_FORMAT_BGR565:
 267                 return true;
 268         default:
 269                 return false;
 270         }
 271 }
 272
 273 static enum vop_data_format vop_convert_format(uint32_t format)
 274 {
 275         switch (format) {
 276         case DRM_FORMAT_XRGB8888:
 277         case DRM_FORMAT_ARGB8888:
 278         case DRM_FORMAT_XBGR8888:
 279         case DRM_FORMAT_ABGR8888:
 280                 return VOP_FMT_ARGB8888;
 281         case DRM_FORMAT_RGB888:
 282         case DRM_FORMAT_BGR888:
 283                 return VOP_FMT_RGB888;
 284         case DRM_FORMAT_RGB565:
 285         case DRM_FORMAT_BGR565:
 286                 return VOP_FMT_RGB565;
 287         case DRM_FORMAT_NV12:
 288                 return VOP_FMT_YUV420SP;
 289         case DRM_FORMAT_NV16:
 290                 return VOP_FMT_YUV422SP;
 291         case DRM_FORMAT_NV24:
 292                 return VOP_FMT_YUV444SP;
 293         default:
 294                 DRM_ERROR("unsupport format[%08x]\n", format);
 295                 return -EINVAL;
 296         }
 297 }
 298
 299 static bool is_yuv_support(uint32_t format)
 300 {
 301         switch (format) {
 302         case DRM_FORMAT_NV12:
 303         case DRM_FORMAT_NV16:
 304         case DRM_FORMAT_NV24:
 305                 return true;
 306         default:
 307                 return false;
 308         }
 309 }
 310
 311 static bool is_alpha_support(uint32_t format)
 312 {
 313         switch (format) {
 314         case DRM_FORMAT_ARGB8888:
 315         case DRM_FORMAT_ABGR8888:
 316                 return true;
 317         default:
 318                 return false;
 319         }
 320 }
 321
 322 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 323                                   uint32_t dst, bool is_horizontal,
 324                                   int vsu_mode, int *vskiplines)
 325 {
 326         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 327
 328         if (is_horizontal) {
 329                 if (mode == SCALE_UP)
 330                         val = GET_SCL_FT_BIC(src, dst);
 331                 else if (mode == SCALE_DOWN)
 332                         val = GET_SCL_FT_BILI_DN(src, dst);
 333         } else {
 334                 if (mode == SCALE_UP) {
 335                         if (vsu_mode == SCALE_UP_BIL)
 336                                 val = GET_SCL_FT_BILI_UP(src, dst);
 337                         else
 338                                 val = GET_SCL_FT_BIC(src, dst);
 339                 } else if (mode == SCALE_DOWN) {
 340                         if (vskiplines) {
 341                                 *vskiplines = scl_get_vskiplines(src, dst);
 342                                 val = scl_get_bili_dn_vskip(src, dst,
 343                                                             *vskiplines);
 344                         } else {
 345                                 val = GET_SCL_FT_BILI_DN(src, dst);
 346                         }
 347                 }
 348         }
 349
 350         return val;
 351 }
 352
 353 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 354                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 355                                 uint32_t dst_h, uint32_t pixel_format)
 356 {
 357         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 358         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 359         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 360         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 361         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 362         bool is_yuv = is_yuv_support(pixel_format);
 363         uint16_t cbcr_src_w = src_w / hsub;
 364         uint16_t cbcr_src_h = src_h / vsub;
 365         uint16_t vsu_mode;
 366         uint16_t lb_mode;
 367         uint32_t val;
 368         int vskiplines = 0;
 369
 370         if (!win->phy->scl)
 371                 return;
 372
 373         if (dst_w > 3840) {
 374                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 375                 return;
 376         }
 377
 378         if (!win->phy->scl->ext) {
 379                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 380                             scl_cal_scale2(src_w, dst_w));
 381                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 382                             scl_cal_scale2(src_h, dst_h));
 383                 if (is_yuv) {
 384                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 385                                     scl_cal_scale2(cbcr_src_w, dst_w));
 386                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 387                                     scl_cal_scale2(cbcr_src_h, dst_h));
 388                 }
 389                 return;
 390         }
 391
 392         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 393         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 394
 395         if (is_yuv) {
 396                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 397                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 398                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 399                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 400                 else
 401                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 402         } else {
 403                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 404                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 405                 else
 406                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 407         }
 408
 409         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 410         if (lb_mode == LB_RGB_3840X2) {
 411                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 412                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 413                         return;
 414                 }
 415                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 416                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 417                         return;
 418                 }
 419                 vsu_mode = SCALE_UP_BIL;
 420         } else if (lb_mode == LB_RGB_2560X4) {
 421                 vsu_mode = SCALE_UP_BIL;
 422         } else {
 423                 vsu_mode = SCALE_UP_BIC;
 424         }
 425
 426         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 427                                 true, 0, NULL);
 428         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 429         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 430                                 false, vsu_mode, &vskiplines);
 431         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 432
 433         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 434         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 435
 436         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 437         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 438         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 439         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 440         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 441         if (is_yuv) {
 442                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 443                                         dst_w, true, 0, NULL);
 444                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 445                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 446                                         dst_h, false, vsu_mode, &vskiplines);
 447                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 448
 449                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 450                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 451                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 452                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 453                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 454                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 455                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 456         }
 457 }
 458
 459 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 460 {
 461         unsigned long flags;
 462
 463         spin_lock_irqsave(&vop->irq_lock, flags);
 464
 465         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 466
 467         spin_unlock_irqrestore(&vop->irq_lock, flags);
 468 }
 469
 470 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 471 {
 472         unsigned long flags;
 473
 474         spin_lock_irqsave(&vop->irq_lock, flags);
 475
 476         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 477
 478         spin_unlock_irqrestore(&vop->irq_lock, flags);
 479 }
 480
 481 static void vop_enable(struct drm_crtc *crtc)
 482 {
 483         struct vop *vop = to_vop(crtc);
 484         int ret, i;
 485
 486         ret = clk_prepare_enable(vop->hclk);
 487         if (ret < 0) {
 488                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 489                 return;
 490         }
 491
 492         ret = clk_prepare_enable(vop->dclk);
 493         if (ret < 0) {
 494                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 495                 goto err_disable_hclk;
 496         }
 497
 498         ret = clk_prepare_enable(vop->aclk);
 499         if (ret < 0) {
 500                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 501                 goto err_disable_dclk;
 502         }
 503
 504         ret = pm_runtime_get_sync(vop->dev);
 505         if (ret < 0) {
 506                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 507                 return;
 508         }
 509
 510         /*
 511          * Slave iommu shares power, irq and clock with vop.  It was associated
 512          * automatically with this master device via common driver code.
 513          * Now that we have enabled the clock we attach it to the shared drm
 514          * mapping.
 515          */
 516         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 517         if (ret) {
 518                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 519                 goto err_disable_aclk;
 520         }
 521
 522         memcpy(vop->regsbak, vop->regs, vop->len);
 523
 524         VOP_CTRL_SET(vop, global_regdone_en, 1);
 525
 526         for (i = 0; i < vop->num_wins; i++) {
 527                 struct vop_win *win = &vop->win[i];
 528
 529                 VOP_WIN_SET(vop, win, gate, 1);
 530         }
 531
 532         spin_lock(&vop->reg_lock);
 533
 534         VOP_CTRL_SET(vop, standby, 0);
 535
 536         spin_unlock(&vop->reg_lock);
 537
 538         enable_irq(vop->irq);
 539
 540         drm_crtc_vblank_on(crtc);
 541
 542         return;
 543
 544 err_disable_aclk:
 545         clk_disable_unprepare(vop->aclk);
 546 err_disable_dclk:
 547         clk_disable_unprepare(vop->dclk);
 548 err_disable_hclk:
 549         clk_disable_unprepare(vop->hclk);
 550 }
 551
 552 static void vop_crtc_disable(struct drm_crtc *crtc)
 553 {
 554         struct vop *vop = to_vop(crtc);
 555         int i;
 556
 557         /*
 558          * We need to make sure that all windows are disabled before we
 559          * disable that crtc. Otherwise we might try to scan from a destroyed
 560          * buffer later.
 561          */
 562         for (i = 0; i < vop->num_wins; i++) {
 563                 struct vop_win *win = &vop->win[i];
 564
 565                 spin_lock(&vop->reg_lock);
 566                 VOP_WIN_SET(vop, win, enable, 0);
 567                 spin_unlock(&vop->reg_lock);
 568         }
 569         vop_cfg_done(vop);
 570
 571         drm_crtc_vblank_off(crtc);
 572
 573         /*
 574          * Vop standby will take effect at end of current frame,
 575          * if dsp hold valid irq happen, it means standby complete.
 576          *
 577          * we must wait standby complete when we want to disable aclk,
 578          * if not, memory bus maybe dead.
 579          */
 580         reinit_completion(&vop->dsp_hold_completion);
 581         vop_dsp_hold_valid_irq_enable(vop);
 582
 583         spin_lock(&vop->reg_lock);
 584
 585         VOP_CTRL_SET(vop, standby, 1);
 586
 587         spin_unlock(&vop->reg_lock);
 588
 589         wait_for_completion(&vop->dsp_hold_completion);
 590
 591         vop_dsp_hold_valid_irq_disable(vop);
 592
 593         disable_irq(vop->irq);
 594
 595         /*
 596          * vop standby complete, so iommu detach is safe.
 597          */
 598         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 599
 600         pm_runtime_put(vop->dev);
 601         clk_disable_unprepare(vop->dclk);
 602         clk_disable_unprepare(vop->aclk);
 603         clk_disable_unprepare(vop->hclk);
 604 }
 605
 606 static void vop_plane_destroy(struct drm_plane *plane)
 607 {
 608         drm_plane_cleanup(plane);
 609 }
 610
 611 static int vop_plane_prepare_fb(struct drm_plane *plane,
 612                                 const struct drm_plane_state *new_state)
 613 {
 614         if (plane->state->fb)
 615                 drm_framebuffer_reference(plane->state->fb);
 616
 617         return 0;
 618 }
 619
 620 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 621                                  const struct drm_plane_state *old_state)
 622 {
 623         if (old_state->fb)
 624                 drm_framebuffer_unreference(old_state->fb);
 625 }
 626
 627 static int vop_plane_atomic_check(struct drm_plane *plane,
 628                            struct drm_plane_state *state)
 629 {
 630         struct drm_crtc *crtc = state->crtc;
 631         struct drm_framebuffer *fb = state->fb;
 632         struct vop_win *win = to_vop_win(plane);
 633         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 634         struct drm_crtc_state *crtc_state;
 635         bool visible;
 636         int ret;
 637         struct drm_rect *dest = &vop_plane_state->dest;
 638         struct drm_rect *src = &vop_plane_state->src;
 639         struct drm_rect clip;
 640         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 641                                         DRM_PLANE_HELPER_NO_SCALING;
 642         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 643                                         DRM_PLANE_HELPER_NO_SCALING;
 644
 645         crtc = crtc ? crtc : plane->state->crtc;
 646         /*
 647          * Both crtc or plane->state->crtc can be null.
 648          */
 649         if (!crtc || !fb)
 650                 goto out_disable;
 651
 652         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 653         if (IS_ERR(crtc_state))
 654                 return PTR_ERR(crtc_state);
 655
 656         src->x1 = state->src_x;
 657         src->y1 = state->src_y;
 658         src->x2 = state->src_x + state->src_w;
 659         src->y2 = state->src_y + state->src_h;
 660         dest->x1 = state->crtc_x;
 661         dest->y1 = state->crtc_y;
 662         dest->x2 = state->crtc_x + state->crtc_w;
 663         dest->y2 = state->crtc_y + state->crtc_h;
 664
 665         clip.x1 = 0;
 666         clip.y1 = 0;
 667         clip.x2 = crtc_state->mode.hdisplay;
 668         clip.y2 = crtc_state->mode.vdisplay;
 669
 670         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 671                                             src, dest, &clip,
 672                                             min_scale,
 673                                             max_scale,
 674                                             true, true, &visible);
 675         if (ret)
 676                 return ret;
 677
 678         if (!visible)
 679                 goto out_disable;
 680
 681         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 682         if (vop_plane_state->format < 0)
 683                 return vop_plane_state->format;
 684
 685         /*
 686          * Src.x1 can be odd when do clip, but yuv plane start point
 687          * need align with 2 pixel.
 688          */
 689         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 690                 return -EINVAL;
 691
 692         vop_plane_state->enable = true;
 693
 694         return 0;
 695
 696 out_disable:
 697         vop_plane_state->enable = false;
 698         return 0;
 699 }
 700
 701 static void vop_plane_atomic_disable(struct drm_plane *plane,
 702                                      struct drm_plane_state *old_state)
 703 {
 704         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 705         struct vop_win *win = to_vop_win(plane);
 706         struct vop *vop = to_vop(old_state->crtc);
 707
 708         if (!old_state->crtc)
 709                 return;
 710
 711         spin_lock(&vop->reg_lock);
 712
 713         VOP_WIN_SET(vop, win, enable, 0);
 714
 715         spin_unlock(&vop->reg_lock);
 716
 717         vop_plane_state->enable = false;
 718 }
 719
 720 static void vop_plane_atomic_update(struct drm_plane *plane,
 721                 struct drm_plane_state *old_state)
 722 {
 723         struct drm_plane_state *state = plane->state;
 724         struct drm_crtc *crtc = state->crtc;
 725         struct vop_win *win = to_vop_win(plane);
 726         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 727         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 728         struct vop *vop = to_vop(state->crtc);
 729         struct drm_framebuffer *fb = state->fb;
 730         unsigned int actual_w, actual_h;
 731         unsigned int dsp_stx, dsp_sty;
 732         uint32_t act_info, dsp_info, dsp_st;
 733         struct drm_rect *src = &vop_plane_state->src;
 734         struct drm_rect *dest = &vop_plane_state->dest;
 735         struct drm_gem_object *obj, *uv_obj;
 736         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 737         unsigned long offset;
 738         dma_addr_t dma_addr;
 739         int ymirror, xmirror;
 740         uint32_t val;
 741         bool rb_swap;
 742
 743         /*
 744          * can't update plane when vop is disabled.
 745          */
 746         if (!crtc)
 747                 return;
 748
 749         if (!vop_plane_state->enable) {
 750                 vop_plane_atomic_disable(plane, old_state);
 751                 return;
 752         }
 753
 754         obj = rockchip_fb_get_gem_obj(fb, 0);
 755         rk_obj = to_rockchip_obj(obj);
 756
 757         actual_w = drm_rect_width(src) >> 16;
 758         actual_h = drm_rect_height(src) >> 16;
 759         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 760
 761         dsp_info = (drm_rect_height(dest) - 1) << 16;
 762         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 763
 764         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 765         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 766         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 767
 768         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 769         if (state->rotation & BIT(DRM_REFLECT_Y))
 770                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 771         else
 772                 offset += (src->y1 >> 16) * fb->pitches[0];
 773         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 774
 775         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 776         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 777
 778         spin_lock(&vop->reg_lock);
 779
 780         VOP_WIN_SET(vop, win, xmirror, xmirror);
 781         VOP_WIN_SET(vop, win, ymirror, ymirror);
 782         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 783         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 784         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 785         if (is_yuv_support(fb->pixel_format)) {
 786                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 787                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 788                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 789
 790                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 791                 rk_uv_obj = to_rockchip_obj(uv_obj);
 792
 793                 offset = (src->x1 >> 16) * bpp / hsub;
 794                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 795
 796                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 797                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 798                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 799         }
 800
 801         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 802                             drm_rect_width(dest), drm_rect_height(dest),
 803                             fb->pixel_format);
 804
 805         VOP_WIN_SET(vop, win, act_info, act_info);
 806         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 807         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 808
 809         rb_swap = has_rb_swapped(fb->pixel_format);
 810         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 811
 812         if (is_alpha_support(fb->pixel_format) &&
 813             (s->dsp_layer_sel & 0x3) != win->win_id) {
 814                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 815                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 816                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 817                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 818                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 819                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 820                         SRC_FACTOR_M0(ALPHA_ONE);
 821                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 822                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 823                 VOP_WIN_SET(vop, win, alpha_en, 1);
 824         } else {
 825                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 826                 VOP_WIN_SET(vop, win, alpha_en, 0);
 827         }
 828
 829         VOP_WIN_SET(vop, win, enable, 1);
 830         spin_unlock(&vop->reg_lock);
 831 }
 832
 833 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 834         .prepare_fb = vop_plane_prepare_fb,
 835         .cleanup_fb = vop_plane_cleanup_fb,
 836         .atomic_check = vop_plane_atomic_check,
 837         .atomic_update = vop_plane_atomic_update,
 838         .atomic_disable = vop_plane_atomic_disable,
 839 };
 840
 841 void vop_atomic_plane_reset(struct drm_plane *plane)
 842 {
 843         struct vop_win *win = to_vop_win(plane);
 844         struct vop_plane_state *vop_plane_state =
 845                                         to_vop_plane_state(plane->state);
 846
 847         if (plane->state && plane->state->fb)
 848                 drm_framebuffer_unreference(plane->state->fb);
 849
 850         kfree(vop_plane_state);
 851         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 852         if (!vop_plane_state)
 853                 return;
 854
 855         vop_plane_state->zpos = win->win_id;
 856         plane->state = &vop_plane_state->base;
 857         plane->state->plane = plane;
 858 }
 859
 860 struct drm_plane_state *
 861 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 862 {
 863         struct vop_plane_state *old_vop_plane_state;
 864         struct vop_plane_state *vop_plane_state;
 865
 866         if (WARN_ON(!plane->state))
 867                 return NULL;
 868
 869         old_vop_plane_state = to_vop_plane_state(plane->state);
 870         vop_plane_state = kmemdup(old_vop_plane_state,
 871                                   sizeof(*vop_plane_state), GFP_KERNEL);
 872         if (!vop_plane_state)
 873                 return NULL;
 874
 875         __drm_atomic_helper_plane_duplicate_state(plane,
 876                                                   &vop_plane_state->base);
 877
 878         return &vop_plane_state->base;
 879 }
 880
 881 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 882                                            struct drm_plane_state *state)
 883 {
 884         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 885
 886         __drm_atomic_helper_plane_destroy_state(plane, state);
 887
 888         kfree(vop_state);
 889 }
 890
 891 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 892                                          struct drm_plane_state *state,
 893                                          struct drm_property *property,
 894                                          uint64_t val)
 895 {
 896         struct vop_win *win = to_vop_win(plane);
 897         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 898
 899         if (property == win->vop->plane_zpos_prop) {
 900                 plane_state->zpos = val;
 901                 return 0;
 902         }
 903
 904         if (property == win->rotation_prop) {
 905                 state->rotation = val;
 906                 return 0;
 907         }
 908
 909         DRM_ERROR("failed to set vop plane property\n");
 910         return -EINVAL;
 911 }
 912
 913 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 914                                          const struct drm_plane_state *state,
 915                                          struct drm_property *property,
 916                                          uint64_t *val)
 917 {
 918         struct vop_win *win = to_vop_win(plane);
 919         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 920
 921         if (property == win->vop->plane_zpos_prop) {
 922                 *val = plane_state->zpos;
 923                 return 0;
 924         }
 925
 926         if (property == win->rotation_prop) {
 927                 *val = state->rotation;
 928                 return 0;
 929         }
 930
 931         DRM_ERROR("failed to get vop plane property\n");
 932         return -EINVAL;
 933 }
 934
 935 static const struct drm_plane_funcs vop_plane_funcs = {
 936         .update_plane   = drm_atomic_helper_update_plane,
 937         .disable_plane  = drm_atomic_helper_disable_plane,
 938         .destroy = vop_plane_destroy,
 939         .reset = vop_atomic_plane_reset,
 940         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 941         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 942         .atomic_set_property = vop_atomic_plane_set_property,
 943         .atomic_get_property = vop_atomic_plane_get_property,
 944 };
 945
 946 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 947 {
 948         struct vop *vop = to_vop(crtc);
 949         unsigned long flags;
 950
 951         spin_lock_irqsave(&vop->irq_lock, flags);
 952
 953         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 954
 955         spin_unlock_irqrestore(&vop->irq_lock, flags);
 956
 957         return 0;
 958 }
 959
 960 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 961 {
 962         struct vop *vop = to_vop(crtc);
 963         unsigned long flags;
 964
 965         spin_lock_irqsave(&vop->irq_lock, flags);
 966
 967         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 968
 969         spin_unlock_irqrestore(&vop->irq_lock, flags);
 970 }
 971
 972 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 973 {
 974         struct vop *vop = to_vop(crtc);
 975
 976         reinit_completion(&vop->wait_update_complete);
 977         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
 978 }
 979
 980 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
 981                                            struct drm_file *file_priv)
 982 {
 983         struct drm_device *drm = crtc->dev;
 984         struct vop *vop = to_vop(crtc);
 985         struct drm_pending_vblank_event *e;
 986         unsigned long flags;
 987
 988         spin_lock_irqsave(&drm->event_lock, flags);
 989         e = vop->event;
 990         if (e && e->base.file_priv == file_priv) {
 991                 vop->event = NULL;
 992
 993                 e->base.destroy(&e->base);
 994                 file_priv->event_space += sizeof(e->event);
 995         }
 996         spin_unlock_irqrestore(&drm->event_lock, flags);
 997 }
 998
 999 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1000         .enable_vblank = vop_crtc_enable_vblank,
1001         .disable_vblank = vop_crtc_disable_vblank,
1002         .wait_for_update = vop_crtc_wait_for_update,
1003         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1004 };
1005
1006 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1007                                 const struct drm_display_mode *mode,
1008                                 struct drm_display_mode *adjusted_mode)
1009 {
1010         struct vop *vop = to_vop(crtc);
1011
1012         adjusted_mode->clock =
1013                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1014
1015         return true;
1016 }
1017
1018 static void vop_crtc_enable(struct drm_crtc *crtc)
1019 {
1020         struct vop *vop = to_vop(crtc);
1021         const struct vop_data *vop_data = vop->data;
1022         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1023         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1024         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1025         u16 hdisplay = adjusted_mode->hdisplay;
1026         u16 htotal = adjusted_mode->htotal;
1027         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1028         u16 hact_end = hact_st + hdisplay;
1029         u16 vdisplay = adjusted_mode->vdisplay;
1030         u16 vtotal = adjusted_mode->vtotal;
1031         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1032         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1033         u16 vact_end = vact_st + vdisplay;
1034         uint32_t val;
1035
1036         vop_enable(crtc);
1037         /*
1038          * If dclk rate is zero, mean that scanout is stop,
1039          * we don't need wait any more.
1040          */
1041         if (clk_get_rate(vop->dclk)) {
1042                 /*
1043                  * Rk3288 vop timing register is immediately, when configure
1044                  * display timing on display time, may cause tearing.
1045                  *
1046                  * Vop standby will take effect at end of current frame,
1047                  * if dsp hold valid irq happen, it means standby complete.
1048                  *
1049                  * mode set:
1050                  *    standby and wait complete --> |----
1051                  *                                  | display time
1052                  *                                  |----
1053                  *                                  |---> dsp hold irq
1054                  *     configure display timing --> |
1055                  *         standby exit             |
1056                  *                                  | new frame start.
1057                  */
1058
1059                 reinit_completion(&vop->dsp_hold_completion);
1060                 vop_dsp_hold_valid_irq_enable(vop);
1061
1062                 spin_lock(&vop->reg_lock);
1063
1064                 VOP_CTRL_SET(vop, standby, 1);
1065
1066                 spin_unlock(&vop->reg_lock);
1067
1068                 wait_for_completion(&vop->dsp_hold_completion);
1069
1070                 vop_dsp_hold_valid_irq_disable(vop);
1071         }
1072
1073         val = 0x8;
1074         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1075         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1076         VOP_CTRL_SET(vop, pin_pol, val);
1077         switch (s->output_type) {
1078         case DRM_MODE_CONNECTOR_LVDS:
1079                 VOP_CTRL_SET(vop, rgb_en, 1);
1080                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1081                 break;
1082         case DRM_MODE_CONNECTOR_eDP:
1083                 VOP_CTRL_SET(vop, edp_en, 1);
1084                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1085                 break;
1086         case DRM_MODE_CONNECTOR_HDMIA:
1087                 VOP_CTRL_SET(vop, hdmi_en, 1);
1088                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1089                 break;
1090         case DRM_MODE_CONNECTOR_DSI:
1091                 VOP_CTRL_SET(vop, mipi_en, 1);
1092                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1093                 break;
1094         default:
1095                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1096         }
1097
1098         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1099             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1100                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1101
1102         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1103
1104         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1105         val = hact_st << 16;
1106         val |= hact_end;
1107         VOP_CTRL_SET(vop, hact_st_end, val);
1108         VOP_CTRL_SET(vop, hpost_st_end, val);
1109
1110         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1111         val = vact_st << 16;
1112         val |= vact_end;
1113         VOP_CTRL_SET(vop, vact_st_end, val);
1114         VOP_CTRL_SET(vop, vpost_st_end, val);
1115
1116         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1117
1118         VOP_CTRL_SET(vop, standby, 0);
1119 }
1120
1121 static int vop_zpos_cmp(const void *a, const void *b)
1122 {
1123         struct vop_zpos *pa = (struct vop_zpos *)a;
1124         struct vop_zpos *pb = (struct vop_zpos *)b;
1125
1126         return pa->zpos - pb->zpos;
1127 }
1128
1129 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1130                                  struct drm_crtc_state *crtc_state)
1131 {
1132         struct drm_atomic_state *state = crtc_state->state;
1133         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1134         struct vop *vop = to_vop(crtc);
1135         const struct vop_data *vop_data = vop->data;
1136         struct drm_plane *plane;
1137         struct drm_plane_state *pstate;
1138         struct vop_plane_state *plane_state;
1139         struct vop_zpos *pzpos;
1140         int dsp_layer_sel = 0;
1141         int i, j, cnt = 0, ret = 0;
1142
1143         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1144         if (!pzpos)
1145                 return -ENOMEM;
1146
1147         for (i = 0; i < vop_data->win_size; i++) {
1148                 const struct vop_win_data *win_data = &vop_data->win[i];
1149                 struct vop_win *win;
1150
1151                 if (!win_data->phy)
1152                         continue;
1153
1154                 for (j = 0; j < vop->num_wins; j++) {
1155                         win = &vop->win[j];
1156
1157                         if (win->win_id == i && !win->area_id)
1158                                 break;
1159                 }
1160                 if (WARN_ON(j >= vop->num_wins)) {
1161                         ret = -EINVAL;
1162                         goto err_free_pzpos;
1163                 }
1164
1165                 plane = &win->base;
1166                 pstate = state->plane_states[drm_plane_index(plane)];
1167                 /*
1168                  * plane might not have changed, in which case take
1169                  * current state:
1170                  */
1171                 if (!pstate)
1172                         pstate = plane->state;
1173                 plane_state = to_vop_plane_state(pstate);
1174                 pzpos[cnt].zpos = plane_state->zpos;
1175                 pzpos[cnt++].win_id = win->win_id;
1176         }
1177
1178         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1179
1180         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1181                 const struct vop_win_data *win_data = &vop_data->win[i];
1182                 int shift = i * 2;
1183
1184                 if (win_data->phy) {
1185                         struct vop_zpos *zpos = &pzpos[cnt++];
1186
1187                         dsp_layer_sel |= zpos->win_id << shift;
1188                 } else {
1189                         dsp_layer_sel |= i << shift;
1190                 }
1191         }
1192
1193         s->dsp_layer_sel = dsp_layer_sel;
1194
1195 err_free_pzpos:
1196         kfree(pzpos);
1197         return ret;
1198 }
1199
1200 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1201                                   struct drm_crtc_state *old_crtc_state)
1202 {
1203         struct rockchip_crtc_state *s =
1204                         to_rockchip_crtc_state(crtc->state);
1205         struct vop *vop = to_vop(crtc);
1206
1207         spin_lock(&vop->reg_lock);
1208
1209         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1210         vop_cfg_done(vop);
1211
1212         spin_unlock(&vop->reg_lock);
1213 }
1214
1215 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1216                                   struct drm_crtc_state *old_crtc_state)
1217 {
1218         struct vop *vop = to_vop(crtc);
1219
1220         if (crtc->state->event) {
1221                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1222
1223                 vop->event = crtc->state->event;
1224                 crtc->state->event = NULL;
1225         }
1226 }
1227
1228 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1229         .enable = vop_crtc_enable,
1230         .disable = vop_crtc_disable,
1231         .mode_fixup = vop_crtc_mode_fixup,
1232         .atomic_check = vop_crtc_atomic_check,
1233         .atomic_flush = vop_crtc_atomic_flush,
1234         .atomic_begin = vop_crtc_atomic_begin,
1235 };
1236
1237 static void vop_crtc_destroy(struct drm_crtc *crtc)
1238 {
1239         drm_crtc_cleanup(crtc);
1240 }
1241
1242 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1243 {
1244         struct rockchip_crtc_state *rockchip_state;
1245
1246         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1247         if (!rockchip_state)
1248                 return NULL;
1249
1250         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1251         return &rockchip_state->base;
1252 }
1253
1254 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1255                                    struct drm_crtc_state *state)
1256 {
1257         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1258
1259         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1260         kfree(s);
1261 }
1262
1263 static const struct drm_crtc_funcs vop_crtc_funcs = {
1264         .set_config = drm_atomic_helper_set_config,
1265         .page_flip = drm_atomic_helper_page_flip,
1266         .destroy = vop_crtc_destroy,
1267         .reset = drm_atomic_helper_crtc_reset,
1268         .atomic_duplicate_state = vop_crtc_duplicate_state,
1269         .atomic_destroy_state = vop_crtc_destroy_state,
1270 };
1271
1272 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1273 {
1274         struct drm_plane *plane = &vop_win->base;
1275         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1276         dma_addr_t yrgb_mst;
1277
1278         if (!state->enable)
1279                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1280
1281         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1282
1283         return yrgb_mst == state->yrgb_mst;
1284 }
1285
1286 static void vop_handle_vblank(struct vop *vop)
1287 {
1288         struct drm_device *drm = vop->drm_dev;
1289         struct drm_crtc *crtc = &vop->crtc;
1290         unsigned long flags;
1291         int i;
1292
1293         for (i = 0; i < vop->num_wins; i++) {
1294                 if (!vop_win_pending_is_complete(&vop->win[i]))
1295                         return;
1296         }
1297
1298         if (vop->event) {
1299                 spin_lock_irqsave(&drm->event_lock, flags);
1300
1301                 drm_crtc_send_vblank_event(crtc, vop->event);
1302                 drm_crtc_vblank_put(crtc);
1303                 vop->event = NULL;
1304
1305                 spin_unlock_irqrestore(&drm->event_lock, flags);
1306         }
1307         if (!completion_done(&vop->wait_update_complete))
1308                 complete(&vop->wait_update_complete);
1309 }
1310
1311 static irqreturn_t vop_isr(int irq, void *data)
1312 {
1313         struct vop *vop = data;
1314         struct drm_crtc *crtc = &vop->crtc;
1315         uint32_t active_irqs;
1316         unsigned long flags;
1317         int ret = IRQ_NONE;
1318
1319         /*
1320          * interrupt register has interrupt status, enable and clear bits, we
1321          * must hold irq_lock to avoid a race with enable/disable_vblank().
1322         */
1323         spin_lock_irqsave(&vop->irq_lock, flags);
1324
1325         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1326         /* Clear all active interrupt sources */
1327         if (active_irqs)
1328                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1329
1330         spin_unlock_irqrestore(&vop->irq_lock, flags);
1331
1332         /* This is expected for vop iommu irqs, since the irq is shared */
1333         if (!active_irqs)
1334                 return IRQ_NONE;
1335
1336         if (active_irqs & DSP_HOLD_VALID_INTR) {
1337                 complete(&vop->dsp_hold_completion);
1338                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1339                 ret = IRQ_HANDLED;
1340         }
1341
1342         if (active_irqs & FS_INTR) {
1343                 drm_crtc_handle_vblank(crtc);
1344                 vop_handle_vblank(vop);
1345                 active_irqs &= ~FS_INTR;
1346                 ret = IRQ_HANDLED;
1347         }
1348
1349         /* Unhandled irqs are spurious. */
1350         if (active_irqs)
1351                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1352
1353         return ret;
1354 }
1355
1356 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1357                           unsigned long possible_crtcs)
1358 {
1359         struct drm_plane *share = NULL;
1360         unsigned int rotations = 0;
1361         struct drm_property *prop;
1362         int ret;
1363
1364         if (win->parent)
1365                 share = &win->parent->base;
1366
1367         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1368                                    possible_crtcs, &vop_plane_funcs,
1369                                    win->data_formats, win->nformats, win->type);
1370         if (ret) {
1371                 DRM_ERROR("failed to initialize plane\n");
1372                 return ret;
1373         }
1374         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1375         drm_object_attach_property(&win->base.base,
1376                                    vop->plane_zpos_prop, win->win_id);
1377
1378         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1379                 rotations |= BIT(DRM_REFLECT_X);
1380
1381         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1382                 rotations |= BIT(DRM_REFLECT_Y);
1383
1384         if (rotations) {
1385                 rotations |= BIT(DRM_ROTATE_0);
1386                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1387                                                          rotations);
1388                 if (!prop) {
1389                         DRM_ERROR("failed to create zpos property\n");
1390                         return -EINVAL;
1391                 }
1392                 drm_object_attach_property(&win->base.base, prop,
1393                                            BIT(DRM_ROTATE_0));
1394                 win->rotation_prop = prop;
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int vop_create_crtc(struct vop *vop)
1401 {
1402         struct device *dev = vop->dev;
1403         struct drm_device *drm_dev = vop->drm_dev;
1404         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1405         struct drm_crtc *crtc = &vop->crtc;
1406         struct device_node *port;
1407         int ret;
1408         int i;
1409
1410         /*
1411          * Create drm_plane for primary and cursor planes first, since we need
1412          * to pass them to drm_crtc_init_with_planes, which sets the
1413          * "possible_crtcs" to the newly initialized crtc.
1414          */
1415         for (i = 0; i < vop->num_wins; i++) {
1416                 struct vop_win *win = &vop->win[i];
1417
1418                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1419                     win->type != DRM_PLANE_TYPE_CURSOR)
1420                         continue;
1421
1422                 ret = vop_plane_init(vop, win, 0);
1423                 if (ret)
1424                         goto err_cleanup_planes;
1425
1426                 plane = &win->base;
1427                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1428                         primary = plane;
1429                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1430                         cursor = plane;
1431
1432         }
1433
1434         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1435                                         &vop_crtc_funcs, NULL);
1436         if (ret)
1437                 goto err_cleanup_planes;
1438
1439         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1440
1441         /*
1442          * Create drm_planes for overlay windows with possible_crtcs restricted
1443          * to the newly created crtc.
1444          */
1445         for (i = 0; i < vop->num_wins; i++) {
1446                 struct vop_win *win = &vop->win[i];
1447                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1448
1449                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1450                         continue;
1451
1452                 ret = vop_plane_init(vop, win, possible_crtcs);
1453                 if (ret)
1454                         goto err_cleanup_crtc;
1455         }
1456
1457         port = of_get_child_by_name(dev->of_node, "port");
1458         if (!port) {
1459                 DRM_ERROR("no port node found in %s\n",
1460                           dev->of_node->full_name);
1461                 ret = -ENOENT;
1462                 goto err_cleanup_crtc;
1463         }
1464
1465         init_completion(&vop->dsp_hold_completion);
1466         init_completion(&vop->wait_update_complete);
1467         crtc->port = port;
1468         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1469
1470         return 0;
1471
1472 err_cleanup_crtc:
1473         drm_crtc_cleanup(crtc);
1474 err_cleanup_planes:
1475         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1476                                  head)
1477                 drm_plane_cleanup(plane);
1478         return ret;
1479 }
1480
1481 static void vop_destroy_crtc(struct vop *vop)
1482 {
1483         struct drm_crtc *crtc = &vop->crtc;
1484         struct drm_device *drm_dev = vop->drm_dev;
1485         struct drm_plane *plane, *tmp;
1486
1487         rockchip_unregister_crtc_funcs(crtc);
1488         of_node_put(crtc->port);
1489
1490         /*
1491          * We need to cleanup the planes now.  Why?
1492          *
1493          * The planes are "&vop->win[i].base".  That means the memory is
1494          * all part of the big "struct vop" chunk of memory.  That memory
1495          * was devm allocated and associated with this component.  We need to
1496          * free it ourselves before vop_unbind() finishes.
1497          */
1498         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1499                                  head)
1500                 vop_plane_destroy(plane);
1501
1502         /*
1503          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1504          * references the CRTC.
1505          */
1506         drm_crtc_cleanup(crtc);
1507 }
1508
1509 /*
1510  * Initialize the vop->win array elements.
1511  */
1512 static int vop_win_init(struct vop *vop)
1513 {
1514         const struct vop_data *vop_data = vop->data;
1515         unsigned int i, j;
1516         unsigned int num_wins = 0;
1517         struct drm_property *prop;
1518
1519         for (i = 0; i < vop_data->win_size; i++) {
1520                 struct vop_win *vop_win = &vop->win[num_wins];
1521                 const struct vop_win_data *win_data = &vop_data->win[i];
1522
1523                 if (!win_data->phy)
1524                         continue;
1525
1526                 vop_win->phy = win_data->phy;
1527                 vop_win->offset = win_data->base;
1528                 vop_win->type = win_data->type;
1529                 vop_win->data_formats = win_data->phy->data_formats;
1530                 vop_win->nformats = win_data->phy->nformats;
1531                 vop_win->vop = vop;
1532                 vop_win->win_id = i;
1533                 vop_win->area_id = 0;
1534                 num_wins++;
1535
1536                 for (j = 0; j < win_data->area_size; j++) {
1537                         struct vop_win *vop_area = &vop->win[num_wins];
1538                         const struct vop_win_phy *area = win_data->area[j];
1539
1540                         vop_area->parent = vop_win;
1541                         vop_area->offset = vop_win->offset;
1542                         vop_area->phy = area;
1543                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1544                         vop_area->data_formats = vop_win->data_formats;
1545                         vop_area->nformats = vop_win->nformats;
1546                         vop_area->vop = vop;
1547                         vop_area->win_id = i;
1548                         vop_area->area_id = j;
1549                         num_wins++;
1550                 }
1551         }
1552
1553         vop->num_wins = num_wins;
1554
1555         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1556                                          "ZPOS", 0, vop->data->win_size);
1557         if (!prop) {
1558                 DRM_ERROR("failed to create zpos property\n");
1559                 return -EINVAL;
1560         }
1561         vop->plane_zpos_prop = prop;
1562
1563         return 0;
1564 }
1565
1566 static int vop_bind(struct device *dev, struct device *master, void *data)
1567 {
1568         struct platform_device *pdev = to_platform_device(dev);
1569         const struct vop_data *vop_data;
1570         struct drm_device *drm_dev = data;
1571         struct vop *vop;
1572         struct resource *res;
1573         size_t alloc_size;
1574         int ret, irq, i;
1575         int num_wins = 0;
1576
1577         vop_data = of_device_get_match_data(dev);
1578         if (!vop_data)
1579                 return -ENODEV;
1580
1581         for (i = 0; i < vop_data->win_size; i++) {
1582                 const struct vop_win_data *win_data = &vop_data->win[i];
1583
1584                 num_wins += win_data->area_size + 1;
1585         }
1586
1587         /* Allocate vop struct and its vop_win array */
1588         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1589         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1590         if (!vop)
1591                 return -ENOMEM;
1592
1593         vop->dev = dev;
1594         vop->data = vop_data;
1595         vop->drm_dev = drm_dev;
1596         vop->num_wins = num_wins;
1597         dev_set_drvdata(dev, vop);
1598
1599         ret = vop_win_init(vop);
1600         if (ret)
1601                 return ret;
1602
1603         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1604         vop->len = resource_size(res);
1605         vop->regs = devm_ioremap_resource(dev, res);
1606         if (IS_ERR(vop->regs))
1607                 return PTR_ERR(vop->regs);
1608
1609         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1610         if (!vop->regsbak)
1611                 return -ENOMEM;
1612
1613         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1614         if (IS_ERR(vop->hclk)) {
1615                 dev_err(vop->dev, "failed to get hclk source\n");
1616                 return PTR_ERR(vop->hclk);
1617         }
1618         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1619         if (IS_ERR(vop->aclk)) {
1620                 dev_err(vop->dev, "failed to get aclk source\n");
1621                 return PTR_ERR(vop->aclk);
1622         }
1623         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1624         if (IS_ERR(vop->dclk)) {
1625                 dev_err(vop->dev, "failed to get dclk source\n");
1626                 return PTR_ERR(vop->dclk);
1627         }
1628
1629         irq = platform_get_irq(pdev, 0);
1630         if (irq < 0) {
1631                 dev_err(dev, "cannot find irq for vop\n");
1632                 return irq;
1633         }
1634         vop->irq = (unsigned int)irq;
1635
1636         spin_lock_init(&vop->reg_lock);
1637         spin_lock_init(&vop->irq_lock);
1638
1639         mutex_init(&vop->vsync_mutex);
1640
1641         ret = devm_request_irq(dev, vop->irq, vop_isr,
1642                                IRQF_SHARED, dev_name(dev), vop);
1643         if (ret)
1644                 return ret;
1645
1646         /* IRQ is initially disabled; it gets enabled in power_on */
1647         disable_irq(vop->irq);
1648
1649         ret = vop_create_crtc(vop);
1650         if (ret)
1651                 return ret;
1652
1653         pm_runtime_enable(&pdev->dev);
1654         return 0;
1655 }
1656
1657 static void vop_unbind(struct device *dev, struct device *master, void *data)
1658 {
1659         struct vop *vop = dev_get_drvdata(dev);
1660
1661         pm_runtime_disable(dev);
1662         vop_destroy_crtc(vop);
1663 }
1664
1665 const struct component_ops vop_component_ops = {
1666         .bind = vop_bind,
1667         .unbind = vop_unbind,
1668 };
1669 EXPORT_SYMBOL_GPL(vop_component_ops);