drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/component.h>
  28
  29 #include <linux/reset.h>
  30 #include <linux/delay.h>
  31
  32 #include "rockchip_drm_drv.h"
  33 #include "rockchip_drm_gem.h"
  34 #include "rockchip_drm_fb.h"
  35 #include "rockchip_drm_vop.h"
  36
  37 #define VOP_REG(off, _mask, s) \
  38                 {.offset = off, \
  39                  .mask = _mask, \
  40                  .shift = s,}
  41
  42 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  43                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  44 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  45                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  46
  47 #define REG_SET(x, base, reg, v, mode) \
  48                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  49
  50 #define VOP_WIN_SET(x, win, name, v) \
  51                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  52 #define VOP_CTRL_SET(x, name, v) \
  53                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  54
  55 #define VOP_WIN_GET(x, win, name) \
  56                 vop_read_reg(x, win->base, &win->phy->name)
  57
  58 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  59                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  60
  61 #define to_vop(x) container_of(x, struct vop, crtc)
  62 #define to_vop_win(x) container_of(x, struct vop_win, base)
  63
  64 struct vop_win_state {
  65         struct list_head head;
  66         struct drm_framebuffer *fb;
  67         dma_addr_t yrgb_mst;
  68         struct drm_pending_vblank_event *event;
  69 };
  70
  71 struct vop_win {
  72         struct drm_plane base;
  73         const struct vop_win_data *data;
  74         struct vop *vop;
  75
  76         struct list_head pending;
  77         struct vop_win_state *active;
  78 };
  79
  80 struct vop {
  81         struct drm_crtc crtc;
  82         struct device *dev;
  83         struct drm_device *drm_dev;
  84         bool is_enabled;
  85
  86         int connector_type;
  87         int connector_out_mode;
  88
  89         /* mutex vsync_ work */
  90         struct mutex vsync_mutex;
  91         bool vsync_work_pending;
  92         struct completion dsp_hold_completion;
  93
  94         const struct vop_data *data;
  95
  96         uint32_t *regsbak;
  97         void __iomem *regs;
  98
  99         /* physical map length of vop register */
 100         uint32_t len;
 101
 102         /* one time only one process allowed to config the register */
 103         spinlock_t reg_lock;
 104         /* lock vop irq reg */
 105         spinlock_t irq_lock;
 106
 107         unsigned int irq;
 108
 109         /* vop AHP clk */
 110         struct clk *hclk;
 111         /* vop dclk */
 112         struct clk *dclk;
 113         /* vop share memory frequency */
 114         struct clk *aclk;
 115
 116         /* vop dclk reset */
 117         struct reset_control *dclk_rst;
 118
 119         int pipe;
 120
 121         struct vop_win win[];
 122 };
 123
 124 enum vop_data_format {
 125         VOP_FMT_ARGB8888 = 0,
 126         VOP_FMT_RGB888,
 127         VOP_FMT_RGB565,
 128         VOP_FMT_YUV420SP = 4,
 129         VOP_FMT_YUV422SP,
 130         VOP_FMT_YUV444SP,
 131 };
 132
 133 struct vop_reg_data {
 134         uint32_t offset;
 135         uint32_t value;
 136 };
 137
 138 struct vop_reg {
 139         uint32_t offset;
 140         uint32_t shift;
 141         uint32_t mask;
 142 };
 143
 144 struct vop_ctrl {
 145         struct vop_reg standby;
 146         struct vop_reg data_blank;
 147         struct vop_reg gate_en;
 148         struct vop_reg mmu_en;
 149         struct vop_reg rgb_en;
 150         struct vop_reg edp_en;
 151         struct vop_reg hdmi_en;
 152         struct vop_reg mipi_en;
 153         struct vop_reg out_mode;
 154         struct vop_reg dither_down;
 155         struct vop_reg dither_up;
 156         struct vop_reg pin_pol;
 157
 158         struct vop_reg htotal_pw;
 159         struct vop_reg hact_st_end;
 160         struct vop_reg vtotal_pw;
 161         struct vop_reg vact_st_end;
 162         struct vop_reg hpost_st_end;
 163         struct vop_reg vpost_st_end;
 164 };
 165
 166 struct vop_win_phy {
 167         const uint32_t *data_formats;
 168         uint32_t nformats;
 169
 170         struct vop_reg enable;
 171         struct vop_reg format;
 172         struct vop_reg rb_swap;
 173         struct vop_reg act_info;
 174         struct vop_reg dsp_info;
 175         struct vop_reg dsp_st;
 176         struct vop_reg yrgb_mst;
 177         struct vop_reg uv_mst;
 178         struct vop_reg yrgb_vir;
 179         struct vop_reg uv_vir;
 180
 181         struct vop_reg dst_alpha_ctl;
 182         struct vop_reg src_alpha_ctl;
 183 };
 184
 185 struct vop_win_data {
 186         uint32_t base;
 187         const struct vop_win_phy *phy;
 188         enum drm_plane_type type;
 189 };
 190
 191 struct vop_data {
 192         const struct vop_reg_data *init_table;
 193         unsigned int table_size;
 194         const struct vop_ctrl *ctrl;
 195         const struct vop_win_data *win;
 196         unsigned int win_size;
 197 };
 198
 199 static const uint32_t formats_01[] = {
 200         DRM_FORMAT_XRGB8888,
 201         DRM_FORMAT_ARGB8888,
 202         DRM_FORMAT_XBGR8888,
 203         DRM_FORMAT_ABGR8888,
 204         DRM_FORMAT_RGB888,
 205         DRM_FORMAT_BGR888,
 206         DRM_FORMAT_RGB565,
 207         DRM_FORMAT_BGR565,
 208         DRM_FORMAT_NV12,
 209         DRM_FORMAT_NV16,
 210         DRM_FORMAT_NV24,
 211 };
 212
 213 static const uint32_t formats_234[] = {
 214         DRM_FORMAT_XRGB8888,
 215         DRM_FORMAT_ARGB8888,
 216         DRM_FORMAT_XBGR8888,
 217         DRM_FORMAT_ABGR8888,
 218         DRM_FORMAT_RGB888,
 219         DRM_FORMAT_BGR888,
 220         DRM_FORMAT_RGB565,
 221         DRM_FORMAT_BGR565,
 222 };
 223
 224 static const struct vop_win_phy win01_data = {
 225         .data_formats = formats_01,
 226         .nformats = ARRAY_SIZE(formats_01),
 227         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 228         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 229         .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
 230         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 231         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 232         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 233         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 234         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 235         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 236         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 237         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 238         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 239 };
 240
 241 static const struct vop_win_phy win23_data = {
 242         .data_formats = formats_234,
 243         .nformats = ARRAY_SIZE(formats_234),
 244         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 245         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 246         .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
 247         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 248         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 249         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 250         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 251         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 252         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 253 };
 254
 255 static const struct vop_win_phy cursor_data = {
 256         .data_formats = formats_234,
 257         .nformats = ARRAY_SIZE(formats_234),
 258         .enable = VOP_REG(HWC_CTRL0, 0x1, 0),
 259         .format = VOP_REG(HWC_CTRL0, 0x7, 1),
 260         .rb_swap = VOP_REG(HWC_CTRL0, 0x1, 12),
 261         .dsp_st = VOP_REG(HWC_DSP_ST, 0x1fff1fff, 0),
 262         .yrgb_mst = VOP_REG(HWC_MST, 0xffffffff, 0),
 263 };
 264
 265 static const struct vop_ctrl ctrl_data = {
 266         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 267         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 268         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 269         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 270         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 271         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 272         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 273         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 274         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 275         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 276         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 277         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 278         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 279         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 280         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 281         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 282         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 283         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 284 };
 285
 286 static const struct vop_reg_data vop_init_reg_table[] = {
 287         {SYS_CTRL, 0x00c00000},
 288         {DSP_CTRL0, 0x00000000},
 289         {WIN0_CTRL0, 0x00000080},
 290         {WIN1_CTRL0, 0x00000080},
 291 };
 292
 293 /*
 294  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 295  * special support to get alpha blending working.  For now, just use overlay
 296  * window 3 for the drm cursor.
 297  *
 298  */
 299 static const struct vop_win_data rk3288_vop_win_data[] = {
 300         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 301         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
 302         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 303         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
 304         { .base = 0x00, .phy = &cursor_data, .type = DRM_PLANE_TYPE_OVERLAY },
 305 };
 306
 307 static const struct vop_data rk3288_vop = {
 308         .init_table = vop_init_reg_table,
 309         .table_size = ARRAY_SIZE(vop_init_reg_table),
 310         .ctrl = &ctrl_data,
 311         .win = rk3288_vop_win_data,
 312         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 313 };
 314
 315 static const struct of_device_id vop_driver_dt_match[] = {
 316         { .compatible = "rockchip,rk3288-vop",
 317           .data = &rk3288_vop },
 318         {},
 319 };
 320
 321 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 322 {
 323         writel(v, vop->regs + offset);
 324         vop->regsbak[offset >> 2] = v;
 325 }
 326
 327 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 328 {
 329         return readl(vop->regs + offset);
 330 }
 331
 332 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 333                                     const struct vop_reg *reg)
 334 {
 335         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 336 }
 337
 338 static inline void vop_cfg_done(struct vop *vop)
 339 {
 340         writel(0x01, vop->regs + REG_CFG_DONE);
 341 }
 342
 343 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 344                                   uint32_t mask, uint32_t v)
 345 {
 346         if (mask) {
 347                 uint32_t cached_val = vop->regsbak[offset >> 2];
 348
 349                 cached_val = (cached_val & ~mask) | v;
 350                 writel(cached_val, vop->regs + offset);
 351                 vop->regsbak[offset >> 2] = cached_val;
 352         }
 353 }
 354
 355 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 356                                           uint32_t mask, uint32_t v)
 357 {
 358         if (mask) {
 359                 uint32_t cached_val = vop->regsbak[offset >> 2];
 360
 361                 cached_val = (cached_val & ~mask) | v;
 362                 writel_relaxed(cached_val, vop->regs + offset);
 363                 vop->regsbak[offset >> 2] = cached_val;
 364         }
 365 }
 366
 367 static bool has_rb_swapped(uint32_t format)
 368 {
 369         switch (format) {
 370         case DRM_FORMAT_XBGR8888:
 371         case DRM_FORMAT_ABGR8888:
 372         case DRM_FORMAT_BGR888:
 373         case DRM_FORMAT_BGR565:
 374                 return true;
 375         default:
 376                 return false;
 377         }
 378 }
 379
 380 static enum vop_data_format vop_convert_format(uint32_t format)
 381 {
 382         switch (format) {
 383         case DRM_FORMAT_XRGB8888:
 384         case DRM_FORMAT_ARGB8888:
 385         case DRM_FORMAT_XBGR8888:
 386         case DRM_FORMAT_ABGR8888:
 387                 return VOP_FMT_ARGB8888;
 388         case DRM_FORMAT_RGB888:
 389         case DRM_FORMAT_BGR888:
 390                 return VOP_FMT_RGB888;
 391         case DRM_FORMAT_RGB565:
 392         case DRM_FORMAT_BGR565:
 393                 return VOP_FMT_RGB565;
 394         case DRM_FORMAT_NV12:
 395                 return VOP_FMT_YUV420SP;
 396         case DRM_FORMAT_NV16:
 397                 return VOP_FMT_YUV422SP;
 398         case DRM_FORMAT_NV24:
 399                 return VOP_FMT_YUV444SP;
 400         default:
 401                 DRM_ERROR("unsupport format[%08x]\n", format);
 402                 return -EINVAL;
 403         }
 404 }
 405
 406 static bool is_alpha_support(uint32_t format)
 407 {
 408         switch (format) {
 409         case DRM_FORMAT_ARGB8888:
 410         case DRM_FORMAT_ABGR8888:
 411                 return true;
 412         default:
 413                 return false;
 414         }
 415 }
 416
 417 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 418 {
 419         unsigned long flags;
 420
 421         if (WARN_ON(!vop->is_enabled))
 422                 return;
 423
 424         spin_lock_irqsave(&vop->irq_lock, flags);
 425
 426         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 427                        DSP_HOLD_VALID_INTR_EN(1));
 428
 429         spin_unlock_irqrestore(&vop->irq_lock, flags);
 430 }
 431
 432 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 433 {
 434         unsigned long flags;
 435
 436         if (WARN_ON(!vop->is_enabled))
 437                 return;
 438
 439         spin_lock_irqsave(&vop->irq_lock, flags);
 440
 441         vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
 442                        DSP_HOLD_VALID_INTR_EN(0));
 443
 444         spin_unlock_irqrestore(&vop->irq_lock, flags);
 445 }
 446
 447 static void vop_enable(struct drm_crtc *crtc)
 448 {
 449         struct vop *vop = to_vop(crtc);
 450         int ret;
 451
 452         if (vop->is_enabled)
 453                 return;
 454
 455         ret = pm_runtime_get_sync(vop->dev);
 456         if (ret < 0) {
 457                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 458                 return;
 459         }
 460
 461         ret = clk_enable(vop->hclk);
 462         if (ret < 0) {
 463                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 464                 return;
 465         }
 466
 467         ret = clk_enable(vop->dclk);
 468         if (ret < 0) {
 469                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 470                 goto err_disable_hclk;
 471         }
 472
 473         ret = clk_enable(vop->aclk);
 474         if (ret < 0) {
 475                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 476                 goto err_disable_dclk;
 477         }
 478
 479         /*
 480          * Slave iommu shares power, irq and clock with vop.  It was associated
 481          * automatically with this master device via common driver code.
 482          * Now that we have enabled the clock we attach it to the shared drm
 483          * mapping.
 484          */
 485         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 486         if (ret) {
 487                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 488                 goto err_disable_aclk;
 489         }
 490
 491         /*
 492          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 493          */
 494         vop->is_enabled = true;
 495
 496         spin_lock(&vop->reg_lock);
 497
 498         VOP_CTRL_SET(vop, standby, 0);
 499
 500         spin_unlock(&vop->reg_lock);
 501
 502         enable_irq(vop->irq);
 503
 504         drm_vblank_on(vop->drm_dev, vop->pipe);
 505
 506         return;
 507
 508 err_disable_aclk:
 509         clk_disable(vop->aclk);
 510 err_disable_dclk:
 511         clk_disable(vop->dclk);
 512 err_disable_hclk:
 513         clk_disable(vop->hclk);
 514 }
 515
 516 static void vop_disable(struct drm_crtc *crtc)
 517 {
 518         struct vop *vop = to_vop(crtc);
 519
 520         if (!vop->is_enabled)
 521                 return;
 522
 523         drm_vblank_off(crtc->dev, vop->pipe);
 524
 525         /*
 526          * Vop standby will take effect at end of current frame,
 527          * if dsp hold valid irq happen, it means standby complete.
 528          *
 529          * we must wait standby complete when we want to disable aclk,
 530          * if not, memory bus maybe dead.
 531          */
 532         reinit_completion(&vop->dsp_hold_completion);
 533         vop_dsp_hold_valid_irq_enable(vop);
 534
 535         spin_lock(&vop->reg_lock);
 536
 537         VOP_CTRL_SET(vop, standby, 1);
 538
 539         spin_unlock(&vop->reg_lock);
 540
 541         wait_for_completion(&vop->dsp_hold_completion);
 542
 543         vop_dsp_hold_valid_irq_disable(vop);
 544
 545         disable_irq(vop->irq);
 546
 547         vop->is_enabled = false;
 548
 549         /*
 550          * vop standby complete, so iommu detach is safe.
 551          */
 552         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 553
 554         clk_disable(vop->dclk);
 555         clk_disable(vop->aclk);
 556         clk_disable(vop->hclk);
 557         pm_runtime_put(vop->dev);
 558 }
 559
 560 /*
 561  * Caller must hold vsync_mutex.
 562  */
 563 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
 564 {
 565         struct vop_win_state *last;
 566         struct vop_win_state *active = vop_win->active;
 567
 568         if (list_empty(&vop_win->pending))
 569                 return active ? active->fb : NULL;
 570
 571         last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
 572         return last ? last->fb : NULL;
 573 }
 574
 575 /*
 576  * Caller must hold vsync_mutex.
 577  */
 578 static int vop_win_queue_fb(struct vop_win *vop_win,
 579                             struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
 580                             struct drm_pending_vblank_event *event)
 581 {
 582         struct vop_win_state *state;
 583
 584         state = kzalloc(sizeof(*state), GFP_KERNEL);
 585         if (!state)
 586                 return -ENOMEM;
 587
 588         state->fb = fb;
 589         state->yrgb_mst = yrgb_mst;
 590         state->event = event;
 591
 592         list_add_tail(&state->head, &vop_win->pending);
 593
 594         return 0;
 595 }
 596
 597 static int vop_update_plane_event(struct drm_plane *plane,
 598                                   struct drm_crtc *crtc,
 599                                   struct drm_framebuffer *fb, int crtc_x,
 600                                   int crtc_y, unsigned int crtc_w,
 601                                   unsigned int crtc_h, uint32_t src_x,
 602                                   uint32_t src_y, uint32_t src_w,
 603                                   uint32_t src_h,
 604                                   struct drm_pending_vblank_event *event)
 605 {
 606         struct vop_win *vop_win = to_vop_win(plane);
 607         const struct vop_win_data *win = vop_win->data;
 608         struct vop *vop = to_vop(crtc);
 609         struct drm_gem_object *obj;
 610         struct rockchip_gem_object *rk_obj;
 611         unsigned long offset;
 612         unsigned int actual_w;
 613         unsigned int actual_h;
 614         unsigned int dsp_stx;
 615         unsigned int dsp_sty;
 616         unsigned int y_vir_stride;
 617         dma_addr_t yrgb_mst;
 618         enum vop_data_format format;
 619         uint32_t val;
 620         bool is_alpha;
 621         bool rb_swap;
 622         bool visible;
 623         int ret;
 624         struct drm_rect dest = {
 625                 .x1 = crtc_x,
 626                 .y1 = crtc_y,
 627                 .x2 = crtc_x + crtc_w,
 628                 .y2 = crtc_y + crtc_h,
 629         };
 630         struct drm_rect src = {
 631                 /* 16.16 fixed point */
 632                 .x1 = src_x,
 633                 .y1 = src_y,
 634                 .x2 = src_x + src_w,
 635                 .y2 = src_y + src_h,
 636         };
 637         const struct drm_rect clip = {
 638                 .x2 = crtc->mode.hdisplay,
 639                 .y2 = crtc->mode.vdisplay,
 640         };
 641         bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
 642
 643         ret = drm_plane_helper_check_update(plane, crtc, fb,
 644                                             &src, &dest, &clip,
 645                                             DRM_PLANE_HELPER_NO_SCALING,
 646                                             DRM_PLANE_HELPER_NO_SCALING,
 647                                             can_position, false, &visible);
 648         if (ret)
 649                 return ret;
 650
 651         if (!visible)
 652                 return 0;
 653
 654         is_alpha = is_alpha_support(fb->pixel_format);
 655         rb_swap = has_rb_swapped(fb->pixel_format);
 656         format = vop_convert_format(fb->pixel_format);
 657         if (format < 0)
 658                 return format;
 659
 660         obj = rockchip_fb_get_gem_obj(fb, 0);
 661         if (!obj) {
 662                 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
 663                 return -EINVAL;
 664         }
 665
 666         rk_obj = to_rockchip_obj(obj);
 667
 668         actual_w = (src.x2 - src.x1) >> 16;
 669         actual_h = (src.y2 - src.y1) >> 16;
 670         crtc_x = max(0, crtc_x);
 671         crtc_y = max(0, crtc_y);
 672
 673         dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start;
 674         dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start;
 675
 676         offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
 677         offset += (src.y1 >> 16) * fb->pitches[0];
 678         yrgb_mst = rk_obj->dma_addr + offset;
 679
 680         y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3);
 681
 682         /*
 683          * If this plane update changes the plane's framebuffer, (or more
 684          * precisely, if this update has a different framebuffer than the last
 685          * update), enqueue it so we can track when it completes.
 686          *
 687          * Only when we discover that this update has completed, can we
 688          * unreference any previous framebuffers.
 689          */
 690         mutex_lock(&vop->vsync_mutex);
 691         if (fb != vop_win_last_pending_fb(vop_win)) {
 692                 ret = drm_vblank_get(plane->dev, vop->pipe);
 693                 if (ret) {
 694                         DRM_ERROR("failed to get vblank, %d\n", ret);
 695                         mutex_unlock(&vop->vsync_mutex);
 696                         return ret;
 697                 }
 698
 699                 drm_framebuffer_reference(fb);
 700
 701                 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
 702                 if (ret) {
 703                         drm_vblank_put(plane->dev, vop->pipe);
 704                         mutex_unlock(&vop->vsync_mutex);
 705                         return ret;
 706                 }
 707
 708                 vop->vsync_work_pending = true;
 709         }
 710         mutex_unlock(&vop->vsync_mutex);
 711
 712         spin_lock(&vop->reg_lock);
 713
 714         VOP_WIN_SET(vop, win, format, format);
 715         VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 716         VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
 717         val = (actual_h - 1) << 16;
 718         val |= (actual_w - 1) & 0xffff;
 719         VOP_WIN_SET(vop, win, act_info, val);
 720         VOP_WIN_SET(vop, win, dsp_info, val);
 721         val = (dsp_sty - 1) << 16;
 722         val |= (dsp_stx - 1) & 0xffff;
 723         VOP_WIN_SET(vop, win, dsp_st, val);
 724         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 725
 726         if (is_alpha) {
 727                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 728                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 729                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 730                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 731                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 732                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 733                         SRC_FACTOR_M0(ALPHA_ONE);
 734                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 735         } else {
 736                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 737         }
 738
 739         VOP_WIN_SET(vop, win, enable, 1);
 740
 741         vop_cfg_done(vop);
 742         spin_unlock(&vop->reg_lock);
 743
 744         return 0;
 745 }
 746
 747 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 748                             struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 749                             unsigned int crtc_w, unsigned int crtc_h,
 750                             uint32_t src_x, uint32_t src_y, uint32_t src_w,
 751                             uint32_t src_h)
 752 {
 753         return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
 754                                       crtc_h, src_x, src_y, src_w, src_h,
 755                                       NULL);
 756 }
 757
 758 static int vop_update_primary_plane(struct drm_crtc *crtc,
 759                                     struct drm_pending_vblank_event *event)
 760 {
 761         unsigned int crtc_w, crtc_h;
 762
 763         crtc_w = crtc->primary->fb->width - crtc->x;
 764         crtc_h = crtc->primary->fb->height - crtc->y;
 765
 766         return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
 767                                       0, 0, crtc_w, crtc_h, crtc->x << 16,
 768                                       crtc->y << 16, crtc_w << 16,
 769                                       crtc_h << 16, event);
 770 }
 771
 772 static int vop_disable_plane(struct drm_plane *plane)
 773 {
 774         struct vop_win *vop_win = to_vop_win(plane);
 775         const struct vop_win_data *win = vop_win->data;
 776         struct vop *vop;
 777         int ret;
 778
 779         if (!plane->crtc)
 780                 return 0;
 781
 782         vop = to_vop(plane->crtc);
 783
 784         ret = drm_vblank_get(plane->dev, vop->pipe);
 785         if (ret) {
 786                 DRM_ERROR("failed to get vblank, %d\n", ret);
 787                 return ret;
 788         }
 789
 790         mutex_lock(&vop->vsync_mutex);
 791
 792         ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
 793         if (ret) {
 794                 drm_vblank_put(plane->dev, vop->pipe);
 795                 mutex_unlock(&vop->vsync_mutex);
 796                 return ret;
 797         }
 798
 799         vop->vsync_work_pending = true;
 800         mutex_unlock(&vop->vsync_mutex);
 801
 802         spin_lock(&vop->reg_lock);
 803         VOP_WIN_SET(vop, win, enable, 0);
 804         vop_cfg_done(vop);
 805         spin_unlock(&vop->reg_lock);
 806
 807         return 0;
 808 }
 809
 810 static void vop_plane_destroy(struct drm_plane *plane)
 811 {
 812         vop_disable_plane(plane);
 813         drm_plane_cleanup(plane);
 814 }
 815
 816 static const struct drm_plane_funcs vop_plane_funcs = {
 817         .update_plane = vop_update_plane,
 818         .disable_plane = vop_disable_plane,
 819         .destroy = vop_plane_destroy,
 820 };
 821
 822 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 823                                   int connector_type,
 824                                   int out_mode)
 825 {
 826         struct vop *vop = to_vop(crtc);
 827
 828         vop->connector_type = connector_type;
 829         vop->connector_out_mode = out_mode;
 830
 831         return 0;
 832 }
 833 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 834
 835 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 836 {
 837         struct vop *vop = to_vop(crtc);
 838         unsigned long flags;
 839
 840         if (!vop->is_enabled)
 841                 return -EPERM;
 842
 843         spin_lock_irqsave(&vop->irq_lock, flags);
 844
 845         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
 846
 847         spin_unlock_irqrestore(&vop->irq_lock, flags);
 848
 849         return 0;
 850 }
 851
 852 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 853 {
 854         struct vop *vop = to_vop(crtc);
 855         unsigned long flags;
 856
 857         if (!vop->is_enabled)
 858                 return;
 859
 860         spin_lock_irqsave(&vop->irq_lock, flags);
 861         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
 862         spin_unlock_irqrestore(&vop->irq_lock, flags);
 863 }
 864
 865 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 866         .enable_vblank = vop_crtc_enable_vblank,
 867         .disable_vblank = vop_crtc_disable_vblank,
 868 };
 869
 870 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
 871 {
 872         DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
 873
 874         switch (mode) {
 875         case DRM_MODE_DPMS_ON:
 876                 vop_enable(crtc);
 877                 break;
 878         case DRM_MODE_DPMS_STANDBY:
 879         case DRM_MODE_DPMS_SUSPEND:
 880         case DRM_MODE_DPMS_OFF:
 881                 vop_disable(crtc);
 882                 break;
 883         default:
 884                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 885                 break;
 886         }
 887 }
 888
 889 static void vop_crtc_prepare(struct drm_crtc *crtc)
 890 {
 891         vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 892 }
 893
 894 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 895                                 const struct drm_display_mode *mode,
 896                                 struct drm_display_mode *adjusted_mode)
 897 {
 898         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
 899                 return false;
 900
 901         return true;
 902 }
 903
 904 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 905                                   struct drm_framebuffer *old_fb)
 906 {
 907         int ret;
 908
 909         crtc->x = x;
 910         crtc->y = y;
 911
 912         ret = vop_update_primary_plane(crtc, NULL);
 913         if (ret < 0) {
 914                 DRM_ERROR("fail to update plane\n");
 915                 return ret;
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int vop_crtc_mode_set(struct drm_crtc *crtc,
 922                              struct drm_display_mode *mode,
 923                              struct drm_display_mode *adjusted_mode,
 924                              int x, int y, struct drm_framebuffer *fb)
 925 {
 926         struct vop *vop = to_vop(crtc);
 927         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 928         u16 hdisplay = adjusted_mode->hdisplay;
 929         u16 htotal = adjusted_mode->htotal;
 930         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 931         u16 hact_end = hact_st + hdisplay;
 932         u16 vdisplay = adjusted_mode->vdisplay;
 933         u16 vtotal = adjusted_mode->vtotal;
 934         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 935         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 936         u16 vact_end = vact_st + vdisplay;
 937         int ret, ret_clk;
 938         uint32_t val;
 939
 940         /*
 941          * disable dclk to stop frame scan, so that we can safe config mode and
 942          * enable iommu.
 943          */
 944         clk_disable(vop->dclk);
 945
 946         switch (vop->connector_type) {
 947         case DRM_MODE_CONNECTOR_LVDS:
 948                 VOP_CTRL_SET(vop, rgb_en, 1);
 949                 break;
 950         case DRM_MODE_CONNECTOR_eDP:
 951                 VOP_CTRL_SET(vop, edp_en, 1);
 952                 break;
 953         case DRM_MODE_CONNECTOR_HDMIA:
 954                 VOP_CTRL_SET(vop, hdmi_en, 1);
 955                 break;
 956         default:
 957                 DRM_ERROR("unsupport connector_type[%d]\n",
 958                           vop->connector_type);
 959                 ret = -EINVAL;
 960                 goto out;
 961         };
 962         VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
 963
 964         val = 0x8;
 965         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
 966         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
 967         VOP_CTRL_SET(vop, pin_pol, val);
 968
 969         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 970         val = hact_st << 16;
 971         val |= hact_end;
 972         VOP_CTRL_SET(vop, hact_st_end, val);
 973         VOP_CTRL_SET(vop, hpost_st_end, val);
 974
 975         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 976         val = vact_st << 16;
 977         val |= vact_end;
 978         VOP_CTRL_SET(vop, vact_st_end, val);
 979         VOP_CTRL_SET(vop, vpost_st_end, val);
 980
 981         ret = vop_crtc_mode_set_base(crtc, x, y, fb);
 982         if (ret)
 983                 goto out;
 984
 985         /*
 986          * reset dclk, take all mode config affect, so the clk would run in
 987          * correct frame.
 988          */
 989         reset_control_assert(vop->dclk_rst);
 990         usleep_range(10, 20);
 991         reset_control_deassert(vop->dclk_rst);
 992
 993         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 994 out:
 995         ret_clk = clk_enable(vop->dclk);
 996         if (ret_clk < 0) {
 997                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
 998                 return ret_clk;
 999         }
1000
1001         return ret;
1002 }
1003
1004 static void vop_crtc_commit(struct drm_crtc *crtc)
1005 {
1006 }
1007
1008 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1009         .dpms = vop_crtc_dpms,
1010         .prepare = vop_crtc_prepare,
1011         .mode_fixup = vop_crtc_mode_fixup,
1012         .mode_set = vop_crtc_mode_set,
1013         .mode_set_base = vop_crtc_mode_set_base,
1014         .commit = vop_crtc_commit,
1015 };
1016
1017 static int vop_crtc_page_flip(struct drm_crtc *crtc,
1018                               struct drm_framebuffer *fb,
1019                               struct drm_pending_vblank_event *event,
1020                               uint32_t page_flip_flags)
1021 {
1022         struct vop *vop = to_vop(crtc);
1023         struct drm_framebuffer *old_fb = crtc->primary->fb;
1024         int ret;
1025
1026         /* when the page flip is requested, crtc should be on */
1027         if (!vop->is_enabled) {
1028                 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1029                 return 0;
1030         }
1031
1032         crtc->primary->fb = fb;
1033
1034         ret = vop_update_primary_plane(crtc, event);
1035         if (ret)
1036                 crtc->primary->fb = old_fb;
1037
1038         return ret;
1039 }
1040
1041 static void vop_win_state_complete(struct vop_win *vop_win,
1042                                    struct vop_win_state *state)
1043 {
1044         struct vop *vop = vop_win->vop;
1045         struct drm_crtc *crtc = &vop->crtc;
1046         struct drm_device *drm = crtc->dev;
1047         unsigned long flags;
1048
1049         if (state->event) {
1050                 spin_lock_irqsave(&drm->event_lock, flags);
1051                 drm_send_vblank_event(drm, -1, state->event);
1052                 spin_unlock_irqrestore(&drm->event_lock, flags);
1053         }
1054
1055         list_del(&state->head);
1056         drm_vblank_put(crtc->dev, vop->pipe);
1057 }
1058
1059 static void vop_crtc_destroy(struct drm_crtc *crtc)
1060 {
1061         drm_crtc_cleanup(crtc);
1062 }
1063
1064 static const struct drm_crtc_funcs vop_crtc_funcs = {
1065         .set_config = drm_crtc_helper_set_config,
1066         .page_flip = vop_crtc_page_flip,
1067         .destroy = vop_crtc_destroy,
1068 };
1069
1070 static bool vop_win_state_is_active(struct vop_win *vop_win,
1071                                     struct vop_win_state *state)
1072 {
1073         bool active = false;
1074
1075         if (state->fb) {
1076                 dma_addr_t yrgb_mst;
1077
1078                 /* check yrgb_mst to tell if pending_fb is now front */
1079                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1080
1081                 active = (yrgb_mst == state->yrgb_mst);
1082         } else {
1083                 bool enabled;
1084
1085                 /* if enable bit is clear, plane is now disabled */
1086                 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1087
1088                 active = (enabled == 0);
1089         }
1090
1091         return active;
1092 }
1093
1094 static void vop_win_state_destroy(struct vop_win_state *state)
1095 {
1096         struct drm_framebuffer *fb = state->fb;
1097
1098         if (fb)
1099                 drm_framebuffer_unreference(fb);
1100
1101         kfree(state);
1102 }
1103
1104 static void vop_win_update_state(struct vop_win *vop_win)
1105 {
1106         struct vop_win_state *state, *n, *new_active = NULL;
1107
1108         /* Check if any pending states are now active */
1109         list_for_each_entry(state, &vop_win->pending, head)
1110                 if (vop_win_state_is_active(vop_win, state)) {
1111                         new_active = state;
1112                         break;
1113                 }
1114
1115         if (!new_active)
1116                 return;
1117
1118         /*
1119          * Destroy any 'skipped' pending states - states that were queued
1120          * before the newly active state.
1121          */
1122         list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1123                 if (state == new_active)
1124                         break;
1125                 vop_win_state_complete(vop_win, state);
1126                 vop_win_state_destroy(state);
1127         }
1128
1129         vop_win_state_complete(vop_win, new_active);
1130
1131         if (vop_win->active)
1132                 vop_win_state_destroy(vop_win->active);
1133         vop_win->active = new_active;
1134 }
1135
1136 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1137 {
1138         return !list_empty(&vop_win->pending);
1139 }
1140
1141 static irqreturn_t vop_isr_thread(int irq, void *data)
1142 {
1143         struct vop *vop = data;
1144         const struct vop_data *vop_data = vop->data;
1145         unsigned int i;
1146
1147         mutex_lock(&vop->vsync_mutex);
1148
1149         if (!vop->vsync_work_pending)
1150                 goto done;
1151
1152         vop->vsync_work_pending = false;
1153
1154         for (i = 0; i < vop_data->win_size; i++) {
1155                 struct vop_win *vop_win = &vop->win[i];
1156
1157                 vop_win_update_state(vop_win);
1158                 if (vop_win_has_pending_state(vop_win))
1159                         vop->vsync_work_pending = true;
1160         }
1161
1162 done:
1163         mutex_unlock(&vop->vsync_mutex);
1164
1165         return IRQ_HANDLED;
1166 }
1167
1168 static irqreturn_t vop_isr(int irq, void *data)
1169 {
1170         struct vop *vop = data;
1171         uint32_t intr0_reg, active_irqs;
1172         unsigned long flags;
1173         int ret = IRQ_NONE;
1174
1175         /*
1176          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1177          * must hold irq_lock to avoid a race with enable/disable_vblank().
1178         */
1179         spin_lock_irqsave(&vop->irq_lock, flags);
1180         intr0_reg = vop_readl(vop, INTR_CTRL0);
1181         active_irqs = intr0_reg & INTR_MASK;
1182         /* Clear all active interrupt sources */
1183         if (active_irqs)
1184                 vop_writel(vop, INTR_CTRL0,
1185                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1186         spin_unlock_irqrestore(&vop->irq_lock, flags);
1187
1188         /* This is expected for vop iommu irqs, since the irq is shared */
1189         if (!active_irqs)
1190                 return IRQ_NONE;
1191
1192         if (active_irqs & DSP_HOLD_VALID_INTR) {
1193                 complete(&vop->dsp_hold_completion);
1194                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1195                 ret = IRQ_HANDLED;
1196         }
1197
1198         if (active_irqs & FS_INTR) {
1199                 drm_handle_vblank(vop->drm_dev, vop->pipe);
1200                 active_irqs &= ~FS_INTR;
1201                 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1202         }
1203
1204         /* Unhandled irqs are spurious. */
1205         if (active_irqs)
1206                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1207
1208         return ret;
1209 }
1210
1211 static int vop_create_crtc(struct vop *vop)
1212 {
1213         const struct vop_data *vop_data = vop->data;
1214         struct device *dev = vop->dev;
1215         struct drm_device *drm_dev = vop->drm_dev;
1216         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1217         struct drm_crtc *crtc = &vop->crtc;
1218         struct device_node *port;
1219         int ret;
1220         int i;
1221
1222         /*
1223          * Create drm_plane for primary and cursor planes first, since we need
1224          * to pass them to drm_crtc_init_with_planes, which sets the
1225          * "possible_crtcs" to the newly initialized crtc.
1226          */
1227         for (i = 0; i < vop_data->win_size; i++) {
1228                 struct vop_win *vop_win = &vop->win[i];
1229                 const struct vop_win_data *win_data = vop_win->data;
1230
1231                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1232                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1233                         continue;
1234
1235                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1236                                                0, &vop_plane_funcs,
1237                                                win_data->phy->data_formats,
1238                                                win_data->phy->nformats,
1239                                                win_data->type);
1240                 if (ret) {
1241                         DRM_ERROR("failed to initialize plane\n");
1242                         goto err_cleanup_planes;
1243                 }
1244
1245                 plane = &vop_win->base;
1246                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1247                         primary = plane;
1248                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1249                         cursor = plane;
1250         }
1251
1252         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1253                                         &vop_crtc_funcs);
1254         if (ret)
1255                 return ret;
1256
1257         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1258
1259         /*
1260          * Create drm_planes for overlay windows with possible_crtcs restricted
1261          * to the newly created crtc.
1262          */
1263         for (i = 0; i < vop_data->win_size; i++) {
1264                 struct vop_win *vop_win = &vop->win[i];
1265                 const struct vop_win_data *win_data = vop_win->data;
1266                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1267
1268                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1269                         continue;
1270
1271                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1272                                                possible_crtcs,
1273                                                &vop_plane_funcs,
1274                                                win_data->phy->data_formats,
1275                                                win_data->phy->nformats,
1276                                                win_data->type);
1277                 if (ret) {
1278                         DRM_ERROR("failed to initialize overlay plane\n");
1279                         goto err_cleanup_crtc;
1280                 }
1281         }
1282
1283         port = of_get_child_by_name(dev->of_node, "port");
1284         if (!port) {
1285                 DRM_ERROR("no port node found in %s\n",
1286                           dev->of_node->full_name);
1287                 goto err_cleanup_crtc;
1288         }
1289
1290         init_completion(&vop->dsp_hold_completion);
1291         crtc->port = port;
1292         vop->pipe = drm_crtc_index(crtc);
1293         rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1294
1295         return 0;
1296
1297 err_cleanup_crtc:
1298         drm_crtc_cleanup(crtc);
1299 err_cleanup_planes:
1300         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1301                 drm_plane_cleanup(plane);
1302         return ret;
1303 }
1304
1305 static void vop_destroy_crtc(struct vop *vop)
1306 {
1307         struct drm_crtc *crtc = &vop->crtc;
1308
1309         rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1310         of_node_put(crtc->port);
1311         drm_crtc_cleanup(crtc);
1312 }
1313
1314 static int vop_initial(struct vop *vop)
1315 {
1316         const struct vop_data *vop_data = vop->data;
1317         const struct vop_reg_data *init_table = vop_data->init_table;
1318         struct reset_control *ahb_rst;
1319         int i, ret;
1320
1321         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1322         if (IS_ERR(vop->hclk)) {
1323                 dev_err(vop->dev, "failed to get hclk source\n");
1324                 return PTR_ERR(vop->hclk);
1325         }
1326         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1327         if (IS_ERR(vop->aclk)) {
1328                 dev_err(vop->dev, "failed to get aclk source\n");
1329                 return PTR_ERR(vop->aclk);
1330         }
1331         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1332         if (IS_ERR(vop->dclk)) {
1333                 dev_err(vop->dev, "failed to get dclk source\n");
1334                 return PTR_ERR(vop->dclk);
1335         }
1336
1337         ret = clk_prepare(vop->hclk);
1338         if (ret < 0) {
1339                 dev_err(vop->dev, "failed to prepare hclk\n");
1340                 return ret;
1341         }
1342
1343         ret = clk_prepare(vop->dclk);
1344         if (ret < 0) {
1345                 dev_err(vop->dev, "failed to prepare dclk\n");
1346                 goto err_unprepare_hclk;
1347         }
1348
1349         ret = clk_prepare(vop->aclk);
1350         if (ret < 0) {
1351                 dev_err(vop->dev, "failed to prepare aclk\n");
1352                 goto err_unprepare_dclk;
1353         }
1354
1355         /*
1356          * enable hclk, so that we can config vop register.
1357          */
1358         ret = clk_enable(vop->hclk);
1359         if (ret < 0) {
1360                 dev_err(vop->dev, "failed to prepare aclk\n");
1361                 goto err_unprepare_aclk;
1362         }
1363         /*
1364          * do hclk_reset, reset all vop registers.
1365          */
1366         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1367         if (IS_ERR(ahb_rst)) {
1368                 dev_err(vop->dev, "failed to get ahb reset\n");
1369                 ret = PTR_ERR(ahb_rst);
1370                 goto err_disable_hclk;
1371         }
1372         reset_control_assert(ahb_rst);
1373         usleep_range(10, 20);
1374         reset_control_deassert(ahb_rst);
1375
1376         memcpy(vop->regsbak, vop->regs, vop->len);
1377
1378         for (i = 0; i < vop_data->table_size; i++)
1379                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1380
1381         for (i = 0; i < vop_data->win_size; i++) {
1382                 const struct vop_win_data *win = &vop_data->win[i];
1383
1384                 VOP_WIN_SET(vop, win, enable, 0);
1385         }
1386
1387         vop_cfg_done(vop);
1388
1389         /*
1390          * do dclk_reset, let all config take affect.
1391          */
1392         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1393         if (IS_ERR(vop->dclk_rst)) {
1394                 dev_err(vop->dev, "failed to get dclk reset\n");
1395                 ret = PTR_ERR(vop->dclk_rst);
1396                 goto err_unprepare_aclk;
1397         }
1398         reset_control_assert(vop->dclk_rst);
1399         usleep_range(10, 20);
1400         reset_control_deassert(vop->dclk_rst);
1401
1402         clk_disable(vop->hclk);
1403
1404         vop->is_enabled = false;
1405
1406         return 0;
1407
1408 err_disable_hclk:
1409         clk_disable(vop->hclk);
1410 err_unprepare_aclk:
1411         clk_unprepare(vop->aclk);
1412 err_unprepare_dclk:
1413         clk_unprepare(vop->dclk);
1414 err_unprepare_hclk:
1415         clk_unprepare(vop->hclk);
1416         return ret;
1417 }
1418
1419 /*
1420  * Initialize the vop->win array elements.
1421  */
1422 static void vop_win_init(struct vop *vop)
1423 {
1424         const struct vop_data *vop_data = vop->data;
1425         unsigned int i;
1426
1427         for (i = 0; i < vop_data->win_size; i++) {
1428                 struct vop_win *vop_win = &vop->win[i];
1429                 const struct vop_win_data *win_data = &vop_data->win[i];
1430
1431                 vop_win->data = win_data;
1432                 vop_win->vop = vop;
1433                 INIT_LIST_HEAD(&vop_win->pending);
1434         }
1435 }
1436
1437 static int vop_bind(struct device *dev, struct device *master, void *data)
1438 {
1439         struct platform_device *pdev = to_platform_device(dev);
1440         const struct of_device_id *of_id;
1441         const struct vop_data *vop_data;
1442         struct drm_device *drm_dev = data;
1443         struct vop *vop;
1444         struct resource *res;
1445         size_t alloc_size;
1446         int ret, irq;
1447
1448         of_id = of_match_device(vop_driver_dt_match, dev);
1449         vop_data = of_id->data;
1450         if (!vop_data)
1451                 return -ENODEV;
1452
1453         /* Allocate vop struct and its vop_win array */
1454         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1455         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1456         if (!vop)
1457                 return -ENOMEM;
1458
1459         vop->dev = dev;
1460         vop->data = vop_data;
1461         vop->drm_dev = drm_dev;
1462         dev_set_drvdata(dev, vop);
1463
1464         vop_win_init(vop);
1465
1466         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1467         vop->len = resource_size(res);
1468         vop->regs = devm_ioremap_resource(dev, res);
1469         if (IS_ERR(vop->regs))
1470                 return PTR_ERR(vop->regs);
1471
1472         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1473         if (!vop->regsbak)
1474                 return -ENOMEM;
1475
1476         ret = vop_initial(vop);
1477         if (ret < 0) {
1478                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1479                 return ret;
1480         }
1481
1482         irq = platform_get_irq(pdev, 0);
1483         if (irq < 0) {
1484                 dev_err(dev, "cannot find irq for vop\n");
1485                 return irq;
1486         }
1487         vop->irq = (unsigned int)irq;
1488
1489         spin_lock_init(&vop->reg_lock);
1490         spin_lock_init(&vop->irq_lock);
1491
1492         mutex_init(&vop->vsync_mutex);
1493
1494         ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1495                                         IRQF_SHARED, dev_name(dev), vop);
1496         if (ret)
1497                 return ret;
1498
1499         /* IRQ is initially disabled; it gets enabled in power_on */
1500         disable_irq(vop->irq);
1501
1502         ret = vop_create_crtc(vop);
1503         if (ret)
1504                 return ret;
1505
1506         pm_runtime_enable(&pdev->dev);
1507         return 0;
1508 }
1509
1510 static void vop_unbind(struct device *dev, struct device *master, void *data)
1511 {
1512         struct vop *vop = dev_get_drvdata(dev);
1513
1514         pm_runtime_disable(dev);
1515         vop_destroy_crtc(vop);
1516 }
1517
1518 static const struct component_ops vop_component_ops = {
1519         .bind = vop_bind,
1520         .unbind = vop_unbind,
1521 };
1522
1523 static int vop_probe(struct platform_device *pdev)
1524 {
1525         struct device *dev = &pdev->dev;
1526
1527         if (!dev->of_node) {
1528                 dev_err(dev, "can't find vop devices\n");
1529                 return -ENODEV;
1530         }
1531
1532         return component_add(dev, &vop_component_ops);
1533 }
1534
1535 static int vop_remove(struct platform_device *pdev)
1536 {
1537         component_del(&pdev->dev, &vop_component_ops);
1538
1539         return 0;
1540 }
1541
1542 struct platform_driver vop_platform_driver = {
1543         .probe = vop_probe,
1544         .remove = vop_remove,
1545         .driver = {
1546                 .name = "rockchip-vop",
1547                 .owner = THIS_MODULE,
1548                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1549         },
1550 };
1551
1552 module_platform_driver(vop_platform_driver);
1553
1554 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1555 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1556 MODULE_LICENSE("GPL v2");