drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/iopoll.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/component.h>
  31
  32 #include <linux/reset.h>
  33 #include <linux/delay.h>
  34 #include <linux/sort.h>
  35 #include <uapi/drm/rockchip_drm.h>
  36
  37 #include "rockchip_drm_drv.h"
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_fb.h"
  40 #include "rockchip_drm_vop.h"
  41
  42 #define VOP_REG_SUPPORT(vop, reg) \
  43                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  44                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  45                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  46                 reg.mask))
  47
  48 #define VOP_WIN_SUPPORT(vop, win, name) \
  49                 VOP_REG_SUPPORT(vop, win->phy->name)
  50
  51 #define VOP_CTRL_SUPPORT(vop, name) \
  52                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  53
  54 #define VOP_INTR_SUPPORT(vop, name) \
  55                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  56
  57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  58                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  59
  60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  61         do { \
  62                 if (VOP_REG_SUPPORT(vop, reg)) \
  63                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  64                                   v, reg.write_mask, relaxed); \
  65                 else \
  66                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  67         } while(0)
  68
  69 #define REG_SET(x, name, off, reg, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  72                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  73
  74 #define VOP_WIN_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  77                 REG_SET(x, name, 0, win->ext->name, v, true)
  78 #define VOP_SCL_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  80 #define VOP_SCL_SET_EXT(x, win, name, v) \
  81                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  82
  83 #define VOP_CTRL_SET(x, name, v) \
  84                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  85
  86 #define VOP_INTR_GET(vop, name) \
  87                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  88
  89 #define VOP_INTR_SET(vop, name, v) \
  90                 REG_SET(vop, name, 0, vop->data->intr->name, \
  91                         v, false)
  92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  93                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  94                              mask, v, false)
  95
  96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  97         do { \
  98                 int i, reg = 0, mask = 0; \
  99                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 100                         if (vop->data->intr->intrs[i] & type) { \
 101                                 reg |= (v) << i; \
 102                                 mask |= 1 << i; \
 103                         } \
 104                 } \
 105                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 106         } while (0)
 107 #define VOP_INTR_GET_TYPE(vop, name, type) \
 108                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 109
 110 #define VOP_CTRL_GET(x, name) \
 111                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 112
 113 #define VOP_WIN_GET(x, win, name) \
 114                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 115
 116 #define VOP_WIN_NAME(win, name) \
 117                 (vop_get_win_phy(win, &win->phy->name)->name)
 118
 119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 120                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 121
 122 #define to_vop(x) container_of(x, struct vop, crtc)
 123 #define to_vop_win(x) container_of(x, struct vop_win, base)
 124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 125
 126 struct vop_zpos {
 127         int win_id;
 128         int zpos;
 129 };
 130
 131 struct vop_plane_state {
 132         struct drm_plane_state base;
 133         int format;
 134         int zpos;
 135         struct drm_rect src;
 136         struct drm_rect dest;
 137         dma_addr_t yrgb_mst;
 138         dma_addr_t uv_mst;
 139         const uint32_t *y2r_table;
 140         const uint32_t *r2r_table;
 141         const uint32_t *r2y_table;
 142         bool enable;
 143 };
 144
 145 struct vop_win {
 146         struct vop_win *parent;
 147         struct drm_plane base;
 148
 149         int win_id;
 150         int area_id;
 151         uint32_t offset;
 152         enum drm_plane_type type;
 153         const struct vop_win_phy *phy;
 154         const struct vop_csc *csc;
 155         const uint32_t *data_formats;
 156         uint32_t nformats;
 157         struct vop *vop;
 158
 159         struct drm_property *rotation_prop;
 160         struct vop_plane_state state;
 161 };
 162
 163 struct vop {
 164         struct drm_crtc crtc;
 165         struct device *dev;
 166         struct drm_device *drm_dev;
 167         struct drm_property *plane_zpos_prop;
 168         struct drm_property *plane_feature_prop;
 169         struct drm_property *feature_prop;
 170         bool is_iommu_enabled;
 171         bool is_iommu_needed;
 172         bool is_enabled;
 173
 174         /* mutex vsync_ work */
 175         struct mutex vsync_mutex;
 176         bool vsync_work_pending;
 177         bool loader_protect;
 178         struct completion dsp_hold_completion;
 179         struct completion wait_update_complete;
 180         struct drm_pending_vblank_event *event;
 181
 182         struct completion line_flag_completion;
 183
 184         const struct vop_data *data;
 185         int num_wins;
 186
 187         uint32_t *regsbak;
 188         void __iomem *regs;
 189
 190         /* physical map length of vop register */
 191         uint32_t len;
 192
 193         /* one time only one process allowed to config the register */
 194         spinlock_t reg_lock;
 195         /* lock vop irq reg */
 196         spinlock_t irq_lock;
 197
 198         unsigned int irq;
 199
 200         /* vop AHP clk */
 201         struct clk *hclk;
 202         /* vop dclk */
 203         struct clk *dclk;
 204         /* vop share memory frequency */
 205         struct clk *aclk;
 206
 207         /* vop dclk reset */
 208         struct reset_control *dclk_rst;
 209
 210         struct vop_win win[];
 211 };
 212
 213 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 214 {
 215         writel(v, vop->regs + offset);
 216         vop->regsbak[offset >> 2] = v;
 217 }
 218
 219 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 220 {
 221         return readl(vop->regs + offset);
 222 }
 223
 224 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 225                                     const struct vop_reg *reg)
 226 {
 227         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 228 }
 229
 230 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 231                                   uint32_t mask, uint32_t shift, uint32_t v,
 232                                   bool write_mask, bool relaxed)
 233 {
 234         if (!mask)
 235                 return;
 236
 237         if (write_mask) {
 238                 v = ((v & mask) << shift) | (mask << (shift + 16));
 239         } else {
 240                 uint32_t cached_val = vop->regsbak[offset >> 2];
 241
 242                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 243                 vop->regsbak[offset >> 2] = v;
 244         }
 245
 246         if (relaxed)
 247                 writel_relaxed(v, vop->regs + offset);
 248         else
 249                 writel(v, vop->regs + offset);
 250 }
 251
 252 static inline const struct vop_win_phy *
 253 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 254 {
 255         if (!reg->mask && win->parent)
 256                 return win->parent->phy;
 257
 258         return win->phy;
 259 }
 260
 261 static inline uint32_t vop_get_intr_type(struct vop *vop,
 262                                          const struct vop_reg *reg, int type)
 263 {
 264         uint32_t i, ret = 0;
 265         uint32_t regs = vop_read_reg(vop, 0, reg);
 266
 267         for (i = 0; i < vop->data->intr->nintrs; i++) {
 268                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 269                         ret |= vop->data->intr->intrs[i];
 270         }
 271
 272         return ret;
 273 }
 274
 275 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 276 {
 277         int i;
 278
 279         if (!table)
 280                 return;
 281
 282         for (i = 0; i < 8; i++)
 283                 vop_writel(vop, offset + i * 4, table[i]);
 284 }
 285
 286 static inline void vop_cfg_done(struct vop *vop)
 287 {
 288         VOP_CTRL_SET(vop, cfg_done, 1);
 289 }
 290
 291 static bool vop_is_allwin_disabled(struct vop *vop)
 292 {
 293         int i;
 294
 295         for (i = 0; i < vop->num_wins; i++) {
 296                 struct vop_win *win = &vop->win[i];
 297
 298                 if (VOP_WIN_GET(vop, win, enable) != 0)
 299                         return false;
 300         }
 301
 302         return true;
 303 }
 304
 305 static bool vop_is_cfg_done_complete(struct vop *vop)
 306 {
 307         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 308 }
 309
 310 static bool vop_fs_irq_is_active(struct vop *vop)
 311 {
 312         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 313 }
 314
 315 static bool vop_line_flag_is_active(struct vop *vop)
 316 {
 317         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 318 }
 319
 320 static bool has_rb_swapped(uint32_t format)
 321 {
 322         switch (format) {
 323         case DRM_FORMAT_XBGR8888:
 324         case DRM_FORMAT_ABGR8888:
 325         case DRM_FORMAT_BGR888:
 326         case DRM_FORMAT_BGR565:
 327                 return true;
 328         default:
 329                 return false;
 330         }
 331 }
 332
 333 static enum vop_data_format vop_convert_format(uint32_t format)
 334 {
 335         switch (format) {
 336         case DRM_FORMAT_XRGB8888:
 337         case DRM_FORMAT_ARGB8888:
 338         case DRM_FORMAT_XBGR8888:
 339         case DRM_FORMAT_ABGR8888:
 340                 return VOP_FMT_ARGB8888;
 341         case DRM_FORMAT_RGB888:
 342         case DRM_FORMAT_BGR888:
 343                 return VOP_FMT_RGB888;
 344         case DRM_FORMAT_RGB565:
 345         case DRM_FORMAT_BGR565:
 346                 return VOP_FMT_RGB565;
 347         case DRM_FORMAT_NV12:
 348         case DRM_FORMAT_NV12_10:
 349                 return VOP_FMT_YUV420SP;
 350         case DRM_FORMAT_NV16:
 351         case DRM_FORMAT_NV16_10:
 352                 return VOP_FMT_YUV422SP;
 353         case DRM_FORMAT_NV24:
 354         case DRM_FORMAT_NV24_10:
 355                 return VOP_FMT_YUV444SP;
 356         default:
 357                 DRM_ERROR("unsupport format[%08x]\n", format);
 358                 return -EINVAL;
 359         }
 360 }
 361
 362 static bool is_yuv_support(uint32_t format)
 363 {
 364         switch (format) {
 365         case DRM_FORMAT_NV12:
 366         case DRM_FORMAT_NV12_10:
 367         case DRM_FORMAT_NV16:
 368         case DRM_FORMAT_NV16_10:
 369         case DRM_FORMAT_NV24:
 370         case DRM_FORMAT_NV24_10:
 371                 return true;
 372         default:
 373                 return false;
 374         }
 375 }
 376
 377 static bool is_yuv_10bit(uint32_t format)
 378 {
 379         switch (format) {
 380         case DRM_FORMAT_NV12_10:
 381         case DRM_FORMAT_NV16_10:
 382         case DRM_FORMAT_NV24_10:
 383                 return true;
 384         default:
 385                 return false;
 386         }
 387 }
 388
 389 static bool is_alpha_support(uint32_t format)
 390 {
 391         switch (format) {
 392         case DRM_FORMAT_ARGB8888:
 393         case DRM_FORMAT_ABGR8888:
 394                 return true;
 395         default:
 396                 return false;
 397         }
 398 }
 399
 400 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 401                                   uint32_t dst, bool is_horizontal,
 402                                   int vsu_mode, int *vskiplines)
 403 {
 404         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 405
 406         if (is_horizontal) {
 407                 if (mode == SCALE_UP)
 408                         val = GET_SCL_FT_BIC(src, dst);
 409                 else if (mode == SCALE_DOWN)
 410                         val = GET_SCL_FT_BILI_DN(src, dst);
 411         } else {
 412                 if (mode == SCALE_UP) {
 413                         if (vsu_mode == SCALE_UP_BIL)
 414                                 val = GET_SCL_FT_BILI_UP(src, dst);
 415                         else
 416                                 val = GET_SCL_FT_BIC(src, dst);
 417                 } else if (mode == SCALE_DOWN) {
 418                         if (vskiplines) {
 419                                 *vskiplines = scl_get_vskiplines(src, dst);
 420                                 val = scl_get_bili_dn_vskip(src, dst,
 421                                                             *vskiplines);
 422                         } else {
 423                                 val = GET_SCL_FT_BILI_DN(src, dst);
 424                         }
 425                 }
 426         }
 427
 428         return val;
 429 }
 430
 431 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 432                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 433                                 uint32_t dst_h, uint32_t pixel_format)
 434 {
 435         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 436         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 437         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 438         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 439         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 440         bool is_yuv = is_yuv_support(pixel_format);
 441         uint16_t cbcr_src_w = src_w / hsub;
 442         uint16_t cbcr_src_h = src_h / vsub;
 443         uint16_t vsu_mode;
 444         uint16_t lb_mode;
 445         uint32_t val;
 446         int vskiplines = 0;
 447
 448         if (!win->phy->scl)
 449                 return;
 450
 451         if (dst_w > 3840) {
 452                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 453                 return;
 454         }
 455
 456         if (!win->phy->scl->ext) {
 457                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 458                             scl_cal_scale2(src_w, dst_w));
 459                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 460                             scl_cal_scale2(src_h, dst_h));
 461                 if (is_yuv) {
 462                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 463                                     scl_cal_scale2(cbcr_src_w, dst_w));
 464                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 465                                     scl_cal_scale2(cbcr_src_h, dst_h));
 466                 }
 467                 return;
 468         }
 469
 470         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 471         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 472
 473         if (is_yuv) {
 474                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 475                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 476                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 477                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 478                 else
 479                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 480         } else {
 481                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 482                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 483                 else
 484                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 485         }
 486
 487         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 488         if (lb_mode == LB_RGB_3840X2) {
 489                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 490                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 491                         return;
 492                 }
 493                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 494                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 495                         return;
 496                 }
 497                 vsu_mode = SCALE_UP_BIL;
 498         } else if (lb_mode == LB_RGB_2560X4) {
 499                 vsu_mode = SCALE_UP_BIL;
 500         } else {
 501                 vsu_mode = SCALE_UP_BIC;
 502         }
 503
 504         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 505                                 true, 0, NULL);
 506         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 507         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 508                                 false, vsu_mode, &vskiplines);
 509         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 510
 511         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 512         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 513
 514         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 515         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 516         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 517         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 518         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 519         if (is_yuv) {
 520                 vskiplines = 0;
 521
 522                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 523                                         dst_w, true, 0, NULL);
 524                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 525                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 526                                         dst_h, false, vsu_mode, &vskiplines);
 527                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 528
 529                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 530                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 531                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 532                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 533                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 534                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 535                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 536         }
 537 }
 538
 539 /*
 540  * rk3399 colorspace path:
 541  *      Input        Win csc                     Output
 542  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 543  *    RGB        --> R2Y                  __/
 544  *
 545  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 546  *    RGB        --> 709To2020->R2Y       __/
 547  *
 548  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 549  *    RGB        --> R2Y                  __/
 550  *
 551  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 552  *    RGB        --> 709To2020->R2Y       __/
 553  *
 554  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 555  *    RGB        --> R2Y                  __/
 556  *
 557  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 558  *    RGB        --> R2Y(601)             __/
 559  *
 560  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 561  *    RGB        --> bypass               __/
 562  *
 563  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 564  *
 565  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 566  *
 567  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 568  *
 569  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 570  */
 571 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 572                          bool is_input_yuv, bool is_output_yuv,
 573                          int input_csc, int output_csc,
 574                          const uint32_t **y2r_table,
 575                          const uint32_t **r2r_table,
 576                          const uint32_t **r2y_table)
 577 {
 578         *y2r_table = NULL;
 579         *r2r_table = NULL;
 580         *r2y_table = NULL;
 581
 582         if (is_output_yuv) {
 583                 if (output_csc == CSC_BT2020) {
 584                         if (is_input_yuv) {
 585                                 if (input_csc == CSC_BT2020)
 586                                         return 0;
 587                                 *y2r_table = csc_table->y2r_bt709;
 588                         }
 589                         if (input_csc != CSC_BT2020)
 590                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 591                         *r2y_table = csc_table->r2y_bt2020;
 592                 } else {
 593                         if (is_input_yuv && input_csc == CSC_BT2020)
 594                                 *y2r_table = csc_table->y2r_bt2020;
 595                         if (input_csc == CSC_BT2020)
 596                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 597                         if (!is_input_yuv || *y2r_table) {
 598                                 if (output_csc == CSC_BT709)
 599                                         *r2y_table = csc_table->r2y_bt709;
 600                                 else
 601                                         *r2y_table = csc_table->r2y_bt601;
 602                         }
 603                 }
 604         } else {
 605                 if (!is_input_yuv)
 606                         return 0;
 607
 608                 /*
 609                  * is possible use bt2020 on rgb mode?
 610                  */
 611                 if (WARN_ON(output_csc == CSC_BT2020))
 612                         return -EINVAL;
 613
 614                 if (input_csc == CSC_BT2020)
 615                         *y2r_table = csc_table->y2r_bt2020;
 616                 else if (input_csc == CSC_BT709)
 617                         *y2r_table = csc_table->y2r_bt709;
 618                 else
 619                         *y2r_table = csc_table->y2r_bt601;
 620
 621                 if (input_csc == CSC_BT2020)
 622                         /*
 623                          * We don't have bt601 to bt709 table, force use bt709.
 624                          */
 625                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 626         }
 627
 628         return 0;
 629 }
 630
 631 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 632                                 struct drm_crtc_state *crtc_state)
 633 {
 634         struct vop *vop = to_vop(crtc);
 635         struct drm_atomic_state *state = crtc_state->state;
 636         const struct vop_csc_table *csc_table = vop->data->csc_table;
 637         struct drm_plane_state *pstate;
 638         struct drm_plane *plane;
 639         bool is_yuv;
 640         int ret;
 641
 642         if (!csc_table)
 643                 return 0;
 644
 645         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 646                 struct vop_plane_state *vop_plane_state;
 647
 648                 pstate = drm_atomic_get_plane_state(state, plane);
 649                 if (IS_ERR(pstate))
 650                         return PTR_ERR(pstate);
 651                 vop_plane_state = to_vop_plane_state(pstate);
 652
 653                 if (!pstate->fb)
 654                         continue;
 655                 is_yuv = is_yuv_support(pstate->fb->pixel_format);
 656
 657                 /*
 658                  * TODO: force set input and output csc mode.
 659                  */
 660                 ret = vop_csc_setup(csc_table, is_yuv, false,
 661                                     CSC_BT709, CSC_BT709,
 662                                     &vop_plane_state->y2r_table,
 663                                     &vop_plane_state->r2r_table,
 664                                     &vop_plane_state->r2y_table);
 665                 if (ret)
 666                         return ret;
 667         }
 668
 669         return 0;
 670 }
 671
 672 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 673 {
 674         unsigned long flags;
 675
 676         spin_lock_irqsave(&vop->irq_lock, flags);
 677
 678         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 679         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 680
 681         spin_unlock_irqrestore(&vop->irq_lock, flags);
 682 }
 683
 684 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 685 {
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&vop->irq_lock, flags);
 689
 690         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 691
 692         spin_unlock_irqrestore(&vop->irq_lock, flags);
 693 }
 694
 695 /*
 696  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 697  *     the "FRAME_SYNC" interrupt.
 698  * (2) the active data region of each frame ends at dsp_vact_end
 699  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 700  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 701  *
 702  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 703  * Interrupts
 704  * LINE_FLAG -------------------------------+
 705  * FRAME_SYNC ----+                         |
 706  *                |                         |
 707  *                v                         v
 708  *                | Vsync | Vbp |  Vactive  | Vfp |
 709  *                        ^     ^           ^     ^
 710  *                        |     |           |     |
 711  *                        |     |           |     |
 712  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 713  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 714  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 715  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 716  */
 717 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 718 {
 719         uint32_t line_flag_irq;
 720         unsigned long flags;
 721
 722         spin_lock_irqsave(&vop->irq_lock, flags);
 723
 724         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 725
 726         spin_unlock_irqrestore(&vop->irq_lock, flags);
 727
 728         return !!line_flag_irq;
 729 }
 730
 731 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 732 {
 733         unsigned long flags;
 734
 735         if (WARN_ON(!vop->is_enabled))
 736                 return;
 737
 738         spin_lock_irqsave(&vop->irq_lock, flags);
 739
 740         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 741         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 742         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 743
 744         spin_unlock_irqrestore(&vop->irq_lock, flags);
 745 }
 746
 747 static void vop_line_flag_irq_disable(struct vop *vop)
 748 {
 749         unsigned long flags;
 750
 751         if (WARN_ON(!vop->is_enabled))
 752                 return;
 753
 754         spin_lock_irqsave(&vop->irq_lock, flags);
 755
 756         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 757
 758         spin_unlock_irqrestore(&vop->irq_lock, flags);
 759 }
 760
 761 static void vop_enable(struct drm_crtc *crtc)
 762 {
 763         struct vop *vop = to_vop(crtc);
 764         int ret, i;
 765
 766         ret = clk_prepare_enable(vop->hclk);
 767         if (ret < 0) {
 768                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 769                 return;
 770         }
 771
 772         ret = clk_prepare_enable(vop->dclk);
 773         if (ret < 0) {
 774                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 775                 goto err_disable_hclk;
 776         }
 777
 778         ret = clk_prepare_enable(vop->aclk);
 779         if (ret < 0) {
 780                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 781                 goto err_disable_dclk;
 782         }
 783
 784         ret = pm_runtime_get_sync(vop->dev);
 785         if (ret < 0) {
 786                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 787                 return;
 788         }
 789
 790         memcpy(vop->regsbak, vop->regs, vop->len);
 791
 792         VOP_CTRL_SET(vop, global_regdone_en, 1);
 793         VOP_CTRL_SET(vop, dsp_blank, 0);
 794
 795         /*
 796          * We need to make sure that all windows are disabled before resume
 797          * the crtc. Otherwise we might try to scan from a destroyed
 798          * buffer later.
 799          */
 800         for (i = 0; i < vop->num_wins; i++) {
 801                 struct vop_win *win = &vop->win[i];
 802
 803                 if (win->phy->scl && win->phy->scl->ext) {
 804                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 805                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 806                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 807                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 808                 }
 809                 VOP_WIN_SET(vop, win, enable, 0);
 810                 VOP_WIN_SET(vop, win, gate, 1);
 811         }
 812         VOP_CTRL_SET(vop, afbdc_en, 0);
 813         vop_cfg_done(vop);
 814
 815         vop->is_enabled = true;
 816
 817         spin_lock(&vop->reg_lock);
 818
 819         /*
 820          * enable vop, all the register would take effect when vop exit standby
 821          */
 822         VOP_CTRL_SET(vop, standby, 0);
 823
 824         spin_unlock(&vop->reg_lock);
 825
 826         enable_irq(vop->irq);
 827
 828         drm_crtc_vblank_on(crtc);
 829
 830         return;
 831
 832 err_disable_dclk:
 833         clk_disable_unprepare(vop->dclk);
 834 err_disable_hclk:
 835         clk_disable_unprepare(vop->hclk);
 836 }
 837
 838 static void vop_crtc_disable(struct drm_crtc *crtc)
 839 {
 840         struct vop *vop = to_vop(crtc);
 841
 842         drm_crtc_vblank_off(crtc);
 843
 844         /*
 845          * Vop standby will take effect at end of current frame,
 846          * if dsp hold valid irq happen, it means standby complete.
 847          *
 848          * we must wait standby complete when we want to disable aclk,
 849          * if not, memory bus maybe dead.
 850          */
 851         reinit_completion(&vop->dsp_hold_completion);
 852         vop_dsp_hold_valid_irq_enable(vop);
 853
 854         spin_lock(&vop->reg_lock);
 855
 856         VOP_CTRL_SET(vop, standby, 1);
 857
 858         spin_unlock(&vop->reg_lock);
 859
 860         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 861                                              msecs_to_jiffies(50)));
 862
 863         vop_dsp_hold_valid_irq_disable(vop);
 864
 865         disable_irq(vop->irq);
 866
 867         vop->is_enabled = false;
 868         if (vop->is_iommu_enabled) {
 869                 /*
 870                  * vop standby complete, so iommu detach is safe.
 871                  */
 872                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 873                 vop->is_iommu_enabled = false;
 874         }
 875
 876         pm_runtime_put(vop->dev);
 877         clk_disable_unprepare(vop->dclk);
 878         clk_disable_unprepare(vop->aclk);
 879         clk_disable_unprepare(vop->hclk);
 880 }
 881
 882 static void vop_plane_destroy(struct drm_plane *plane)
 883 {
 884         drm_plane_cleanup(plane);
 885 }
 886
 887 static int vop_plane_prepare_fb(struct drm_plane *plane,
 888                                 const struct drm_plane_state *new_state)
 889 {
 890         if (plane->state->fb)
 891                 drm_framebuffer_reference(plane->state->fb);
 892
 893         return 0;
 894 }
 895
 896 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 897                                  const struct drm_plane_state *old_state)
 898 {
 899         if (old_state->fb)
 900                 drm_framebuffer_unreference(old_state->fb);
 901 }
 902
 903 static int vop_plane_atomic_check(struct drm_plane *plane,
 904                            struct drm_plane_state *state)
 905 {
 906         struct drm_crtc *crtc = state->crtc;
 907         struct drm_framebuffer *fb = state->fb;
 908         struct vop_win *win = to_vop_win(plane);
 909         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 910         struct drm_crtc_state *crtc_state;
 911         bool visible;
 912         int ret;
 913         struct drm_rect *dest = &vop_plane_state->dest;
 914         struct drm_rect *src = &vop_plane_state->src;
 915         struct drm_rect clip;
 916         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 917                                         DRM_PLANE_HELPER_NO_SCALING;
 918         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 919                                         DRM_PLANE_HELPER_NO_SCALING;
 920         unsigned long offset;
 921         dma_addr_t dma_addr;
 922
 923         crtc = crtc ? crtc : plane->state->crtc;
 924         /*
 925          * Both crtc or plane->state->crtc can be null.
 926          */
 927         if (!crtc || !fb)
 928                 goto out_disable;
 929
 930         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 931         if (IS_ERR(crtc_state))
 932                 return PTR_ERR(crtc_state);
 933
 934         src->x1 = state->src_x;
 935         src->y1 = state->src_y;
 936         src->x2 = state->src_x + state->src_w;
 937         src->y2 = state->src_y + state->src_h;
 938         dest->x1 = state->crtc_x;
 939         dest->y1 = state->crtc_y;
 940         dest->x2 = state->crtc_x + state->crtc_w;
 941         dest->y2 = state->crtc_y + state->crtc_h;
 942
 943         clip.x1 = 0;
 944         clip.y1 = 0;
 945         clip.x2 = crtc_state->mode.hdisplay;
 946         clip.y2 = crtc_state->mode.vdisplay;
 947
 948         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 949                                             src, dest, &clip,
 950                                             min_scale,
 951                                             max_scale,
 952                                             true, true, &visible);
 953         if (ret)
 954                 return ret;
 955
 956         if (!visible)
 957                 goto out_disable;
 958
 959         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 960         if (vop_plane_state->format < 0)
 961                 return vop_plane_state->format;
 962
 963         /*
 964          * Src.x1 can be odd when do clip, but yuv plane start point
 965          * need align with 2 pixel.
 966          */
 967         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 968                 return -EINVAL;
 969
 970         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 971         if (state->rotation & BIT(DRM_REFLECT_Y))
 972                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 973         else
 974                 offset += (src->y1 >> 16) * fb->pitches[0];
 975
 976         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 977         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 978         if (is_yuv_support(fb->pixel_format)) {
 979                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 980                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 981                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
 982
 983                 offset = (src->x1 >> 16) * bpp / hsub / 8;
 984                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 985
 986                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
 987                 dma_addr += offset + fb->offsets[1];
 988                 vop_plane_state->uv_mst = dma_addr;
 989         }
 990
 991         vop_plane_state->enable = true;
 992
 993         return 0;
 994
 995 out_disable:
 996         vop_plane_state->enable = false;
 997         return 0;
 998 }
 999
1000 static void vop_plane_atomic_disable(struct drm_plane *plane,
1001                                      struct drm_plane_state *old_state)
1002 {
1003         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1004         struct vop_win *win = to_vop_win(plane);
1005         struct vop *vop = to_vop(old_state->crtc);
1006
1007         if (!old_state->crtc)
1008                 return;
1009
1010         spin_lock(&vop->reg_lock);
1011
1012         /*
1013          * FIXUP: some of the vop scale would be abnormal after windows power
1014          * on/off so deinit scale to scale_none mode.
1015          */
1016         if (win->phy->scl && win->phy->scl->ext) {
1017                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1018                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1019                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1020                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1021         }
1022         VOP_WIN_SET(vop, win, enable, 0);
1023
1024         spin_unlock(&vop->reg_lock);
1025
1026         vop_plane_state->enable = false;
1027 }
1028
1029 static void vop_plane_atomic_update(struct drm_plane *plane,
1030                 struct drm_plane_state *old_state)
1031 {
1032         struct drm_plane_state *state = plane->state;
1033         struct drm_crtc *crtc = state->crtc;
1034         struct vop_win *win = to_vop_win(plane);
1035         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1036         struct rockchip_crtc_state *s;
1037         struct vop *vop;
1038         struct drm_framebuffer *fb = state->fb;
1039         unsigned int actual_w, actual_h;
1040         unsigned int dsp_stx, dsp_sty;
1041         uint32_t act_info, dsp_info, dsp_st;
1042         struct drm_rect *src = &vop_plane_state->src;
1043         struct drm_rect *dest = &vop_plane_state->dest;
1044         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1045         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1046         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1047         int ymirror, xmirror;
1048         uint32_t val;
1049         bool rb_swap;
1050
1051         /*
1052          * can't update plane when vop is disabled.
1053          */
1054         if (!crtc)
1055                 return;
1056
1057         if (!vop_plane_state->enable) {
1058                 vop_plane_atomic_disable(plane, old_state);
1059                 return;
1060         }
1061
1062         actual_w = drm_rect_width(src) >> 16;
1063         actual_h = drm_rect_height(src) >> 16;
1064         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1065
1066         dsp_info = (drm_rect_height(dest) - 1) << 16;
1067         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1068
1069         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1070         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1071         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1072
1073         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1074         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1075
1076         vop = to_vop(state->crtc);
1077         s = to_rockchip_crtc_state(crtc->state);
1078
1079         spin_lock(&vop->reg_lock);
1080
1081         VOP_WIN_SET(vop, win, xmirror, xmirror);
1082         VOP_WIN_SET(vop, win, ymirror, ymirror);
1083         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1084         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1085         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1086         if (is_yuv_support(fb->pixel_format)) {
1087                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1088                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1089         }
1090         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1091
1092         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1093                             drm_rect_width(dest), drm_rect_height(dest),
1094                             fb->pixel_format);
1095
1096         VOP_WIN_SET(vop, win, act_info, act_info);
1097         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1098         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1099
1100         rb_swap = has_rb_swapped(fb->pixel_format);
1101         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1102
1103         if (is_alpha_support(fb->pixel_format) &&
1104             (s->dsp_layer_sel & 0x3) != win->win_id) {
1105                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1106                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1107                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1108                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1109                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1110                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1111                         SRC_FACTOR_M0(ALPHA_ONE);
1112                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1113                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1114                 VOP_WIN_SET(vop, win, alpha_en, 1);
1115         } else {
1116                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1117                 VOP_WIN_SET(vop, win, alpha_en, 0);
1118         }
1119
1120         if (win->csc) {
1121                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1122                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1123                 vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
1124                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1125                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1126                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1127         }
1128         VOP_WIN_SET(vop, win, enable, 1);
1129         spin_unlock(&vop->reg_lock);
1130         vop->is_iommu_needed = true;
1131 }
1132
1133 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1134         .prepare_fb = vop_plane_prepare_fb,
1135         .cleanup_fb = vop_plane_cleanup_fb,
1136         .atomic_check = vop_plane_atomic_check,
1137         .atomic_update = vop_plane_atomic_update,
1138         .atomic_disable = vop_plane_atomic_disable,
1139 };
1140
1141 void vop_atomic_plane_reset(struct drm_plane *plane)
1142 {
1143         struct vop_win *win = to_vop_win(plane);
1144         struct vop_plane_state *vop_plane_state =
1145                                         to_vop_plane_state(plane->state);
1146
1147         if (plane->state && plane->state->fb)
1148                 drm_framebuffer_unreference(plane->state->fb);
1149
1150         kfree(vop_plane_state);
1151         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1152         if (!vop_plane_state)
1153                 return;
1154
1155         vop_plane_state->zpos = win->win_id;
1156         plane->state = &vop_plane_state->base;
1157         plane->state->plane = plane;
1158 }
1159
1160 struct drm_plane_state *
1161 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1162 {
1163         struct vop_plane_state *old_vop_plane_state;
1164         struct vop_plane_state *vop_plane_state;
1165
1166         if (WARN_ON(!plane->state))
1167                 return NULL;
1168
1169         old_vop_plane_state = to_vop_plane_state(plane->state);
1170         vop_plane_state = kmemdup(old_vop_plane_state,
1171                                   sizeof(*vop_plane_state), GFP_KERNEL);
1172         if (!vop_plane_state)
1173                 return NULL;
1174
1175         __drm_atomic_helper_plane_duplicate_state(plane,
1176                                                   &vop_plane_state->base);
1177
1178         return &vop_plane_state->base;
1179 }
1180
1181 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1182                                            struct drm_plane_state *state)
1183 {
1184         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1185
1186         __drm_atomic_helper_plane_destroy_state(plane, state);
1187
1188         kfree(vop_state);
1189 }
1190
1191 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1192                                          struct drm_plane_state *state,
1193                                          struct drm_property *property,
1194                                          uint64_t val)
1195 {
1196         struct vop_win *win = to_vop_win(plane);
1197         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1198
1199         if (property == win->vop->plane_zpos_prop) {
1200                 plane_state->zpos = val;
1201                 return 0;
1202         }
1203
1204         if (property == win->rotation_prop) {
1205                 state->rotation = val;
1206                 return 0;
1207         }
1208
1209         DRM_ERROR("failed to set vop plane property\n");
1210         return -EINVAL;
1211 }
1212
1213 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1214                                          const struct drm_plane_state *state,
1215                                          struct drm_property *property,
1216                                          uint64_t *val)
1217 {
1218         struct vop_win *win = to_vop_win(plane);
1219         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1220
1221         if (property == win->vop->plane_zpos_prop) {
1222                 *val = plane_state->zpos;
1223                 return 0;
1224         }
1225
1226         if (property == win->rotation_prop) {
1227                 *val = state->rotation;
1228                 return 0;
1229         }
1230
1231         DRM_ERROR("failed to get vop plane property\n");
1232         return -EINVAL;
1233 }
1234
1235 static const struct drm_plane_funcs vop_plane_funcs = {
1236         .update_plane   = drm_atomic_helper_update_plane,
1237         .disable_plane  = drm_atomic_helper_disable_plane,
1238         .destroy = vop_plane_destroy,
1239         .reset = vop_atomic_plane_reset,
1240         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1241         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1242         .atomic_set_property = vop_atomic_plane_set_property,
1243         .atomic_get_property = vop_atomic_plane_get_property,
1244 };
1245
1246 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1247 {
1248         struct vop *vop = to_vop(crtc);
1249         unsigned long flags;
1250
1251         if (!vop->is_enabled)
1252                 return -EPERM;
1253
1254         spin_lock_irqsave(&vop->irq_lock, flags);
1255
1256         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1257         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1258
1259         spin_unlock_irqrestore(&vop->irq_lock, flags);
1260
1261         return 0;
1262 }
1263
1264 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1265 {
1266         struct vop *vop = to_vop(crtc);
1267         unsigned long flags;
1268
1269         if (!vop->is_enabled)
1270                 return;
1271
1272         spin_lock_irqsave(&vop->irq_lock, flags);
1273
1274         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1275
1276         spin_unlock_irqrestore(&vop->irq_lock, flags);
1277 }
1278
1279 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1280 {
1281         struct vop *vop = to_vop(crtc);
1282
1283         reinit_completion(&vop->wait_update_complete);
1284         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1285 }
1286
1287 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1288                                            struct drm_file *file_priv)
1289 {
1290         struct drm_device *drm = crtc->dev;
1291         struct vop *vop = to_vop(crtc);
1292         struct drm_pending_vblank_event *e;
1293         unsigned long flags;
1294
1295         spin_lock_irqsave(&drm->event_lock, flags);
1296         e = vop->event;
1297         if (e && e->base.file_priv == file_priv) {
1298                 vop->event = NULL;
1299
1300                 e->base.destroy(&e->base);
1301                 file_priv->event_space += sizeof(e->event);
1302         }
1303         spin_unlock_irqrestore(&drm->event_lock, flags);
1304 }
1305
1306 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1307 {
1308         struct vop *vop = to_vop(crtc);
1309
1310         if (on == vop->loader_protect)
1311                 return 0;
1312
1313         if (on) {
1314                 vop_enable(crtc);
1315                 vop->loader_protect = true;
1316         } else {
1317                 vop_crtc_disable(crtc);
1318
1319                 vop->loader_protect = false;
1320         }
1321
1322         return 0;
1323 }
1324
1325 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1326 {
1327         struct vop_win *win = to_vop_win(plane);
1328         struct drm_plane_state *state = plane->state;
1329         struct vop_plane_state *pstate = to_vop_plane_state(state);
1330         struct drm_rect *src, *dest;
1331         struct drm_framebuffer *fb = state->fb;
1332         int i;
1333
1334         seq_printf(s, "win%d-%d: status=%s\n", win->win_id, win->area_id,
1335                    pstate->enable ? "active" : "disabled");
1336         if (!fb)
1337                 return 0;
1338
1339         src = &pstate->src;
1340         dest = &pstate->dest;
1341
1342         seq_printf(s, "\tformat: %s\n", drm_get_format_name(fb->pixel_format));
1343         seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1344         seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1345                    src->y1 >> 16, drm_rect_width(src) >> 16,
1346                    drm_rect_height(src) >> 16);
1347         seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1348                    drm_rect_width(dest), drm_rect_height(dest));
1349
1350         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1351                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1352                 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1353                            i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1354         }
1355
1356         return 0;
1357 }
1358
1359 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1360 {
1361         struct vop *vop = to_vop(crtc);
1362         struct drm_crtc_state *crtc_state = crtc->state;
1363         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1364         struct drm_plane *plane;
1365         int i;
1366
1367         seq_printf(s, "vop name: %s status=%s\n", dev_name(vop->dev),
1368                    crtc_state->active ? "active" : "disabled");
1369
1370         if (!crtc_state->active)
1371                 return 0;
1372
1373         seq_printf(s, "Display mode: %s fps[%d] clk[%d] type[%d] flag[%x]\n",
1374                    mode->name, drm_mode_vrefresh(mode), mode->clock,
1375                    mode->type, mode->flags);
1376         seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1377                    mode->hsync_end, mode->htotal);
1378         seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1379                    mode->vsync_end, mode->vtotal);
1380
1381         for (i = 0; i < vop->num_wins; i++) {
1382                 plane = &vop->win[i].base;
1383                 vop_plane_info_dump(s, plane);
1384         }
1385
1386         return 0;
1387 }
1388
1389 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1390         .loader_protect = vop_crtc_loader_protect,
1391         .enable_vblank = vop_crtc_enable_vblank,
1392         .disable_vblank = vop_crtc_disable_vblank,
1393         .wait_for_update = vop_crtc_wait_for_update,
1394         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1395         .debugfs_dump = vop_crtc_debugfs_dump,
1396 };
1397
1398 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1399                                 const struct drm_display_mode *mode,
1400                                 struct drm_display_mode *adjusted_mode)
1401 {
1402         struct vop *vop = to_vop(crtc);
1403
1404         adjusted_mode->clock =
1405                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1406
1407         return true;
1408 }
1409
1410 static void vop_crtc_enable(struct drm_crtc *crtc)
1411 {
1412         struct vop *vop = to_vop(crtc);
1413         const struct vop_data *vop_data = vop->data;
1414         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1415         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1416         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1417         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1418         u16 htotal = adjusted_mode->crtc_htotal;
1419         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1420         u16 hact_end = hact_st + hdisplay;
1421         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1422         u16 vtotal = adjusted_mode->crtc_vtotal;
1423         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1424         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1425         u16 vact_end = vact_st + vdisplay;
1426         uint32_t version = vop->data->version;
1427         uint32_t val;
1428
1429         vop_enable(crtc);
1430         /*
1431          * If dclk rate is zero, mean that scanout is stop,
1432          * we don't need wait any more.
1433          *
1434          * Since vop version(3,4), vop timing is frame effect, not need config
1435          * timing register on vblank.
1436          */
1437         if (clk_get_rate(vop->dclk) &&
1438             !(VOP_MAJOR(version) == 3 && VOP_MINOR(version) >= 4)) {
1439                 /*
1440                  * Rk3288 vop timing register is immediately, when configure
1441                  * display timing on display time, may cause tearing.
1442                  *
1443                  * Vop standby will take effect at end of current frame,
1444                  * if dsp hold valid irq happen, it means standby complete.
1445                  *
1446                  * mode set:
1447                  *    standby and wait complete --> |----
1448                  *                                  | display time
1449                  *                                  |----
1450                  *                                  |---> dsp hold irq
1451                  *     configure display timing --> |
1452                  *         standby exit             |
1453                  *                                  | new frame start.
1454                  */
1455
1456                 reinit_completion(&vop->dsp_hold_completion);
1457                 vop_dsp_hold_valid_irq_enable(vop);
1458
1459                 spin_lock(&vop->reg_lock);
1460
1461                 VOP_CTRL_SET(vop, standby, 1);
1462
1463                 spin_unlock(&vop->reg_lock);
1464
1465                 WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
1466                                                      msecs_to_jiffies(50)));
1467
1468                 vop_dsp_hold_valid_irq_disable(vop);
1469         }
1470
1471         val = BIT(DCLK_INVERT);
1472         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1473                    0 : BIT(HSYNC_POSITIVE);
1474         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1475                    0 : BIT(VSYNC_POSITIVE);
1476         VOP_CTRL_SET(vop, pin_pol, val);
1477         switch (s->output_type) {
1478         case DRM_MODE_CONNECTOR_LVDS:
1479                 VOP_CTRL_SET(vop, rgb_en, 1);
1480                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1481                 break;
1482         case DRM_MODE_CONNECTOR_eDP:
1483                 VOP_CTRL_SET(vop, edp_en, 1);
1484                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1485                 break;
1486         case DRM_MODE_CONNECTOR_HDMIA:
1487                 VOP_CTRL_SET(vop, hdmi_en, 1);
1488                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1489                 break;
1490         case DRM_MODE_CONNECTOR_DSI:
1491                 VOP_CTRL_SET(vop, mipi_en, 1);
1492                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1493                 break;
1494         case DRM_MODE_CONNECTOR_DisplayPort:
1495                 val &= ~BIT(DCLK_INVERT);
1496                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1497                 VOP_CTRL_SET(vop, dp_en, 1);
1498                 break;
1499         default:
1500                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1501         }
1502
1503         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1504             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1505                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1506
1507         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1508         switch (s->bus_format) {
1509         case MEDIA_BUS_FMT_RGB565_1X16:
1510                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1511                 break;
1512         case MEDIA_BUS_FMT_RGB666_1X18:
1513         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1514                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1515                 break;
1516         case MEDIA_BUS_FMT_RGB888_1X24:
1517         default:
1518                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1519                 break;
1520         }
1521         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1522                 val |= PRE_DITHER_DOWN_EN(0);
1523         else
1524                 val |= PRE_DITHER_DOWN_EN(1);
1525         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1526         VOP_CTRL_SET(vop, dither_down, val);
1527
1528         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1529         val = hact_st << 16;
1530         val |= hact_end;
1531         VOP_CTRL_SET(vop, hact_st_end, val);
1532         VOP_CTRL_SET(vop, hpost_st_end, val);
1533
1534         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1535         val = vact_st << 16;
1536         val |= vact_end;
1537         VOP_CTRL_SET(vop, vact_st_end, val);
1538         VOP_CTRL_SET(vop, vpost_st_end, val);
1539         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1540                 u16 vact_st_f1 = vtotal + vact_st + 1;
1541                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1542
1543                 val = vact_st_f1 << 16 | vact_end_f1;
1544                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1545                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1546
1547                 val = vtotal << 16 | (vtotal + vsync_len);
1548                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1549                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1550                 VOP_CTRL_SET(vop, p2i_en, 1);
1551         } else {
1552                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1553                 VOP_CTRL_SET(vop, p2i_en, 0);
1554         }
1555
1556         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1557
1558         VOP_CTRL_SET(vop, standby, 0);
1559 }
1560
1561 static int vop_zpos_cmp(const void *a, const void *b)
1562 {
1563         struct vop_zpos *pa = (struct vop_zpos *)a;
1564         struct vop_zpos *pb = (struct vop_zpos *)b;
1565
1566         return pa->zpos - pb->zpos;
1567 }
1568
1569 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1570                                   struct drm_crtc_state *crtc_state)
1571 {
1572         struct vop *vop = to_vop(crtc);
1573         const struct vop_data *vop_data = vop->data;
1574         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1575         struct drm_atomic_state *state = crtc_state->state;
1576         struct drm_plane *plane;
1577         struct drm_plane_state *pstate;
1578         struct vop_plane_state *plane_state;
1579         struct vop_win *win;
1580         int afbdc_format;
1581         int i;
1582
1583         s->afbdc_en = 0;
1584
1585         for_each_plane_in_state(state, plane, pstate, i) {
1586                 struct drm_framebuffer *fb = pstate->fb;
1587                 struct drm_rect *src;
1588
1589                 win = to_vop_win(plane);
1590                 plane_state = to_vop_plane_state(pstate);
1591
1592                 if (pstate->crtc != crtc || !fb)
1593                         continue;
1594
1595                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1596                         continue;
1597
1598                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1599                         DRM_ERROR("not support afbdc\n");
1600                         return -EINVAL;
1601                 }
1602
1603                 switch (plane_state->format) {
1604                 case VOP_FMT_ARGB8888:
1605                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1606                         break;
1607                 case VOP_FMT_RGB888:
1608                         afbdc_format = AFBDC_FMT_U8U8U8;
1609                         break;
1610                 case VOP_FMT_RGB565:
1611                         afbdc_format = AFBDC_FMT_RGB565;
1612                         break;
1613                 default:
1614                         return -EINVAL;
1615                 }
1616
1617                 if (s->afbdc_en) {
1618                         DRM_ERROR("vop only support one afbc layer\n");
1619                         return -EINVAL;
1620                 }
1621
1622                 src = &plane_state->src;
1623                 if (src->x1 || src->y1 || fb->offsets[0]) {
1624                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1625                                   win->win_id);
1626                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1627                                   src->x1, src->y1, fb->offsets[0]);
1628                         return -EINVAL;
1629                 }
1630                 s->afbdc_win_format = afbdc_format;
1631                 s->afbdc_win_width = pstate->fb->width - 1;
1632                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1633                 s->afbdc_win_id = win->win_id;
1634                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1635                 s->afbdc_en = 1;
1636         }
1637
1638         return 0;
1639 }
1640
1641 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1642                                  struct drm_crtc_state *crtc_state)
1643 {
1644         struct drm_atomic_state *state = crtc_state->state;
1645         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1646         struct vop *vop = to_vop(crtc);
1647         const struct vop_data *vop_data = vop->data;
1648         struct drm_plane *plane;
1649         struct drm_plane_state *pstate;
1650         struct vop_plane_state *plane_state;
1651         struct vop_zpos *pzpos;
1652         int dsp_layer_sel = 0;
1653         int i, j, cnt = 0, ret = 0;
1654
1655         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1656         if (ret)
1657                 return ret;
1658
1659         ret = vop_csc_atomic_check(crtc, crtc_state);
1660         if (ret)
1661                 return ret;
1662
1663         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1664         if (!pzpos)
1665                 return -ENOMEM;
1666
1667         for (i = 0; i < vop_data->win_size; i++) {
1668                 const struct vop_win_data *win_data = &vop_data->win[i];
1669                 struct vop_win *win;
1670
1671                 if (!win_data->phy)
1672                         continue;
1673
1674                 for (j = 0; j < vop->num_wins; j++) {
1675                         win = &vop->win[j];
1676
1677                         if (win->win_id == i && !win->area_id)
1678                                 break;
1679                 }
1680                 if (WARN_ON(j >= vop->num_wins)) {
1681                         ret = -EINVAL;
1682                         goto err_free_pzpos;
1683                 }
1684
1685                 plane = &win->base;
1686                 pstate = state->plane_states[drm_plane_index(plane)];
1687                 /*
1688                  * plane might not have changed, in which case take
1689                  * current state:
1690                  */
1691                 if (!pstate)
1692                         pstate = plane->state;
1693                 plane_state = to_vop_plane_state(pstate);
1694                 pzpos[cnt].zpos = plane_state->zpos;
1695                 pzpos[cnt++].win_id = win->win_id;
1696         }
1697
1698         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1699
1700         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1701                 const struct vop_win_data *win_data = &vop_data->win[i];
1702                 int shift = i * 2;
1703
1704                 if (win_data->phy) {
1705                         struct vop_zpos *zpos = &pzpos[cnt++];
1706
1707                         dsp_layer_sel |= zpos->win_id << shift;
1708                 } else {
1709                         dsp_layer_sel |= i << shift;
1710                 }
1711         }
1712
1713         s->dsp_layer_sel = dsp_layer_sel;
1714
1715 err_free_pzpos:
1716         kfree(pzpos);
1717         return ret;
1718 }
1719
1720 static void vop_post_config(struct drm_crtc *crtc)
1721 {
1722         struct vop *vop = to_vop(crtc);
1723         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1724         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1725         u16 vtotal = mode->crtc_vtotal;
1726         u16 hdisplay = mode->crtc_hdisplay;
1727         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1728         u16 vdisplay = mode->crtc_vdisplay;
1729         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1730         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1731         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1732         u16 hact_end, vact_end;
1733         u32 val;
1734
1735         hact_st += hdisplay * (100 - s->left_margin) / 200;
1736         hact_end = hact_st + hsize;
1737         val = hact_st << 16;
1738         val |= hact_end;
1739         VOP_CTRL_SET(vop, hpost_st_end, val);
1740         vact_st += vdisplay * (100 - s->top_margin) / 200;
1741         vact_end = vact_st + vsize;
1742         val = vact_st << 16;
1743         val |= vact_end;
1744         VOP_CTRL_SET(vop, vpost_st_end, val);
1745         val = scl_cal_scale2(vdisplay, vsize) << 16;
1746         val |= scl_cal_scale2(hdisplay, hsize);
1747         VOP_CTRL_SET(vop, post_scl_factor, val);
1748         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1749         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1750                 u16 vact_st_f1 = vtotal + vact_st + 1;
1751                 u16 vact_end_f1 = vact_st_f1 + vsize;
1752
1753                 val = vact_st_f1 << 16 | vact_end_f1;
1754                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1755         }
1756 }
1757
1758 static void vop_cfg_update(struct drm_crtc *crtc,
1759                            struct drm_crtc_state *old_crtc_state)
1760 {
1761         struct rockchip_crtc_state *s =
1762                         to_rockchip_crtc_state(crtc->state);
1763         struct vop *vop = to_vop(crtc);
1764
1765         spin_lock(&vop->reg_lock);
1766
1767         if (s->afbdc_en) {
1768                 uint32_t pic_size;
1769
1770                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1771                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1772                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1773                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1774                 pic_size = (s->afbdc_win_width & 0xffff);
1775                 pic_size |= s->afbdc_win_height << 16;
1776                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1777         }
1778
1779         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1780         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1781         vop_post_config(crtc);
1782
1783         spin_unlock(&vop->reg_lock);
1784 }
1785
1786 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1787                                   struct drm_crtc_state *old_crtc_state)
1788 {
1789         struct vop *vop = to_vop(crtc);
1790
1791         vop_cfg_update(crtc, old_crtc_state);
1792
1793         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1794                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1795                 int ret;
1796
1797                 if (need_wait_vblank) {
1798                         bool active;
1799
1800                         disable_irq(vop->irq);
1801                         drm_crtc_vblank_get(crtc);
1802                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1803
1804                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1805                                                         vop, active, active,
1806                                                         0, 50 * 1000);
1807                         if (ret)
1808                                 dev_err(vop->dev, "wait fs irq timeout\n");
1809
1810                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1811                         vop_cfg_done(vop);
1812
1813                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1814                                                         vop, active, active,
1815                                                         0, 50 * 1000);
1816                         if (ret)
1817                                 dev_err(vop->dev, "wait line flag timeout\n");
1818
1819                         enable_irq(vop->irq);
1820                 }
1821                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1822                 if (ret)
1823                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1824                                 ret);
1825
1826                 if (need_wait_vblank) {
1827                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1828                         drm_crtc_vblank_put(crtc);
1829                 }
1830
1831                 vop->is_iommu_enabled = true;
1832         }
1833
1834         vop_cfg_done(vop);
1835 }
1836
1837 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1838                                   struct drm_crtc_state *old_crtc_state)
1839 {
1840         struct vop *vop = to_vop(crtc);
1841
1842         if (crtc->state->event) {
1843                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1844
1845                 vop->event = crtc->state->event;
1846                 crtc->state->event = NULL;
1847         }
1848 }
1849
1850 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1851         .enable = vop_crtc_enable,
1852         .disable = vop_crtc_disable,
1853         .mode_fixup = vop_crtc_mode_fixup,
1854         .atomic_check = vop_crtc_atomic_check,
1855         .atomic_flush = vop_crtc_atomic_flush,
1856         .atomic_begin = vop_crtc_atomic_begin,
1857 };
1858
1859 static void vop_crtc_destroy(struct drm_crtc *crtc)
1860 {
1861         drm_crtc_cleanup(crtc);
1862 }
1863
1864 static void vop_crtc_reset(struct drm_crtc *crtc)
1865 {
1866         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1867
1868         if (crtc->state) {
1869                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1870                 kfree(s);
1871         }
1872
1873         s = kzalloc(sizeof(*s), GFP_KERNEL);
1874         if (!s)
1875                 return;
1876         crtc->state = &s->base;
1877         crtc->state->crtc = crtc;
1878         s->left_margin = 100;
1879         s->right_margin = 100;
1880         s->top_margin = 100;
1881         s->bottom_margin = 100;
1882 }
1883
1884 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1885 {
1886         struct rockchip_crtc_state *rockchip_state, *old_state;
1887
1888         old_state = to_rockchip_crtc_state(crtc->state);
1889         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1890         if (!rockchip_state)
1891                 return NULL;
1892
1893         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1894         return &rockchip_state->base;
1895 }
1896
1897 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1898                                    struct drm_crtc_state *state)
1899 {
1900         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1901
1902         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1903         kfree(s);
1904 }
1905
1906 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
1907                                         const struct drm_crtc_state *state,
1908                                         struct drm_property *property,
1909                                         uint64_t *val)
1910 {
1911         struct drm_device *drm_dev = crtc->dev;
1912         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1913         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1914
1915         if (property == mode_config->tv_left_margin_property) {
1916                 *val = s->left_margin;
1917                 return 0;
1918         }
1919
1920         if (property == mode_config->tv_right_margin_property) {
1921                 *val = s->right_margin;
1922                 return 0;
1923         }
1924
1925         if (property == mode_config->tv_top_margin_property) {
1926                 *val = s->top_margin;
1927                 return 0;
1928         }
1929
1930         if (property == mode_config->tv_bottom_margin_property) {
1931                 *val = s->bottom_margin;
1932                 return 0;
1933         }
1934
1935         DRM_ERROR("failed to get vop crtc property\n");
1936         return -EINVAL;
1937 }
1938
1939 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
1940                                         struct drm_crtc_state *state,
1941                                         struct drm_property *property,
1942                                         uint64_t val)
1943 {
1944         struct drm_device *drm_dev = crtc->dev;
1945         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1946         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1947
1948         if (property == mode_config->tv_left_margin_property) {
1949                 s->left_margin = val;
1950                 return 0;
1951         }
1952
1953         if (property == mode_config->tv_right_margin_property) {
1954                 s->right_margin = val;
1955                 return 0;
1956         }
1957
1958         if (property == mode_config->tv_top_margin_property) {
1959                 s->top_margin = val;
1960                 return 0;
1961         }
1962
1963         if (property == mode_config->tv_bottom_margin_property) {
1964                 s->bottom_margin = val;
1965                 return 0;
1966         }
1967
1968         DRM_ERROR("failed to set vop crtc property\n");
1969         return -EINVAL;
1970 }
1971
1972 static const struct drm_crtc_funcs vop_crtc_funcs = {
1973         .set_config = drm_atomic_helper_set_config,
1974         .page_flip = drm_atomic_helper_page_flip,
1975         .destroy = vop_crtc_destroy,
1976         .reset = vop_crtc_reset,
1977         .atomic_get_property = vop_crtc_atomic_get_property,
1978         .atomic_set_property = vop_crtc_atomic_set_property,
1979         .atomic_duplicate_state = vop_crtc_duplicate_state,
1980         .atomic_destroy_state = vop_crtc_destroy_state,
1981 };
1982
1983 static void vop_handle_vblank(struct vop *vop)
1984 {
1985         struct drm_device *drm = vop->drm_dev;
1986         struct drm_crtc *crtc = &vop->crtc;
1987         unsigned long flags;
1988
1989         if (!vop_is_cfg_done_complete(vop))
1990                 return;
1991
1992         if (vop->event) {
1993                 spin_lock_irqsave(&drm->event_lock, flags);
1994
1995                 drm_crtc_send_vblank_event(crtc, vop->event);
1996                 drm_crtc_vblank_put(crtc);
1997                 vop->event = NULL;
1998
1999                 spin_unlock_irqrestore(&drm->event_lock, flags);
2000         }
2001         if (!completion_done(&vop->wait_update_complete))
2002                 complete(&vop->wait_update_complete);
2003 }
2004
2005 static irqreturn_t vop_isr(int irq, void *data)
2006 {
2007         struct vop *vop = data;
2008         struct drm_crtc *crtc = &vop->crtc;
2009         uint32_t active_irqs;
2010         unsigned long flags;
2011         int ret = IRQ_NONE;
2012
2013         /*
2014          * interrupt register has interrupt status, enable and clear bits, we
2015          * must hold irq_lock to avoid a race with enable/disable_vblank().
2016         */
2017         spin_lock_irqsave(&vop->irq_lock, flags);
2018
2019         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2020         /* Clear all active interrupt sources */
2021         if (active_irqs)
2022                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2023
2024         spin_unlock_irqrestore(&vop->irq_lock, flags);
2025
2026         /* This is expected for vop iommu irqs, since the irq is shared */
2027         if (!active_irqs)
2028                 return IRQ_NONE;
2029
2030         if (active_irqs & DSP_HOLD_VALID_INTR) {
2031                 complete(&vop->dsp_hold_completion);
2032                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2033                 ret = IRQ_HANDLED;
2034         }
2035
2036         if (active_irqs & LINE_FLAG_INTR) {
2037                 complete(&vop->line_flag_completion);
2038                 active_irqs &= ~LINE_FLAG_INTR;
2039                 ret = IRQ_HANDLED;
2040         }
2041
2042         if (active_irqs & FS_INTR) {
2043                 drm_crtc_handle_vblank(crtc);
2044                 vop_handle_vblank(vop);
2045                 active_irqs &= ~FS_INTR;
2046                 ret = IRQ_HANDLED;
2047         }
2048
2049         /* Unhandled irqs are spurious. */
2050         if (active_irqs)
2051                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2052
2053         return ret;
2054 }
2055
2056 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2057                           unsigned long possible_crtcs)
2058 {
2059         struct drm_plane *share = NULL;
2060         unsigned int rotations = 0;
2061         struct drm_property *prop;
2062         uint64_t feature = 0;
2063         int ret;
2064
2065         if (win->parent)
2066                 share = &win->parent->base;
2067
2068         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2069                                    possible_crtcs, &vop_plane_funcs,
2070                                    win->data_formats, win->nformats, win->type);
2071         if (ret) {
2072                 DRM_ERROR("failed to initialize plane\n");
2073                 return ret;
2074         }
2075         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2076         drm_object_attach_property(&win->base.base,
2077                                    vop->plane_zpos_prop, win->win_id);
2078
2079         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2080                 rotations |= BIT(DRM_REFLECT_X);
2081
2082         if (VOP_WIN_SUPPORT(vop, win, ymirror))
2083                 rotations |= BIT(DRM_REFLECT_Y);
2084
2085         if (rotations) {
2086                 rotations |= BIT(DRM_ROTATE_0);
2087                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2088                                                          rotations);
2089                 if (!prop) {
2090                         DRM_ERROR("failed to create zpos property\n");
2091                         return -EINVAL;
2092                 }
2093                 drm_object_attach_property(&win->base.base, prop,
2094                                            BIT(DRM_ROTATE_0));
2095                 win->rotation_prop = prop;
2096         }
2097         if (win->phy->scl)
2098                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2099         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2100             VOP_WIN_SUPPORT(vop, win, alpha_en))
2101                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2102
2103         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2104                                    feature);
2105
2106         return 0;
2107 }
2108
2109 static int vop_create_crtc(struct vop *vop)
2110 {
2111         struct device *dev = vop->dev;
2112         const struct vop_data *vop_data = vop->data;
2113         struct drm_device *drm_dev = vop->drm_dev;
2114         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2115         struct drm_crtc *crtc = &vop->crtc;
2116         struct device_node *port;
2117         uint64_t feature = 0;
2118         int ret;
2119         int i;
2120
2121         /*
2122          * Create drm_plane for primary and cursor planes first, since we need
2123          * to pass them to drm_crtc_init_with_planes, which sets the
2124          * "possible_crtcs" to the newly initialized crtc.
2125          */
2126         for (i = 0; i < vop->num_wins; i++) {
2127                 struct vop_win *win = &vop->win[i];
2128
2129                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2130                     win->type != DRM_PLANE_TYPE_CURSOR)
2131                         continue;
2132
2133                 ret = vop_plane_init(vop, win, 0);
2134                 if (ret)
2135                         goto err_cleanup_planes;
2136
2137                 plane = &win->base;
2138                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2139                         primary = plane;
2140                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2141                         cursor = plane;
2142
2143         }
2144
2145         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2146                                         &vop_crtc_funcs, NULL);
2147         if (ret)
2148                 goto err_cleanup_planes;
2149
2150         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2151
2152         /*
2153          * Create drm_planes for overlay windows with possible_crtcs restricted
2154          * to the newly created crtc.
2155          */
2156         for (i = 0; i < vop->num_wins; i++) {
2157                 struct vop_win *win = &vop->win[i];
2158                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2159
2160                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2161                         continue;
2162
2163                 ret = vop_plane_init(vop, win, possible_crtcs);
2164                 if (ret)
2165                         goto err_cleanup_crtc;
2166         }
2167
2168         port = of_get_child_by_name(dev->of_node, "port");
2169         if (!port) {
2170                 DRM_ERROR("no port node found in %s\n",
2171                           dev->of_node->full_name);
2172                 ret = -ENOENT;
2173                 goto err_cleanup_crtc;
2174         }
2175
2176         init_completion(&vop->dsp_hold_completion);
2177         init_completion(&vop->wait_update_complete);
2178         init_completion(&vop->line_flag_completion);
2179         crtc->port = port;
2180         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2181
2182         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2183         if (ret)
2184                 goto err_unregister_crtc_funcs;
2185 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2186         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2187
2188         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2189         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2190         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2191         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2192 #undef VOP_ATTACH_MODE_CONFIG_PROP
2193
2194         if (vop_data->feature & VOP_FEATURE_AFBDC)
2195                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2196         drm_object_attach_property(&crtc->base, vop->feature_prop,
2197                                    feature);
2198
2199         return 0;
2200
2201 err_unregister_crtc_funcs:
2202         rockchip_unregister_crtc_funcs(crtc);
2203 err_cleanup_crtc:
2204         drm_crtc_cleanup(crtc);
2205 err_cleanup_planes:
2206         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2207                                  head)
2208                 drm_plane_cleanup(plane);
2209         return ret;
2210 }
2211
2212 static void vop_destroy_crtc(struct vop *vop)
2213 {
2214         struct drm_crtc *crtc = &vop->crtc;
2215         struct drm_device *drm_dev = vop->drm_dev;
2216         struct drm_plane *plane, *tmp;
2217
2218         rockchip_unregister_crtc_funcs(crtc);
2219         of_node_put(crtc->port);
2220
2221         /*
2222          * We need to cleanup the planes now.  Why?
2223          *
2224          * The planes are "&vop->win[i].base".  That means the memory is
2225          * all part of the big "struct vop" chunk of memory.  That memory
2226          * was devm allocated and associated with this component.  We need to
2227          * free it ourselves before vop_unbind() finishes.
2228          */
2229         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2230                                  head)
2231                 vop_plane_destroy(plane);
2232
2233         /*
2234          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2235          * references the CRTC.
2236          */
2237         drm_crtc_cleanup(crtc);
2238 }
2239
2240 /*
2241  * Initialize the vop->win array elements.
2242  */
2243 static int vop_win_init(struct vop *vop)
2244 {
2245         const struct vop_data *vop_data = vop->data;
2246         unsigned int i, j;
2247         unsigned int num_wins = 0;
2248         struct drm_property *prop;
2249         static const struct drm_prop_enum_list props[] = {
2250                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2251                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2252         };
2253         static const struct drm_prop_enum_list crtc_props[] = {
2254                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2255         };
2256
2257         for (i = 0; i < vop_data->win_size; i++) {
2258                 struct vop_win *vop_win = &vop->win[num_wins];
2259                 const struct vop_win_data *win_data = &vop_data->win[i];
2260
2261                 if (!win_data->phy)
2262                         continue;
2263
2264                 vop_win->phy = win_data->phy;
2265                 vop_win->csc = win_data->csc;
2266                 vop_win->offset = win_data->base;
2267                 vop_win->type = win_data->type;
2268                 vop_win->data_formats = win_data->phy->data_formats;
2269                 vop_win->nformats = win_data->phy->nformats;
2270                 vop_win->vop = vop;
2271                 vop_win->win_id = i;
2272                 vop_win->area_id = 0;
2273                 num_wins++;
2274
2275                 for (j = 0; j < win_data->area_size; j++) {
2276                         struct vop_win *vop_area = &vop->win[num_wins];
2277                         const struct vop_win_phy *area = win_data->area[j];
2278
2279                         vop_area->parent = vop_win;
2280                         vop_area->offset = vop_win->offset;
2281                         vop_area->phy = area;
2282                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2283                         vop_area->data_formats = vop_win->data_formats;
2284                         vop_area->nformats = vop_win->nformats;
2285                         vop_area->vop = vop;
2286                         vop_area->win_id = i;
2287                         vop_area->area_id = j;
2288                         num_wins++;
2289                 }
2290         }
2291
2292         vop->num_wins = num_wins;
2293
2294         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2295                                          "ZPOS", 0, vop->data->win_size);
2296         if (!prop) {
2297                 DRM_ERROR("failed to create zpos property\n");
2298                 return -EINVAL;
2299         }
2300         vop->plane_zpos_prop = prop;
2301
2302         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2303                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2304                                 props, ARRAY_SIZE(props),
2305                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2306                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2307         if (!vop->plane_feature_prop) {
2308                 DRM_ERROR("failed to create feature property\n");
2309                 return -EINVAL;
2310         }
2311
2312         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2313                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2314                                 crtc_props, ARRAY_SIZE(crtc_props),
2315                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2316         if (!vop->feature_prop) {
2317                 DRM_ERROR("failed to create vop feature property\n");
2318                 return -EINVAL;
2319         }
2320
2321         return 0;
2322 }
2323
2324 /**
2325  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2326  * @crtc: CRTC to enable line flag
2327  * @line_num: interested line number
2328  * @mstimeout: millisecond for timeout
2329  *
2330  * Driver would hold here until the interested line flag interrupt have
2331  * happened or timeout to wait.
2332  *
2333  * Returns:
2334  * Zero on success, negative errno on failure.
2335  */
2336 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2337                                 unsigned int mstimeout)
2338 {
2339         struct vop *vop = to_vop(crtc);
2340         unsigned long jiffies_left;
2341
2342         if (!crtc || !vop->is_enabled)
2343                 return -ENODEV;
2344
2345         if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2346                 return -EINVAL;
2347
2348         if (vop_line_flag_irq_is_enabled(vop))
2349                 return -EBUSY;
2350
2351         reinit_completion(&vop->line_flag_completion);
2352         vop_line_flag_irq_enable(vop, line_num);
2353
2354         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2355                                                    msecs_to_jiffies(mstimeout));
2356         vop_line_flag_irq_disable(vop);
2357
2358         if (jiffies_left == 0) {
2359                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2360                 return -ETIMEDOUT;
2361         }
2362
2363         return 0;
2364 }
2365 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2366
2367 static int vop_bind(struct device *dev, struct device *master, void *data)
2368 {
2369         struct platform_device *pdev = to_platform_device(dev);
2370         const struct vop_data *vop_data;
2371         struct drm_device *drm_dev = data;
2372         struct vop *vop;
2373         struct resource *res;
2374         size_t alloc_size;
2375         int ret, irq, i;
2376         int num_wins = 0;
2377
2378         vop_data = of_device_get_match_data(dev);
2379         if (!vop_data)
2380                 return -ENODEV;
2381
2382         for (i = 0; i < vop_data->win_size; i++) {
2383                 const struct vop_win_data *win_data = &vop_data->win[i];
2384
2385                 num_wins += win_data->area_size + 1;
2386         }
2387
2388         /* Allocate vop struct and its vop_win array */
2389         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2390         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2391         if (!vop)
2392                 return -ENOMEM;
2393
2394         vop->dev = dev;
2395         vop->data = vop_data;
2396         vop->drm_dev = drm_dev;
2397         vop->num_wins = num_wins;
2398         dev_set_drvdata(dev, vop);
2399
2400         ret = vop_win_init(vop);
2401         if (ret)
2402                 return ret;
2403
2404         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2405         vop->len = resource_size(res);
2406         vop->regs = devm_ioremap_resource(dev, res);
2407         if (IS_ERR(vop->regs))
2408                 return PTR_ERR(vop->regs);
2409
2410         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2411         if (!vop->regsbak)
2412                 return -ENOMEM;
2413
2414         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2415         if (IS_ERR(vop->hclk)) {
2416                 dev_err(vop->dev, "failed to get hclk source\n");
2417                 return PTR_ERR(vop->hclk);
2418         }
2419         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2420         if (IS_ERR(vop->aclk)) {
2421                 dev_err(vop->dev, "failed to get aclk source\n");
2422                 return PTR_ERR(vop->aclk);
2423         }
2424         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2425         if (IS_ERR(vop->dclk)) {
2426                 dev_err(vop->dev, "failed to get dclk source\n");
2427                 return PTR_ERR(vop->dclk);
2428         }
2429
2430         irq = platform_get_irq(pdev, 0);
2431         if (irq < 0) {
2432                 dev_err(dev, "cannot find irq for vop\n");
2433                 return irq;
2434         }
2435         vop->irq = (unsigned int)irq;
2436
2437         spin_lock_init(&vop->reg_lock);
2438         spin_lock_init(&vop->irq_lock);
2439
2440         mutex_init(&vop->vsync_mutex);
2441
2442         ret = devm_request_irq(dev, vop->irq, vop_isr,
2443                                IRQF_SHARED, dev_name(dev), vop);
2444         if (ret)
2445                 return ret;
2446
2447         /* IRQ is initially disabled; it gets enabled in power_on */
2448         disable_irq(vop->irq);
2449
2450         ret = vop_create_crtc(vop);
2451         if (ret)
2452                 return ret;
2453
2454         pm_runtime_enable(&pdev->dev);
2455         return 0;
2456 }
2457
2458 static void vop_unbind(struct device *dev, struct device *master, void *data)
2459 {
2460         struct vop *vop = dev_get_drvdata(dev);
2461
2462         pm_runtime_disable(dev);
2463         vop_destroy_crtc(vop);
2464 }
2465
2466 const struct component_ops vop_component_ops = {
2467         .bind = vop_bind,
2468         .unbind = vop_unbind,
2469 };
2470 EXPORT_SYMBOL_GPL(vop_component_ops);