2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_plane_helper.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
26 #include <linux/of_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/component.h>
30 #include <linux/reset.h>
31 #include <linux/delay.h>
33 #include "rockchip_drm_drv.h"
34 #include "rockchip_drm_gem.h"
35 #include "rockchip_drm_fb.h"
36 #include "rockchip_drm_vop.h"
38 #define VOP_REG(off, _mask, s) \
43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
44 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
46 vop_mask_write(x, off, (mask) << shift, (v) << shift)
48 #define REG_SET(x, base, reg, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
51 #define VOP_WIN_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->name, v, RELAXED)
53 #define VOP_SCL_SET(x, win, name, v) \
54 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
55 #define VOP_CTRL_SET(x, name, v) \
56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
58 #define VOP_WIN_GET(x, win, name) \
59 vop_read_reg(x, win->base, &win->phy->name)
61 #define VOP_WIN_GET_YRGBADDR(vop, win) \
62 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
64 #define to_vop(x) container_of(x, struct vop, crtc)
65 #define to_vop_win(x) container_of(x, struct vop_win, base)
67 struct vop_win_state {
68 struct list_head head;
69 struct drm_framebuffer *fb;
71 struct drm_pending_vblank_event *event;
75 struct drm_plane base;
76 const struct vop_win_data *data;
79 struct list_head pending;
80 struct vop_win_state *active;
86 struct drm_device *drm_dev;
90 int connector_out_mode;
92 /* mutex vsync_ work */
93 struct mutex vsync_mutex;
94 bool vsync_work_pending;
95 struct completion dsp_hold_completion;
97 const struct vop_data *data;
102 /* physical map length of vop register */
105 /* one time only one process allowed to config the register */
107 /* lock vop irq reg */
116 /* vop share memory frequency */
120 struct reset_control *dclk_rst;
124 struct vop_win win[];
127 enum vop_data_format {
128 VOP_FMT_ARGB8888 = 0,
131 VOP_FMT_YUV420SP = 4,
136 struct vop_reg_data {
148 struct vop_reg standby;
149 struct vop_reg data_blank;
150 struct vop_reg gate_en;
151 struct vop_reg mmu_en;
152 struct vop_reg rgb_en;
153 struct vop_reg edp_en;
154 struct vop_reg hdmi_en;
155 struct vop_reg mipi_en;
156 struct vop_reg out_mode;
157 struct vop_reg dither_down;
158 struct vop_reg dither_up;
159 struct vop_reg pin_pol;
161 struct vop_reg htotal_pw;
162 struct vop_reg hact_st_end;
163 struct vop_reg vtotal_pw;
164 struct vop_reg vact_st_end;
165 struct vop_reg hpost_st_end;
166 struct vop_reg vpost_st_end;
169 struct vop_scl_regs {
170 struct vop_reg cbcr_vsd_mode;
171 struct vop_reg cbcr_vsu_mode;
172 struct vop_reg cbcr_hsd_mode;
173 struct vop_reg cbcr_ver_scl_mode;
174 struct vop_reg cbcr_hor_scl_mode;
175 struct vop_reg yrgb_vsd_mode;
176 struct vop_reg yrgb_vsu_mode;
177 struct vop_reg yrgb_hsd_mode;
178 struct vop_reg yrgb_ver_scl_mode;
179 struct vop_reg yrgb_hor_scl_mode;
180 struct vop_reg line_load_mode;
181 struct vop_reg cbcr_axi_gather_num;
182 struct vop_reg yrgb_axi_gather_num;
183 struct vop_reg vsd_cbcr_gt2;
184 struct vop_reg vsd_cbcr_gt4;
185 struct vop_reg vsd_yrgb_gt2;
186 struct vop_reg vsd_yrgb_gt4;
187 struct vop_reg bic_coe_sel;
188 struct vop_reg cbcr_axi_gather_en;
189 struct vop_reg yrgb_axi_gather_en;
191 struct vop_reg lb_mode;
192 struct vop_reg scale_yrgb_x;
193 struct vop_reg scale_yrgb_y;
194 struct vop_reg scale_cbcr_x;
195 struct vop_reg scale_cbcr_y;
199 const struct vop_scl_regs *scl;
200 const uint32_t *data_formats;
203 struct vop_reg enable;
204 struct vop_reg format;
205 struct vop_reg rb_swap;
206 struct vop_reg act_info;
207 struct vop_reg dsp_info;
208 struct vop_reg dsp_st;
209 struct vop_reg yrgb_mst;
210 struct vop_reg uv_mst;
211 struct vop_reg yrgb_vir;
212 struct vop_reg uv_vir;
214 struct vop_reg dst_alpha_ctl;
215 struct vop_reg src_alpha_ctl;
218 struct vop_win_data {
220 const struct vop_win_phy *phy;
221 enum drm_plane_type type;
225 const struct vop_reg_data *init_table;
226 unsigned int table_size;
227 const struct vop_ctrl *ctrl;
228 const struct vop_win_data *win;
229 unsigned int win_size;
232 static const uint32_t formats_01[] = {
246 static const uint32_t formats_234[] = {
257 static const struct vop_scl_regs win_full_scl = {
258 .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
259 .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
260 .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
261 .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
262 .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
263 .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
264 .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
265 .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
266 .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
267 .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
268 .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
269 .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
270 .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
271 .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
272 .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
273 .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
274 .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
275 .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
276 .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
277 .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
278 .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
279 .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
280 .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
281 .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
282 .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
285 static const struct vop_win_phy win01_data = {
286 .scl = &win_full_scl,
287 .data_formats = formats_01,
288 .nformats = ARRAY_SIZE(formats_01),
289 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
290 .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
291 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
292 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
293 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
294 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
295 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
296 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
297 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
298 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
299 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
300 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
303 static const struct vop_win_phy win23_data = {
304 .data_formats = formats_234,
305 .nformats = ARRAY_SIZE(formats_234),
306 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
307 .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
308 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
309 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
310 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
311 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
312 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
313 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
314 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
317 static const struct vop_ctrl ctrl_data = {
318 .standby = VOP_REG(SYS_CTRL, 0x1, 22),
319 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
320 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
321 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
322 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
323 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
324 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
325 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
326 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
327 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
328 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
329 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
330 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
331 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
332 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
333 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
334 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
335 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
338 static const struct vop_reg_data vop_init_reg_table[] = {
339 {SYS_CTRL, 0x00c00000},
340 {DSP_CTRL0, 0x00000000},
341 {WIN0_CTRL0, 0x00000080},
342 {WIN1_CTRL0, 0x00000080},
343 /* TODO: Win2/3 support multiple area function, but we haven't found
344 * a suitable way to use it yet, so let's just use them as other windows
345 * with only area 0 enabled.
347 {WIN2_CTRL0, 0x00000010},
348 {WIN3_CTRL0, 0x00000010},
352 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
353 * special support to get alpha blending working. For now, just use overlay
354 * window 3 for the drm cursor.
357 static const struct vop_win_data rk3288_vop_win_data[] = {
358 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
359 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
360 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
361 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
364 static const struct vop_data rk3288_vop = {
365 .init_table = vop_init_reg_table,
366 .table_size = ARRAY_SIZE(vop_init_reg_table),
368 .win = rk3288_vop_win_data,
369 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
372 static const struct of_device_id vop_driver_dt_match[] = {
373 { .compatible = "rockchip,rk3288-vop",
374 .data = &rk3288_vop },
378 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
380 writel(v, vop->regs + offset);
381 vop->regsbak[offset >> 2] = v;
384 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
386 return readl(vop->regs + offset);
389 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
390 const struct vop_reg *reg)
392 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
395 static inline void vop_cfg_done(struct vop *vop)
397 writel(0x01, vop->regs + REG_CFG_DONE);
400 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
401 uint32_t mask, uint32_t v)
404 uint32_t cached_val = vop->regsbak[offset >> 2];
406 cached_val = (cached_val & ~mask) | v;
407 writel(cached_val, vop->regs + offset);
408 vop->regsbak[offset >> 2] = cached_val;
412 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
413 uint32_t mask, uint32_t v)
416 uint32_t cached_val = vop->regsbak[offset >> 2];
418 cached_val = (cached_val & ~mask) | v;
419 writel_relaxed(cached_val, vop->regs + offset);
420 vop->regsbak[offset >> 2] = cached_val;
424 static bool has_rb_swapped(uint32_t format)
427 case DRM_FORMAT_XBGR8888:
428 case DRM_FORMAT_ABGR8888:
429 case DRM_FORMAT_BGR888:
430 case DRM_FORMAT_BGR565:
437 static enum vop_data_format vop_convert_format(uint32_t format)
440 case DRM_FORMAT_XRGB8888:
441 case DRM_FORMAT_ARGB8888:
442 case DRM_FORMAT_XBGR8888:
443 case DRM_FORMAT_ABGR8888:
444 return VOP_FMT_ARGB8888;
445 case DRM_FORMAT_RGB888:
446 case DRM_FORMAT_BGR888:
447 return VOP_FMT_RGB888;
448 case DRM_FORMAT_RGB565:
449 case DRM_FORMAT_BGR565:
450 return VOP_FMT_RGB565;
451 case DRM_FORMAT_NV12:
452 return VOP_FMT_YUV420SP;
453 case DRM_FORMAT_NV16:
454 return VOP_FMT_YUV422SP;
455 case DRM_FORMAT_NV24:
456 return VOP_FMT_YUV444SP;
458 DRM_ERROR("unsupport format[%08x]\n", format);
463 static bool is_yuv_support(uint32_t format)
466 case DRM_FORMAT_NV12:
467 case DRM_FORMAT_NV16:
468 case DRM_FORMAT_NV24:
475 static bool is_alpha_support(uint32_t format)
478 case DRM_FORMAT_ARGB8888:
479 case DRM_FORMAT_ABGR8888:
486 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
487 uint32_t dst, bool is_horizontal,
488 int vsu_mode, int *vskiplines)
490 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
493 if (mode == SCALE_UP)
494 val = GET_SCL_FT_BIC(src, dst);
495 else if (mode == SCALE_DOWN)
496 val = GET_SCL_FT_BILI_DN(src, dst);
498 if (mode == SCALE_UP) {
499 if (vsu_mode == SCALE_UP_BIL)
500 val = GET_SCL_FT_BILI_UP(src, dst);
502 val = GET_SCL_FT_BIC(src, dst);
503 } else if (mode == SCALE_DOWN) {
505 *vskiplines = scl_get_vskiplines(src, dst);
506 val = scl_get_bili_dn_vskip(src, dst,
509 val = GET_SCL_FT_BILI_DN(src, dst);
517 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
518 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
519 uint32_t dst_h, uint32_t pixel_format)
521 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
522 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
523 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
524 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
525 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
526 bool is_yuv = is_yuv_support(pixel_format);
527 uint16_t cbcr_src_w = src_w / hsub;
528 uint16_t cbcr_src_h = src_h / vsub;
535 DRM_ERROR("Maximum destination width (3840) exceeded\n");
539 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
540 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
543 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
544 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
545 if (cbcr_hor_scl_mode == SCALE_DOWN)
546 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
548 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
550 if (yrgb_hor_scl_mode == SCALE_DOWN)
551 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
553 lb_mode = scl_vop_cal_lb_mode(src_w, false);
556 VOP_SCL_SET(vop, win, lb_mode, lb_mode);
557 if (lb_mode == LB_RGB_3840X2) {
558 if (yrgb_ver_scl_mode != SCALE_NONE) {
559 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
562 if (cbcr_ver_scl_mode != SCALE_NONE) {
563 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
566 vsu_mode = SCALE_UP_BIL;
567 } else if (lb_mode == LB_RGB_2560X4) {
568 vsu_mode = SCALE_UP_BIL;
570 vsu_mode = SCALE_UP_BIC;
573 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
575 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
576 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
577 false, vsu_mode, &vskiplines);
578 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
580 VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
581 VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
583 VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
584 VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
585 VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
586 VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
587 VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
589 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
590 dst_w, true, 0, NULL);
591 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
592 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
593 dst_h, false, vsu_mode, &vskiplines);
594 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
596 VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
597 VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
598 VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
599 VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
600 VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
601 VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
602 VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
606 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
610 if (WARN_ON(!vop->is_enabled))
613 spin_lock_irqsave(&vop->irq_lock, flags);
615 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
616 DSP_HOLD_VALID_INTR_EN(1));
618 spin_unlock_irqrestore(&vop->irq_lock, flags);
621 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
625 if (WARN_ON(!vop->is_enabled))
628 spin_lock_irqsave(&vop->irq_lock, flags);
630 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
631 DSP_HOLD_VALID_INTR_EN(0));
633 spin_unlock_irqrestore(&vop->irq_lock, flags);
636 static void vop_enable(struct drm_crtc *crtc)
638 struct vop *vop = to_vop(crtc);
644 ret = pm_runtime_get_sync(vop->dev);
646 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
650 ret = clk_enable(vop->hclk);
652 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
656 ret = clk_enable(vop->dclk);
658 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
659 goto err_disable_hclk;
662 ret = clk_enable(vop->aclk);
664 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
665 goto err_disable_dclk;
669 * Slave iommu shares power, irq and clock with vop. It was associated
670 * automatically with this master device via common driver code.
671 * Now that we have enabled the clock we attach it to the shared drm
674 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
676 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
677 goto err_disable_aclk;
680 memcpy(vop->regs, vop->regsbak, vop->len);
682 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
684 vop->is_enabled = true;
686 spin_lock(&vop->reg_lock);
688 VOP_CTRL_SET(vop, standby, 0);
690 spin_unlock(&vop->reg_lock);
692 enable_irq(vop->irq);
694 drm_vblank_on(vop->drm_dev, vop->pipe);
699 clk_disable(vop->aclk);
701 clk_disable(vop->dclk);
703 clk_disable(vop->hclk);
706 static void vop_disable(struct drm_crtc *crtc)
708 struct vop *vop = to_vop(crtc);
710 if (!vop->is_enabled)
713 drm_vblank_off(crtc->dev, vop->pipe);
716 * Vop standby will take effect at end of current frame,
717 * if dsp hold valid irq happen, it means standby complete.
719 * we must wait standby complete when we want to disable aclk,
720 * if not, memory bus maybe dead.
722 reinit_completion(&vop->dsp_hold_completion);
723 vop_dsp_hold_valid_irq_enable(vop);
725 spin_lock(&vop->reg_lock);
727 VOP_CTRL_SET(vop, standby, 1);
729 spin_unlock(&vop->reg_lock);
731 wait_for_completion(&vop->dsp_hold_completion);
733 vop_dsp_hold_valid_irq_disable(vop);
735 disable_irq(vop->irq);
737 vop->is_enabled = false;
740 * vop standby complete, so iommu detach is safe.
742 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
744 clk_disable(vop->dclk);
745 clk_disable(vop->aclk);
746 clk_disable(vop->hclk);
747 pm_runtime_put(vop->dev);
751 * Caller must hold vsync_mutex.
753 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
755 struct vop_win_state *last;
756 struct vop_win_state *active = vop_win->active;
758 if (list_empty(&vop_win->pending))
759 return active ? active->fb : NULL;
761 last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
762 return last ? last->fb : NULL;
766 * Caller must hold vsync_mutex.
768 static int vop_win_queue_fb(struct vop_win *vop_win,
769 struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
770 struct drm_pending_vblank_event *event)
772 struct vop_win_state *state;
774 state = kzalloc(sizeof(*state), GFP_KERNEL);
779 state->yrgb_mst = yrgb_mst;
780 state->event = event;
782 list_add_tail(&state->head, &vop_win->pending);
787 static int vop_update_plane_event(struct drm_plane *plane,
788 struct drm_crtc *crtc,
789 struct drm_framebuffer *fb, int crtc_x,
790 int crtc_y, unsigned int crtc_w,
791 unsigned int crtc_h, uint32_t src_x,
792 uint32_t src_y, uint32_t src_w,
794 struct drm_pending_vblank_event *event)
796 struct vop_win *vop_win = to_vop_win(plane);
797 const struct vop_win_data *win = vop_win->data;
798 struct vop *vop = to_vop(crtc);
799 struct drm_gem_object *obj;
800 struct rockchip_gem_object *rk_obj;
801 struct drm_gem_object *uv_obj;
802 struct rockchip_gem_object *rk_uv_obj;
803 unsigned long offset;
804 unsigned int actual_w;
805 unsigned int actual_h;
806 unsigned int dsp_stx;
807 unsigned int dsp_sty;
808 unsigned int y_vir_stride;
809 unsigned int uv_vir_stride = 0;
811 dma_addr_t uv_mst = 0;
812 enum vop_data_format format;
819 struct drm_rect dest = {
822 .x2 = crtc_x + crtc_w,
823 .y2 = crtc_y + crtc_h,
825 struct drm_rect src = {
826 /* 16.16 fixed point */
832 const struct drm_rect clip = {
833 .x2 = crtc->mode.hdisplay,
834 .y2 = crtc->mode.vdisplay,
836 bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
837 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
838 DRM_PLANE_HELPER_NO_SCALING;
839 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
840 DRM_PLANE_HELPER_NO_SCALING;
842 ret = drm_plane_helper_check_update(plane, crtc, fb,
846 can_position, false, &visible);
853 is_alpha = is_alpha_support(fb->pixel_format);
854 rb_swap = has_rb_swapped(fb->pixel_format);
855 is_yuv = is_yuv_support(fb->pixel_format);
857 format = vop_convert_format(fb->pixel_format);
861 obj = rockchip_fb_get_gem_obj(fb, 0);
863 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
867 rk_obj = to_rockchip_obj(obj);
871 * Src.x1 can be odd when do clip, but yuv plane start point
872 * need align with 2 pixel.
874 val = (src.x1 >> 16) % 2;
879 actual_w = (src.x2 - src.x1) >> 16;
880 actual_h = (src.y2 - src.y1) >> 16;
882 dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
883 dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
885 offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
886 offset += (src.y1 >> 16) * fb->pitches[0];
888 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
889 y_vir_stride = fb->pitches[0] >> 2;
892 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
893 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
894 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
896 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
898 DRM_ERROR("fail to get uv object from framebuffer\n");
901 rk_uv_obj = to_rockchip_obj(uv_obj);
902 uv_vir_stride = fb->pitches[1] >> 2;
904 offset = (src.x1 >> 16) * bpp / hsub;
905 offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
907 uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
911 * If this plane update changes the plane's framebuffer, (or more
912 * precisely, if this update has a different framebuffer than the last
913 * update), enqueue it so we can track when it completes.
915 * Only when we discover that this update has completed, can we
916 * unreference any previous framebuffers.
918 mutex_lock(&vop->vsync_mutex);
919 if (fb != vop_win_last_pending_fb(vop_win)) {
920 ret = drm_vblank_get(plane->dev, vop->pipe);
922 DRM_ERROR("failed to get vblank, %d\n", ret);
923 mutex_unlock(&vop->vsync_mutex);
927 drm_framebuffer_reference(fb);
929 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
931 drm_vblank_put(plane->dev, vop->pipe);
932 mutex_unlock(&vop->vsync_mutex);
936 vop->vsync_work_pending = true;
938 mutex_unlock(&vop->vsync_mutex);
940 spin_lock(&vop->reg_lock);
942 VOP_WIN_SET(vop, win, format, format);
943 VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
944 VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
946 VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
947 VOP_WIN_SET(vop, win, uv_mst, uv_mst);
951 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
952 dest.x2 - dest.x1, dest.y2 - dest.y1,
955 val = (actual_h - 1) << 16;
956 val |= (actual_w - 1) & 0xffff;
957 VOP_WIN_SET(vop, win, act_info, val);
959 val = (dest.y2 - dest.y1 - 1) << 16;
960 val |= (dest.x2 - dest.x1 - 1) & 0xffff;
961 VOP_WIN_SET(vop, win, dsp_info, val);
962 val = (dsp_sty - 1) << 16;
963 val |= (dsp_stx - 1) & 0xffff;
964 VOP_WIN_SET(vop, win, dsp_st, val);
965 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
968 VOP_WIN_SET(vop, win, dst_alpha_ctl,
969 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
970 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
971 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
972 SRC_BLEND_M0(ALPHA_PER_PIX) |
973 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
974 SRC_FACTOR_M0(ALPHA_ONE);
975 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
977 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
980 VOP_WIN_SET(vop, win, enable, 1);
983 spin_unlock(&vop->reg_lock);
988 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
989 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
990 unsigned int crtc_w, unsigned int crtc_h,
991 uint32_t src_x, uint32_t src_y, uint32_t src_w,
994 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
995 crtc_h, src_x, src_y, src_w, src_h,
999 static int vop_update_primary_plane(struct drm_crtc *crtc,
1000 struct drm_pending_vblank_event *event)
1002 unsigned int crtc_w, crtc_h;
1004 crtc_w = crtc->primary->fb->width - crtc->x;
1005 crtc_h = crtc->primary->fb->height - crtc->y;
1007 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
1008 0, 0, crtc_w, crtc_h, crtc->x << 16,
1009 crtc->y << 16, crtc_w << 16,
1010 crtc_h << 16, event);
1013 static int vop_disable_plane(struct drm_plane *plane)
1015 struct vop_win *vop_win = to_vop_win(plane);
1016 const struct vop_win_data *win = vop_win->data;
1023 vop = to_vop(plane->crtc);
1025 ret = drm_vblank_get(plane->dev, vop->pipe);
1027 DRM_ERROR("failed to get vblank, %d\n", ret);
1031 mutex_lock(&vop->vsync_mutex);
1033 ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
1035 drm_vblank_put(plane->dev, vop->pipe);
1036 mutex_unlock(&vop->vsync_mutex);
1040 vop->vsync_work_pending = true;
1041 mutex_unlock(&vop->vsync_mutex);
1043 spin_lock(&vop->reg_lock);
1044 VOP_WIN_SET(vop, win, enable, 0);
1046 spin_unlock(&vop->reg_lock);
1051 static void vop_plane_destroy(struct drm_plane *plane)
1053 vop_disable_plane(plane);
1054 drm_plane_cleanup(plane);
1057 static const struct drm_plane_funcs vop_plane_funcs = {
1058 .update_plane = vop_update_plane,
1059 .disable_plane = vop_disable_plane,
1060 .destroy = vop_plane_destroy,
1063 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
1067 struct vop *vop = to_vop(crtc);
1069 vop->connector_type = connector_type;
1070 vop->connector_out_mode = out_mode;
1074 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
1076 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1078 struct vop *vop = to_vop(crtc);
1079 unsigned long flags;
1081 if (!vop->is_enabled)
1084 spin_lock_irqsave(&vop->irq_lock, flags);
1086 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
1088 spin_unlock_irqrestore(&vop->irq_lock, flags);
1093 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1095 struct vop *vop = to_vop(crtc);
1096 unsigned long flags;
1098 if (!vop->is_enabled)
1101 spin_lock_irqsave(&vop->irq_lock, flags);
1102 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
1103 spin_unlock_irqrestore(&vop->irq_lock, flags);
1106 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1107 .enable_vblank = vop_crtc_enable_vblank,
1108 .disable_vblank = vop_crtc_disable_vblank,
1111 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
1113 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
1116 case DRM_MODE_DPMS_ON:
1119 case DRM_MODE_DPMS_STANDBY:
1120 case DRM_MODE_DPMS_SUSPEND:
1121 case DRM_MODE_DPMS_OFF:
1125 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
1130 static void vop_crtc_prepare(struct drm_crtc *crtc)
1132 vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1135 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1136 const struct drm_display_mode *mode,
1137 struct drm_display_mode *adjusted_mode)
1139 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
1145 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1146 struct drm_framebuffer *old_fb)
1153 ret = vop_update_primary_plane(crtc, NULL);
1155 DRM_ERROR("fail to update plane\n");
1162 static int vop_crtc_mode_set(struct drm_crtc *crtc,
1163 struct drm_display_mode *mode,
1164 struct drm_display_mode *adjusted_mode,
1165 int x, int y, struct drm_framebuffer *fb)
1167 struct vop *vop = to_vop(crtc);
1168 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1169 u16 hdisplay = adjusted_mode->hdisplay;
1170 u16 htotal = adjusted_mode->htotal;
1171 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1172 u16 hact_end = hact_st + hdisplay;
1173 u16 vdisplay = adjusted_mode->vdisplay;
1174 u16 vtotal = adjusted_mode->vtotal;
1175 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1176 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1177 u16 vact_end = vact_st + vdisplay;
1182 * disable dclk to stop frame scan, so that we can safe config mode and
1185 clk_disable(vop->dclk);
1187 switch (vop->connector_type) {
1188 case DRM_MODE_CONNECTOR_LVDS:
1189 VOP_CTRL_SET(vop, rgb_en, 1);
1191 case DRM_MODE_CONNECTOR_eDP:
1192 VOP_CTRL_SET(vop, edp_en, 1);
1194 case DRM_MODE_CONNECTOR_HDMIA:
1195 VOP_CTRL_SET(vop, hdmi_en, 1);
1198 DRM_ERROR("unsupport connector_type[%d]\n",
1199 vop->connector_type);
1203 VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
1206 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1207 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1208 VOP_CTRL_SET(vop, pin_pol, val);
1210 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1211 val = hact_st << 16;
1213 VOP_CTRL_SET(vop, hact_st_end, val);
1214 VOP_CTRL_SET(vop, hpost_st_end, val);
1216 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1217 val = vact_st << 16;
1219 VOP_CTRL_SET(vop, vact_st_end, val);
1220 VOP_CTRL_SET(vop, vpost_st_end, val);
1222 ret = vop_crtc_mode_set_base(crtc, x, y, fb);
1227 * reset dclk, take all mode config affect, so the clk would run in
1230 reset_control_assert(vop->dclk_rst);
1231 usleep_range(10, 20);
1232 reset_control_deassert(vop->dclk_rst);
1234 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1236 ret_clk = clk_enable(vop->dclk);
1238 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
1245 static void vop_crtc_commit(struct drm_crtc *crtc)
1249 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1250 .dpms = vop_crtc_dpms,
1251 .prepare = vop_crtc_prepare,
1252 .mode_fixup = vop_crtc_mode_fixup,
1253 .mode_set = vop_crtc_mode_set,
1254 .mode_set_base = vop_crtc_mode_set_base,
1255 .commit = vop_crtc_commit,
1258 static int vop_crtc_page_flip(struct drm_crtc *crtc,
1259 struct drm_framebuffer *fb,
1260 struct drm_pending_vblank_event *event,
1261 uint32_t page_flip_flags)
1263 struct vop *vop = to_vop(crtc);
1264 struct drm_framebuffer *old_fb = crtc->primary->fb;
1267 /* when the page flip is requested, crtc should be on */
1268 if (!vop->is_enabled) {
1269 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1273 crtc->primary->fb = fb;
1275 ret = vop_update_primary_plane(crtc, event);
1277 crtc->primary->fb = old_fb;
1282 static void vop_win_state_complete(struct vop_win *vop_win,
1283 struct vop_win_state *state)
1285 struct vop *vop = vop_win->vop;
1286 struct drm_crtc *crtc = &vop->crtc;
1287 struct drm_device *drm = crtc->dev;
1288 unsigned long flags;
1291 spin_lock_irqsave(&drm->event_lock, flags);
1292 drm_send_vblank_event(drm, -1, state->event);
1293 spin_unlock_irqrestore(&drm->event_lock, flags);
1296 list_del(&state->head);
1297 drm_vblank_put(crtc->dev, vop->pipe);
1300 static void vop_crtc_destroy(struct drm_crtc *crtc)
1302 drm_crtc_cleanup(crtc);
1305 static const struct drm_crtc_funcs vop_crtc_funcs = {
1306 .set_config = drm_crtc_helper_set_config,
1307 .page_flip = vop_crtc_page_flip,
1308 .destroy = vop_crtc_destroy,
1311 static bool vop_win_state_is_active(struct vop_win *vop_win,
1312 struct vop_win_state *state)
1314 bool active = false;
1317 dma_addr_t yrgb_mst;
1319 /* check yrgb_mst to tell if pending_fb is now front */
1320 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1322 active = (yrgb_mst == state->yrgb_mst);
1326 /* if enable bit is clear, plane is now disabled */
1327 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1329 active = (enabled == 0);
1335 static void vop_win_state_destroy(struct vop_win_state *state)
1337 struct drm_framebuffer *fb = state->fb;
1340 drm_framebuffer_unreference(fb);
1345 static void vop_win_update_state(struct vop_win *vop_win)
1347 struct vop_win_state *state, *n, *new_active = NULL;
1349 /* Check if any pending states are now active */
1350 list_for_each_entry(state, &vop_win->pending, head)
1351 if (vop_win_state_is_active(vop_win, state)) {
1360 * Destroy any 'skipped' pending states - states that were queued
1361 * before the newly active state.
1363 list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1364 if (state == new_active)
1366 vop_win_state_complete(vop_win, state);
1367 vop_win_state_destroy(state);
1370 vop_win_state_complete(vop_win, new_active);
1372 if (vop_win->active)
1373 vop_win_state_destroy(vop_win->active);
1374 vop_win->active = new_active;
1377 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1379 return !list_empty(&vop_win->pending);
1382 static irqreturn_t vop_isr_thread(int irq, void *data)
1384 struct vop *vop = data;
1385 const struct vop_data *vop_data = vop->data;
1388 mutex_lock(&vop->vsync_mutex);
1390 if (!vop->vsync_work_pending)
1393 vop->vsync_work_pending = false;
1395 for (i = 0; i < vop_data->win_size; i++) {
1396 struct vop_win *vop_win = &vop->win[i];
1398 vop_win_update_state(vop_win);
1399 if (vop_win_has_pending_state(vop_win))
1400 vop->vsync_work_pending = true;
1404 mutex_unlock(&vop->vsync_mutex);
1409 static irqreturn_t vop_isr(int irq, void *data)
1411 struct vop *vop = data;
1412 uint32_t intr0_reg, active_irqs;
1413 unsigned long flags;
1417 * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1418 * must hold irq_lock to avoid a race with enable/disable_vblank().
1420 spin_lock_irqsave(&vop->irq_lock, flags);
1421 intr0_reg = vop_readl(vop, INTR_CTRL0);
1422 active_irqs = intr0_reg & INTR_MASK;
1423 /* Clear all active interrupt sources */
1425 vop_writel(vop, INTR_CTRL0,
1426 intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1427 spin_unlock_irqrestore(&vop->irq_lock, flags);
1429 /* This is expected for vop iommu irqs, since the irq is shared */
1433 if (active_irqs & DSP_HOLD_VALID_INTR) {
1434 complete(&vop->dsp_hold_completion);
1435 active_irqs &= ~DSP_HOLD_VALID_INTR;
1439 if (active_irqs & FS_INTR) {
1440 drm_handle_vblank(vop->drm_dev, vop->pipe);
1441 active_irqs &= ~FS_INTR;
1442 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1445 /* Unhandled irqs are spurious. */
1447 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1452 static int vop_create_crtc(struct vop *vop)
1454 const struct vop_data *vop_data = vop->data;
1455 struct device *dev = vop->dev;
1456 struct drm_device *drm_dev = vop->drm_dev;
1457 struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1458 struct drm_crtc *crtc = &vop->crtc;
1459 struct device_node *port;
1464 * Create drm_plane for primary and cursor planes first, since we need
1465 * to pass them to drm_crtc_init_with_planes, which sets the
1466 * "possible_crtcs" to the newly initialized crtc.
1468 for (i = 0; i < vop_data->win_size; i++) {
1469 struct vop_win *vop_win = &vop->win[i];
1470 const struct vop_win_data *win_data = vop_win->data;
1472 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1473 win_data->type != DRM_PLANE_TYPE_CURSOR)
1476 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1477 0, &vop_plane_funcs,
1478 win_data->phy->data_formats,
1479 win_data->phy->nformats,
1482 DRM_ERROR("failed to initialize plane\n");
1483 goto err_cleanup_planes;
1486 plane = &vop_win->base;
1487 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1489 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1493 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1498 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1501 * Create drm_planes for overlay windows with possible_crtcs restricted
1502 * to the newly created crtc.
1504 for (i = 0; i < vop_data->win_size; i++) {
1505 struct vop_win *vop_win = &vop->win[i];
1506 const struct vop_win_data *win_data = vop_win->data;
1507 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1509 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1512 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1515 win_data->phy->data_formats,
1516 win_data->phy->nformats,
1519 DRM_ERROR("failed to initialize overlay plane\n");
1520 goto err_cleanup_crtc;
1524 port = of_get_child_by_name(dev->of_node, "port");
1526 DRM_ERROR("no port node found in %s\n",
1527 dev->of_node->full_name);
1528 goto err_cleanup_crtc;
1531 init_completion(&vop->dsp_hold_completion);
1533 vop->pipe = drm_crtc_index(crtc);
1534 rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1539 drm_crtc_cleanup(crtc);
1541 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1542 drm_plane_cleanup(plane);
1546 static void vop_destroy_crtc(struct vop *vop)
1548 struct drm_crtc *crtc = &vop->crtc;
1550 rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1551 of_node_put(crtc->port);
1552 drm_crtc_cleanup(crtc);
1555 static int vop_initial(struct vop *vop)
1557 const struct vop_data *vop_data = vop->data;
1558 const struct vop_reg_data *init_table = vop_data->init_table;
1559 struct reset_control *ahb_rst;
1562 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1563 if (IS_ERR(vop->hclk)) {
1564 dev_err(vop->dev, "failed to get hclk source\n");
1565 return PTR_ERR(vop->hclk);
1567 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1568 if (IS_ERR(vop->aclk)) {
1569 dev_err(vop->dev, "failed to get aclk source\n");
1570 return PTR_ERR(vop->aclk);
1572 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1573 if (IS_ERR(vop->dclk)) {
1574 dev_err(vop->dev, "failed to get dclk source\n");
1575 return PTR_ERR(vop->dclk);
1578 ret = clk_prepare(vop->hclk);
1580 dev_err(vop->dev, "failed to prepare hclk\n");
1584 ret = clk_prepare(vop->dclk);
1586 dev_err(vop->dev, "failed to prepare dclk\n");
1587 goto err_unprepare_hclk;
1590 ret = clk_prepare(vop->aclk);
1592 dev_err(vop->dev, "failed to prepare aclk\n");
1593 goto err_unprepare_dclk;
1597 * enable hclk, so that we can config vop register.
1599 ret = clk_enable(vop->hclk);
1601 dev_err(vop->dev, "failed to prepare aclk\n");
1602 goto err_unprepare_aclk;
1605 * do hclk_reset, reset all vop registers.
1607 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1608 if (IS_ERR(ahb_rst)) {
1609 dev_err(vop->dev, "failed to get ahb reset\n");
1610 ret = PTR_ERR(ahb_rst);
1611 goto err_disable_hclk;
1613 reset_control_assert(ahb_rst);
1614 usleep_range(10, 20);
1615 reset_control_deassert(ahb_rst);
1617 memcpy(vop->regsbak, vop->regs, vop->len);
1619 for (i = 0; i < vop_data->table_size; i++)
1620 vop_writel(vop, init_table[i].offset, init_table[i].value);
1622 for (i = 0; i < vop_data->win_size; i++) {
1623 const struct vop_win_data *win = &vop_data->win[i];
1625 VOP_WIN_SET(vop, win, enable, 0);
1631 * do dclk_reset, let all config take affect.
1633 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1634 if (IS_ERR(vop->dclk_rst)) {
1635 dev_err(vop->dev, "failed to get dclk reset\n");
1636 ret = PTR_ERR(vop->dclk_rst);
1637 goto err_unprepare_aclk;
1639 reset_control_assert(vop->dclk_rst);
1640 usleep_range(10, 20);
1641 reset_control_deassert(vop->dclk_rst);
1643 clk_disable(vop->hclk);
1645 vop->is_enabled = false;
1650 clk_disable(vop->hclk);
1652 clk_unprepare(vop->aclk);
1654 clk_unprepare(vop->dclk);
1656 clk_unprepare(vop->hclk);
1661 * Initialize the vop->win array elements.
1663 static void vop_win_init(struct vop *vop)
1665 const struct vop_data *vop_data = vop->data;
1668 for (i = 0; i < vop_data->win_size; i++) {
1669 struct vop_win *vop_win = &vop->win[i];
1670 const struct vop_win_data *win_data = &vop_data->win[i];
1672 vop_win->data = win_data;
1674 INIT_LIST_HEAD(&vop_win->pending);
1678 static int vop_bind(struct device *dev, struct device *master, void *data)
1680 struct platform_device *pdev = to_platform_device(dev);
1681 const struct of_device_id *of_id;
1682 const struct vop_data *vop_data;
1683 struct drm_device *drm_dev = data;
1685 struct resource *res;
1689 of_id = of_match_device(vop_driver_dt_match, dev);
1690 vop_data = of_id->data;
1694 /* Allocate vop struct and its vop_win array */
1695 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1696 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1701 vop->data = vop_data;
1702 vop->drm_dev = drm_dev;
1703 dev_set_drvdata(dev, vop);
1707 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1708 vop->len = resource_size(res);
1709 vop->regs = devm_ioremap_resource(dev, res);
1710 if (IS_ERR(vop->regs))
1711 return PTR_ERR(vop->regs);
1713 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1717 ret = vop_initial(vop);
1719 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1723 irq = platform_get_irq(pdev, 0);
1725 dev_err(dev, "cannot find irq for vop\n");
1728 vop->irq = (unsigned int)irq;
1730 spin_lock_init(&vop->reg_lock);
1731 spin_lock_init(&vop->irq_lock);
1733 mutex_init(&vop->vsync_mutex);
1735 ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1736 IRQF_SHARED, dev_name(dev), vop);
1740 /* IRQ is initially disabled; it gets enabled in power_on */
1741 disable_irq(vop->irq);
1743 ret = vop_create_crtc(vop);
1747 pm_runtime_enable(&pdev->dev);
1751 static void vop_unbind(struct device *dev, struct device *master, void *data)
1753 struct vop *vop = dev_get_drvdata(dev);
1755 pm_runtime_disable(dev);
1756 vop_destroy_crtc(vop);
1759 static const struct component_ops vop_component_ops = {
1761 .unbind = vop_unbind,
1764 static int vop_probe(struct platform_device *pdev)
1766 struct device *dev = &pdev->dev;
1768 if (!dev->of_node) {
1769 dev_err(dev, "can't find vop devices\n");
1773 return component_add(dev, &vop_component_ops);
1776 static int vop_remove(struct platform_device *pdev)
1778 component_del(&pdev->dev, &vop_component_ops);
1783 struct platform_driver vop_platform_driver = {
1785 .remove = vop_remove,
1787 .name = "rockchip-vop",
1788 .owner = THIS_MODULE,
1789 .of_match_table = of_match_ptr(vop_driver_dt_match),
1793 module_platform_driver(vop_platform_driver);
1795 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1796 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1797 MODULE_LICENSE("GPL v2");