drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34
  35 #include "rockchip_drm_drv.h"
  36 #include "rockchip_drm_gem.h"
  37 #include "rockchip_drm_fb.h"
  38 #include "rockchip_drm_vop.h"
  39
  40 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
  41                 vop_mask_write(x, off, mask, shift, v, write_mask, true)
  42
  43 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
  44                 vop_mask_write(x, off, mask, shift, v, write_mask, false)
  45
  46 #define REG_SET(x, off, reg, v, mode) \
  47                 __REG_SET_##mode(x, off + reg.offset, \
  48                                  reg.mask, reg.shift, v, reg.write_mask)
  49 #define REG_SET_MASK(x, off, reg, mask, v, mode) \
  50                 __REG_SET_##mode(x, off + reg.offset, \
  51                                  mask, reg.shift, v, reg.write_mask)
  52
  53 #define VOP_WIN_SET(x, win, name, v) \
  54                 REG_SET(x, win->offset, VOP_WIN_NAME(win, name), v, RELAXED)
  55 #define VOP_SCL_SET(x, win, name, v) \
  56                 REG_SET(x, win->offset, win->phy->scl->name, v, RELAXED)
  57 #define VOP_SCL_SET_EXT(x, win, name, v) \
  58                 REG_SET(x, win->offset, win->phy->scl->ext->name, v, RELAXED)
  59
  60 #define VOP_CTRL_SET(x, name, v) \
  61                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  62
  63 #define VOP_INTR_GET(vop, name) \
  64                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  65
  66 #define VOP_INTR_SET(vop, name, mask, v) \
  67                 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
  68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  69         do { \
  70                 int i, reg = 0, mask = 0; \
  71                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  72                         if (vop->data->intr->intrs[i] & type) { \
  73                                 reg |= (v) << i; \
  74                                 mask |= 1 << i; \
  75                         } \
  76                 } \
  77                 VOP_INTR_SET(vop, name, mask, reg); \
  78         } while (0)
  79 #define VOP_INTR_GET_TYPE(vop, name, type) \
  80                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  81
  82 #define VOP_WIN_GET(x, win, name) \
  83                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
  84
  85 #define VOP_WIN_NAME(win, name) \
  86                 (vop_get_win_phy(win, &win->phy->name)->name)
  87
  88 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  89                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
  90
  91 #define to_vop(x) container_of(x, struct vop, crtc)
  92 #define to_vop_win(x) container_of(x, struct vop_win, base)
  93 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
  94
  95 struct vop_zpos {
  96         int win_id;
  97         int zpos;
  98 };
  99
 100 struct vop_plane_state {
 101         struct drm_plane_state base;
 102         int format;
 103         int zpos;
 104         struct drm_rect src;
 105         struct drm_rect dest;
 106         dma_addr_t yrgb_mst;
 107         bool enable;
 108 };
 109
 110 struct vop_win {
 111         struct vop_win *parent;
 112         struct drm_plane base;
 113
 114         int win_id;
 115         int area_id;
 116         uint32_t offset;
 117         enum drm_plane_type type;
 118         const struct vop_win_phy *phy;
 119         const uint32_t *data_formats;
 120         uint32_t nformats;
 121         struct vop *vop;
 122
 123         struct vop_plane_state state;
 124 };
 125
 126 struct vop {
 127         struct drm_crtc crtc;
 128         struct device *dev;
 129         struct drm_device *drm_dev;
 130         struct drm_property *plane_zpos_prop;
 131         bool is_enabled;
 132
 133         /* mutex vsync_ work */
 134         struct mutex vsync_mutex;
 135         bool vsync_work_pending;
 136         struct completion dsp_hold_completion;
 137         struct completion wait_update_complete;
 138         struct drm_pending_vblank_event *event;
 139
 140         const struct vop_data *data;
 141         int num_wins;
 142
 143         uint32_t *regsbak;
 144         void __iomem *regs;
 145
 146         /* physical map length of vop register */
 147         uint32_t len;
 148
 149         /* one time only one process allowed to config the register */
 150         spinlock_t reg_lock;
 151         /* lock vop irq reg */
 152         spinlock_t irq_lock;
 153
 154         unsigned int irq;
 155
 156         /* vop AHP clk */
 157         struct clk *hclk;
 158         /* vop dclk */
 159         struct clk *dclk;
 160         /* vop share memory frequency */
 161         struct clk *aclk;
 162
 163         /* vop dclk reset */
 164         struct reset_control *dclk_rst;
 165
 166         struct vop_win win[];
 167 };
 168
 169 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 170 {
 171         writel(v, vop->regs + offset);
 172         vop->regsbak[offset >> 2] = v;
 173 }
 174
 175 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 176 {
 177         return readl(vop->regs + offset);
 178 }
 179
 180 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 181                                     const struct vop_reg *reg)
 182 {
 183         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 184 }
 185
 186 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 187                                   uint32_t mask, uint32_t shift, uint32_t v,
 188                                   bool write_mask, bool relaxed)
 189 {
 190         if (!mask)
 191                 return;
 192
 193         if (write_mask) {
 194                 v = (v << shift) | (mask << (shift + 16));
 195         } else {
 196                 uint32_t cached_val = vop->regsbak[offset >> 2];
 197
 198                 v = (cached_val & ~(mask << shift)) | (v << shift);
 199                 vop->regsbak[offset >> 2] = v;
 200         }
 201
 202         if (relaxed)
 203                 writel_relaxed(v, vop->regs + offset);
 204         else
 205                 writel(v, vop->regs + offset);
 206 }
 207
 208 static inline const struct vop_win_phy *
 209 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 210 {
 211         if (!reg->mask && win->parent)
 212                 return win->parent->phy;
 213
 214         return win->phy;
 215 }
 216
 217 static inline uint32_t vop_get_intr_type(struct vop *vop,
 218                                          const struct vop_reg *reg, int type)
 219 {
 220         uint32_t i, ret = 0;
 221         uint32_t regs = vop_read_reg(vop, 0, reg);
 222
 223         for (i = 0; i < vop->data->intr->nintrs; i++) {
 224                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 225                         ret |= vop->data->intr->intrs[i];
 226         }
 227
 228         return ret;
 229 }
 230
 231 static inline void vop_cfg_done(struct vop *vop)
 232 {
 233         VOP_CTRL_SET(vop, cfg_done, 1);
 234 }
 235
 236 static bool has_rb_swapped(uint32_t format)
 237 {
 238         switch (format) {
 239         case DRM_FORMAT_XBGR8888:
 240         case DRM_FORMAT_ABGR8888:
 241         case DRM_FORMAT_BGR888:
 242         case DRM_FORMAT_BGR565:
 243                 return true;
 244         default:
 245                 return false;
 246         }
 247 }
 248
 249 static enum vop_data_format vop_convert_format(uint32_t format)
 250 {
 251         switch (format) {
 252         case DRM_FORMAT_XRGB8888:
 253         case DRM_FORMAT_ARGB8888:
 254         case DRM_FORMAT_XBGR8888:
 255         case DRM_FORMAT_ABGR8888:
 256                 return VOP_FMT_ARGB8888;
 257         case DRM_FORMAT_RGB888:
 258         case DRM_FORMAT_BGR888:
 259                 return VOP_FMT_RGB888;
 260         case DRM_FORMAT_RGB565:
 261         case DRM_FORMAT_BGR565:
 262                 return VOP_FMT_RGB565;
 263         case DRM_FORMAT_NV12:
 264                 return VOP_FMT_YUV420SP;
 265         case DRM_FORMAT_NV16:
 266                 return VOP_FMT_YUV422SP;
 267         case DRM_FORMAT_NV24:
 268                 return VOP_FMT_YUV444SP;
 269         default:
 270                 DRM_ERROR("unsupport format[%08x]\n", format);
 271                 return -EINVAL;
 272         }
 273 }
 274
 275 static bool is_yuv_support(uint32_t format)
 276 {
 277         switch (format) {
 278         case DRM_FORMAT_NV12:
 279         case DRM_FORMAT_NV16:
 280         case DRM_FORMAT_NV24:
 281                 return true;
 282         default:
 283                 return false;
 284         }
 285 }
 286
 287 static bool is_alpha_support(uint32_t format)
 288 {
 289         switch (format) {
 290         case DRM_FORMAT_ARGB8888:
 291         case DRM_FORMAT_ABGR8888:
 292                 return true;
 293         default:
 294                 return false;
 295         }
 296 }
 297
 298 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 299                                   uint32_t dst, bool is_horizontal,
 300                                   int vsu_mode, int *vskiplines)
 301 {
 302         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 303
 304         if (is_horizontal) {
 305                 if (mode == SCALE_UP)
 306                         val = GET_SCL_FT_BIC(src, dst);
 307                 else if (mode == SCALE_DOWN)
 308                         val = GET_SCL_FT_BILI_DN(src, dst);
 309         } else {
 310                 if (mode == SCALE_UP) {
 311                         if (vsu_mode == SCALE_UP_BIL)
 312                                 val = GET_SCL_FT_BILI_UP(src, dst);
 313                         else
 314                                 val = GET_SCL_FT_BIC(src, dst);
 315                 } else if (mode == SCALE_DOWN) {
 316                         if (vskiplines) {
 317                                 *vskiplines = scl_get_vskiplines(src, dst);
 318                                 val = scl_get_bili_dn_vskip(src, dst,
 319                                                             *vskiplines);
 320                         } else {
 321                                 val = GET_SCL_FT_BILI_DN(src, dst);
 322                         }
 323                 }
 324         }
 325
 326         return val;
 327 }
 328
 329 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 330                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 331                                 uint32_t dst_h, uint32_t pixel_format)
 332 {
 333         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 334         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 335         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 336         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 337         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 338         bool is_yuv = is_yuv_support(pixel_format);
 339         uint16_t cbcr_src_w = src_w / hsub;
 340         uint16_t cbcr_src_h = src_h / vsub;
 341         uint16_t vsu_mode;
 342         uint16_t lb_mode;
 343         uint32_t val;
 344         int vskiplines;
 345
 346         if (!win->phy->scl)
 347                 return;
 348
 349         if (dst_w > 3840) {
 350                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 351                 return;
 352         }
 353
 354         if (!win->phy->scl->ext) {
 355                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 356                             scl_cal_scale2(src_w, dst_w));
 357                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 358                             scl_cal_scale2(src_h, dst_h));
 359                 if (is_yuv) {
 360                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 361                                     scl_cal_scale2(src_w, dst_w));
 362                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 363                                     scl_cal_scale2(src_h, dst_h));
 364                 }
 365                 return;
 366         }
 367
 368         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 369         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 370
 371         if (is_yuv) {
 372                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 373                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 374                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 375                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 376                 else
 377                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 378         } else {
 379                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 380                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 381                 else
 382                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 383         }
 384
 385         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 386         if (lb_mode == LB_RGB_3840X2) {
 387                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 388                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 389                         return;
 390                 }
 391                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 392                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 393                         return;
 394                 }
 395                 vsu_mode = SCALE_UP_BIL;
 396         } else if (lb_mode == LB_RGB_2560X4) {
 397                 vsu_mode = SCALE_UP_BIL;
 398         } else {
 399                 vsu_mode = SCALE_UP_BIC;
 400         }
 401
 402         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 403                                 true, 0, NULL);
 404         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 405         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 406                                 false, vsu_mode, &vskiplines);
 407         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 408
 409         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 410         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 411
 412         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 413         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 414         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 415         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 416         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 417         if (is_yuv) {
 418                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 419                                         dst_w, true, 0, NULL);
 420                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 421                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 422                                         dst_h, false, vsu_mode, &vskiplines);
 423                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 424
 425                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 426                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 427                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 428                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 429                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 430                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 431                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 432         }
 433 }
 434
 435 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 436 {
 437         unsigned long flags;
 438
 439         if (WARN_ON(!vop->is_enabled))
 440                 return;
 441
 442         spin_lock_irqsave(&vop->irq_lock, flags);
 443
 444         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 445
 446         spin_unlock_irqrestore(&vop->irq_lock, flags);
 447 }
 448
 449 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 450 {
 451         unsigned long flags;
 452
 453         if (WARN_ON(!vop->is_enabled))
 454                 return;
 455
 456         spin_lock_irqsave(&vop->irq_lock, flags);
 457
 458         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 459
 460         spin_unlock_irqrestore(&vop->irq_lock, flags);
 461 }
 462
 463 static void vop_enable(struct drm_crtc *crtc)
 464 {
 465         struct vop *vop = to_vop(crtc);
 466         int ret;
 467
 468         if (vop->is_enabled)
 469                 return;
 470
 471         ret = pm_runtime_get_sync(vop->dev);
 472         if (ret < 0) {
 473                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 474                 return;
 475         }
 476
 477         ret = clk_enable(vop->hclk);
 478         if (ret < 0) {
 479                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 480                 return;
 481         }
 482
 483         ret = clk_enable(vop->dclk);
 484         if (ret < 0) {
 485                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 486                 goto err_disable_hclk;
 487         }
 488
 489         ret = clk_enable(vop->aclk);
 490         if (ret < 0) {
 491                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 492                 goto err_disable_dclk;
 493         }
 494
 495         /*
 496          * Slave iommu shares power, irq and clock with vop.  It was associated
 497          * automatically with this master device via common driver code.
 498          * Now that we have enabled the clock we attach it to the shared drm
 499          * mapping.
 500          */
 501         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 502         if (ret) {
 503                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 504                 goto err_disable_aclk;
 505         }
 506
 507         memcpy(vop->regs, vop->regsbak, vop->len);
 508         /*
 509          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 510          */
 511         vop->is_enabled = true;
 512
 513         spin_lock(&vop->reg_lock);
 514
 515         VOP_CTRL_SET(vop, standby, 0);
 516
 517         spin_unlock(&vop->reg_lock);
 518
 519         enable_irq(vop->irq);
 520
 521         drm_crtc_vblank_on(crtc);
 522
 523         return;
 524
 525 err_disable_aclk:
 526         clk_disable(vop->aclk);
 527 err_disable_dclk:
 528         clk_disable(vop->dclk);
 529 err_disable_hclk:
 530         clk_disable(vop->hclk);
 531 }
 532
 533 static void vop_crtc_disable(struct drm_crtc *crtc)
 534 {
 535         struct vop *vop = to_vop(crtc);
 536         int i;
 537
 538         if (!vop->is_enabled)
 539                 return;
 540
 541         /*
 542          * We need to make sure that all windows are disabled before we
 543          * disable that crtc. Otherwise we might try to scan from a destroyed
 544          * buffer later.
 545          */
 546         for (i = 0; i < vop->num_wins; i++) {
 547                 struct vop_win *win = &vop->win[i];
 548
 549                 spin_lock(&vop->reg_lock);
 550                 VOP_WIN_SET(vop, win, enable, 0);
 551                 spin_unlock(&vop->reg_lock);
 552         }
 553
 554         drm_crtc_vblank_off(crtc);
 555
 556         /*
 557          * Vop standby will take effect at end of current frame,
 558          * if dsp hold valid irq happen, it means standby complete.
 559          *
 560          * we must wait standby complete when we want to disable aclk,
 561          * if not, memory bus maybe dead.
 562          */
 563         reinit_completion(&vop->dsp_hold_completion);
 564         vop_dsp_hold_valid_irq_enable(vop);
 565
 566         spin_lock(&vop->reg_lock);
 567
 568         VOP_CTRL_SET(vop, standby, 1);
 569
 570         spin_unlock(&vop->reg_lock);
 571
 572         wait_for_completion(&vop->dsp_hold_completion);
 573
 574         vop_dsp_hold_valid_irq_disable(vop);
 575
 576         disable_irq(vop->irq);
 577
 578         vop->is_enabled = false;
 579
 580         /*
 581          * vop standby complete, so iommu detach is safe.
 582          */
 583         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 584
 585         clk_disable(vop->dclk);
 586         clk_disable(vop->aclk);
 587         clk_disable(vop->hclk);
 588         pm_runtime_put(vop->dev);
 589 }
 590
 591 static void vop_plane_destroy(struct drm_plane *plane)
 592 {
 593         drm_plane_cleanup(plane);
 594 }
 595
 596 static int vop_plane_atomic_check(struct drm_plane *plane,
 597                            struct drm_plane_state *state)
 598 {
 599         struct drm_crtc *crtc = state->crtc;
 600         struct drm_framebuffer *fb = state->fb;
 601         struct vop_win *win = to_vop_win(plane);
 602         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 603         bool visible;
 604         int ret;
 605         struct drm_rect *dest = &vop_plane_state->dest;
 606         struct drm_rect *src = &vop_plane_state->src;
 607         struct drm_rect clip;
 608         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 609                                         DRM_PLANE_HELPER_NO_SCALING;
 610         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 611                                         DRM_PLANE_HELPER_NO_SCALING;
 612
 613         crtc = crtc ? crtc : plane->state->crtc;
 614         /*
 615          * Both crtc or plane->state->crtc can be null.
 616          */
 617         if (!crtc || !fb)
 618                 goto out_disable;
 619         src->x1 = state->src_x;
 620         src->y1 = state->src_y;
 621         src->x2 = state->src_x + state->src_w;
 622         src->y2 = state->src_y + state->src_h;
 623         dest->x1 = state->crtc_x;
 624         dest->y1 = state->crtc_y;
 625         dest->x2 = state->crtc_x + state->crtc_w;
 626         dest->y2 = state->crtc_y + state->crtc_h;
 627
 628         clip.x1 = 0;
 629         clip.y1 = 0;
 630         clip.x2 = crtc->mode.hdisplay;
 631         clip.y2 = crtc->mode.vdisplay;
 632
 633         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 634                                             src, dest, &clip,
 635                                             min_scale,
 636                                             max_scale,
 637                                             true, true, &visible);
 638         if (ret)
 639                 return ret;
 640
 641         if (!visible)
 642                 goto out_disable;
 643
 644         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 645         if (vop_plane_state->format < 0)
 646                 return vop_plane_state->format;
 647
 648         /*
 649          * Src.x1 can be odd when do clip, but yuv plane start point
 650          * need align with 2 pixel.
 651          */
 652         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 653                 return -EINVAL;
 654
 655         vop_plane_state->enable = true;
 656
 657         return 0;
 658
 659 out_disable:
 660         vop_plane_state->enable = false;
 661         return 0;
 662 }
 663
 664 static void vop_plane_atomic_disable(struct drm_plane *plane,
 665                                      struct drm_plane_state *old_state)
 666 {
 667         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 668         struct vop_win *win = to_vop_win(plane);
 669         struct vop *vop = to_vop(old_state->crtc);
 670
 671         if (!old_state->crtc)
 672                 return;
 673
 674         spin_lock(&vop->reg_lock);
 675
 676         VOP_WIN_SET(vop, win, enable, 0);
 677
 678         spin_unlock(&vop->reg_lock);
 679
 680         vop_plane_state->enable = false;
 681 }
 682
 683 static void vop_plane_atomic_update(struct drm_plane *plane,
 684                 struct drm_plane_state *old_state)
 685 {
 686         struct drm_plane_state *state = plane->state;
 687         struct drm_crtc *crtc = state->crtc;
 688         struct vop_win *win = to_vop_win(plane);
 689         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 690         struct vop *vop = to_vop(state->crtc);
 691         struct drm_framebuffer *fb = state->fb;
 692         unsigned int actual_w, actual_h;
 693         unsigned int dsp_stx, dsp_sty;
 694         uint32_t act_info, dsp_info, dsp_st;
 695         struct drm_rect *src = &vop_plane_state->src;
 696         struct drm_rect *dest = &vop_plane_state->dest;
 697         struct drm_gem_object *obj, *uv_obj;
 698         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 699         unsigned long offset;
 700         dma_addr_t dma_addr;
 701         uint32_t val;
 702         bool rb_swap;
 703
 704         /*
 705          * can't update plane when vop is disabled.
 706          */
 707         if (!crtc)
 708                 return;
 709
 710         if (WARN_ON(!vop->is_enabled))
 711                 return;
 712
 713         if (!vop_plane_state->enable) {
 714                 vop_plane_atomic_disable(plane, old_state);
 715                 return;
 716         }
 717
 718         obj = rockchip_fb_get_gem_obj(fb, 0);
 719         rk_obj = to_rockchip_obj(obj);
 720
 721         actual_w = drm_rect_width(src) >> 16;
 722         actual_h = drm_rect_height(src) >> 16;
 723         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 724
 725         dsp_info = (drm_rect_height(dest) - 1) << 16;
 726         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 727
 728         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 729         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 730         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 731
 732         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 733         offset += (src->y1 >> 16) * fb->pitches[0];
 734         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 735
 736         spin_lock(&vop->reg_lock);
 737
 738         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 739         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 740         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 741         if (is_yuv_support(fb->pixel_format)) {
 742                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 743                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 744                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 745
 746                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 747                 rk_uv_obj = to_rockchip_obj(uv_obj);
 748
 749                 offset = (src->x1 >> 16) * bpp / hsub;
 750                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 751
 752                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 753                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 754                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 755         }
 756
 757         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 758                             drm_rect_width(dest), drm_rect_height(dest),
 759                             fb->pixel_format);
 760
 761         VOP_WIN_SET(vop, win, act_info, act_info);
 762         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 763         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 764
 765         rb_swap = has_rb_swapped(fb->pixel_format);
 766         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 767
 768         if (is_alpha_support(fb->pixel_format)) {
 769                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 770                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 771                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 772                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 773                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 774                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 775                         SRC_FACTOR_M0(ALPHA_ONE);
 776                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 777         } else {
 778                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 779         }
 780
 781         VOP_WIN_SET(vop, win, enable, 1);
 782         spin_unlock(&vop->reg_lock);
 783 }
 784
 785 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 786         .atomic_check = vop_plane_atomic_check,
 787         .atomic_update = vop_plane_atomic_update,
 788         .atomic_disable = vop_plane_atomic_disable,
 789 };
 790
 791 void vop_atomic_plane_reset(struct drm_plane *plane)
 792 {
 793         struct vop_win *win = to_vop_win(plane);
 794         struct vop_plane_state *vop_plane_state =
 795                                         to_vop_plane_state(plane->state);
 796
 797         if (plane->state && plane->state->fb)
 798                 drm_framebuffer_unreference(plane->state->fb);
 799
 800         kfree(vop_plane_state);
 801         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 802         if (!vop_plane_state)
 803                 return;
 804
 805         vop_plane_state->zpos = win->win_id;
 806         plane->state = &vop_plane_state->base;
 807         plane->state->plane = plane;
 808 }
 809
 810 struct drm_plane_state *
 811 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 812 {
 813         struct vop_plane_state *old_vop_plane_state;
 814         struct vop_plane_state *vop_plane_state;
 815
 816         if (WARN_ON(!plane->state))
 817                 return NULL;
 818
 819         old_vop_plane_state = to_vop_plane_state(plane->state);
 820         vop_plane_state = kmemdup(old_vop_plane_state,
 821                                   sizeof(*vop_plane_state), GFP_KERNEL);
 822         if (!vop_plane_state)
 823                 return NULL;
 824
 825         __drm_atomic_helper_plane_duplicate_state(plane,
 826                                                   &vop_plane_state->base);
 827
 828         return &vop_plane_state->base;
 829 }
 830
 831 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 832                                            struct drm_plane_state *state)
 833 {
 834         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 835
 836         __drm_atomic_helper_plane_destroy_state(plane, state);
 837
 838         kfree(vop_state);
 839 }
 840
 841 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 842                                          struct drm_plane_state *state,
 843                                          struct drm_property *property,
 844                                          uint64_t val)
 845 {
 846         struct vop_win *win = to_vop_win(plane);
 847         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 848
 849         if (property == win->vop->plane_zpos_prop) {
 850                 plane_state->zpos = val;
 851                 return 0;
 852         }
 853
 854         DRM_ERROR("failed to set vop plane property\n");
 855         return -EINVAL;
 856 }
 857
 858 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 859                                          const struct drm_plane_state *state,
 860                                          struct drm_property *property,
 861                                          uint64_t *val)
 862 {
 863         struct vop_win *win = to_vop_win(plane);
 864         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 865
 866         if (property == win->vop->plane_zpos_prop) {
 867                 *val = plane_state->zpos;
 868                 return 0;
 869         }
 870
 871         DRM_ERROR("failed to get vop plane property\n");
 872         return -EINVAL;
 873 }
 874
 875 static const struct drm_plane_funcs vop_plane_funcs = {
 876         .update_plane   = drm_atomic_helper_update_plane,
 877         .disable_plane  = drm_atomic_helper_disable_plane,
 878         .destroy = vop_plane_destroy,
 879         .reset = vop_atomic_plane_reset,
 880         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 881         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 882         .atomic_set_property = vop_atomic_plane_set_property,
 883         .atomic_get_property = vop_atomic_plane_get_property,
 884 };
 885
 886 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 887 {
 888         struct vop *vop = to_vop(crtc);
 889         unsigned long flags;
 890
 891         if (WARN_ON(!vop->is_enabled))
 892                 return -EPERM;
 893
 894         spin_lock_irqsave(&vop->irq_lock, flags);
 895
 896         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 897
 898         spin_unlock_irqrestore(&vop->irq_lock, flags);
 899
 900         return 0;
 901 }
 902
 903 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 904 {
 905         struct vop *vop = to_vop(crtc);
 906         unsigned long flags;
 907
 908         if (WARN_ON(!vop->is_enabled))
 909                 return;
 910
 911         spin_lock_irqsave(&vop->irq_lock, flags);
 912
 913         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 914
 915         spin_unlock_irqrestore(&vop->irq_lock, flags);
 916 }
 917
 918 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 919 {
 920         struct vop *vop = to_vop(crtc);
 921
 922         reinit_completion(&vop->wait_update_complete);
 923         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
 924 }
 925
 926 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
 927                                            struct drm_file *file_priv)
 928 {
 929         struct drm_device *drm = crtc->dev;
 930         struct vop *vop = to_vop(crtc);
 931         struct drm_pending_vblank_event *e;
 932         unsigned long flags;
 933
 934         spin_lock_irqsave(&drm->event_lock, flags);
 935         e = vop->event;
 936         if (e && e->base.file_priv == file_priv) {
 937                 vop->event = NULL;
 938
 939                 e->base.destroy(&e->base);
 940                 file_priv->event_space += sizeof(e->event);
 941         }
 942         spin_unlock_irqrestore(&drm->event_lock, flags);
 943 }
 944
 945 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 946         .enable_vblank = vop_crtc_enable_vblank,
 947         .disable_vblank = vop_crtc_disable_vblank,
 948         .wait_for_update = vop_crtc_wait_for_update,
 949         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
 950 };
 951
 952 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 953                                 const struct drm_display_mode *mode,
 954                                 struct drm_display_mode *adjusted_mode)
 955 {
 956         struct vop *vop = to_vop(crtc);
 957
 958         adjusted_mode->clock =
 959                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
 960
 961         return true;
 962 }
 963
 964 static void vop_crtc_enable(struct drm_crtc *crtc)
 965 {
 966         struct vop *vop = to_vop(crtc);
 967         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 968         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 969         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 970         u16 hdisplay = adjusted_mode->hdisplay;
 971         u16 htotal = adjusted_mode->htotal;
 972         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 973         u16 hact_end = hact_st + hdisplay;
 974         u16 vdisplay = adjusted_mode->vdisplay;
 975         u16 vtotal = adjusted_mode->vtotal;
 976         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 977         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 978         u16 vact_end = vact_st + vdisplay;
 979         uint32_t val;
 980
 981         vop_enable(crtc);
 982         /*
 983          * If dclk rate is zero, mean that scanout is stop,
 984          * we don't need wait any more.
 985          */
 986         if (clk_get_rate(vop->dclk)) {
 987                 /*
 988                  * Rk3288 vop timing register is immediately, when configure
 989                  * display timing on display time, may cause tearing.
 990                  *
 991                  * Vop standby will take effect at end of current frame,
 992                  * if dsp hold valid irq happen, it means standby complete.
 993                  *
 994                  * mode set:
 995                  *    standby and wait complete --> |----
 996                  *                                  | display time
 997                  *                                  |----
 998                  *                                  |---> dsp hold irq
 999                  *     configure display timing --> |
1000                  *         standby exit             |
1001                  *                                  | new frame start.
1002                  */
1003
1004                 reinit_completion(&vop->dsp_hold_completion);
1005                 vop_dsp_hold_valid_irq_enable(vop);
1006
1007                 spin_lock(&vop->reg_lock);
1008
1009                 VOP_CTRL_SET(vop, standby, 1);
1010
1011                 spin_unlock(&vop->reg_lock);
1012
1013                 wait_for_completion(&vop->dsp_hold_completion);
1014
1015                 vop_dsp_hold_valid_irq_disable(vop);
1016         }
1017
1018         val = 0x8;
1019         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1020         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1021         VOP_CTRL_SET(vop, pin_pol, val);
1022         switch (s->output_type) {
1023         case DRM_MODE_CONNECTOR_LVDS:
1024                 VOP_CTRL_SET(vop, rgb_en, 1);
1025                 break;
1026         case DRM_MODE_CONNECTOR_eDP:
1027                 VOP_CTRL_SET(vop, edp_en, 1);
1028                 break;
1029         case DRM_MODE_CONNECTOR_HDMIA:
1030                 VOP_CTRL_SET(vop, hdmi_en, 1);
1031                 break;
1032         case DRM_MODE_CONNECTOR_DSI:
1033                 VOP_CTRL_SET(vop, mipi_en, 1);
1034                 break;
1035         default:
1036                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1037         }
1038         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1039
1040         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1041         val = hact_st << 16;
1042         val |= hact_end;
1043         VOP_CTRL_SET(vop, hact_st_end, val);
1044         VOP_CTRL_SET(vop, hpost_st_end, val);
1045
1046         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1047         val = vact_st << 16;
1048         val |= vact_end;
1049         VOP_CTRL_SET(vop, vact_st_end, val);
1050         VOP_CTRL_SET(vop, vpost_st_end, val);
1051
1052         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1053
1054         VOP_CTRL_SET(vop, standby, 0);
1055 }
1056
1057 static int vop_zpos_cmp(const void *a, const void *b)
1058 {
1059         struct vop_zpos *pa = (struct vop_zpos *)a;
1060         struct vop_zpos *pb = (struct vop_zpos *)b;
1061
1062         return pb->zpos - pa->zpos;
1063 }
1064
1065 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1066                                  struct drm_crtc_state *state)
1067 {
1068         struct drm_device *dev = crtc->dev;
1069         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1070         struct vop *vop = to_vop(crtc);
1071         struct drm_plane *plane;
1072         struct vop_zpos *pzpos;
1073         int dsp_layer_sel = 0;
1074         int i, cnt = 0, ret = 0;
1075
1076         pzpos = kmalloc_array(vop->num_wins, sizeof(*pzpos), GFP_KERNEL);
1077         if (!pzpos)
1078                 return -ENOMEM;
1079
1080         drm_atomic_crtc_state_for_each_plane(plane, state) {
1081                 struct drm_plane_state *pstate;
1082                 struct vop_plane_state *plane_state;
1083                 struct vop_win *win = to_vop_win(plane);
1084
1085                 if (plane->parent)
1086                         continue;
1087                 if (cnt >= vop->num_wins) {
1088                         dev_err(dev->dev, "too many planes!\n");
1089                         ret = -EINVAL;
1090                         goto err_free_pzpos;
1091                 }
1092                 pstate = state->state->plane_states[drm_plane_index(plane)];
1093
1094                 /*
1095                  * plane might not have changed, in which case take
1096                  * current state:
1097                  */
1098                 if (!pstate)
1099                         pstate = plane->state;
1100                 plane_state = to_vop_plane_state(pstate);
1101                 pzpos[cnt].zpos = plane_state->zpos;
1102                 pzpos[cnt].win_id = win->win_id;
1103
1104                 cnt++;
1105         }
1106
1107         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1108
1109         for (i = 0; i < cnt; i++) {
1110                 struct vop_zpos *zpos = &pzpos[i];
1111
1112                 dsp_layer_sel <<= 2;
1113                 dsp_layer_sel |= zpos->win_id;
1114         }
1115
1116         s->dsp_layer_sel = dsp_layer_sel;
1117
1118 err_free_pzpos:
1119         kfree(pzpos);
1120         return ret;
1121 }
1122
1123 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1124                                   struct drm_crtc_state *old_crtc_state)
1125 {
1126         struct rockchip_crtc_state *s =
1127                         to_rockchip_crtc_state(crtc->state);
1128         struct vop *vop = to_vop(crtc);
1129
1130         if (WARN_ON(!vop->is_enabled))
1131                 return;
1132
1133         spin_lock(&vop->reg_lock);
1134
1135         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1136         vop_cfg_done(vop);
1137
1138         spin_unlock(&vop->reg_lock);
1139 }
1140
1141 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1142                                   struct drm_crtc_state *old_crtc_state)
1143 {
1144         struct vop *vop = to_vop(crtc);
1145
1146         if (crtc->state->event) {
1147                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1148
1149                 vop->event = crtc->state->event;
1150                 crtc->state->event = NULL;
1151         }
1152 }
1153
1154 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1155         .enable = vop_crtc_enable,
1156         .disable = vop_crtc_disable,
1157         .mode_fixup = vop_crtc_mode_fixup,
1158         .atomic_check = vop_crtc_atomic_check,
1159         .atomic_flush = vop_crtc_atomic_flush,
1160         .atomic_begin = vop_crtc_atomic_begin,
1161 };
1162
1163 static void vop_crtc_destroy(struct drm_crtc *crtc)
1164 {
1165         drm_crtc_cleanup(crtc);
1166 }
1167
1168 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1169 {
1170         struct rockchip_crtc_state *rockchip_state;
1171
1172         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1173         if (!rockchip_state)
1174                 return NULL;
1175
1176         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1177         return &rockchip_state->base;
1178 }
1179
1180 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1181                                    struct drm_crtc_state *state)
1182 {
1183         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1184
1185         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1186         kfree(s);
1187 }
1188
1189 static const struct drm_crtc_funcs vop_crtc_funcs = {
1190         .set_config = drm_atomic_helper_set_config,
1191         .page_flip = drm_atomic_helper_page_flip,
1192         .destroy = vop_crtc_destroy,
1193         .reset = drm_atomic_helper_crtc_reset,
1194         .atomic_duplicate_state = vop_crtc_duplicate_state,
1195         .atomic_destroy_state = vop_crtc_destroy_state,
1196 };
1197
1198 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1199 {
1200         struct drm_plane *plane = &vop_win->base;
1201         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1202         dma_addr_t yrgb_mst;
1203
1204         if (!state->enable)
1205                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1206
1207         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1208
1209         return yrgb_mst == state->yrgb_mst;
1210 }
1211
1212 static void vop_handle_vblank(struct vop *vop)
1213 {
1214         struct drm_device *drm = vop->drm_dev;
1215         struct drm_crtc *crtc = &vop->crtc;
1216         unsigned long flags;
1217         int i;
1218
1219         for (i = 0; i < vop->num_wins; i++) {
1220                 if (!vop_win_pending_is_complete(&vop->win[i]))
1221                         return;
1222         }
1223
1224         if (vop->event) {
1225                 spin_lock_irqsave(&drm->event_lock, flags);
1226
1227                 drm_crtc_send_vblank_event(crtc, vop->event);
1228                 drm_crtc_vblank_put(crtc);
1229                 vop->event = NULL;
1230
1231                 spin_unlock_irqrestore(&drm->event_lock, flags);
1232         }
1233         if (!completion_done(&vop->wait_update_complete))
1234                 complete(&vop->wait_update_complete);
1235 }
1236
1237 static irqreturn_t vop_isr(int irq, void *data)
1238 {
1239         struct vop *vop = data;
1240         struct drm_crtc *crtc = &vop->crtc;
1241         uint32_t active_irqs;
1242         unsigned long flags;
1243         int ret = IRQ_NONE;
1244
1245         /*
1246          * interrupt register has interrupt status, enable and clear bits, we
1247          * must hold irq_lock to avoid a race with enable/disable_vblank().
1248         */
1249         spin_lock_irqsave(&vop->irq_lock, flags);
1250
1251         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1252         /* Clear all active interrupt sources */
1253         if (active_irqs)
1254                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1255
1256         spin_unlock_irqrestore(&vop->irq_lock, flags);
1257
1258         /* This is expected for vop iommu irqs, since the irq is shared */
1259         if (!active_irqs)
1260                 return IRQ_NONE;
1261
1262         if (active_irqs & DSP_HOLD_VALID_INTR) {
1263                 complete(&vop->dsp_hold_completion);
1264                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1265                 ret = IRQ_HANDLED;
1266         }
1267
1268         if (active_irqs & FS_INTR) {
1269                 drm_crtc_handle_vblank(crtc);
1270                 vop_handle_vblank(vop);
1271                 active_irqs &= ~FS_INTR;
1272                 ret = IRQ_HANDLED;
1273         }
1274
1275         /* Unhandled irqs are spurious. */
1276         if (active_irqs)
1277                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1278
1279         return ret;
1280 }
1281
1282 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1283                           unsigned long possible_crtcs)
1284 {
1285         struct drm_plane *share = NULL;
1286         int ret;
1287
1288         if (win->parent)
1289                 share = &win->parent->base;
1290
1291         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1292                                    possible_crtcs, &vop_plane_funcs,
1293                                    win->data_formats, win->nformats, win->type);
1294         if (ret) {
1295                 DRM_ERROR("failed to initialize plane\n");
1296                 return ret;
1297         }
1298         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1299         drm_object_attach_property(&win->base.base,
1300                                    vop->plane_zpos_prop, win->win_id);
1301         return 0;
1302 }
1303
1304 static int vop_create_crtc(struct vop *vop)
1305 {
1306         struct device *dev = vop->dev;
1307         struct drm_device *drm_dev = vop->drm_dev;
1308         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1309         struct drm_crtc *crtc = &vop->crtc;
1310         struct device_node *port;
1311         int ret;
1312         int i;
1313
1314         /*
1315          * Create drm_plane for primary and cursor planes first, since we need
1316          * to pass them to drm_crtc_init_with_planes, which sets the
1317          * "possible_crtcs" to the newly initialized crtc.
1318          */
1319         for (i = 0; i < vop->num_wins; i++) {
1320                 struct vop_win *win = &vop->win[i];
1321
1322                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1323                     win->type != DRM_PLANE_TYPE_CURSOR)
1324                         continue;
1325
1326                 if (vop_plane_init(vop, win, 0))
1327                         goto err_cleanup_planes;
1328
1329                 plane = &win->base;
1330                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1331                         primary = plane;
1332                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1333                         cursor = plane;
1334
1335         }
1336
1337         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1338                                         &vop_crtc_funcs, NULL);
1339         if (ret)
1340                 goto err_cleanup_planes;
1341
1342         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1343
1344         /*
1345          * Create drm_planes for overlay windows with possible_crtcs restricted
1346          * to the newly created crtc.
1347          */
1348         for (i = 0; i < vop->num_wins; i++) {
1349                 struct vop_win *win = &vop->win[i];
1350                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1351
1352                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1353                         continue;
1354
1355                 if (vop_plane_init(vop, win, possible_crtcs))
1356                         goto err_cleanup_crtc;
1357         }
1358
1359         port = of_get_child_by_name(dev->of_node, "port");
1360         if (!port) {
1361                 DRM_ERROR("no port node found in %s\n",
1362                           dev->of_node->full_name);
1363                 ret = -ENOENT;
1364                 goto err_cleanup_crtc;
1365         }
1366
1367         init_completion(&vop->dsp_hold_completion);
1368         init_completion(&vop->wait_update_complete);
1369         crtc->port = port;
1370         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1371
1372         return 0;
1373
1374 err_cleanup_crtc:
1375         drm_crtc_cleanup(crtc);
1376 err_cleanup_planes:
1377         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1378                                  head)
1379                 drm_plane_cleanup(plane);
1380         return ret;
1381 }
1382
1383 static void vop_destroy_crtc(struct vop *vop)
1384 {
1385         struct drm_crtc *crtc = &vop->crtc;
1386         struct drm_device *drm_dev = vop->drm_dev;
1387         struct drm_plane *plane, *tmp;
1388
1389         rockchip_unregister_crtc_funcs(crtc);
1390         of_node_put(crtc->port);
1391
1392         /*
1393          * We need to cleanup the planes now.  Why?
1394          *
1395          * The planes are "&vop->win[i].base".  That means the memory is
1396          * all part of the big "struct vop" chunk of memory.  That memory
1397          * was devm allocated and associated with this component.  We need to
1398          * free it ourselves before vop_unbind() finishes.
1399          */
1400         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1401                                  head)
1402                 vop_plane_destroy(plane);
1403
1404         /*
1405          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1406          * references the CRTC.
1407          */
1408         drm_crtc_cleanup(crtc);
1409 }
1410
1411 static int vop_initial(struct vop *vop)
1412 {
1413         const struct vop_data *vop_data = vop->data;
1414         const struct vop_reg_data *init_table = vop_data->init_table;
1415         struct reset_control *ahb_rst;
1416         int i, ret;
1417
1418         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1419         if (IS_ERR(vop->hclk)) {
1420                 dev_err(vop->dev, "failed to get hclk source\n");
1421                 return PTR_ERR(vop->hclk);
1422         }
1423         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1424         if (IS_ERR(vop->aclk)) {
1425                 dev_err(vop->dev, "failed to get aclk source\n");
1426                 return PTR_ERR(vop->aclk);
1427         }
1428         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1429         if (IS_ERR(vop->dclk)) {
1430                 dev_err(vop->dev, "failed to get dclk source\n");
1431                 return PTR_ERR(vop->dclk);
1432         }
1433
1434         ret = clk_prepare(vop->dclk);
1435         if (ret < 0) {
1436                 dev_err(vop->dev, "failed to prepare dclk\n");
1437                 return ret;
1438         }
1439
1440         /* Enable both the hclk and aclk to setup the vop */
1441         ret = clk_prepare_enable(vop->hclk);
1442         if (ret < 0) {
1443                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1444                 goto err_unprepare_dclk;
1445         }
1446
1447         ret = clk_prepare_enable(vop->aclk);
1448         if (ret < 0) {
1449                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1450                 goto err_disable_hclk;
1451         }
1452
1453         /*
1454          * do hclk_reset, reset all vop registers.
1455          */
1456         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1457         if (IS_ERR(ahb_rst)) {
1458                 dev_err(vop->dev, "failed to get ahb reset\n");
1459                 ret = PTR_ERR(ahb_rst);
1460                 goto err_disable_aclk;
1461         }
1462         reset_control_assert(ahb_rst);
1463         usleep_range(10, 20);
1464         reset_control_deassert(ahb_rst);
1465
1466         memcpy(vop->regsbak, vop->regs, vop->len);
1467
1468         for (i = 0; i < vop_data->table_size; i++)
1469                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1470
1471         for (i = 0; i < vop->num_wins; i++) {
1472                 struct vop_win *win = &vop->win[i];
1473
1474                 VOP_WIN_SET(vop, win, enable, 0);
1475         }
1476
1477         vop_cfg_done(vop);
1478
1479         /*
1480          * do dclk_reset, let all config take affect.
1481          */
1482         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1483         if (IS_ERR(vop->dclk_rst)) {
1484                 dev_err(vop->dev, "failed to get dclk reset\n");
1485                 ret = PTR_ERR(vop->dclk_rst);
1486                 goto err_disable_aclk;
1487         }
1488         reset_control_assert(vop->dclk_rst);
1489         usleep_range(10, 20);
1490         reset_control_deassert(vop->dclk_rst);
1491
1492         clk_disable(vop->hclk);
1493         clk_disable(vop->aclk);
1494
1495         vop->is_enabled = false;
1496
1497         return 0;
1498
1499 err_disable_aclk:
1500         clk_disable_unprepare(vop->aclk);
1501 err_disable_hclk:
1502         clk_disable_unprepare(vop->hclk);
1503 err_unprepare_dclk:
1504         clk_unprepare(vop->dclk);
1505         return ret;
1506 }
1507
1508 /*
1509  * Initialize the vop->win array elements.
1510  */
1511 static int vop_win_init(struct vop *vop)
1512 {
1513         const struct vop_data *vop_data = vop->data;
1514         unsigned int i, j;
1515         unsigned int num_wins = 0;
1516         struct drm_property *prop;
1517
1518         for (i = 0; i < vop_data->win_size; i++) {
1519                 struct vop_win *vop_win = &vop->win[num_wins];
1520                 const struct vop_win_data *win_data = &vop_data->win[i];
1521
1522                 vop_win->phy = win_data->phy;
1523                 vop_win->offset = win_data->base;
1524                 vop_win->type = win_data->type;
1525                 vop_win->data_formats = win_data->phy->data_formats;
1526                 vop_win->nformats = win_data->phy->nformats;
1527                 vop_win->vop = vop;
1528                 vop_win->win_id = i;
1529                 vop_win->area_id = 0;
1530                 num_wins++;
1531
1532                 for (j = 0; j < win_data->area_size; j++) {
1533                         struct vop_win *vop_area = &vop->win[num_wins];
1534                         const struct vop_win_phy *area = win_data->area[j];
1535
1536                         vop_area->parent = vop_win;
1537                         vop_area->offset = vop_win->offset;
1538                         vop_area->phy = area;
1539                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1540                         vop_area->data_formats = vop_win->data_formats;
1541                         vop_area->nformats = vop_win->nformats;
1542                         vop_area->vop = vop;
1543                         vop_area->win_id = i;
1544                         vop_area->area_id = j;
1545                         num_wins++;
1546                 }
1547         }
1548         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1549                                          "ZPOS", 0, vop->data->win_size);
1550         if (!prop) {
1551                 DRM_ERROR("failed to create zpos property\n");
1552                 return -EINVAL;
1553         }
1554         vop->plane_zpos_prop = prop;
1555
1556         return 0;
1557 }
1558
1559 static int vop_bind(struct device *dev, struct device *master, void *data)
1560 {
1561         struct platform_device *pdev = to_platform_device(dev);
1562         const struct vop_data *vop_data;
1563         struct drm_device *drm_dev = data;
1564         struct vop *vop;
1565         struct resource *res;
1566         size_t alloc_size;
1567         int ret, irq, i;
1568         int num_wins = 0;
1569
1570         vop_data = of_device_get_match_data(dev);
1571         if (!vop_data)
1572                 return -ENODEV;
1573
1574         for (i = 0; i < vop_data->win_size; i++) {
1575                 const struct vop_win_data *win_data = &vop_data->win[i];
1576
1577                 num_wins += win_data->area_size + 1;
1578         }
1579
1580         /* Allocate vop struct and its vop_win array */
1581         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1582         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1583         if (!vop)
1584                 return -ENOMEM;
1585
1586         vop->dev = dev;
1587         vop->data = vop_data;
1588         vop->drm_dev = drm_dev;
1589         vop->num_wins = num_wins;
1590         dev_set_drvdata(dev, vop);
1591
1592         ret = vop_win_init(vop);
1593         if (ret)
1594                 return ret;
1595
1596         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1597         vop->len = resource_size(res);
1598         vop->regs = devm_ioremap_resource(dev, res);
1599         if (IS_ERR(vop->regs))
1600                 return PTR_ERR(vop->regs);
1601
1602         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1603         if (!vop->regsbak)
1604                 return -ENOMEM;
1605
1606         ret = vop_initial(vop);
1607         if (ret < 0) {
1608                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1609                 return ret;
1610         }
1611
1612         irq = platform_get_irq(pdev, 0);
1613         if (irq < 0) {
1614                 dev_err(dev, "cannot find irq for vop\n");
1615                 return irq;
1616         }
1617         vop->irq = (unsigned int)irq;
1618
1619         spin_lock_init(&vop->reg_lock);
1620         spin_lock_init(&vop->irq_lock);
1621
1622         mutex_init(&vop->vsync_mutex);
1623
1624         ret = devm_request_irq(dev, vop->irq, vop_isr,
1625                                IRQF_SHARED, dev_name(dev), vop);
1626         if (ret)
1627                 return ret;
1628
1629         /* IRQ is initially disabled; it gets enabled in power_on */
1630         disable_irq(vop->irq);
1631
1632         ret = vop_create_crtc(vop);
1633         if (ret)
1634                 return ret;
1635
1636         pm_runtime_enable(&pdev->dev);
1637         return 0;
1638 }
1639
1640 static void vop_unbind(struct device *dev, struct device *master, void *data)
1641 {
1642         struct vop *vop = dev_get_drvdata(dev);
1643
1644         pm_runtime_disable(dev);
1645         vop_destroy_crtc(vop);
1646 }
1647
1648 const struct component_ops vop_component_ops = {
1649         .bind = vop_bind,
1650         .unbind = vop_unbind,
1651 };
1652 EXPORT_SYMBOL_GPL(vop_component_ops);