drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/devfreq.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/iopoll.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/component.h>
  33
  34 #include <linux/reset.h>
  35 #include <linux/delay.h>
  36 #include <linux/sort.h>
  37 #include <uapi/drm/rockchip_drm.h>
  38
  39 #include "rockchip_drm_drv.h"
  40 #include "rockchip_drm_gem.h"
  41 #include "rockchip_drm_fb.h"
  42 #include "rockchip_drm_vop.h"
  43
  44 #define VOP_REG_SUPPORT(vop, reg) \
  45                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  46                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  47                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  48                 reg.mask))
  49
  50 #define VOP_WIN_SUPPORT(vop, win, name) \
  51                 VOP_REG_SUPPORT(vop, win->phy->name)
  52
  53 #define VOP_CTRL_SUPPORT(vop, name) \
  54                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  55
  56 #define VOP_INTR_SUPPORT(vop, name) \
  57                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  58
  59 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  60                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  61
  62 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  63         do { \
  64                 if (VOP_REG_SUPPORT(vop, reg)) \
  65                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  66                                   v, reg.write_mask, relaxed); \
  67                 else \
  68                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  69         } while(0)
  70
  71 #define REG_SET(x, name, off, reg, v, relaxed) \
  72                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  73 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  74                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  75
  76 #define VOP_WIN_SET(x, win, name, v) \
  77                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  78 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  79                 REG_SET(x, name, 0, win->ext->name, v, true)
  80 #define VOP_SCL_SET(x, win, name, v) \
  81                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  82 #define VOP_SCL_SET_EXT(x, win, name, v) \
  83                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  84
  85 #define VOP_CTRL_SET(x, name, v) \
  86                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  87
  88 #define VOP_INTR_GET(vop, name) \
  89                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  90
  91 #define VOP_INTR_SET(vop, name, v) \
  92                 REG_SET(vop, name, 0, vop->data->intr->name, \
  93                         v, false)
  94 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  95                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  96                              mask, v, false)
  97
  98 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  99         do { \
 100                 int i, reg = 0, mask = 0; \
 101                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 102                         if (vop->data->intr->intrs[i] & type) { \
 103                                 reg |= (v) << i; \
 104                                 mask |= 1 << i; \
 105                         } \
 106                 } \
 107                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 108         } while (0)
 109 #define VOP_INTR_GET_TYPE(vop, name, type) \
 110                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 111
 112 #define VOP_CTRL_GET(x, name) \
 113                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 114
 115 #define VOP_WIN_GET(x, win, name) \
 116                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 117
 118 #define VOP_WIN_NAME(win, name) \
 119                 (vop_get_win_phy(win, &win->phy->name)->name)
 120
 121 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 122                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 123
 124 #define to_vop(x) container_of(x, struct vop, crtc)
 125 #define to_vop_win(x) container_of(x, struct vop_win, base)
 126 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 127
 128 struct vop_zpos {
 129         int win_id;
 130         int zpos;
 131 };
 132
 133 struct vop_plane_state {
 134         struct drm_plane_state base;
 135         int format;
 136         int zpos;
 137         unsigned int logo_ymirror;
 138         struct drm_rect src;
 139         struct drm_rect dest;
 140         dma_addr_t yrgb_mst;
 141         dma_addr_t uv_mst;
 142         const uint32_t *y2r_table;
 143         const uint32_t *r2r_table;
 144         const uint32_t *r2y_table;
 145         bool enable;
 146 };
 147
 148 struct vop_win {
 149         struct vop_win *parent;
 150         struct drm_plane base;
 151
 152         int win_id;
 153         int area_id;
 154         uint32_t offset;
 155         enum drm_plane_type type;
 156         const struct vop_win_phy *phy;
 157         const struct vop_csc *csc;
 158         const uint32_t *data_formats;
 159         uint32_t nformats;
 160         struct vop *vop;
 161
 162         struct drm_property *rotation_prop;
 163         struct vop_plane_state state;
 164 };
 165
 166 struct vop {
 167         struct drm_crtc crtc;
 168         struct device *dev;
 169         struct drm_device *drm_dev;
 170         struct drm_property *plane_zpos_prop;
 171         struct drm_property *plane_feature_prop;
 172         struct drm_property *feature_prop;
 173         bool is_iommu_enabled;
 174         bool is_iommu_needed;
 175         bool is_enabled;
 176
 177         /* mutex vsync_ work */
 178         struct mutex vsync_mutex;
 179         bool vsync_work_pending;
 180         bool loader_protect;
 181         struct completion dsp_hold_completion;
 182         struct completion wait_update_complete;
 183         struct drm_pending_vblank_event *event;
 184
 185         struct completion line_flag_completion;
 186
 187         const struct vop_data *data;
 188         int num_wins;
 189
 190         uint32_t *regsbak;
 191         void __iomem *regs;
 192
 193         /* physical map length of vop register */
 194         uint32_t len;
 195
 196         void __iomem *lut_regs;
 197         u32 *lut;
 198         u32 lut_len;
 199         bool lut_active;
 200
 201         /* one time only one process allowed to config the register */
 202         spinlock_t reg_lock;
 203         /* lock vop irq reg */
 204         spinlock_t irq_lock;
 205         /* mutex vop enable and disable */
 206         struct mutex vop_lock;
 207
 208         unsigned int irq;
 209
 210         /* vop AHP clk */
 211         struct clk *hclk;
 212         /* vop dclk */
 213         struct clk *dclk;
 214         /* vop share memory frequency */
 215         struct clk *aclk;
 216         /* vop source handling, optional */
 217         struct clk *dclk_source;
 218
 219         /* vop dclk reset */
 220         struct reset_control *dclk_rst;
 221
 222         struct devfreq *devfreq;
 223         struct notifier_block dmc_nb;
 224
 225         struct vop_win win[];
 226 };
 227
 228 struct vop *dmc_vop;
 229
 230 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 231 {
 232         writel(v, vop->regs + offset);
 233         vop->regsbak[offset >> 2] = v;
 234 }
 235
 236 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 237 {
 238         return readl(vop->regs + offset);
 239 }
 240
 241 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 242                                     const struct vop_reg *reg)
 243 {
 244         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 245 }
 246
 247 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 248                                   uint32_t mask, uint32_t shift, uint32_t v,
 249                                   bool write_mask, bool relaxed)
 250 {
 251         if (!mask)
 252                 return;
 253
 254         if (write_mask) {
 255                 v = ((v & mask) << shift) | (mask << (shift + 16));
 256         } else {
 257                 uint32_t cached_val = vop->regsbak[offset >> 2];
 258
 259                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 260                 vop->regsbak[offset >> 2] = v;
 261         }
 262
 263         if (relaxed)
 264                 writel_relaxed(v, vop->regs + offset);
 265         else
 266                 writel(v, vop->regs + offset);
 267 }
 268
 269 static inline const struct vop_win_phy *
 270 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 271 {
 272         if (!reg->mask && win->parent)
 273                 return win->parent->phy;
 274
 275         return win->phy;
 276 }
 277
 278 static inline uint32_t vop_get_intr_type(struct vop *vop,
 279                                          const struct vop_reg *reg, int type)
 280 {
 281         uint32_t i, ret = 0;
 282         uint32_t regs = vop_read_reg(vop, 0, reg);
 283
 284         for (i = 0; i < vop->data->intr->nintrs; i++) {
 285                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 286                         ret |= vop->data->intr->intrs[i];
 287         }
 288
 289         return ret;
 290 }
 291
 292 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 293 {
 294         int i;
 295
 296         if (!table)
 297                 return;
 298
 299         for (i = 0; i < 8; i++)
 300                 vop_writel(vop, offset + i * 4, table[i]);
 301 }
 302
 303 static inline void vop_cfg_done(struct vop *vop)
 304 {
 305         VOP_CTRL_SET(vop, cfg_done, 1);
 306 }
 307
 308 static bool vop_is_allwin_disabled(struct vop *vop)
 309 {
 310         int i;
 311
 312         for (i = 0; i < vop->num_wins; i++) {
 313                 struct vop_win *win = &vop->win[i];
 314
 315                 if (VOP_WIN_GET(vop, win, enable) != 0)
 316                         return false;
 317         }
 318
 319         return true;
 320 }
 321
 322 static bool vop_is_cfg_done_complete(struct vop *vop)
 323 {
 324         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 325 }
 326
 327 static bool vop_fs_irq_is_active(struct vop *vop)
 328 {
 329         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 330 }
 331
 332 static bool vop_line_flag_is_active(struct vop *vop)
 333 {
 334         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 335 }
 336
 337 static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
 338 {
 339         writel(v, vop->lut_regs + offset);
 340 }
 341
 342 static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
 343 {
 344         return readl(vop->lut_regs + offset);
 345 }
 346
 347 static bool has_rb_swapped(uint32_t format)
 348 {
 349         switch (format) {
 350         case DRM_FORMAT_XBGR8888:
 351         case DRM_FORMAT_ABGR8888:
 352         case DRM_FORMAT_BGR888:
 353         case DRM_FORMAT_BGR565:
 354                 return true;
 355         default:
 356                 return false;
 357         }
 358 }
 359
 360 static enum vop_data_format vop_convert_format(uint32_t format)
 361 {
 362         switch (format) {
 363         case DRM_FORMAT_XRGB8888:
 364         case DRM_FORMAT_ARGB8888:
 365         case DRM_FORMAT_XBGR8888:
 366         case DRM_FORMAT_ABGR8888:
 367                 return VOP_FMT_ARGB8888;
 368         case DRM_FORMAT_RGB888:
 369         case DRM_FORMAT_BGR888:
 370                 return VOP_FMT_RGB888;
 371         case DRM_FORMAT_RGB565:
 372         case DRM_FORMAT_BGR565:
 373                 return VOP_FMT_RGB565;
 374         case DRM_FORMAT_NV12:
 375         case DRM_FORMAT_NV12_10:
 376                 return VOP_FMT_YUV420SP;
 377         case DRM_FORMAT_NV16:
 378         case DRM_FORMAT_NV16_10:
 379                 return VOP_FMT_YUV422SP;
 380         case DRM_FORMAT_NV24:
 381         case DRM_FORMAT_NV24_10:
 382                 return VOP_FMT_YUV444SP;
 383         default:
 384                 DRM_ERROR("unsupport format[%08x]\n", format);
 385                 return -EINVAL;
 386         }
 387 }
 388
 389 static bool is_yuv_output(uint32_t bus_format)
 390 {
 391         switch (bus_format) {
 392         case MEDIA_BUS_FMT_YUV8_1X24:
 393         case MEDIA_BUS_FMT_YUV10_1X30:
 394         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 395         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 396                 return true;
 397         default:
 398                 return false;
 399         }
 400 }
 401
 402 static bool is_yuv_support(uint32_t format)
 403 {
 404         switch (format) {
 405         case DRM_FORMAT_NV12:
 406         case DRM_FORMAT_NV12_10:
 407         case DRM_FORMAT_NV16:
 408         case DRM_FORMAT_NV16_10:
 409         case DRM_FORMAT_NV24:
 410         case DRM_FORMAT_NV24_10:
 411                 return true;
 412         default:
 413                 return false;
 414         }
 415 }
 416
 417 static bool is_yuv_10bit(uint32_t format)
 418 {
 419         switch (format) {
 420         case DRM_FORMAT_NV12_10:
 421         case DRM_FORMAT_NV16_10:
 422         case DRM_FORMAT_NV24_10:
 423                 return true;
 424         default:
 425                 return false;
 426         }
 427 }
 428
 429 static bool is_alpha_support(uint32_t format)
 430 {
 431         switch (format) {
 432         case DRM_FORMAT_ARGB8888:
 433         case DRM_FORMAT_ABGR8888:
 434                 return true;
 435         default:
 436                 return false;
 437         }
 438 }
 439
 440 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 441                                   uint32_t dst, bool is_horizontal,
 442                                   int vsu_mode, int *vskiplines)
 443 {
 444         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 445
 446         if (is_horizontal) {
 447                 if (mode == SCALE_UP)
 448                         val = GET_SCL_FT_BIC(src, dst);
 449                 else if (mode == SCALE_DOWN)
 450                         val = GET_SCL_FT_BILI_DN(src, dst);
 451         } else {
 452                 if (mode == SCALE_UP) {
 453                         if (vsu_mode == SCALE_UP_BIL)
 454                                 val = GET_SCL_FT_BILI_UP(src, dst);
 455                         else
 456                                 val = GET_SCL_FT_BIC(src, dst);
 457                 } else if (mode == SCALE_DOWN) {
 458                         if (vskiplines) {
 459                                 *vskiplines = scl_get_vskiplines(src, dst);
 460                                 val = scl_get_bili_dn_vskip(src, dst,
 461                                                             *vskiplines);
 462                         } else {
 463                                 val = GET_SCL_FT_BILI_DN(src, dst);
 464                         }
 465                 }
 466         }
 467
 468         return val;
 469 }
 470
 471 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 472                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 473                                 uint32_t dst_h, uint32_t pixel_format)
 474 {
 475         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 476         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 477         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 478         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 479         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 480         bool is_yuv = is_yuv_support(pixel_format);
 481         uint16_t cbcr_src_w = src_w / hsub;
 482         uint16_t cbcr_src_h = src_h / vsub;
 483         uint16_t vsu_mode;
 484         uint16_t lb_mode;
 485         uint32_t val;
 486         int vskiplines = 0;
 487
 488         if (!win->phy->scl)
 489                 return;
 490
 491         if (!win->phy->scl->ext) {
 492                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 493                             scl_cal_scale2(src_w, dst_w));
 494                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 495                             scl_cal_scale2(src_h, dst_h));
 496                 if (is_yuv) {
 497                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 498                                     scl_cal_scale2(cbcr_src_w, dst_w));
 499                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 500                                     scl_cal_scale2(cbcr_src_h, dst_h));
 501                 }
 502                 return;
 503         }
 504
 505         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 506         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 507
 508         if (is_yuv) {
 509                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 510                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 511                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 512                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 513                 else
 514                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 515         } else {
 516                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 517                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 518                 else
 519                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 520         }
 521
 522         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 523         if (lb_mode == LB_RGB_3840X2) {
 524                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 525                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 526                         return;
 527                 }
 528                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 529                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 530                         return;
 531                 }
 532                 vsu_mode = SCALE_UP_BIL;
 533         } else if (lb_mode == LB_RGB_2560X4) {
 534                 vsu_mode = SCALE_UP_BIL;
 535         } else {
 536                 vsu_mode = SCALE_UP_BIC;
 537         }
 538
 539         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 540                                 true, 0, NULL);
 541         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 542         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 543                                 false, vsu_mode, &vskiplines);
 544         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 545
 546         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 547         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 548
 549         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 550         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 551         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 552         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 553         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 554         if (is_yuv) {
 555                 vskiplines = 0;
 556
 557                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 558                                         dst_w, true, 0, NULL);
 559                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 560                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 561                                         dst_h, false, vsu_mode, &vskiplines);
 562                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 563
 564                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 565                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 566                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 567                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 568                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 569                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 570                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 571         }
 572 }
 573
 574 /*
 575  * rk3399 colorspace path:
 576  *      Input        Win csc                     Output
 577  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 578  *    RGB        --> R2Y                  __/
 579  *
 580  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 581  *    RGB        --> 709To2020->R2Y       __/
 582  *
 583  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 584  *    RGB        --> R2Y                  __/
 585  *
 586  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 587  *    RGB        --> 709To2020->R2Y       __/
 588  *
 589  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 590  *    RGB        --> R2Y                  __/
 591  *
 592  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 593  *    RGB        --> R2Y(601)             __/
 594  *
 595  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 596  *    RGB        --> bypass               __/
 597  *
 598  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 599  *
 600  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 601  *
 602  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 603  *
 604  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 605  */
 606 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 607                          bool is_input_yuv, bool is_output_yuv,
 608                          int input_csc, int output_csc,
 609                          const uint32_t **y2r_table,
 610                          const uint32_t **r2r_table,
 611                          const uint32_t **r2y_table)
 612 {
 613         *y2r_table = NULL;
 614         *r2r_table = NULL;
 615         *r2y_table = NULL;
 616
 617         if (is_output_yuv) {
 618                 if (output_csc == CSC_BT2020) {
 619                         if (is_input_yuv) {
 620                                 if (input_csc == CSC_BT2020)
 621                                         return 0;
 622                                 *y2r_table = csc_table->y2r_bt709;
 623                         }
 624                         if (input_csc != CSC_BT2020)
 625                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 626                         *r2y_table = csc_table->r2y_bt2020;
 627                 } else {
 628                         if (is_input_yuv && input_csc == CSC_BT2020)
 629                                 *y2r_table = csc_table->y2r_bt2020;
 630                         if (input_csc == CSC_BT2020)
 631                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 632                         if (!is_input_yuv || *y2r_table) {
 633                                 if (output_csc == CSC_BT709)
 634                                         *r2y_table = csc_table->r2y_bt709;
 635                                 else
 636                                         *r2y_table = csc_table->r2y_bt601;
 637                         }
 638                 }
 639         } else {
 640                 if (!is_input_yuv)
 641                         return 0;
 642
 643                 /*
 644                  * is possible use bt2020 on rgb mode?
 645                  */
 646                 if (WARN_ON(output_csc == CSC_BT2020))
 647                         return -EINVAL;
 648
 649                 if (input_csc == CSC_BT2020)
 650                         *y2r_table = csc_table->y2r_bt2020;
 651                 else if (input_csc == CSC_BT709)
 652                         *y2r_table = csc_table->y2r_bt709;
 653                 else
 654                         *y2r_table = csc_table->y2r_bt601;
 655
 656                 if (input_csc == CSC_BT2020)
 657                         /*
 658                          * We don't have bt601 to bt709 table, force use bt709.
 659                          */
 660                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 661         }
 662
 663         return 0;
 664 }
 665
 666 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 667                                 struct drm_crtc_state *crtc_state)
 668 {
 669         struct vop *vop = to_vop(crtc);
 670         struct drm_atomic_state *state = crtc_state->state;
 671         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 672         const struct vop_csc_table *csc_table = vop->data->csc_table;
 673         struct drm_plane_state *pstate;
 674         struct drm_plane *plane;
 675         bool is_input_yuv, is_output_yuv;
 676         int ret;
 677
 678         if (!csc_table)
 679                 return 0;
 680
 681         is_output_yuv = is_yuv_output(s->bus_format);
 682
 683         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 684                 struct vop_plane_state *vop_plane_state;
 685
 686                 pstate = drm_atomic_get_plane_state(state, plane);
 687                 if (IS_ERR(pstate))
 688                         return PTR_ERR(pstate);
 689                 vop_plane_state = to_vop_plane_state(pstate);
 690
 691                 if (!pstate->fb)
 692                         continue;
 693                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 694
 695                 /*
 696                  * TODO: force set input and output csc mode.
 697                  */
 698                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 699                                     CSC_BT709, CSC_BT709,
 700                                     &vop_plane_state->y2r_table,
 701                                     &vop_plane_state->r2r_table,
 702                                     &vop_plane_state->r2y_table);
 703                 if (ret)
 704                         return ret;
 705         }
 706
 707         return 0;
 708 }
 709
 710 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 711 {
 712         unsigned long flags;
 713
 714         spin_lock_irqsave(&vop->irq_lock, flags);
 715
 716         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 717         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 718
 719         spin_unlock_irqrestore(&vop->irq_lock, flags);
 720 }
 721
 722 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 723 {
 724         unsigned long flags;
 725
 726         spin_lock_irqsave(&vop->irq_lock, flags);
 727
 728         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 729
 730         spin_unlock_irqrestore(&vop->irq_lock, flags);
 731 }
 732
 733 /*
 734  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 735  *     the "FRAME_SYNC" interrupt.
 736  * (2) the active data region of each frame ends at dsp_vact_end
 737  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 738  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 739  *
 740  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 741  * Interrupts
 742  * LINE_FLAG -------------------------------+
 743  * FRAME_SYNC ----+                         |
 744  *                |                         |
 745  *                v                         v
 746  *                | Vsync | Vbp |  Vactive  | Vfp |
 747  *                        ^     ^           ^     ^
 748  *                        |     |           |     |
 749  *                        |     |           |     |
 750  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 751  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 752  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 753  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 754  */
 755 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 756 {
 757         uint32_t line_flag_irq;
 758         unsigned long flags;
 759
 760         spin_lock_irqsave(&vop->irq_lock, flags);
 761
 762         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 763
 764         spin_unlock_irqrestore(&vop->irq_lock, flags);
 765
 766         return !!line_flag_irq;
 767 }
 768
 769 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 770 {
 771         unsigned long flags;
 772
 773         if (WARN_ON(!vop->is_enabled))
 774                 return;
 775
 776         spin_lock_irqsave(&vop->irq_lock, flags);
 777
 778         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 779         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 780         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 781
 782         spin_unlock_irqrestore(&vop->irq_lock, flags);
 783 }
 784
 785 static void vop_line_flag_irq_disable(struct vop *vop)
 786 {
 787         unsigned long flags;
 788
 789         if (WARN_ON(!vop->is_enabled))
 790                 return;
 791
 792         spin_lock_irqsave(&vop->irq_lock, flags);
 793
 794         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 795
 796         spin_unlock_irqrestore(&vop->irq_lock, flags);
 797 }
 798
 799 static void vop_crtc_load_lut(struct drm_crtc *crtc)
 800 {
 801         struct vop *vop = to_vop(crtc);
 802         int i, dle, lut_idx;
 803
 804         if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
 805                 return;
 806
 807         if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
 808                 return;
 809
 810         if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 811                 spin_lock(&vop->reg_lock);
 812                 VOP_CTRL_SET(vop, dsp_lut_en, 0);
 813                 vop_cfg_done(vop);
 814                 spin_unlock(&vop->reg_lock);
 815
 816 #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
 817                 readx_poll_timeout(CTRL_GET, dsp_lut_en,
 818                                 dle, !dle, 5, 33333);
 819         } else {
 820                 lut_idx = CTRL_GET(lut_buffer_index);
 821         }
 822
 823         for (i = 0; i < vop->lut_len; i++)
 824                 vop_write_lut(vop, i << 2, vop->lut[i]);
 825
 826         spin_lock(&vop->reg_lock);
 827
 828         VOP_CTRL_SET(vop, dsp_lut_en, 1);
 829         VOP_CTRL_SET(vop, update_gamma_lut, 1);
 830         vop_cfg_done(vop);
 831         vop->lut_active = true;
 832
 833         spin_unlock(&vop->reg_lock);
 834
 835         if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
 836                 readx_poll_timeout(CTRL_GET, lut_buffer_index,
 837                                    dle, dle != lut_idx, 5, 33333);
 838                 /* FIXME:
 839                  * update_gamma value auto clean to 0 by HW, should not
 840                  * bakeup it.
 841                  */
 842                 VOP_CTRL_SET(vop, update_gamma_lut, 0);
 843         }
 844 #undef CTRL_GET
 845 }
 846
 847 void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 848                                     u16 blue, int regno)
 849 {
 850         struct vop *vop = to_vop(crtc);
 851         u32 lut_len = vop->lut_len;
 852         u32 r, g, b;
 853
 854         if (regno >= lut_len || !vop->lut)
 855                 return;
 856
 857         r = red * (lut_len - 1) / 0xffff;
 858         g = green * (lut_len - 1) / 0xffff;
 859         b = blue * (lut_len - 1) / 0xffff;
 860         vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
 861 }
 862
 863 void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 864                                     u16 *blue, int regno)
 865 {
 866         struct vop *vop = to_vop(crtc);
 867         u32 lut_len = vop->lut_len;
 868         u32 r, g, b;
 869
 870         if (regno >= lut_len || !vop->lut)
 871                 return;
 872
 873         r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
 874         g = (vop->lut[regno] / lut_len) & (lut_len - 1);
 875         b = vop->lut[regno] & (lut_len - 1);
 876         *red = r * 0xffff / (lut_len - 1);
 877         *green = g * 0xffff / (lut_len - 1);
 878         *blue = b * 0xffff / (lut_len - 1);
 879 }
 880
 881 static void vop_power_enable(struct drm_crtc *crtc)
 882 {
 883         struct vop *vop = to_vop(crtc);
 884         int ret;
 885
 886         ret = clk_prepare_enable(vop->hclk);
 887         if (ret < 0) {
 888                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 889                 return;
 890         }
 891
 892         ret = clk_prepare_enable(vop->dclk);
 893         if (ret < 0) {
 894                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 895                 goto err_disable_hclk;
 896         }
 897
 898         ret = clk_prepare_enable(vop->aclk);
 899         if (ret < 0) {
 900                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 901                 goto err_disable_dclk;
 902         }
 903
 904         ret = pm_runtime_get_sync(vop->dev);
 905         if (ret < 0) {
 906                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 907                 return;
 908         }
 909
 910         memcpy(vop->regsbak, vop->regs, vop->len);
 911
 912         vop->is_enabled = true;
 913
 914         return;
 915
 916 err_disable_dclk:
 917         clk_disable_unprepare(vop->dclk);
 918 err_disable_hclk:
 919         clk_disable_unprepare(vop->hclk);
 920 }
 921
 922 static void vop_initial(struct drm_crtc *crtc)
 923 {
 924         struct vop *vop = to_vop(crtc);
 925         int i;
 926
 927         vop_power_enable(crtc);
 928
 929         VOP_CTRL_SET(vop, global_regdone_en, 1);
 930         VOP_CTRL_SET(vop, dsp_blank, 0);
 931
 932         /*
 933          * restore the lut table.
 934          */
 935         if (vop->lut_active)
 936                 vop_crtc_load_lut(crtc);
 937
 938         /*
 939          * We need to make sure that all windows are disabled before resume
 940          * the crtc. Otherwise we might try to scan from a destroyed
 941          * buffer later.
 942          */
 943         for (i = 0; i < vop->num_wins; i++) {
 944                 struct vop_win *win = &vop->win[i];
 945                 int channel = i * 2 + 1;
 946
 947                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 948                 if (win->phy->scl && win->phy->scl->ext) {
 949                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 950                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 951                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 952                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 953                 }
 954                 VOP_WIN_SET(vop, win, enable, 0);
 955                 VOP_WIN_SET(vop, win, gate, 1);
 956         }
 957         VOP_CTRL_SET(vop, afbdc_en, 0);
 958 }
 959
 960 static void vop_crtc_disable(struct drm_crtc *crtc)
 961 {
 962         struct vop *vop = to_vop(crtc);
 963
 964         mutex_lock(&vop->vop_lock);
 965         drm_crtc_vblank_off(crtc);
 966
 967         /*
 968          * Vop standby will take effect at end of current frame,
 969          * if dsp hold valid irq happen, it means standby complete.
 970          *
 971          * we must wait standby complete when we want to disable aclk,
 972          * if not, memory bus maybe dead.
 973          */
 974         reinit_completion(&vop->dsp_hold_completion);
 975         vop_dsp_hold_valid_irq_enable(vop);
 976
 977         spin_lock(&vop->reg_lock);
 978
 979         VOP_CTRL_SET(vop, standby, 1);
 980
 981         spin_unlock(&vop->reg_lock);
 982
 983         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 984                                              msecs_to_jiffies(50)));
 985
 986         vop_dsp_hold_valid_irq_disable(vop);
 987
 988         disable_irq(vop->irq);
 989
 990         vop->is_enabled = false;
 991         if (vop->is_iommu_enabled) {
 992                 /*
 993                  * vop standby complete, so iommu detach is safe.
 994                  */
 995                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 996                 vop->is_iommu_enabled = false;
 997         }
 998
 999         pm_runtime_put(vop->dev);
1000         clk_disable_unprepare(vop->dclk);
1001         clk_disable_unprepare(vop->aclk);
1002         clk_disable_unprepare(vop->hclk);
1003         mutex_unlock(&vop->vop_lock);
1004 }
1005
1006 static void vop_plane_destroy(struct drm_plane *plane)
1007 {
1008         drm_plane_cleanup(plane);
1009 }
1010
1011 static int vop_plane_prepare_fb(struct drm_plane *plane,
1012                                 const struct drm_plane_state *new_state)
1013 {
1014         if (plane->state->fb)
1015                 drm_framebuffer_reference(plane->state->fb);
1016
1017         return 0;
1018 }
1019
1020 static void vop_plane_cleanup_fb(struct drm_plane *plane,
1021                                  const struct drm_plane_state *old_state)
1022 {
1023         if (old_state->fb)
1024                 drm_framebuffer_unreference(old_state->fb);
1025 }
1026
1027 static int vop_plane_atomic_check(struct drm_plane *plane,
1028                            struct drm_plane_state *state)
1029 {
1030         struct drm_crtc *crtc = state->crtc;
1031         struct drm_framebuffer *fb = state->fb;
1032         struct vop_win *win = to_vop_win(plane);
1033         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1034         struct drm_crtc_state *crtc_state;
1035         const struct vop_data *vop_data;
1036         struct vop *vop;
1037         bool visible;
1038         int ret;
1039         struct drm_rect *dest = &vop_plane_state->dest;
1040         struct drm_rect *src = &vop_plane_state->src;
1041         struct drm_rect clip;
1042         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1043                                         DRM_PLANE_HELPER_NO_SCALING;
1044         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1045                                         DRM_PLANE_HELPER_NO_SCALING;
1046         unsigned long offset;
1047         dma_addr_t dma_addr;
1048         u16 vdisplay;
1049
1050         crtc = crtc ? crtc : plane->state->crtc;
1051         /*
1052          * Both crtc or plane->state->crtc can be null.
1053          */
1054         if (!crtc || !fb)
1055                 goto out_disable;
1056
1057         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1058         if (IS_ERR(crtc_state))
1059                 return PTR_ERR(crtc_state);
1060
1061         src->x1 = state->src_x;
1062         src->y1 = state->src_y;
1063         src->x2 = state->src_x + state->src_w;
1064         src->y2 = state->src_y + state->src_h;
1065         dest->x1 = state->crtc_x;
1066         dest->y1 = state->crtc_y;
1067         dest->x2 = state->crtc_x + state->crtc_w;
1068         dest->y2 = state->crtc_y + state->crtc_h;
1069
1070         vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
1071         if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
1072                 vdisplay *= 2;
1073
1074         clip.x1 = 0;
1075         clip.y1 = 0;
1076         clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
1077         clip.y2 = vdisplay;
1078
1079         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
1080                                             src, dest, &clip,
1081                                             min_scale,
1082                                             max_scale,
1083                                             true, true, &visible);
1084         if (ret)
1085                 return ret;
1086
1087         if (!visible)
1088                 goto out_disable;
1089
1090         vop_plane_state->format = vop_convert_format(fb->pixel_format);
1091         if (vop_plane_state->format < 0)
1092                 return vop_plane_state->format;
1093
1094         vop = to_vop(crtc);
1095         vop_data = vop->data;
1096
1097         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
1098             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
1099                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
1100                           drm_rect_width(src) >> 16,
1101                           drm_rect_height(src) >> 16,
1102                           vop_data->max_input.width,
1103                           vop_data->max_input.height);
1104                 return -EINVAL;
1105         }
1106
1107         /*
1108          * Src.x1 can be odd when do clip, but yuv plane start point
1109          * need align with 2 pixel.
1110          */
1111         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
1112                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
1113                 return -EINVAL;
1114         }
1115
1116         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
1117         if (state->rotation & BIT(DRM_REFLECT_Y) ||
1118             (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
1119                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1120         else
1121                 offset += (src->y1 >> 16) * fb->pitches[0];
1122
1123         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
1124         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
1125         if (is_yuv_support(fb->pixel_format)) {
1126                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1127                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1128                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1129
1130                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1131                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1132
1133                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1134                 dma_addr += offset + fb->offsets[1];
1135                 vop_plane_state->uv_mst = dma_addr;
1136         }
1137
1138         vop_plane_state->enable = true;
1139
1140         return 0;
1141
1142 out_disable:
1143         vop_plane_state->enable = false;
1144         return 0;
1145 }
1146
1147 static void vop_plane_atomic_disable(struct drm_plane *plane,
1148                                      struct drm_plane_state *old_state)
1149 {
1150         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1151         struct vop_win *win = to_vop_win(plane);
1152         struct vop *vop = to_vop(old_state->crtc);
1153
1154         if (!old_state->crtc)
1155                 return;
1156
1157         spin_lock(&vop->reg_lock);
1158
1159         /*
1160          * FIXUP: some of the vop scale would be abnormal after windows power
1161          * on/off so deinit scale to scale_none mode.
1162          */
1163         if (win->phy->scl && win->phy->scl->ext) {
1164                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1165                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1166                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1167                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1168         }
1169         VOP_WIN_SET(vop, win, enable, 0);
1170
1171         spin_unlock(&vop->reg_lock);
1172
1173         vop_plane_state->enable = false;
1174 }
1175
1176 static void vop_plane_atomic_update(struct drm_plane *plane,
1177                 struct drm_plane_state *old_state)
1178 {
1179         struct drm_plane_state *state = plane->state;
1180         struct drm_crtc *crtc = state->crtc;
1181         struct vop_win *win = to_vop_win(plane);
1182         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1183         struct rockchip_crtc_state *s;
1184         struct vop *vop;
1185         struct drm_framebuffer *fb = state->fb;
1186         unsigned int actual_w, actual_h;
1187         unsigned int dsp_stx, dsp_sty;
1188         uint32_t act_info, dsp_info, dsp_st;
1189         struct drm_rect *src = &vop_plane_state->src;
1190         struct drm_rect *dest = &vop_plane_state->dest;
1191         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1192         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1193         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1194         int ymirror, xmirror;
1195         uint32_t val;
1196         bool rb_swap;
1197
1198         /*
1199          * can't update plane when vop is disabled.
1200          */
1201         if (!crtc)
1202                 return;
1203
1204         if (!vop_plane_state->enable) {
1205                 vop_plane_atomic_disable(plane, old_state);
1206                 return;
1207         }
1208
1209         actual_w = drm_rect_width(src) >> 16;
1210         actual_h = drm_rect_height(src) >> 16;
1211         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1212
1213         dsp_info = (drm_rect_height(dest) - 1) << 16;
1214         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1215
1216         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1217         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1218         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1219
1220         ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
1221                   (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
1222         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1223
1224         vop = to_vop(state->crtc);
1225         s = to_rockchip_crtc_state(crtc->state);
1226
1227         spin_lock(&vop->reg_lock);
1228
1229         VOP_WIN_SET(vop, win, xmirror, xmirror);
1230         VOP_WIN_SET(vop, win, ymirror, ymirror);
1231         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1232         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1233         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1234         if (is_yuv_support(fb->pixel_format)) {
1235                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1236                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1237         }
1238         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1239
1240         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1241                             drm_rect_width(dest), drm_rect_height(dest),
1242                             fb->pixel_format);
1243
1244         VOP_WIN_SET(vop, win, act_info, act_info);
1245         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1246         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1247
1248         rb_swap = has_rb_swapped(fb->pixel_format);
1249         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1250
1251         if (is_alpha_support(fb->pixel_format) &&
1252             (s->dsp_layer_sel & 0x3) != win->win_id) {
1253                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1254                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1255                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1256                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1257                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1258                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1259                         SRC_FACTOR_M0(ALPHA_ONE);
1260                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1261                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1262                 VOP_WIN_SET(vop, win, alpha_en, 1);
1263         } else {
1264                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1265                 VOP_WIN_SET(vop, win, alpha_en, 0);
1266         }
1267
1268         if (win->csc) {
1269                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1270                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1271                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1272                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1273                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1274                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1275         }
1276         VOP_WIN_SET(vop, win, enable, 1);
1277         spin_unlock(&vop->reg_lock);
1278         vop->is_iommu_needed = true;
1279 }
1280
1281 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1282         .prepare_fb = vop_plane_prepare_fb,
1283         .cleanup_fb = vop_plane_cleanup_fb,
1284         .atomic_check = vop_plane_atomic_check,
1285         .atomic_update = vop_plane_atomic_update,
1286         .atomic_disable = vop_plane_atomic_disable,
1287 };
1288
1289 void vop_atomic_plane_reset(struct drm_plane *plane)
1290 {
1291         struct vop_win *win = to_vop_win(plane);
1292         struct vop_plane_state *vop_plane_state =
1293                                         to_vop_plane_state(plane->state);
1294
1295         if (plane->state && plane->state->fb)
1296                 drm_framebuffer_unreference(plane->state->fb);
1297
1298         kfree(vop_plane_state);
1299         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1300         if (!vop_plane_state)
1301                 return;
1302
1303         vop_plane_state->zpos = win->win_id;
1304         plane->state = &vop_plane_state->base;
1305         plane->state->plane = plane;
1306 }
1307
1308 struct drm_plane_state *
1309 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1310 {
1311         struct vop_plane_state *old_vop_plane_state;
1312         struct vop_plane_state *vop_plane_state;
1313
1314         if (WARN_ON(!plane->state))
1315                 return NULL;
1316
1317         old_vop_plane_state = to_vop_plane_state(plane->state);
1318         vop_plane_state = kmemdup(old_vop_plane_state,
1319                                   sizeof(*vop_plane_state), GFP_KERNEL);
1320         if (!vop_plane_state)
1321                 return NULL;
1322
1323         __drm_atomic_helper_plane_duplicate_state(plane,
1324                                                   &vop_plane_state->base);
1325
1326         return &vop_plane_state->base;
1327 }
1328
1329 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1330                                            struct drm_plane_state *state)
1331 {
1332         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1333
1334         __drm_atomic_helper_plane_destroy_state(plane, state);
1335
1336         kfree(vop_state);
1337 }
1338
1339 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1340                                          struct drm_plane_state *state,
1341                                          struct drm_property *property,
1342                                          uint64_t val)
1343 {
1344         struct rockchip_drm_private *private = plane->dev->dev_private;
1345         struct vop_win *win = to_vop_win(plane);
1346         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1347
1348         if (property == win->vop->plane_zpos_prop) {
1349                 plane_state->zpos = val;
1350                 return 0;
1351         }
1352
1353         if (property == win->rotation_prop) {
1354                 state->rotation = val;
1355                 return 0;
1356         }
1357
1358         if (property == private->logo_ymirror_prop) {
1359                 WARN_ON(!rockchip_fb_is_logo(state->fb));
1360                 plane_state->logo_ymirror = val;
1361                 return 0;
1362         }
1363
1364         DRM_ERROR("failed to set vop plane property\n");
1365         return -EINVAL;
1366 }
1367
1368 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1369                                          const struct drm_plane_state *state,
1370                                          struct drm_property *property,
1371                                          uint64_t *val)
1372 {
1373         struct vop_win *win = to_vop_win(plane);
1374         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1375
1376         if (property == win->vop->plane_zpos_prop) {
1377                 *val = plane_state->zpos;
1378                 return 0;
1379         }
1380
1381         if (property == win->rotation_prop) {
1382                 *val = state->rotation;
1383                 return 0;
1384         }
1385
1386         DRM_ERROR("failed to get vop plane property\n");
1387         return -EINVAL;
1388 }
1389
1390 static const struct drm_plane_funcs vop_plane_funcs = {
1391         .update_plane   = drm_atomic_helper_update_plane,
1392         .disable_plane  = drm_atomic_helper_disable_plane,
1393         .destroy = vop_plane_destroy,
1394         .reset = vop_atomic_plane_reset,
1395         .set_property = drm_atomic_helper_plane_set_property,
1396         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1397         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1398         .atomic_set_property = vop_atomic_plane_set_property,
1399         .atomic_get_property = vop_atomic_plane_get_property,
1400 };
1401
1402 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1403 {
1404         struct vop *vop = to_vop(crtc);
1405         unsigned long flags;
1406
1407         if (!vop->is_enabled)
1408                 return -EPERM;
1409
1410         spin_lock_irqsave(&vop->irq_lock, flags);
1411
1412         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1413         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1414
1415         spin_unlock_irqrestore(&vop->irq_lock, flags);
1416
1417         return 0;
1418 }
1419
1420 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1421 {
1422         struct vop *vop = to_vop(crtc);
1423         unsigned long flags;
1424
1425         if (!vop->is_enabled)
1426                 return;
1427
1428         spin_lock_irqsave(&vop->irq_lock, flags);
1429
1430         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1431
1432         spin_unlock_irqrestore(&vop->irq_lock, flags);
1433 }
1434
1435 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1436 {
1437         struct vop *vop = to_vop(crtc);
1438
1439         reinit_completion(&vop->wait_update_complete);
1440         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete,
1441                                              msecs_to_jiffies(1000)));
1442 }
1443
1444 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1445                                            struct drm_file *file_priv)
1446 {
1447         struct drm_device *drm = crtc->dev;
1448         struct vop *vop = to_vop(crtc);
1449         struct drm_pending_vblank_event *e;
1450         unsigned long flags;
1451
1452         spin_lock_irqsave(&drm->event_lock, flags);
1453         e = vop->event;
1454         if (e && e->base.file_priv == file_priv) {
1455                 vop->event = NULL;
1456
1457                 e->base.destroy(&e->base);
1458                 file_priv->event_space += sizeof(e->event);
1459         }
1460         spin_unlock_irqrestore(&drm->event_lock, flags);
1461 }
1462
1463 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1464 {
1465         struct vop *vop = to_vop(crtc);
1466
1467         if (on == vop->loader_protect)
1468                 return 0;
1469
1470         if (on) {
1471                 vop_power_enable(crtc);
1472                 enable_irq(vop->irq);
1473                 drm_crtc_vblank_on(crtc);
1474                 vop->loader_protect = true;
1475         } else {
1476                 vop_crtc_disable(crtc);
1477
1478                 vop->loader_protect = false;
1479         }
1480
1481         return 0;
1482 }
1483
1484 #define DEBUG_PRINT(args...) \
1485                 do { \
1486                         if (s) \
1487                                 seq_printf(s, args); \
1488                         else \
1489                                 printk(args); \
1490                 } while (0)
1491
1492 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1493 {
1494         struct vop_win *win = to_vop_win(plane);
1495         struct drm_plane_state *state = plane->state;
1496         struct vop_plane_state *pstate = to_vop_plane_state(state);
1497         struct drm_rect *src, *dest;
1498         struct drm_framebuffer *fb = state->fb;
1499         int i;
1500
1501         DEBUG_PRINT("    win%d-%d: %s\n", win->win_id, win->area_id,
1502                     pstate->enable ? "ACTIVE" : "DISABLED");
1503         if (!fb)
1504                 return 0;
1505
1506         src = &pstate->src;
1507         dest = &pstate->dest;
1508
1509         DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1510                     fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1511         DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
1512         DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1513                     src->y1 >> 16, drm_rect_width(src) >> 16,
1514                     drm_rect_height(src) >> 16);
1515         DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1516                     drm_rect_width(dest), drm_rect_height(dest));
1517
1518         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1519                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1520                 DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1521                             i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1528 {
1529         struct vop *vop = to_vop(crtc);
1530         struct drm_crtc_state *crtc_state = crtc->state;
1531         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1532         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1533         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1534         struct drm_plane *plane;
1535         int i;
1536
1537         DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
1538                     crtc_state->active ? "ACTIVE" : "DISABLED");
1539
1540         if (!crtc_state->active)
1541                 return 0;
1542
1543         DEBUG_PRINT("    Connector: %s\n",
1544                     drm_get_connector_name(state->output_type));
1545         DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
1546                     state->bus_format, state->output_mode);
1547         DEBUG_PRINT("    Display mode: %dx%d%s%d\n",
1548                     mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1549                     drm_mode_vrefresh(mode));
1550         DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1551                     mode->clock, mode->crtc_clock, mode->type, mode->flags);
1552         DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1553                     mode->hsync_end, mode->htotal);
1554         DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1555                     mode->vsync_end, mode->vtotal);
1556
1557         for (i = 0; i < vop->num_wins; i++) {
1558                 plane = &vop->win[i].base;
1559                 vop_plane_info_dump(s, plane);
1560         }
1561
1562         return 0;
1563 }
1564
1565 static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
1566 {
1567         struct vop *vop = to_vop(crtc);
1568         struct drm_crtc_state *crtc_state = crtc->state;
1569         int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
1570         int i;
1571
1572         if (!crtc_state->active)
1573                 return;
1574
1575         for (i = 0; i < dump_len; i += 4) {
1576                 if (i % 16 == 0)
1577                         DEBUG_PRINT("\n0x%08x: ", i);
1578                 DEBUG_PRINT("%08x ", vop_readl(vop, i));
1579         }
1580 }
1581
1582 #undef DEBUG_PRINT
1583
1584 static enum drm_mode_status
1585 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1586                     int output_type)
1587 {
1588         struct vop *vop = to_vop(crtc);
1589         const struct vop_data *vop_data = vop->data;
1590         int request_clock = mode->clock;
1591         int clock;
1592
1593         if (mode->hdisplay > vop_data->max_output.width)
1594                 return MODE_BAD_HVALUE;
1595
1596         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
1597             VOP_MAJOR(vop->data->version) == 3 &&
1598             VOP_MINOR(vop->data->version) <= 2)
1599                 return MODE_BAD;
1600
1601         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1602                 request_clock *= 2;
1603         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1604
1605         /*
1606          * Hdmi or DisplayPort request a Accurate clock.
1607          */
1608         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1609             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1610                 if (clock != request_clock)
1611                         return MODE_CLOCK_RANGE;
1612
1613         return MODE_OK;
1614 }
1615
1616 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1617         .loader_protect = vop_crtc_loader_protect,
1618         .enable_vblank = vop_crtc_enable_vblank,
1619         .disable_vblank = vop_crtc_disable_vblank,
1620         .wait_for_update = vop_crtc_wait_for_update,
1621         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1622         .debugfs_dump = vop_crtc_debugfs_dump,
1623         .regs_dump = vop_crtc_regs_dump,
1624         .mode_valid = vop_crtc_mode_valid,
1625 };
1626
1627 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1628                                 const struct drm_display_mode *mode,
1629                                 struct drm_display_mode *adj_mode)
1630 {
1631         struct vop *vop = to_vop(crtc);
1632         const struct vop_data *vop_data = vop->data;
1633
1634         if (mode->hdisplay > vop_data->max_output.width)
1635                 return false;
1636
1637         drm_mode_set_crtcinfo(adj_mode,
1638                               CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
1639
1640         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1641                 adj_mode->crtc_clock *= 2;
1642
1643         adj_mode->crtc_clock =
1644                 clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
1645
1646         return true;
1647 }
1648
1649 static void vop_crtc_enable(struct drm_crtc *crtc)
1650 {
1651         struct vop *vop = to_vop(crtc);
1652         const struct vop_data *vop_data = vop->data;
1653         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1654         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1655         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1656         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1657         u16 htotal = adjusted_mode->crtc_htotal;
1658         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1659         u16 hact_end = hact_st + hdisplay;
1660         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1661         u16 vtotal = adjusted_mode->crtc_vtotal;
1662         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1663         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1664         u16 vact_end = vact_st + vdisplay;
1665         uint32_t val;
1666
1667         mutex_lock(&vop->vop_lock);
1668         vop_initial(crtc);
1669
1670         val = BIT(DCLK_INVERT);
1671         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1672                    0 : BIT(HSYNC_POSITIVE);
1673         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1674                    0 : BIT(VSYNC_POSITIVE);
1675         VOP_CTRL_SET(vop, pin_pol, val);
1676
1677         if (vop->dclk_source && s->pll && s->pll->pll) {
1678                 if (clk_set_parent(vop->dclk_source, s->pll->pll))
1679                         DRM_DEV_ERROR(vop->dev,
1680                                       "failed to set dclk's parents\n");
1681         }
1682
1683         switch (s->output_type) {
1684         case DRM_MODE_CONNECTOR_LVDS:
1685                 VOP_CTRL_SET(vop, rgb_en, 1);
1686                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1687                 break;
1688         case DRM_MODE_CONNECTOR_eDP:
1689                 VOP_CTRL_SET(vop, edp_en, 1);
1690                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1691                 break;
1692         case DRM_MODE_CONNECTOR_HDMIA:
1693                 VOP_CTRL_SET(vop, hdmi_en, 1);
1694                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1695                 break;
1696         case DRM_MODE_CONNECTOR_DSI:
1697                 VOP_CTRL_SET(vop, mipi_en, 1);
1698                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1699                 break;
1700         case DRM_MODE_CONNECTOR_DisplayPort:
1701                 val &= ~BIT(DCLK_INVERT);
1702                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1703                 VOP_CTRL_SET(vop, dp_en, 1);
1704                 break;
1705         case DRM_MODE_CONNECTOR_TV:
1706                 if (vdisplay == CVBS_PAL_VDISPLAY)
1707                         VOP_CTRL_SET(vop, tve_sw_mode, 1);
1708                 else
1709                         VOP_CTRL_SET(vop, tve_sw_mode, 0);
1710
1711                 VOP_CTRL_SET(vop, tve_dclk_pol, 1);
1712                 VOP_CTRL_SET(vop, tve_dclk_en, 1);
1713                 /* use the same pol reg with hdmi */
1714                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1715                 VOP_CTRL_SET(vop, sw_genlock, 1);
1716                 VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
1717                 VOP_CTRL_SET(vop, dither_up, 1);
1718                 break;
1719         default:
1720                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1721         }
1722
1723         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1724             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1725                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1726
1727         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1728         switch (s->bus_format) {
1729         case MEDIA_BUS_FMT_RGB565_1X16:
1730                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1731                 break;
1732         case MEDIA_BUS_FMT_RGB666_1X18:
1733         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1734                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1735                 break;
1736         case MEDIA_BUS_FMT_YUV8_1X24:
1737         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1738                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1739                 break;
1740         case MEDIA_BUS_FMT_YUV10_1X30:
1741         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1742                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1743                 break;
1744         case MEDIA_BUS_FMT_RGB888_1X24:
1745         default:
1746                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1747                 break;
1748         }
1749
1750         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1751                 val |= PRE_DITHER_DOWN_EN(0);
1752         else
1753                 val |= PRE_DITHER_DOWN_EN(1);
1754         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1755         VOP_CTRL_SET(vop, dither_down, val);
1756         VOP_CTRL_SET(vop, dclk_ddr,
1757                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1758         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1759         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1760         VOP_CTRL_SET(vop, dsp_background,
1761                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1762
1763         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1764         val = hact_st << 16;
1765         val |= hact_end;
1766         VOP_CTRL_SET(vop, hact_st_end, val);
1767         VOP_CTRL_SET(vop, hpost_st_end, val);
1768
1769         val = vact_st << 16;
1770         val |= vact_end;
1771         VOP_CTRL_SET(vop, vact_st_end, val);
1772         VOP_CTRL_SET(vop, vpost_st_end, val);
1773
1774         VOP_INTR_SET(vop, line_flag_num[0], vact_end);
1775         VOP_INTR_SET(vop, line_flag_num[1],
1776                      vact_end - us_to_vertical_line(adjusted_mode, 1000));
1777         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1778                 u16 vact_st_f1 = vtotal + vact_st + 1;
1779                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1780
1781                 val = vact_st_f1 << 16 | vact_end_f1;
1782                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1783                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1784
1785                 val = vtotal << 16 | (vtotal + vsync_len);
1786                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1787                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1788                 VOP_CTRL_SET(vop, p2i_en, 1);
1789                 vtotal += vtotal + 1;
1790         } else {
1791                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1792                 VOP_CTRL_SET(vop, p2i_en, 0);
1793         }
1794         VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
1795
1796         VOP_CTRL_SET(vop, core_dclk_div,
1797                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1798
1799         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1800
1801         vop_cfg_done(vop);
1802         /*
1803          * enable vop, all the register would take effect when vop exit standby
1804          */
1805         VOP_CTRL_SET(vop, standby, 0);
1806
1807         enable_irq(vop->irq);
1808         drm_crtc_vblank_on(crtc);
1809         mutex_unlock(&vop->vop_lock);
1810 }
1811
1812 static int vop_zpos_cmp(const void *a, const void *b)
1813 {
1814         struct vop_zpos *pa = (struct vop_zpos *)a;
1815         struct vop_zpos *pb = (struct vop_zpos *)b;
1816
1817         return pa->zpos - pb->zpos;
1818 }
1819
1820 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1821                                   struct drm_crtc_state *crtc_state)
1822 {
1823         struct vop *vop = to_vop(crtc);
1824         const struct vop_data *vop_data = vop->data;
1825         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1826         struct drm_atomic_state *state = crtc_state->state;
1827         struct drm_plane *plane;
1828         struct drm_plane_state *pstate;
1829         struct vop_plane_state *plane_state;
1830         struct vop_win *win;
1831         int afbdc_format;
1832         int i;
1833
1834         s->afbdc_en = 0;
1835
1836         for_each_plane_in_state(state, plane, pstate, i) {
1837                 struct drm_framebuffer *fb = pstate->fb;
1838                 struct drm_rect *src;
1839
1840                 win = to_vop_win(plane);
1841                 plane_state = to_vop_plane_state(pstate);
1842
1843                 if (pstate->crtc != crtc || !fb)
1844                         continue;
1845
1846                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1847                         continue;
1848
1849                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1850                         DRM_ERROR("not support afbdc\n");
1851                         return -EINVAL;
1852                 }
1853
1854                 switch (plane_state->format) {
1855                 case VOP_FMT_ARGB8888:
1856                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1857                         break;
1858                 case VOP_FMT_RGB888:
1859                         afbdc_format = AFBDC_FMT_U8U8U8;
1860                         break;
1861                 case VOP_FMT_RGB565:
1862                         afbdc_format = AFBDC_FMT_RGB565;
1863                         break;
1864                 default:
1865                         return -EINVAL;
1866                 }
1867
1868                 if (s->afbdc_en) {
1869                         DRM_ERROR("vop only support one afbc layer\n");
1870                         return -EINVAL;
1871                 }
1872
1873                 src = &plane_state->src;
1874                 if (src->x1 || src->y1 || fb->offsets[0]) {
1875                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1876                                   win->win_id);
1877                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1878                                   src->x1, src->y1, fb->offsets[0]);
1879                         return -EINVAL;
1880                 }
1881                 s->afbdc_win_format = afbdc_format;
1882                 s->afbdc_win_width = pstate->fb->width - 1;
1883                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1884                 s->afbdc_win_id = win->win_id;
1885                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1886                 s->afbdc_en = 1;
1887         }
1888
1889         return 0;
1890 }
1891
1892 static void vop_dclk_source_generate(struct drm_crtc *crtc,
1893                                      struct drm_crtc_state *crtc_state)
1894 {
1895         struct rockchip_drm_private *private = crtc->dev->dev_private;
1896         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1897         struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
1898         struct vop *vop = to_vop(crtc);
1899
1900         if (!vop->dclk_source)
1901                 return;
1902
1903         if (crtc_state->active) {
1904                 WARN_ON(s->pll && !s->pll->use_count);
1905                 if (!s->pll || s->pll->use_count > 1 ||
1906                     s->output_type != old_s->output_type) {
1907                         if (s->pll)
1908                                 s->pll->use_count--;
1909
1910                         if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
1911                             !private->default_pll.use_count)
1912                                 s->pll = &private->default_pll;
1913                         else
1914                                 s->pll = &private->hdmi_pll;
1915
1916                         s->pll->use_count++;
1917                 }
1918         } else if (s->pll) {
1919                 s->pll->use_count--;
1920                 s->pll = NULL;
1921         }
1922         if (s->pll && s->pll != old_s->pll)
1923                 crtc_state->mode_changed = true;
1924 }
1925
1926 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1927                                  struct drm_crtc_state *crtc_state)
1928 {
1929         struct drm_atomic_state *state = crtc_state->state;
1930         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1931         struct vop *vop = to_vop(crtc);
1932         const struct vop_data *vop_data = vop->data;
1933         struct drm_plane *plane;
1934         struct drm_plane_state *pstate;
1935         struct vop_plane_state *plane_state;
1936         struct vop_zpos *pzpos;
1937         int dsp_layer_sel = 0;
1938         int i, j, cnt = 0, ret = 0;
1939
1940         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1941         if (ret)
1942                 return ret;
1943
1944         ret = vop_csc_atomic_check(crtc, crtc_state);
1945         if (ret)
1946                 return ret;
1947
1948         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1949         if (!pzpos)
1950                 return -ENOMEM;
1951
1952         for (i = 0; i < vop_data->win_size; i++) {
1953                 const struct vop_win_data *win_data = &vop_data->win[i];
1954                 struct vop_win *win;
1955
1956                 if (!win_data->phy)
1957                         continue;
1958
1959                 for (j = 0; j < vop->num_wins; j++) {
1960                         win = &vop->win[j];
1961
1962                         if (win->win_id == i && !win->area_id)
1963                                 break;
1964                 }
1965                 if (WARN_ON(j >= vop->num_wins)) {
1966                         ret = -EINVAL;
1967                         goto err_free_pzpos;
1968                 }
1969
1970                 plane = &win->base;
1971                 pstate = state->plane_states[drm_plane_index(plane)];
1972                 /*
1973                  * plane might not have changed, in which case take
1974                  * current state:
1975                  */
1976                 if (!pstate)
1977                         pstate = plane->state;
1978                 plane_state = to_vop_plane_state(pstate);
1979                 pzpos[cnt].zpos = plane_state->zpos;
1980                 pzpos[cnt++].win_id = win->win_id;
1981         }
1982
1983         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1984
1985         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1986                 const struct vop_win_data *win_data = &vop_data->win[i];
1987                 int shift = i * 2;
1988
1989                 if (win_data->phy) {
1990                         struct vop_zpos *zpos = &pzpos[cnt++];
1991
1992                         dsp_layer_sel |= zpos->win_id << shift;
1993                 } else {
1994                         dsp_layer_sel |= i << shift;
1995                 }
1996         }
1997
1998         s->dsp_layer_sel = dsp_layer_sel;
1999
2000         vop_dclk_source_generate(crtc, crtc_state);
2001
2002 err_free_pzpos:
2003         kfree(pzpos);
2004         return ret;
2005 }
2006
2007 static void vop_post_config(struct drm_crtc *crtc)
2008 {
2009         struct vop *vop = to_vop(crtc);
2010         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2011         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2012         u16 vtotal = mode->crtc_vtotal;
2013         u16 hdisplay = mode->crtc_hdisplay;
2014         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2015         u16 vdisplay = mode->crtc_vdisplay;
2016         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2017         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
2018         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
2019         u16 hact_end, vact_end;
2020         u32 val;
2021
2022         hact_st += hdisplay * (100 - s->left_margin) / 200;
2023         hact_end = hact_st + hsize;
2024         val = hact_st << 16;
2025         val |= hact_end;
2026         VOP_CTRL_SET(vop, hpost_st_end, val);
2027         vact_st += vdisplay * (100 - s->top_margin) / 200;
2028         vact_end = vact_st + vsize;
2029         val = vact_st << 16;
2030         val |= vact_end;
2031         VOP_CTRL_SET(vop, vpost_st_end, val);
2032         val = scl_cal_scale2(vdisplay, vsize) << 16;
2033         val |= scl_cal_scale2(hdisplay, hsize);
2034         VOP_CTRL_SET(vop, post_scl_factor, val);
2035         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
2036         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2037                 u16 vact_st_f1 = vtotal + vact_st + 1;
2038                 u16 vact_end_f1 = vact_st_f1 + vsize;
2039
2040                 val = vact_st_f1 << 16 | vact_end_f1;
2041                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
2042         }
2043 }
2044
2045 static void vop_cfg_update(struct drm_crtc *crtc,
2046                            struct drm_crtc_state *old_crtc_state)
2047 {
2048         struct rockchip_crtc_state *s =
2049                         to_rockchip_crtc_state(crtc->state);
2050         struct vop *vop = to_vop(crtc);
2051
2052         spin_lock(&vop->reg_lock);
2053
2054         if (s->afbdc_en) {
2055                 uint32_t pic_size;
2056
2057                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
2058                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
2059                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
2060                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
2061                 pic_size = (s->afbdc_win_width & 0xffff);
2062                 pic_size |= s->afbdc_win_height << 16;
2063                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
2064         }
2065
2066         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
2067         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
2068         vop_post_config(crtc);
2069
2070         spin_unlock(&vop->reg_lock);
2071 }
2072
2073 static bool vop_fs_irq_is_pending(struct vop *vop)
2074 {
2075         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
2076 }
2077
2078 static void vop_wait_for_irq_handler(struct vop *vop)
2079 {
2080         bool pending;
2081         int ret;
2082
2083         /*
2084          * Spin until frame start interrupt status bit goes low, which means
2085          * that interrupt handler was invoked and cleared it. The timeout of
2086          * 10 msecs is really too long, but it is just a safety measure if
2087          * something goes really wrong. The wait will only happen in the very
2088          * unlikely case of a vblank happening exactly at the same time and
2089          * shouldn't exceed microseconds range.
2090          */
2091         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
2092                                         !pending, 0, 10 * 1000);
2093         if (ret)
2094                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
2095
2096         synchronize_irq(vop->irq);
2097 }
2098
2099 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
2100                                   struct drm_crtc_state *old_crtc_state)
2101 {
2102         struct vop *vop = to_vop(crtc);
2103
2104         vop_cfg_update(crtc, old_crtc_state);
2105
2106         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
2107                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
2108                 int ret;
2109
2110                 if (need_wait_vblank) {
2111                         bool active;
2112
2113                         disable_irq(vop->irq);
2114                         drm_crtc_vblank_get(crtc);
2115                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
2116
2117                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
2118                                                         vop, active, active,
2119                                                         0, 50 * 1000);
2120                         if (ret)
2121                                 dev_err(vop->dev, "wait fs irq timeout\n");
2122
2123                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
2124                         vop_cfg_done(vop);
2125
2126                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
2127                                                         vop, active, active,
2128                                                         0, 50 * 1000);
2129                         if (ret)
2130                                 dev_err(vop->dev, "wait line flag timeout\n");
2131
2132                         enable_irq(vop->irq);
2133                 }
2134                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
2135                 if (ret)
2136                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
2137                                 ret);
2138
2139                 if (need_wait_vblank) {
2140                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
2141                         drm_crtc_vblank_put(crtc);
2142                 }
2143
2144                 vop->is_iommu_enabled = true;
2145         }
2146
2147         vop_cfg_done(vop);
2148
2149         /*
2150          * There is a (rather unlikely) possiblity that a vblank interrupt
2151          * fired before we set the cfg_done bit. To avoid spuriously
2152          * signalling flip completion we need to wait for it to finish.
2153          */
2154         vop_wait_for_irq_handler(vop);
2155 }
2156
2157 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
2158                                   struct drm_crtc_state *old_crtc_state)
2159 {
2160         struct vop *vop = to_vop(crtc);
2161
2162         if (crtc->state->event) {
2163                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
2164
2165                 vop->event = crtc->state->event;
2166                 crtc->state->event = NULL;
2167         }
2168 }
2169
2170 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
2171         .load_lut = vop_crtc_load_lut,
2172         .enable = vop_crtc_enable,
2173         .disable = vop_crtc_disable,
2174         .mode_fixup = vop_crtc_mode_fixup,
2175         .atomic_check = vop_crtc_atomic_check,
2176         .atomic_flush = vop_crtc_atomic_flush,
2177         .atomic_begin = vop_crtc_atomic_begin,
2178 };
2179
2180 static void vop_crtc_destroy(struct drm_crtc *crtc)
2181 {
2182         drm_crtc_cleanup(crtc);
2183 }
2184
2185 static void vop_crtc_reset(struct drm_crtc *crtc)
2186 {
2187         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
2188         struct rockchip_drm_private *private = crtc->dev->dev_private;
2189         struct vop *vop = to_vop(crtc);
2190
2191         if (crtc->state) {
2192                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
2193                 kfree(s);
2194         }
2195
2196         s = kzalloc(sizeof(*s), GFP_KERNEL);
2197         if (!s)
2198                 return;
2199         crtc->state = &s->base;
2200         crtc->state->crtc = crtc;
2201
2202         if (vop->dclk_source) {
2203                 struct clk *parent;
2204
2205                 parent = clk_get_parent(vop->dclk_source);
2206                 if (parent) {
2207                         if (clk_is_match(private->default_pll.pll, parent))
2208                                 s->pll = &private->default_pll;
2209                         else if (clk_is_match(private->hdmi_pll.pll, parent))
2210                                 s->pll = &private->hdmi_pll;
2211                         if (s->pll)
2212                                 s->pll->use_count++;
2213                 }
2214         }
2215         s->left_margin = 100;
2216         s->right_margin = 100;
2217         s->top_margin = 100;
2218         s->bottom_margin = 100;
2219 }
2220
2221 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
2222 {
2223         struct rockchip_crtc_state *rockchip_state, *old_state;
2224
2225         old_state = to_rockchip_crtc_state(crtc->state);
2226         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
2227         if (!rockchip_state)
2228                 return NULL;
2229
2230         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
2231         return &rockchip_state->base;
2232 }
2233
2234 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
2235                                    struct drm_crtc_state *state)
2236 {
2237         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2238
2239         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
2240         kfree(s);
2241 }
2242
2243 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
2244                                         const struct drm_crtc_state *state,
2245                                         struct drm_property *property,
2246                                         uint64_t *val)
2247 {
2248         struct drm_device *drm_dev = crtc->dev;
2249         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2250         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2251
2252         if (property == mode_config->tv_left_margin_property) {
2253                 *val = s->left_margin;
2254                 return 0;
2255         }
2256
2257         if (property == mode_config->tv_right_margin_property) {
2258                 *val = s->right_margin;
2259                 return 0;
2260         }
2261
2262         if (property == mode_config->tv_top_margin_property) {
2263                 *val = s->top_margin;
2264                 return 0;
2265         }
2266
2267         if (property == mode_config->tv_bottom_margin_property) {
2268                 *val = s->bottom_margin;
2269                 return 0;
2270         }
2271
2272         DRM_ERROR("failed to get vop crtc property\n");
2273         return -EINVAL;
2274 }
2275
2276 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
2277                                         struct drm_crtc_state *state,
2278                                         struct drm_property *property,
2279                                         uint64_t val)
2280 {
2281         struct drm_device *drm_dev = crtc->dev;
2282         struct drm_mode_config *mode_config = &drm_dev->mode_config;
2283         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
2284
2285         if (property == mode_config->tv_left_margin_property) {
2286                 s->left_margin = val;
2287                 return 0;
2288         }
2289
2290         if (property == mode_config->tv_right_margin_property) {
2291                 s->right_margin = val;
2292                 return 0;
2293         }
2294
2295         if (property == mode_config->tv_top_margin_property) {
2296                 s->top_margin = val;
2297                 return 0;
2298         }
2299
2300         if (property == mode_config->tv_bottom_margin_property) {
2301                 s->bottom_margin = val;
2302                 return 0;
2303         }
2304
2305         DRM_ERROR("failed to set vop crtc property\n");
2306         return -EINVAL;
2307 }
2308
2309 static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2310                                u16 *blue, uint32_t start, uint32_t size)
2311 {
2312         struct vop *vop = to_vop(crtc);
2313         int end = min_t(u32, start + size, vop->lut_len);
2314         int i;
2315
2316         if (!vop->lut)
2317                 return;
2318
2319         for (i = start; i < end; i++)
2320                 rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
2321                                                blue[i], i);
2322
2323         vop_crtc_load_lut(crtc);
2324 }
2325
2326 static const struct drm_crtc_funcs vop_crtc_funcs = {
2327         .gamma_set = vop_crtc_gamma_set,
2328         .set_config = drm_atomic_helper_set_config,
2329         .page_flip = drm_atomic_helper_page_flip,
2330         .destroy = vop_crtc_destroy,
2331         .reset = vop_crtc_reset,
2332         .set_property = drm_atomic_helper_crtc_set_property,
2333         .atomic_get_property = vop_crtc_atomic_get_property,
2334         .atomic_set_property = vop_crtc_atomic_set_property,
2335         .atomic_duplicate_state = vop_crtc_duplicate_state,
2336         .atomic_destroy_state = vop_crtc_destroy_state,
2337 };
2338
2339 static void vop_handle_vblank(struct vop *vop)
2340 {
2341         struct drm_device *drm = vop->drm_dev;
2342         struct drm_crtc *crtc = &vop->crtc;
2343         unsigned long flags;
2344
2345         if (!vop_is_cfg_done_complete(vop))
2346                 return;
2347
2348         if (vop->event) {
2349                 spin_lock_irqsave(&drm->event_lock, flags);
2350
2351                 drm_crtc_send_vblank_event(crtc, vop->event);
2352                 drm_crtc_vblank_put(crtc);
2353                 vop->event = NULL;
2354
2355                 spin_unlock_irqrestore(&drm->event_lock, flags);
2356         }
2357         if (!completion_done(&vop->wait_update_complete))
2358                 complete(&vop->wait_update_complete);
2359 }
2360
2361 static irqreturn_t vop_isr(int irq, void *data)
2362 {
2363         struct vop *vop = data;
2364         struct drm_crtc *crtc = &vop->crtc;
2365         uint32_t active_irqs;
2366         unsigned long flags;
2367         int ret = IRQ_NONE;
2368
2369         /*
2370          * interrupt register has interrupt status, enable and clear bits, we
2371          * must hold irq_lock to avoid a race with enable/disable_vblank().
2372         */
2373         spin_lock_irqsave(&vop->irq_lock, flags);
2374
2375         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2376         /* Clear all active interrupt sources */
2377         if (active_irqs)
2378                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2379
2380         spin_unlock_irqrestore(&vop->irq_lock, flags);
2381
2382         /* This is expected for vop iommu irqs, since the irq is shared */
2383         if (!active_irqs)
2384                 return IRQ_NONE;
2385
2386         if (active_irqs & DSP_HOLD_VALID_INTR) {
2387                 complete(&vop->dsp_hold_completion);
2388                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2389                 ret = IRQ_HANDLED;
2390         }
2391
2392         if (active_irqs & LINE_FLAG_INTR) {
2393                 complete(&vop->line_flag_completion);
2394                 active_irqs &= ~LINE_FLAG_INTR;
2395                 ret = IRQ_HANDLED;
2396         }
2397
2398         if (active_irqs & FS_INTR) {
2399                 drm_crtc_handle_vblank(crtc);
2400                 vop_handle_vblank(vop);
2401                 active_irqs &= ~FS_INTR;
2402                 ret = IRQ_HANDLED;
2403         }
2404
2405         /* Unhandled irqs are spurious. */
2406         if (active_irqs)
2407                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2408
2409         return ret;
2410 }
2411
2412 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2413                           unsigned long possible_crtcs)
2414 {
2415         struct rockchip_drm_private *private = vop->drm_dev->dev_private;
2416         struct drm_plane *share = NULL;
2417         unsigned int rotations = 0;
2418         struct drm_property *prop;
2419         uint64_t feature = 0;
2420         int ret;
2421
2422         if (win->parent)
2423                 share = &win->parent->base;
2424
2425         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2426                                    possible_crtcs, &vop_plane_funcs,
2427                                    win->data_formats, win->nformats, win->type);
2428         if (ret) {
2429                 DRM_ERROR("failed to initialize plane\n");
2430                 return ret;
2431         }
2432         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2433         drm_object_attach_property(&win->base.base,
2434                                    vop->plane_zpos_prop, win->win_id);
2435
2436         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2437                 rotations |= BIT(DRM_REFLECT_X);
2438
2439         if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
2440                 rotations |= BIT(DRM_REFLECT_Y);
2441
2442                 prop = drm_property_create_bool(vop->drm_dev,
2443                                                 DRM_MODE_PROP_ATOMIC,
2444                                                 "LOGO_YMIRROR");
2445                 if (!prop)
2446                         return -ENOMEM;
2447                 private->logo_ymirror_prop = prop;
2448         }
2449
2450         if (rotations) {
2451                 rotations |= BIT(DRM_ROTATE_0);
2452                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2453                                                          rotations);
2454                 if (!prop) {
2455                         DRM_ERROR("failed to create zpos property\n");
2456                         return -EINVAL;
2457                 }
2458                 drm_object_attach_property(&win->base.base, prop,
2459                                            BIT(DRM_ROTATE_0));
2460                 win->rotation_prop = prop;
2461         }
2462         if (win->phy->scl)
2463                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2464         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2465             VOP_WIN_SUPPORT(vop, win, alpha_en))
2466                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2467
2468         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2469                                    feature);
2470
2471         return 0;
2472 }
2473
2474 static int vop_create_crtc(struct vop *vop)
2475 {
2476         struct device *dev = vop->dev;
2477         const struct vop_data *vop_data = vop->data;
2478         struct drm_device *drm_dev = vop->drm_dev;
2479         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2480         struct drm_crtc *crtc = &vop->crtc;
2481         struct device_node *port;
2482         uint64_t feature = 0;
2483         int ret;
2484         int i;
2485
2486         /*
2487          * Create drm_plane for primary and cursor planes first, since we need
2488          * to pass them to drm_crtc_init_with_planes, which sets the
2489          * "possible_crtcs" to the newly initialized crtc.
2490          */
2491         for (i = 0; i < vop->num_wins; i++) {
2492                 struct vop_win *win = &vop->win[i];
2493
2494                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2495                     win->type != DRM_PLANE_TYPE_CURSOR)
2496                         continue;
2497
2498                 ret = vop_plane_init(vop, win, 0);
2499                 if (ret)
2500                         goto err_cleanup_planes;
2501
2502                 plane = &win->base;
2503                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2504                         primary = plane;
2505                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2506                         cursor = plane;
2507
2508         }
2509
2510         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2511                                         &vop_crtc_funcs, NULL);
2512         if (ret)
2513                 goto err_cleanup_planes;
2514
2515         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2516
2517         /*
2518          * Create drm_planes for overlay windows with possible_crtcs restricted
2519          * to the newly created crtc.
2520          */
2521         for (i = 0; i < vop->num_wins; i++) {
2522                 struct vop_win *win = &vop->win[i];
2523                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2524
2525                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2526                         continue;
2527
2528                 ret = vop_plane_init(vop, win, possible_crtcs);
2529                 if (ret)
2530                         goto err_cleanup_crtc;
2531         }
2532
2533         port = of_get_child_by_name(dev->of_node, "port");
2534         if (!port) {
2535                 DRM_ERROR("no port node found in %s\n",
2536                           dev->of_node->full_name);
2537                 ret = -ENOENT;
2538                 goto err_cleanup_crtc;
2539         }
2540
2541         init_completion(&vop->dsp_hold_completion);
2542         init_completion(&vop->wait_update_complete);
2543         init_completion(&vop->line_flag_completion);
2544         crtc->port = port;
2545         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2546
2547         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2548         if (ret)
2549                 goto err_unregister_crtc_funcs;
2550 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2551         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2552
2553         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2554         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2555         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2556         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2557 #undef VOP_ATTACH_MODE_CONFIG_PROP
2558
2559         if (vop_data->feature & VOP_FEATURE_AFBDC)
2560                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2561         drm_object_attach_property(&crtc->base, vop->feature_prop,
2562                                    feature);
2563         if (vop->lut_regs) {
2564                 u16 *r_base, *g_base, *b_base;
2565                 u32 lut_len = vop->lut_len;
2566
2567                 drm_mode_crtc_set_gamma_size(crtc, lut_len);
2568                 vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
2569                                               GFP_KERNEL);
2570                 if (!vop->lut)
2571                         return -ENOMEM;
2572
2573                 r_base = crtc->gamma_store;
2574                 g_base = r_base + crtc->gamma_size;
2575                 b_base = g_base + crtc->gamma_size;
2576
2577                 for (i = 0; i < lut_len; i++) {
2578                         vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
2579                         rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
2580                                                        &g_base[i], &b_base[i],
2581                                                        i);
2582                 }
2583         }
2584
2585         return 0;
2586
2587 err_unregister_crtc_funcs:
2588         rockchip_unregister_crtc_funcs(crtc);
2589 err_cleanup_crtc:
2590         drm_crtc_cleanup(crtc);
2591 err_cleanup_planes:
2592         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2593                                  head)
2594                 drm_plane_cleanup(plane);
2595         return ret;
2596 }
2597
2598 static void vop_destroy_crtc(struct vop *vop)
2599 {
2600         struct drm_crtc *crtc = &vop->crtc;
2601         struct drm_device *drm_dev = vop->drm_dev;
2602         struct drm_plane *plane, *tmp;
2603
2604         rockchip_unregister_crtc_funcs(crtc);
2605         of_node_put(crtc->port);
2606
2607         /*
2608          * We need to cleanup the planes now.  Why?
2609          *
2610          * The planes are "&vop->win[i].base".  That means the memory is
2611          * all part of the big "struct vop" chunk of memory.  That memory
2612          * was devm allocated and associated with this component.  We need to
2613          * free it ourselves before vop_unbind() finishes.
2614          */
2615         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2616                                  head)
2617                 vop_plane_destroy(plane);
2618
2619         /*
2620          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2621          * references the CRTC.
2622          */
2623         drm_crtc_cleanup(crtc);
2624 }
2625
2626 /*
2627  * Initialize the vop->win array elements.
2628  */
2629 static int vop_win_init(struct vop *vop)
2630 {
2631         const struct vop_data *vop_data = vop->data;
2632         unsigned int i, j;
2633         unsigned int num_wins = 0;
2634         struct drm_property *prop;
2635         static const struct drm_prop_enum_list props[] = {
2636                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2637                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2638         };
2639         static const struct drm_prop_enum_list crtc_props[] = {
2640                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2641         };
2642
2643         for (i = 0; i < vop_data->win_size; i++) {
2644                 struct vop_win *vop_win = &vop->win[num_wins];
2645                 const struct vop_win_data *win_data = &vop_data->win[i];
2646
2647                 if (!win_data->phy)
2648                         continue;
2649
2650                 vop_win->phy = win_data->phy;
2651                 vop_win->csc = win_data->csc;
2652                 vop_win->offset = win_data->base;
2653                 vop_win->type = win_data->type;
2654                 vop_win->data_formats = win_data->phy->data_formats;
2655                 vop_win->nformats = win_data->phy->nformats;
2656                 vop_win->vop = vop;
2657                 vop_win->win_id = i;
2658                 vop_win->area_id = 0;
2659                 num_wins++;
2660
2661                 for (j = 0; j < win_data->area_size; j++) {
2662                         struct vop_win *vop_area = &vop->win[num_wins];
2663                         const struct vop_win_phy *area = win_data->area[j];
2664
2665                         vop_area->parent = vop_win;
2666                         vop_area->offset = vop_win->offset;
2667                         vop_area->phy = area;
2668                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2669                         vop_area->data_formats = vop_win->data_formats;
2670                         vop_area->nformats = vop_win->nformats;
2671                         vop_area->vop = vop;
2672                         vop_area->win_id = i;
2673                         vop_area->area_id = j;
2674                         num_wins++;
2675                 }
2676         }
2677
2678         vop->num_wins = num_wins;
2679
2680         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2681                                          "ZPOS", 0, vop->data->win_size);
2682         if (!prop) {
2683                 DRM_ERROR("failed to create zpos property\n");
2684                 return -EINVAL;
2685         }
2686         vop->plane_zpos_prop = prop;
2687
2688         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2689                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2690                                 props, ARRAY_SIZE(props),
2691                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2692                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2693         if (!vop->plane_feature_prop) {
2694                 DRM_ERROR("failed to create feature property\n");
2695                 return -EINVAL;
2696         }
2697
2698         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2699                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2700                                 crtc_props, ARRAY_SIZE(crtc_props),
2701                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2702         if (!vop->feature_prop) {
2703                 DRM_ERROR("failed to create vop feature property\n");
2704                 return -EINVAL;
2705         }
2706
2707         return 0;
2708 }
2709
2710 /**
2711  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2712  * @crtc: CRTC to enable line flag
2713  * @line_num: interested line number
2714  * @mstimeout: millisecond for timeout
2715  *
2716  * Driver would hold here until the interested line flag interrupt have
2717  * happened or timeout to wait.
2718  *
2719  * Returns:
2720  * Zero on success, negative errno on failure.
2721  */
2722 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2723                                 unsigned int mstimeout)
2724 {
2725         struct vop *vop = to_vop(crtc);
2726         unsigned long jiffies_left;
2727         int ret = 0;
2728
2729         if (!crtc || !vop->is_enabled)
2730                 return -ENODEV;
2731
2732         mutex_lock(&vop->vop_lock);
2733
2734         if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
2735                 ret = -EINVAL;
2736                 goto out;
2737         }
2738
2739         if (vop_line_flag_irq_is_enabled(vop)) {
2740                 ret = -EBUSY;
2741                 goto out;
2742         }
2743
2744         reinit_completion(&vop->line_flag_completion);
2745         vop_line_flag_irq_enable(vop, line_num);
2746
2747         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2748                                                    msecs_to_jiffies(mstimeout));
2749         vop_line_flag_irq_disable(vop);
2750
2751         if (jiffies_left == 0) {
2752                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2753                 ret = -ETIMEDOUT;
2754                 goto out;
2755         }
2756
2757 out:
2758         mutex_unlock(&vop->vop_lock);
2759
2760         return ret;
2761 }
2762 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2763
2764 static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
2765                              void *data)
2766 {
2767         if (event == DEVFREQ_PRECHANGE)
2768                 mutex_lock(&dmc_vop->vop_lock);
2769         else if (event == DEVFREQ_POSTCHANGE)
2770                 mutex_unlock(&dmc_vop->vop_lock);
2771
2772         return NOTIFY_OK;
2773 }
2774
2775 int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
2776 {
2777         if (!dmc_vop)
2778                 return -ENOMEM;
2779
2780         dmc_vop->devfreq = devfreq;
2781         dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
2782         devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
2783                                   DEVFREQ_TRANSITION_NOTIFIER);
2784         return 0;
2785 }
2786 EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
2787
2788 static int vop_bind(struct device *dev, struct device *master, void *data)
2789 {
2790         struct platform_device *pdev = to_platform_device(dev);
2791         const struct vop_data *vop_data;
2792         struct drm_device *drm_dev = data;
2793         struct vop *vop;
2794         struct resource *res;
2795         size_t alloc_size;
2796         int ret, irq, i;
2797         int num_wins = 0;
2798
2799         vop_data = of_device_get_match_data(dev);
2800         if (!vop_data)
2801                 return -ENODEV;
2802
2803         for (i = 0; i < vop_data->win_size; i++) {
2804                 const struct vop_win_data *win_data = &vop_data->win[i];
2805
2806                 num_wins += win_data->area_size + 1;
2807         }
2808
2809         /* Allocate vop struct and its vop_win array */
2810         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2811         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2812         if (!vop)
2813                 return -ENOMEM;
2814
2815         vop->dev = dev;
2816         vop->data = vop_data;
2817         vop->drm_dev = drm_dev;
2818         vop->num_wins = num_wins;
2819         dev_set_drvdata(dev, vop);
2820
2821         ret = vop_win_init(vop);
2822         if (ret)
2823                 return ret;
2824
2825         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
2826         if (!res) {
2827                 dev_warn(vop->dev, "failed to get vop register byname\n");
2828                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2829         }
2830         vop->regs = devm_ioremap_resource(dev, res);
2831         if (IS_ERR(vop->regs))
2832                 return PTR_ERR(vop->regs);
2833         vop->len = resource_size(res);
2834
2835         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2836         if (!vop->regsbak)
2837                 return -ENOMEM;
2838
2839         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
2840         vop->lut_regs = devm_ioremap_resource(dev, res);
2841         if (IS_ERR(vop->lut_regs)) {
2842                 dev_warn(vop->dev, "failed to get vop lut registers\n");
2843                 vop->lut_regs = NULL;
2844         }
2845         if (vop->lut_regs) {
2846                 vop->lut_len = resource_size(res) / sizeof(*vop->lut);
2847                 if (vop->lut_len != 256 && vop->lut_len != 1024) {
2848                         dev_err(vop->dev, "unsupport lut sizes %d\n",
2849                                 vop->lut_len);
2850                         return -EINVAL;
2851                 }
2852         }
2853
2854         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2855         if (IS_ERR(vop->hclk)) {
2856                 dev_err(vop->dev, "failed to get hclk source\n");
2857                 return PTR_ERR(vop->hclk);
2858         }
2859         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2860         if (IS_ERR(vop->aclk)) {
2861                 dev_err(vop->dev, "failed to get aclk source\n");
2862                 return PTR_ERR(vop->aclk);
2863         }
2864         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2865         if (IS_ERR(vop->dclk)) {
2866                 dev_err(vop->dev, "failed to get dclk source\n");
2867                 return PTR_ERR(vop->dclk);
2868         }
2869
2870         vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
2871         if (PTR_ERR(vop->dclk_source) == -ENOENT) {
2872                 vop->dclk_source = NULL;
2873         } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
2874                 return -EPROBE_DEFER;
2875         } else if (IS_ERR(vop->dclk_source)) {
2876                 dev_err(vop->dev, "failed to get dclk source parent\n");
2877                 return PTR_ERR(vop->dclk_source);
2878         }
2879
2880         irq = platform_get_irq(pdev, 0);
2881         if (irq < 0) {
2882                 dev_err(dev, "cannot find irq for vop\n");
2883                 return irq;
2884         }
2885         vop->irq = (unsigned int)irq;
2886
2887         spin_lock_init(&vop->reg_lock);
2888         spin_lock_init(&vop->irq_lock);
2889         mutex_init(&vop->vop_lock);
2890
2891         mutex_init(&vop->vsync_mutex);
2892
2893         ret = devm_request_irq(dev, vop->irq, vop_isr,
2894                                IRQF_SHARED, dev_name(dev), vop);
2895         if (ret)
2896                 return ret;
2897
2898         /* IRQ is initially disabled; it gets enabled in power_on */
2899         disable_irq(vop->irq);
2900
2901         ret = vop_create_crtc(vop);
2902         if (ret)
2903                 return ret;
2904
2905         pm_runtime_enable(&pdev->dev);
2906
2907         dmc_vop = vop;
2908
2909         return 0;
2910 }
2911
2912 static void vop_unbind(struct device *dev, struct device *master, void *data)
2913 {
2914         struct vop *vop = dev_get_drvdata(dev);
2915
2916         pm_runtime_disable(dev);
2917         vop_destroy_crtc(vop);
2918 }
2919
2920 const struct component_ops vop_component_ops = {
2921         .bind = vop_bind,
2922         .unbind = vop_unbind,
2923 };
2924 EXPORT_SYMBOL_GPL(vop_component_ops);