2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
19 * major: IP major vertion, used for IP structure
20 * minor: big feature change under same structure
22 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
23 #define VOP_MAJOR(version) ((version) >> 8)
24 #define VOP_MINOR(version) ((version) & 0xff)
26 #define AFBDC_FMT_RGB565 0x0
27 #define AFBDC_FMT_U8U8U8U8 0x5
28 #define AFBDC_FMT_U8U8U8 0x4
30 enum cabc_stage_mode {
31 LAST_FRAME_PWM_VAL = 0x0,
32 CUR_FRAME_PWM_VAL = 0x1,
36 enum cabc_stage_up_mode {
52 enum vop_data_format {
70 uint32_t begin_minor:4;
73 uint32_t write_mask:1;
77 struct vop_reg y2r_en;
78 struct vop_reg r2r_en;
79 struct vop_reg r2y_en;
87 struct vop_reg standby;
88 struct vop_reg htotal_pw;
89 struct vop_reg hact_st_end;
90 struct vop_reg vtotal_pw;
91 struct vop_reg vact_st_end;
92 struct vop_reg vact_st_end_f1;
93 struct vop_reg vs_st_end_f1;
94 struct vop_reg hpost_st_end;
95 struct vop_reg vpost_st_end;
96 struct vop_reg vpost_st_end_f1;
97 struct vop_reg post_scl_factor;
98 struct vop_reg post_scl_ctrl;
99 struct vop_reg dsp_interlace;
100 struct vop_reg global_regdone_en;
101 struct vop_reg auto_gate_en;
102 struct vop_reg post_lb_mode;
103 struct vop_reg dsp_layer_sel;
104 struct vop_reg overlay_mode;
105 struct vop_reg core_dclk_div;
106 struct vop_reg dclk_ddr;
107 struct vop_reg p2i_en;
108 struct vop_reg rgb_en;
109 struct vop_reg edp_en;
110 struct vop_reg hdmi_en;
111 struct vop_reg mipi_en;
112 struct vop_reg dp_en;
113 struct vop_reg dclk_pol;
114 struct vop_reg pin_pol;
115 struct vop_reg rgb_dclk_pol;
116 struct vop_reg rgb_pin_pol;
117 struct vop_reg hdmi_dclk_pol;
118 struct vop_reg hdmi_pin_pol;
119 struct vop_reg edp_dclk_pol;
120 struct vop_reg edp_pin_pol;
121 struct vop_reg mipi_dclk_pol;
122 struct vop_reg mipi_pin_pol;
123 struct vop_reg dp_dclk_pol;
124 struct vop_reg dp_pin_pol;
125 struct vop_reg dither_up;
126 struct vop_reg dither_down;
128 struct vop_reg sw_dac_sel;
129 struct vop_reg tve_sw_mode;
130 struct vop_reg tve_dclk_pol;
131 struct vop_reg tve_dclk_en;
132 struct vop_reg sw_genlock;
133 struct vop_reg sw_uv_offset_en;
134 struct vop_reg dsp_out_yuv;
135 struct vop_reg dsp_data_swap;
136 struct vop_reg dsp_ccir656_avg;
137 struct vop_reg dsp_black;
138 struct vop_reg dsp_blank;
139 struct vop_reg dsp_outzero;
140 struct vop_reg update_gamma_lut;
141 struct vop_reg lut_buffer_index;
142 struct vop_reg dsp_lut_en;
144 struct vop_reg out_mode;
146 struct vop_reg xmirror;
147 struct vop_reg ymirror;
148 struct vop_reg dsp_background;
151 struct vop_reg afbdc_en;
152 struct vop_reg afbdc_sel;
153 struct vop_reg afbdc_format;
154 struct vop_reg afbdc_hreg_block_split;
155 struct vop_reg afbdc_pic_size;
156 struct vop_reg afbdc_hdr_ptr;
157 struct vop_reg afbdc_rstn;
160 struct vop_reg cabc_total_num;
161 struct vop_reg cabc_config_mode;
162 struct vop_reg cabc_stage_up_mode;
163 struct vop_reg cabc_scale_cfg_value;
164 struct vop_reg cabc_scale_cfg_enable;
165 struct vop_reg cabc_global_dn_limit_en;
166 struct vop_reg cabc_lut_en;
167 struct vop_reg cabc_en;
168 struct vop_reg cabc_handle_en;
169 struct vop_reg cabc_stage_up;
170 struct vop_reg cabc_stage_down;
171 struct vop_reg cabc_global_dn;
172 struct vop_reg cabc_calc_pixel_num;
174 struct vop_reg cfg_done;
180 struct vop_reg line_flag_num[2];
181 struct vop_reg enable;
182 struct vop_reg clear;
183 struct vop_reg status;
186 struct vop_scl_extension {
187 struct vop_reg cbcr_vsd_mode;
188 struct vop_reg cbcr_vsu_mode;
189 struct vop_reg cbcr_hsd_mode;
190 struct vop_reg cbcr_ver_scl_mode;
191 struct vop_reg cbcr_hor_scl_mode;
192 struct vop_reg yrgb_vsd_mode;
193 struct vop_reg yrgb_vsu_mode;
194 struct vop_reg yrgb_hsd_mode;
195 struct vop_reg yrgb_ver_scl_mode;
196 struct vop_reg yrgb_hor_scl_mode;
197 struct vop_reg line_load_mode;
198 struct vop_reg cbcr_axi_gather_num;
199 struct vop_reg yrgb_axi_gather_num;
200 struct vop_reg vsd_cbcr_gt2;
201 struct vop_reg vsd_cbcr_gt4;
202 struct vop_reg vsd_yrgb_gt2;
203 struct vop_reg vsd_yrgb_gt4;
204 struct vop_reg bic_coe_sel;
205 struct vop_reg cbcr_axi_gather_en;
206 struct vop_reg yrgb_axi_gather_en;
207 struct vop_reg lb_mode;
210 struct vop_scl_regs {
211 const struct vop_scl_extension *ext;
213 struct vop_reg scale_yrgb_x;
214 struct vop_reg scale_yrgb_y;
215 struct vop_reg scale_cbcr_x;
216 struct vop_reg scale_cbcr_y;
219 struct vop_csc_table {
220 const uint32_t *y2r_bt601;
221 const uint32_t *y2r_bt601_12_235;
222 const uint32_t *y2r_bt601_10bit;
223 const uint32_t *y2r_bt601_10bit_12_235;
224 const uint32_t *r2y_bt601;
225 const uint32_t *r2y_bt601_12_235;
226 const uint32_t *r2y_bt601_10bit;
227 const uint32_t *r2y_bt601_10bit_12_235;
229 const uint32_t *y2r_bt709;
230 const uint32_t *y2r_bt709_10bit;
231 const uint32_t *r2y_bt709;
232 const uint32_t *r2y_bt709_10bit;
234 const uint32_t *y2r_bt2020;
235 const uint32_t *r2y_bt2020;
237 const uint32_t *r2r_bt709_to_bt2020;
238 const uint32_t *r2r_bt2020_to_bt709;
248 VOP_CSC_R2R_BT2020_TO_BT709,
249 VOP_CSC_R2R_BT709_TO_2020,
252 enum _vop_overlay_mode {
258 const struct vop_scl_regs *scl;
259 const uint32_t *data_formats;
263 struct vop_reg enable;
264 struct vop_reg format;
265 struct vop_reg fmt_10;
266 struct vop_reg xmirror;
267 struct vop_reg ymirror;
268 struct vop_reg rb_swap;
269 struct vop_reg act_info;
270 struct vop_reg dsp_info;
271 struct vop_reg dsp_st;
272 struct vop_reg yrgb_mst;
273 struct vop_reg uv_mst;
274 struct vop_reg yrgb_vir;
275 struct vop_reg uv_vir;
277 struct vop_reg channel;
278 struct vop_reg dst_alpha_ctl;
279 struct vop_reg src_alpha_ctl;
280 struct vop_reg alpha_mode;
281 struct vop_reg alpha_en;
282 struct vop_reg key_color;
283 struct vop_reg key_en;
286 struct vop_win_data {
288 enum drm_plane_type type;
289 const struct vop_win_phy *phy;
290 const struct vop_win_phy **area;
291 const struct vop_csc *csc;
292 unsigned int area_size;
295 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
296 #define VOP_FEATURE_AFBDC BIT(1)
304 const struct vop_reg_data *init_table;
305 unsigned int table_size;
306 const struct vop_ctrl *ctrl;
307 const struct vop_intr *intr;
308 const struct vop_win_data *win;
309 const struct vop_csc_table *csc_table;
310 unsigned int win_size;
312 struct vop_rect max_input;
313 struct vop_rect max_output;
317 #define CVBS_PAL_VDISPLAY 288
319 /* interrupt define */
320 #define DSP_HOLD_VALID_INTR (1 << 0)
321 #define FS_INTR (1 << 1)
322 #define LINE_FLAG_INTR (1 << 2)
323 #define BUS_ERROR_INTR (1 << 3)
324 #define FS_NEW_INTR (1 << 4)
325 #define ADDR_SAME_INTR (1 << 5)
326 #define LINE_FLAG1_INTR (1 << 6)
327 #define WIN0_EMPTY_INTR (1 << 7)
328 #define WIN1_EMPTY_INTR (1 << 8)
329 #define WIN2_EMPTY_INTR (1 << 9)
330 #define WIN3_EMPTY_INTR (1 << 10)
331 #define HWC_EMPTY_INTR (1 << 11)
332 #define POST_BUF_EMPTY_INTR (1 << 12)
333 #define PWM_GEN_INTR (1 << 13)
335 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
336 LINE_FLAG_INTR | BUS_ERROR_INTR | \
337 FS_NEW_INTR | LINE_FLAG1_INTR | \
338 WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
339 WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
340 HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR)
342 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
343 #define FS_INTR_EN(x) ((x) << 5)
344 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
345 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
346 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
347 #define FS_INTR_MASK (1 << 5)
348 #define LINE_FLAG_INTR_MASK (1 << 6)
349 #define BUS_ERROR_INTR_MASK (1 << 7)
351 #define INTR_CLR_SHIFT 8
352 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
353 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
354 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
355 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
357 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
358 #define DSP_LINE_NUM_MASK (0x1fff << 12)
360 /* src alpha ctrl define */
361 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
362 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
363 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
364 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
365 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
366 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
367 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
368 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
369 /* dst alpha ctrl define */
370 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
373 * display output interface supported by rockchip lcdc
375 #define ROCKCHIP_OUT_MODE_P888 0
376 #define ROCKCHIP_OUT_MODE_P666 1
377 #define ROCKCHIP_OUT_MODE_P565 2
378 #define ROCKCHIP_OUT_MODE_YUV420 14
379 /* for use special outface */
380 #define ROCKCHIP_OUT_MODE_AAAA 15
382 #define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
383 #define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
384 #define ROCKCHIP_DSP_MODE(type, mode) \
385 (DRM_MODE_CONNECTOR_##type << 16) | \
386 (ROCKCHIP_OUT_MODE_##mode & 0xffff)
393 enum global_blend_mode {
396 ALPHA_PER_PIX_GLOBAL,
399 enum alpha_cal_mode {
406 ALPHA_SRC_NO_PRE_MUL,
437 enum scale_down_mode {
438 SCALE_DOWN_BIL = 0x0,
442 enum dither_down_mode {
443 RGB888_TO_RGB565 = 0x0,
444 RGB888_TO_RGB666 = 0x1
447 enum dither_down_mode_sel {
448 DITHER_DOWN_ALLEGRO = 0x0,
449 DITHER_DOWN_FRC = 0x1
452 #define PRE_DITHER_DOWN_EN(x) ((x) << 0)
453 #define DITHER_DOWN_EN(x) ((x) << 1)
454 #define DITHER_DOWN_MODE(x) ((x) << 2)
455 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
463 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
464 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
465 #define SCL_MAX_VSKIPLINES 4
466 #define MIN_SCL_FT_AFTER_VSKIP 1
468 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
470 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
473 static inline uint16_t scl_cal_scale2(int src, int dst)
475 return ((src - 1) << 12) / (dst - 1);
478 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
479 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
480 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
482 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
487 act_height = (src_h + vskiplines - 1) / vskiplines;
489 if (act_height == dst_h)
490 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
492 return GET_SCL_FT_BILI_DN(act_height, dst_h);
495 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
505 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
509 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
510 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
516 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
521 lb_mode = LB_RGB_3840X2;
522 else if (width > 1920)
523 lb_mode = LB_RGB_2560X4;
525 lb_mode = LB_RGB_1920X5;
526 else if (width > 1280)
527 lb_mode = LB_YUV_3840X5;
529 lb_mode = LB_YUV_2560X8;
534 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
536 return us * mode->clock / mode->htotal / 1000;
539 extern const struct component_ops vop_component_ops;
540 #endif /* _ROCKCHIP_DRM_VOP_H */