2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * hjc <hjc@rock-chips.com>
5 * mark yao <mark.yao@rock-chips.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef _ROCKCHIP_LVDS_
18 #define _ROCKCHIP_LVDS_
20 #define RK3288_LVDS_CH0_REG0 0x00
21 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
22 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
23 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
24 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
25 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
26 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
27 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
28 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
30 #define RK3288_LVDS_CH0_REG1 0x04
31 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
32 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
33 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3)
34 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2)
35 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1)
36 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)
38 #define RK3288_LVDS_CH0_REG2 0x08
39 #define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7)
40 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6)
41 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5)
42 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4)
43 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3)
44 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2)
45 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1)
46 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)
48 #define RK3288_LVDS_CH0_REG3 0x0c
49 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff
51 #define RK3288_LVDS_CH0_REG4 0x10
52 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5)
53 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4)
54 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3)
55 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2)
56 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1)
57 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
59 #define RK3288_LVDS_CH0_REG5 0x14
60 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5)
61 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4)
62 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3)
63 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2)
64 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1)
65 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)
67 #define RK3288_LVDS_CFG_REGC 0x30
68 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00
69 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff
71 #define RK3288_LVDS_CH0_REGD 0x34
72 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f
74 #define RK3288_LVDS_CH0_REG20 0x80
75 #define RK3288_LVDS_CH0_REG20_MSB 0x45
76 #define RK3288_LVDS_CH0_REG20_LSB 0x44
78 #define RK3288_LVDS_CFG_REG21 0x84
79 #define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92
80 #define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00
81 #define RK3288_LVDS_CH1_OFFSET 0x100
83 /* fbdiv value is split over 2 registers, with bit8 in reg2 */
84 #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
85 (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
86 #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
87 (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
88 #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
89 (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
91 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3)
93 #define RK3366_GRF_SOC_CON0 0x0400
94 #define RK3366_LVDS_VOP_SEL_LIT (BITS_MASK(1, 1, 0) | BITS_EN(1, 0))
95 #define RK3366_LVDS_VOP_SEL_BIG (BITS_MASK(0, 1, 0) | BITS_EN(1, 0))
96 #define RK3366_GRF_SOC_CON5 0x0414
97 #define RK3366_GRF_SOC_CON6 0x0418
99 #define RK3368_GRF_SOC_CON7 0x041c
100 #define RK3368_GRF_SOC_CON15 0x043c
102 #define LVDS_FMT_MASK (0x07 << 16)
103 #define LVDS_MSB BIT(3)
104 #define LVDS_DUAL BIT(4)
105 #define LVDS_FMT_1 BIT(5)
106 #define LVDS_TTL_EN BIT(6)
107 #define LVDS_START_PHASE_RST_1 BIT(7)
108 #define LVDS_DCLK_INV BIT(8)
109 #define LVDS_CH0_EN BIT(11)
110 #define LVDS_CH1_EN BIT(12)
111 #define LVDS_PWRDN BIT(15)
113 #define LVDS_24BIT (0 << 1)
114 #define LVDS_18BIT (1 << 1)
115 #define LVDS_FORMAT_VESA (0 << 0)
116 #define LVDS_FORMAT_JEIDA (1 << 0)
118 #define BITS(x, bit) ((x) << (bit))
119 #define BITS_MASK(x, mask, bit) BITS((x) & (mask), bit)
120 #define BITS_EN(mask, bit) BITS(mask, bit + 16)
122 #define MIPIPHY_REG0 0x0000
124 #define MIPIPHY_REG1 0x0004
125 #define m_SYNC_RST BIT(0)
126 #define m_LDO_PWR_DOWN BIT(1)
127 #define m_PLL_PWR_DOWN BIT(2)
128 #define v_SYNC_RST(x) BITS_MASK(x, 1, 0)
129 #define v_LDO_PWR_DOWN(x) BITS_MASK(x, 1, 1)
130 #define v_PLL_PWR_DOWN(x) BITS_MASK(x, 1, 2)
132 #define MIPIPHY_REG3 0x000c
133 #define m_PREDIV GENMASK(4, 0)
134 #define m_FBDIV_MSB BIT(5)
135 #define v_PREDIV(x) BITS_MASK(x, 0x1f, 0)
136 #define v_FBDIV_MSB(x) BITS_MASK(x, 1, 5)
138 #define MIPIPHY_REG4 0x0010
139 #define v_FBDIV_LSB(x) BITS_MASK(x, 0xff, 0)
141 #define MIPIPHY_REGE0 0x0380
142 #define m_MSB_SEL BIT(0)
143 #define m_DIG_INTER_RST BIT(2)
144 #define m_LVDS_MODE_EN BIT(5)
145 #define m_TTL_MODE_EN BIT(6)
146 #define m_MIPI_MODE_EN BIT(7)
147 #define v_MSB_SEL(x) BITS_MASK(x, 1, 0)
148 #define v_DIG_INTER_RST(x) BITS_MASK(x, 1, 2)
149 #define v_LVDS_MODE_EN(x) BITS_MASK(x, 1, 5)
150 #define v_TTL_MODE_EN(x) BITS_MASK(x, 1, 6)
151 #define v_MIPI_MODE_EN(x) BITS_MASK(x, 1, 7)
153 #define MIPIPHY_REGE1 0x0384
154 #define m_DIG_INTER_EN BIT(7)
155 #define v_DIG_INTER_EN(x) BITS_MASK(x, 1, 7)
157 #define MIPIPHY_REGE3 0x038c
158 #define m_MIPI_EN BIT(0)
159 #define m_LVDS_EN BIT(1)
160 #define m_TTL_EN BIT(2)
161 #define v_MIPI_EN(x) BITS_MASK(x, 1, 0)
162 #define v_LVDS_EN(x) BITS_MASK(x, 1, 1)
163 #define v_TTL_EN(x) BITS_MASK(x, 1, 2)
165 #define MIPIPHY_REGE4 0x0390
166 #define m_VOCM GENMASK(5, 4)
167 #define m_DIFF_V GENMASK(7, 6)
169 #define v_VOCM(x) BITS_MASK(x, 3, 4)
170 #define v_DIFF_V(x) BITS_MASK(x, 3, 6)
172 #define MIPIPHY_REGE8 0x03a0
174 #define MIPIPHY_REGEB 0x03ac
175 #define v_PLL_PWR_OFF(x) BITS_MASK(x, 1, 2)
176 #define v_LANECLK_EN(x) BITS_MASK(x, 1, 3)
177 #define v_LANE3_EN(x) BITS_MASK(x, 1, 4)
178 #define v_LANE2_EN(x) BITS_MASK(x, 1, 5)
179 #define v_LANE1_EN(x) BITS_MASK(x, 1, 6)
180 #define v_LANE0_EN(x) BITS_MASK(x, 1, 7)
182 /* MIPI DSI Controller register */
183 #define MIPIC_PHY_RSTZ 0x00a0
184 #define m_PHY_ENABLE_CLK BIT(2)
185 #define MIPIC_PHY_STATUS 0x00b0
186 #define m_PHY_LOCK_STATUS BIT(0)
188 #define v_RK336X_LVDS_OUTPUT_FORMAT(x) (BITS_MASK(x, 3, 13) | BITS_EN(3, 13))
189 #define v_RK336X_LVDS_MSBSEL(x) (BITS_MASK(x, 1, 11) | BITS_EN(1, 11))
190 #define v_RK336X_LVDSMODE_EN(x) (BITS_MASK(x, 1, 12) | BITS_EN(1, 12))
191 #define v_RK336X_MIPIPHY_TTL_EN(x) (BITS_MASK(x, 1, 15) | BITS_EN(1, 15))
192 #define v_RK336X_MIPIPHY_LANE0_EN(x) (BITS_MASK(x, 1, 5) | BITS_EN(1, 5))
193 #define v_RK336X_MIPIDPI_FORCEX_EN(x) (BITS_MASK(x, 1, 6) | BITS_EN(1, 6))
194 #define v_RK336X_FORCE_JETAG(x) (BITS_MASK(x, 1, 13) | BITS_EN(1, 13))
201 enum rockchip_lvds_sub_devtype {
206 #endif /* _ROCKCHIP_LVDS_ */