drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
  24                          _begin_minor, _end_minor) \
  25                 {.offset = off, \
  26                  .mask = _mask, \
  27                  .shift = s, \
  28                  .write_mask = _write_mask, \
  29                  .major = _major, \
  30                  .begin_minor = _begin_minor, \
  31                  .end_minor = _end_minor,}
  32
  33 #define VOP_REG(off, _mask, s) \
  34                 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
  35
  36 #define VOP_REG_MASK(off, _mask, s) \
  37                 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
  38
  39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
  40                 VOP_REG_VER_MASK(off, _mask, s, false, \
  41                                  _major, _begin_minor, _end_minor)
  42
  43
  44 static const uint32_t formats_win_full[] = {
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_XBGR8888,
  48         DRM_FORMAT_ABGR8888,
  49         DRM_FORMAT_RGB888,
  50         DRM_FORMAT_BGR888,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53         DRM_FORMAT_NV12,
  54         DRM_FORMAT_NV16,
  55         DRM_FORMAT_NV24,
  56         DRM_FORMAT_NV12_10,
  57         DRM_FORMAT_NV16_10,
  58         DRM_FORMAT_NV24_10,
  59 };
  60
  61 static const uint32_t formats_win_lite[] = {
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_ARGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_RGB888,
  67         DRM_FORMAT_BGR888,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_BGR565,
  70 };
  71
  72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  73         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  74         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  75         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  76         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  77         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  78         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  79         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  80         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  81         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  82         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  83         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  84         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  85         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  86         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  87         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  88         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  89         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  90         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  91         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  92         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  93         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  94 };
  95
  96 static const struct vop_scl_regs rk3288_win_full_scl = {
  97         .ext = &rk3288_win_full_scl_ext,
  98         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  99         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 100         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 101         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 102 };
 103
 104 static const struct vop_win_phy rk3288_win01_data = {
 105         .scl = &rk3288_win_full_scl,
 106         .data_formats = formats_win_full,
 107         .nformats = ARRAY_SIZE(formats_win_full),
 108         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 109         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 110         .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
 111         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 112         .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
 113         .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
 114         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 115         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 116         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 117         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 118         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 120         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 121         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
 122         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
 123         .channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
 124 };
 125
 126 static const struct vop_win_phy rk3288_win23_data = {
 127         .data_formats = formats_win_lite,
 128         .nformats = ARRAY_SIZE(formats_win_lite),
 129         .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 130         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 131         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 132         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 133         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 134         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 135         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 136         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 137         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 138         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 139 };
 140
 141 static const struct vop_win_phy rk3288_area1_data = {
 142         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 143         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 144         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 145         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 146         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 147 };
 148
 149 static const struct vop_win_phy rk3288_area2_data = {
 150         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 151         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 152         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 153         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 154         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 155 };
 156
 157 static const struct vop_win_phy rk3288_area3_data = {
 158         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 159         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 160         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 161         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 162         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 163 };
 164
 165 static const struct vop_win_phy *rk3288_area_data[] = {
 166         &rk3288_area1_data,
 167         &rk3288_area2_data,
 168         &rk3288_area3_data
 169 };
 170
 171 static const struct vop_ctrl rk3288_ctrl_data = {
 172         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 173         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 174         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 175         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 176         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 177         .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 178         .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 179         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 180         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 181         .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 182         .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
 183         .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
 184
 185         .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
 186         .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 187         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 188         .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
 189         .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 190         .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
 191         .core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1),
 192         .p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1),
 193         .dclk_ddr = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 8, 3, 4, -1),
 194         .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
 195         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 196         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 197         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 198         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 199         .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
 200         .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
 201         .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
 202         .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1),
 203         .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1),
 204         .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1),
 205         .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
 206         .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1),
 207         .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1),
 208         .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1),
 209         .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1),
 210         .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1),
 211         .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
 212
 213         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 214         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 215
 216         .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
 217         .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
 218         .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
 219         .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 220         .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1),
 221         .lut_buffer_index = VOP_REG_VER(RK3399_DBG_POST_REG1, 0x1, 1, 3, 5, -1),
 222         .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
 223         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 224
 225         .afbdc_rstn = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 3, 3, 5, -1),
 226         .afbdc_en = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 0, 3, 5, -1),
 227         .afbdc_sel = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x3, 1, 3, 5, -1),
 228         .afbdc_format = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1f, 16, 3, 5, -1),
 229         .afbdc_hreg_block_split = VOP_REG_VER(RK3399_AFBCD0_CTRL,
 230                                               0x1, 21, 3, 5, -1),
 231         .afbdc_hdr_ptr = VOP_REG_VER(RK3399_AFBCD0_HDR_PTR, 0xffffffff,
 232                                      0, 3, 5, -1),
 233         .afbdc_pic_size = VOP_REG_VER(RK3399_AFBCD0_PIC_SIZE, 0xffffffff,
 234                                       0, 3, 5, -1),
 235         .cabc_config_mode = VOP_REG_VER(RK3399_CABC_CTRL0, 0x3, 1, 3, 5, -1),
 236         .cabc_calc_pixel_num = VOP_REG_VER(RK3399_CABC_CTRL0, 0x7fffff, 4,
 237                                            3, 5, -1),
 238         .cabc_handle_en = VOP_REG_VER(RK3399_CABC_CTRL0, 0x1, 3, 3, 5, -1),
 239         .cabc_en = VOP_REG_VER(RK3399_CABC_CTRL0, 0x1, 0, 3, 5, -1),
 240         .cabc_total_num = VOP_REG_VER(RK3399_CABC_CTRL1, 0x7fffff, 4, 3, 5, -1),
 241         .cabc_lut_en = VOP_REG_VER(RK3399_CABC_CTRL1, 0x1, 0, 3, 5, -1),
 242         .cabc_stage_up_mode = VOP_REG_VER(RK3399_CABC_CTRL2, 0x1, 19, 3, 5, -1),
 243         .cabc_stage_up = VOP_REG_VER(RK3399_CABC_CTRL2, 0x1ff, 8, 3, 5, -1),
 244         .cabc_stage_down = VOP_REG_VER(RK3399_CABC_CTRL2, 0xff, 0, 3, 5, -1),
 245         .cabc_global_dn = VOP_REG_VER(RK3399_CABC_CTRL3, 0xff, 0, 3, 5, -1),
 246         .cabc_global_dn_limit_en = VOP_REG_VER(RK3399_CABC_CTRL3, 0x1, 8,
 247                                                3, 5, -1),
 248
 249         .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
 250         .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 251
 252         .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
 253
 254         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 255 };
 256
 257 /*
 258  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 259  * special support to get alpha blending working.  For now, just use overlay
 260  * window 3 for the drm cursor.
 261  *
 262  */
 263 static const struct vop_win_data rk3288_vop_win_data[] = {
 264         { .base = 0x00, .phy = &rk3288_win01_data,
 265           .type = DRM_PLANE_TYPE_PRIMARY },
 266         { .base = 0x40, .phy = &rk3288_win01_data,
 267           .type = DRM_PLANE_TYPE_OVERLAY },
 268         { .base = 0x00, .phy = &rk3288_win23_data,
 269           .type = DRM_PLANE_TYPE_OVERLAY,
 270           .area = rk3288_area_data,
 271           .area_size = ARRAY_SIZE(rk3288_area_data), },
 272         { .base = 0x50, .phy = &rk3288_win23_data,
 273           .type = DRM_PLANE_TYPE_CURSOR,
 274           .area = rk3288_area_data,
 275           .area_size = ARRAY_SIZE(rk3288_area_data), },
 276 };
 277
 278 static const int rk3288_vop_intrs[] = {
 279         DSP_HOLD_VALID_INTR,
 280         FS_INTR,
 281         LINE_FLAG_INTR,
 282         BUS_ERROR_INTR,
 283 };
 284
 285 static const struct vop_intr rk3288_vop_intr = {
 286         .intrs = rk3288_vop_intrs,
 287         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 288         .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
 289         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 290         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 291         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 292 };
 293
 294 static const struct vop_data rk3288_vop = {
 295         .version = VOP_VERSION(3, 1),
 296         .feature = VOP_FEATURE_OUTPUT_10BIT,
 297         .max_input = {4096, 8192},
 298         /*
 299          * TODO: rk3288 have two vop, big one support 3840x2160,
 300          * little one only support 2560x1600.
 301          * Now force use 3840x2160.
 302          */
 303         .max_output = {3840, 2160},
 304         .intr = &rk3288_vop_intr,
 305         .ctrl = &rk3288_ctrl_data,
 306         .win = rk3288_vop_win_data,
 307         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 308 };
 309
 310 static const int rk3368_vop_intrs[] = {
 311         FS_INTR,
 312         FS_NEW_INTR,
 313         ADDR_SAME_INTR,
 314         LINE_FLAG_INTR,
 315         LINE_FLAG1_INTR,
 316         BUS_ERROR_INTR,
 317         WIN0_EMPTY_INTR,
 318         WIN1_EMPTY_INTR,
 319         WIN2_EMPTY_INTR,
 320         WIN3_EMPTY_INTR,
 321         HWC_EMPTY_INTR,
 322         POST_BUF_EMPTY_INTR,
 323         PWM_GEN_INTR,
 324         DSP_HOLD_VALID_INTR,
 325 };
 326
 327 static const struct vop_intr rk3368_vop_intr = {
 328         .intrs = rk3368_vop_intrs,
 329         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 330         .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
 331         .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
 332         .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
 333         .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
 334         .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
 335 };
 336
 337 static const struct vop_win_phy rk3368_win23_data = {
 338         .data_formats = formats_win_lite,
 339         .nformats = ARRAY_SIZE(formats_win_lite),
 340         .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
 341         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
 342         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
 343         .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
 344         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
 345         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 346         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
 347         .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
 348         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
 349         .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 350         .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 351 };
 352
 353 static const struct vop_win_phy rk3368_area1_data = {
 354         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
 355         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
 356         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
 357         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 358         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
 359         .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
 360         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
 361 };
 362
 363 static const struct vop_win_phy rk3368_area2_data = {
 364         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
 365         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
 366         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
 367         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 368         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
 369         .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
 370         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
 371 };
 372
 373 static const struct vop_win_phy rk3368_area3_data = {
 374         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
 375         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
 376         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
 377         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 378         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
 379         .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
 380         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
 381 };
 382
 383 static const struct vop_win_phy *rk3368_area_data[] = {
 384         &rk3368_area1_data,
 385         &rk3368_area2_data,
 386         &rk3368_area3_data
 387 };
 388
 389 static const struct vop_win_data rk3368_vop_win_data[] = {
 390         { .base = 0x00, .phy = &rk3288_win01_data,
 391           .type = DRM_PLANE_TYPE_PRIMARY },
 392         { .base = 0x40, .phy = &rk3288_win01_data,
 393           .type = DRM_PLANE_TYPE_OVERLAY },
 394         { .base = 0x00, .phy = &rk3368_win23_data,
 395           .type = DRM_PLANE_TYPE_OVERLAY,
 396           .area = rk3368_area_data,
 397           .area_size = ARRAY_SIZE(rk3368_area_data), },
 398         { .base = 0x50, .phy = &rk3368_win23_data,
 399           .type = DRM_PLANE_TYPE_CURSOR,
 400           .area = rk3368_area_data,
 401           .area_size = ARRAY_SIZE(rk3368_area_data), },
 402 };
 403
 404 static const struct vop_data rk3368_vop = {
 405         .version = VOP_VERSION(3, 2),
 406         .max_input = {4096, 8192},
 407         .max_output = {4096, 2160},
 408         .intr = &rk3368_vop_intr,
 409         .ctrl = &rk3288_ctrl_data,
 410         .win = rk3368_vop_win_data,
 411         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 412 };
 413
 414 static const struct vop_intr rk3366_vop_intr = {
 415         .intrs = rk3368_vop_intrs,
 416         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 417         .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
 418         .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
 419         .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
 420         .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
 421         .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
 422 };
 423
 424 static const struct vop_data rk3366_vop = {
 425         .version = VOP_VERSION(3, 4),
 426         .max_input = {4096, 8192},
 427         .max_output = {4096, 2160},
 428         .intr = &rk3366_vop_intr,
 429         .ctrl = &rk3288_ctrl_data,
 430         .win = rk3368_vop_win_data,
 431         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 432 };
 433
 434 static const uint32_t vop_csc_y2r_bt601[] = {
 435         0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
 436         0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
 437 };
 438
 439 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
 440         0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
 441         0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
 442 };
 443
 444 static const uint32_t vop_csc_r2y_bt601[] = {
 445         0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
 446         0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
 447 };
 448
 449 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
 450         0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
 451         0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
 452 };
 453
 454 static const uint32_t vop_csc_y2r_bt709[] = {
 455         0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
 456         0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
 457 };
 458
 459 static const uint32_t vop_csc_r2y_bt709[] = {
 460         0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
 461         0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
 462 };
 463
 464 static const uint32_t vop_csc_y2r_bt2020[] = {
 465         0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
 466         0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
 467 };
 468
 469 static const uint32_t vop_csc_r2y_bt2020[] = {
 470         0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
 471         0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
 472 };
 473
 474 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
 475         0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
 476         0x0000047a, 0x00000200, 0x00000200, 0x00000200,
 477 };
 478
 479 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
 480         0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
 481         0x00000394, 0x00000200, 0x00000200, 0x00000200,
 482 };
 483
 484 static const struct vop_csc_table rk3399_csc_table = {
 485         .y2r_bt601              = vop_csc_y2r_bt601,
 486         .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
 487         .r2y_bt601              = vop_csc_r2y_bt601,
 488         .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
 489
 490         .y2r_bt709              = vop_csc_y2r_bt709,
 491         .r2y_bt709              = vop_csc_r2y_bt709,
 492
 493         .y2r_bt2020             = vop_csc_y2r_bt2020,
 494         .r2y_bt2020             = vop_csc_r2y_bt2020,
 495
 496         .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
 497         .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
 498 };
 499
 500 static const struct vop_csc rk3399_win0_csc = {
 501         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
 502         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
 503         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
 504         .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
 505         .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
 506         .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
 507 };
 508
 509 static const struct vop_csc rk3399_win1_csc = {
 510         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
 511         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
 512         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
 513         .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
 514         .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
 515         .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
 516 };
 517
 518 static const struct vop_win_data rk3399_vop_win_data[] = {
 519         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 520           .type = DRM_PLANE_TYPE_PRIMARY },
 521         { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
 522           .type = DRM_PLANE_TYPE_OVERLAY },
 523         { .base = 0x00, .phy = &rk3368_win23_data,
 524           .type = DRM_PLANE_TYPE_OVERLAY,
 525           .area = rk3368_area_data,
 526           .area_size = ARRAY_SIZE(rk3368_area_data), },
 527         { .base = 0x50, .phy = &rk3368_win23_data,
 528           .type = DRM_PLANE_TYPE_CURSOR,
 529           .area = rk3368_area_data,
 530           .area_size = ARRAY_SIZE(rk3368_area_data), },
 531 };
 532
 533 static const struct vop_data rk3399_vop_big = {
 534         .version = VOP_VERSION(3, 5),
 535         .csc_table = &rk3399_csc_table,
 536         .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
 537         .max_input = {4096, 8192},
 538         .max_output = {4096, 2160},
 539         .intr = &rk3366_vop_intr,
 540         .ctrl = &rk3288_ctrl_data,
 541         .win = rk3399_vop_win_data,
 542         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 543 };
 544
 545 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 546         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 547           .type = DRM_PLANE_TYPE_PRIMARY },
 548         { .phy = NULL },
 549         { .base = 0x00, .phy = &rk3368_win23_data,
 550           .type = DRM_PLANE_TYPE_CURSOR,
 551           .area = rk3368_area_data,
 552           .area_size = ARRAY_SIZE(rk3368_area_data), },
 553         { .phy = NULL },
 554 };
 555
 556
 557 static const struct vop_data rk3399_vop_lit = {
 558         .version = VOP_VERSION(3, 6),
 559         .csc_table = &rk3399_csc_table,
 560         .max_input = {4096, 8192},
 561         .max_output = {2560, 1600},
 562         .intr = &rk3366_vop_intr,
 563         .ctrl = &rk3288_ctrl_data,
 564         .win = rk3399_vop_lit_win_data,
 565         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 566 };
 567
 568 static const struct vop_win_data rk322x_vop_win_data[] = {
 569         { .base = 0x00, .phy = &rk3288_win01_data,
 570           .type = DRM_PLANE_TYPE_PRIMARY },
 571         { .base = 0x40, .phy = &rk3288_win01_data,
 572           .type = DRM_PLANE_TYPE_CURSOR },
 573 };
 574
 575 static const struct vop_data rk322x_vop = {
 576         .version = VOP_VERSION(3, 7),
 577         .feature = VOP_FEATURE_OUTPUT_10BIT,
 578         .max_input = {4096, 8192},
 579         .max_output = {4096, 2160},
 580         .intr = &rk3366_vop_intr,
 581         .ctrl = &rk3288_ctrl_data,
 582         .win = rk322x_vop_win_data,
 583         .win_size = ARRAY_SIZE(rk322x_vop_win_data),
 584 };
 585
 586 static const struct vop_ctrl rk3328_ctrl_data = {
 587         .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
 588         .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
 589         .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 590         .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
 591         .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 592         .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
 593         .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 594         .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 595         .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 596         .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 597         .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 598         .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
 599         .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
 600         .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
 601         .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
 602         .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
 603         .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
 604         .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
 605         .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
 606         .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
 607         .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
 608         .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
 609         .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24),
 610         .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25),
 611         .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26),
 612         .sw_uv_offset_en  = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
 613         .sw_genlock   = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
 614         .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
 615         .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
 616         .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
 617         .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
 618         .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
 619         .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
 620         .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
 621         .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
 622         .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
 623
 624         .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
 625         .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
 626
 627         .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
 628         .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
 629         .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
 630         .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
 631         .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
 632
 633         .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
 634         .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
 635
 636         .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
 637
 638         .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
 639 };
 640
 641 static const struct vop_intr rk3328_vop_intr = {
 642         .intrs = rk3368_vop_intrs,
 643         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 644         .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
 645         .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
 646         .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
 647         .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
 648         .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
 649 };
 650
 651 static const struct vop_win_data rk3328_vop_win_data[] = {
 652         { .base = 0xd0, .phy = &rk3288_win01_data,
 653           .type = DRM_PLANE_TYPE_PRIMARY },
 654         { .base = 0x1d0, .phy = &rk3288_win01_data,
 655           .type = DRM_PLANE_TYPE_OVERLAY },
 656         { .base = 0x2d0, .phy = &rk3288_win01_data,
 657           .type = DRM_PLANE_TYPE_CURSOR },
 658 };
 659
 660 static const struct vop_data rk3328_vop = {
 661         .version = VOP_VERSION(3, 8),
 662         .feature = VOP_FEATURE_OUTPUT_10BIT,
 663         .max_input = {4096, 8192},
 664         .max_output = {4096, 2160},
 665         .intr = &rk3328_vop_intr,
 666         .ctrl = &rk3328_ctrl_data,
 667         .win = rk3328_vop_win_data,
 668         .win_size = ARRAY_SIZE(rk3328_vop_win_data),
 669 };
 670
 671 static const struct vop_scl_regs rk3066_win_scl = {
 672         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 673         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 674         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 675         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 676 };
 677
 678 static const struct vop_win_phy rk3036_win0_data = {
 679         .scl = &rk3066_win_scl,
 680         .data_formats = formats_win_full,
 681         .nformats = ARRAY_SIZE(formats_win_full),
 682         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 683         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 684         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 685         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 686         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 687         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 688         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 689         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 690         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 691         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
 692         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
 693         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
 694 };
 695
 696 static const struct vop_win_phy rk3036_win1_data = {
 697         .data_formats = formats_win_lite,
 698         .nformats = ARRAY_SIZE(formats_win_lite),
 699         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 700         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 701         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 702         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 703         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 704         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 705         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 706         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 707         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
 708         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
 709 };
 710
 711 static const struct vop_win_data rk3036_vop_win_data[] = {
 712         { .base = 0x00, .phy = &rk3036_win0_data,
 713           .type = DRM_PLANE_TYPE_PRIMARY },
 714         { .base = 0x00, .phy = &rk3036_win1_data,
 715           .type = DRM_PLANE_TYPE_CURSOR },
 716 };
 717
 718 static const int rk3036_vop_intrs[] = {
 719         DSP_HOLD_VALID_INTR,
 720         FS_INTR,
 721         LINE_FLAG_INTR,
 722         BUS_ERROR_INTR,
 723 };
 724
 725 static const struct vop_intr rk3036_intr = {
 726         .intrs = rk3036_vop_intrs,
 727         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 728         .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
 729         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 730         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 731         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 732 };
 733
 734 static const struct vop_ctrl rk3036_ctrl_data = {
 735         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 736         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 737         .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
 738         .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
 739         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
 740         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 741         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 742         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 743         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 744         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 745         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 746 };
 747
 748 static const struct vop_data rk3036_vop = {
 749         .version = VOP_VERSION(2, 2),
 750         .max_input = {1920, 1080},
 751         .max_output = {1920, 1080},
 752         .ctrl = &rk3036_ctrl_data,
 753         .intr = &rk3036_intr,
 754         .win = rk3036_vop_win_data,
 755         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 756 };
 757
 758 static const int rk3366_vop_lit_intrs[] = {
 759         FS_INTR,
 760         FS_NEW_INTR,
 761         ADDR_SAME_INTR,
 762         LINE_FLAG_INTR,
 763         LINE_FLAG1_INTR,
 764         BUS_ERROR_INTR,
 765         WIN0_EMPTY_INTR,
 766         WIN1_EMPTY_INTR,
 767         DSP_HOLD_VALID_INTR,
 768 };
 769
 770 static const struct vop_scl_regs rk3366_lit_win_scl = {
 771         .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 772         .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 773         .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 774         .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 775 };
 776
 777 static const struct vop_win_phy rk3366_lit_win0_data = {
 778         .scl = &rk3366_lit_win_scl,
 779         .data_formats = formats_win_full,
 780         .nformats = ARRAY_SIZE(formats_win_full),
 781
 782         .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
 783         .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
 784         .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
 785         .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
 786         .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
 787         .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
 788         .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
 789         .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
 790         .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
 791         .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
 792
 793         .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
 794         .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
 795         .key_color = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0xffffff, 0),
 796         .key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 24),
 797 };
 798
 799 static const struct vop_win_phy rk3366_lit_win1_data = {
 800         .data_formats = formats_win_lite,
 801         .nformats = ARRAY_SIZE(formats_win_lite),
 802
 803         .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
 804         .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
 805         .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
 806         .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
 807         .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
 808         .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
 809         .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
 810
 811         .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
 812         .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
 813         .key_color = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
 814         .key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
 815 };
 816
 817 static const struct vop_win_data rk3366_vop_lit_win_data[] = {
 818         { .base = 0x00, .phy = &rk3366_lit_win0_data,
 819           .type = DRM_PLANE_TYPE_PRIMARY },
 820         { .base = 0x00, .phy = &rk3366_lit_win1_data,
 821           .type = DRM_PLANE_TYPE_CURSOR },
 822 };
 823
 824 static const struct vop_intr rk3366_lit_intr = {
 825         .intrs = rk3366_vop_lit_intrs,
 826         .nintrs = ARRAY_SIZE(rk3366_vop_lit_intrs),
 827         .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
 828         .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
 829         .status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
 830         .enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
 831         .clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
 832 };
 833
 834 static const struct vop_ctrl rk3366_lit_ctrl_data = {
 835         .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
 836         .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
 837         .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
 838         .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
 839         .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
 840         .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
 841         .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
 842         .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
 843         .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
 844         .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
 845         .dsp_layer_sel = VOP_REG(RK3366_LIT_SYS_CTRL0, 0x1, 1),
 846         .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
 847         .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
 848         .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
 849         .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
 850         .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
 851         .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
 852         .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
 853         .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
 854         .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
 855         .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
 856         .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
 857         .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
 858         .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
 859         .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
 860         .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
 861         .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
 862         .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
 863         .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
 864         .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
 865         .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
 866         .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
 867         .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
 868         .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
 869         .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
 870         .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
 871         .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
 872 };
 873
 874 static const struct vop_data rk3366_vop_lit = {
 875         .max_input = {1920, 8192},
 876         .max_output = {1920, 1080},
 877         .ctrl = &rk3366_lit_ctrl_data,
 878         .intr = &rk3366_lit_intr,
 879         .win = rk3366_vop_lit_win_data,
 880         .win_size = ARRAY_SIZE(rk3366_vop_lit_win_data),
 881 };
 882
 883 static const struct of_device_id vop_driver_dt_match[] = {
 884         { .compatible = "rockchip,rk3036-vop",
 885           .data = &rk3036_vop },
 886         { .compatible = "rockchip,rk3288-vop",
 887           .data = &rk3288_vop },
 888         { .compatible = "rockchip,rk3368-vop",
 889           .data = &rk3368_vop },
 890         { .compatible = "rockchip,rk3366-vop",
 891           .data = &rk3366_vop },
 892         { .compatible = "rockchip,rk3366-vop-lit",
 893           .data = &rk3366_vop_lit },
 894         { .compatible = "rockchip,rk3399-vop-big",
 895           .data = &rk3399_vop_big },
 896         { .compatible = "rockchip,rk3399-vop-lit",
 897           .data = &rk3399_vop_lit },
 898         { .compatible = "rockchip,rk322x-vop",
 899           .data = &rk322x_vop },
 900         { .compatible = "rockchip,rk3328-vop",
 901           .data = &rk3328_vop },
 902         {},
 903 };
 904 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 905
 906 static int vop_probe(struct platform_device *pdev)
 907 {
 908         struct device *dev = &pdev->dev;
 909
 910         if (!dev->of_node) {
 911                 dev_err(dev, "can't find vop devices\n");
 912                 return -ENODEV;
 913         }
 914
 915         return component_add(dev, &vop_component_ops);
 916 }
 917
 918 static int vop_remove(struct platform_device *pdev)
 919 {
 920         component_del(&pdev->dev, &vop_component_ops);
 921
 922         return 0;
 923 }
 924
 925 struct platform_driver vop_platform_driver = {
 926         .probe = vop_probe,
 927         .remove = vop_remove,
 928         .driver = {
 929                 .name = "rockchip-vop",
 930                 .owner = THIS_MODULE,
 931                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 932         },
 933 };
 934
 935 module_platform_driver(vop_platform_driver);
 936
 937 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 938 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 939 MODULE_LICENSE("GPL v2");