2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
24 _begin_minor, _end_minor) \
28 .write_mask = _write_mask, \
30 .begin_minor = _begin_minor, \
31 .end_minor = _end_minor,}
33 #define VOP_REG(off, _mask, s) \
34 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
36 #define VOP_REG_MASK(off, _mask, s) \
37 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
40 VOP_REG_VER_MASK(off, _mask, s, false, \
41 _major, _begin_minor, _end_minor)
44 static const uint32_t formats_win_full[] = {
61 static const uint32_t formats_win_lite[] = {
72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
73 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
74 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
75 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
76 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
77 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
78 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
79 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
80 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
81 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
82 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
83 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
84 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
85 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
86 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
87 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
88 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
89 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
90 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
91 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
92 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
93 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
96 static const struct vop_scl_regs rk3288_win_full_scl = {
97 .ext = &rk3288_win_full_scl_ext,
98 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
99 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
100 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
101 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
104 static const struct vop_win_phy rk3288_win01_data = {
105 .scl = &rk3288_win_full_scl,
106 .data_formats = formats_win_full,
107 .nformats = ARRAY_SIZE(formats_win_full),
108 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
109 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
110 .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
111 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
112 .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
113 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
114 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
115 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
116 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
117 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
118 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
119 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
120 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
121 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
122 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
123 .channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
126 static const struct vop_win_phy rk3288_win23_data = {
127 .data_formats = formats_win_lite,
128 .nformats = ARRAY_SIZE(formats_win_lite),
129 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
130 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
131 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
132 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
133 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
134 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
135 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
136 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
137 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
138 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
141 static const struct vop_win_phy rk3288_area1_data = {
142 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
143 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
144 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
145 .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
146 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
149 static const struct vop_win_phy rk3288_area2_data = {
150 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
151 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
152 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
153 .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
154 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
157 static const struct vop_win_phy rk3288_area3_data = {
158 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
159 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
160 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
161 .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
162 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
165 static const struct vop_win_phy *rk3288_area_data[] = {
171 static const struct vop_ctrl rk3288_ctrl_data = {
172 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
173 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
174 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
175 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
176 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
177 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
178 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
179 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
180 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
181 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
182 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
183 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
185 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
186 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
187 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
188 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
189 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
190 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
191 .core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1),
192 .p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1),
193 .dclk_ddr = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 8, 3, 4, -1),
194 .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
195 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
196 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
197 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
198 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
199 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
200 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1),
201 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
202 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
203 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1),
204 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1),
205 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1),
206 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
207 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1),
208 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1),
209 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1),
210 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1),
211 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1),
212 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
214 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
215 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
217 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
218 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
219 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
220 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
221 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1),
222 .lut_buffer_index = VOP_REG_VER(RK3399_DBG_POST_REG1, 0x1, 1, 3, 5, -1),
223 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
224 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
226 .afbdc_rstn = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 3, 3, 5, -1),
227 .afbdc_en = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 0, 3, 5, -1),
228 .afbdc_sel = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x3, 1, 3, 5, -1),
229 .afbdc_format = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1f, 16, 3, 5, -1),
230 .afbdc_hreg_block_split = VOP_REG_VER(RK3399_AFBCD0_CTRL,
232 .afbdc_hdr_ptr = VOP_REG_VER(RK3399_AFBCD0_HDR_PTR, 0xffffffff,
234 .afbdc_pic_size = VOP_REG_VER(RK3399_AFBCD0_PIC_SIZE, 0xffffffff,
236 .cabc_config_mode = VOP_REG_VER(RK3399_CABC_CTRL0, 0x3, 1, 3, 5, -1),
237 .cabc_calc_pixel_num = VOP_REG_VER(RK3399_CABC_CTRL0, 0x7fffff, 4,
239 .cabc_handle_en = VOP_REG_VER(RK3399_CABC_CTRL0, 0x1, 3, 3, 5, -1),
240 .cabc_en = VOP_REG_VER(RK3399_CABC_CTRL0, 0x1, 0, 3, 5, -1),
241 .cabc_total_num = VOP_REG_VER(RK3399_CABC_CTRL1, 0x7fffff, 4, 3, 5, -1),
242 .cabc_lut_en = VOP_REG_VER(RK3399_CABC_CTRL1, 0x1, 0, 3, 5, -1),
243 .cabc_stage_up_mode = VOP_REG_VER(RK3399_CABC_CTRL2, 0x1, 19, 3, 5, -1),
244 .cabc_stage_up = VOP_REG_VER(RK3399_CABC_CTRL2, 0x1ff, 8, 3, 5, -1),
245 .cabc_stage_down = VOP_REG_VER(RK3399_CABC_CTRL2, 0xff, 0, 3, 5, -1),
246 .cabc_global_dn = VOP_REG_VER(RK3399_CABC_CTRL3, 0xff, 0, 3, 5, -1),
247 .cabc_global_dn_limit_en = VOP_REG_VER(RK3399_CABC_CTRL3, 0x1, 8,
250 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
251 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
253 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
255 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
259 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
260 * special support to get alpha blending working. For now, just use overlay
261 * window 3 for the drm cursor.
264 static const struct vop_win_data rk3288_vop_win_data[] = {
265 { .base = 0x00, .phy = &rk3288_win01_data,
266 .type = DRM_PLANE_TYPE_PRIMARY },
267 { .base = 0x40, .phy = &rk3288_win01_data,
268 .type = DRM_PLANE_TYPE_OVERLAY },
269 { .base = 0x00, .phy = &rk3288_win23_data,
270 .type = DRM_PLANE_TYPE_OVERLAY,
271 .area = rk3288_area_data,
272 .area_size = ARRAY_SIZE(rk3288_area_data), },
273 { .base = 0x50, .phy = &rk3288_win23_data,
274 .type = DRM_PLANE_TYPE_CURSOR,
275 .area = rk3288_area_data,
276 .area_size = ARRAY_SIZE(rk3288_area_data), },
279 static const int rk3288_vop_intrs[] = {
286 static const struct vop_intr rk3288_vop_intr = {
287 .intrs = rk3288_vop_intrs,
288 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
289 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
290 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
291 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
292 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
295 static const struct vop_data rk3288_vop = {
296 .version = VOP_VERSION(3, 1),
297 .feature = VOP_FEATURE_OUTPUT_10BIT,
298 .max_input = {4096, 8192},
300 * TODO: rk3288 have two vop, big one support 3840x2160,
301 * little one only support 2560x1600.
302 * Now force use 3840x2160.
304 .max_output = {3840, 2160},
305 .intr = &rk3288_vop_intr,
306 .ctrl = &rk3288_ctrl_data,
307 .win = rk3288_vop_win_data,
308 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
311 static const int rk3368_vop_intrs[] = {
328 static const struct vop_intr rk3368_vop_intr = {
329 .intrs = rk3368_vop_intrs,
330 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
331 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
332 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
333 .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
334 .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
335 .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
338 static const struct vop_win_phy rk3368_win23_data = {
339 .data_formats = formats_win_lite,
340 .nformats = ARRAY_SIZE(formats_win_lite),
341 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
342 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
343 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
344 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
345 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
346 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
347 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
348 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
349 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
350 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
351 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
354 static const struct vop_win_phy rk3368_area1_data = {
355 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
356 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
357 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
358 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
359 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
360 .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
361 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
364 static const struct vop_win_phy rk3368_area2_data = {
365 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
366 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
367 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
368 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
369 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
370 .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
371 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
374 static const struct vop_win_phy rk3368_area3_data = {
375 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
376 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
377 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
378 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
379 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
380 .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
381 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
384 static const struct vop_win_phy *rk3368_area_data[] = {
390 static const struct vop_win_data rk3368_vop_win_data[] = {
391 { .base = 0x00, .phy = &rk3288_win01_data,
392 .type = DRM_PLANE_TYPE_PRIMARY },
393 { .base = 0x40, .phy = &rk3288_win01_data,
394 .type = DRM_PLANE_TYPE_OVERLAY },
395 { .base = 0x00, .phy = &rk3368_win23_data,
396 .type = DRM_PLANE_TYPE_OVERLAY,
397 .area = rk3368_area_data,
398 .area_size = ARRAY_SIZE(rk3368_area_data), },
399 { .base = 0x50, .phy = &rk3368_win23_data,
400 .type = DRM_PLANE_TYPE_CURSOR,
401 .area = rk3368_area_data,
402 .area_size = ARRAY_SIZE(rk3368_area_data), },
405 static const struct vop_data rk3368_vop = {
406 .version = VOP_VERSION(3, 2),
407 .max_input = {4096, 8192},
408 .max_output = {4096, 2160},
409 .intr = &rk3368_vop_intr,
410 .ctrl = &rk3288_ctrl_data,
411 .win = rk3368_vop_win_data,
412 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
415 static const struct vop_intr rk3366_vop_intr = {
416 .intrs = rk3368_vop_intrs,
417 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
418 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
419 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
420 .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
421 .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
422 .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
425 static const struct vop_data rk3366_vop = {
426 .version = VOP_VERSION(3, 4),
427 .max_input = {4096, 8192},
428 .max_output = {4096, 2160},
429 .intr = &rk3366_vop_intr,
430 .ctrl = &rk3288_ctrl_data,
431 .win = rk3368_vop_win_data,
432 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
435 static const uint32_t vop_csc_y2r_bt601[] = {
436 0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
437 0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
440 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
441 0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
442 0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
445 static const uint32_t vop_csc_r2y_bt601[] = {
446 0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
447 0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
450 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
451 0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
452 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
455 static const uint32_t vop_csc_y2r_bt709[] = {
456 0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
457 0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
460 static const uint32_t vop_csc_r2y_bt709[] = {
461 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
462 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
465 static const uint32_t vop_csc_y2r_bt2020[] = {
466 0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
467 0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
470 static const uint32_t vop_csc_r2y_bt2020[] = {
471 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
472 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
475 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
476 0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
477 0x0000047a, 0x00000200, 0x00000200, 0x00000200,
480 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
481 0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
482 0x00000394, 0x00000200, 0x00000200, 0x00000200,
485 static const struct vop_csc_table rk3399_csc_table = {
486 .y2r_bt601 = vop_csc_y2r_bt601,
487 .y2r_bt601_12_235 = vop_csc_y2r_bt601_12_235,
488 .r2y_bt601 = vop_csc_r2y_bt601,
489 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235,
491 .y2r_bt709 = vop_csc_y2r_bt709,
492 .r2y_bt709 = vop_csc_r2y_bt709,
494 .y2r_bt2020 = vop_csc_y2r_bt2020,
495 .r2y_bt2020 = vop_csc_r2y_bt2020,
497 .r2r_bt709_to_bt2020 = vop_csc_r2r_bt709_to_bt2020,
498 .r2r_bt2020_to_bt709 = vop_csc_r2r_bt2020_to_bt709,
501 static const struct vop_csc rk3399_win0_csc = {
502 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
503 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
504 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
505 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
506 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
507 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
510 static const struct vop_csc rk3399_win1_csc = {
511 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
512 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
513 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
514 .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
515 .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
516 .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
519 static const struct vop_win_data rk3399_vop_win_data[] = {
520 { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
521 .type = DRM_PLANE_TYPE_PRIMARY },
522 { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
523 .type = DRM_PLANE_TYPE_OVERLAY },
524 { .base = 0x00, .phy = &rk3368_win23_data,
525 .type = DRM_PLANE_TYPE_OVERLAY,
526 .area = rk3368_area_data,
527 .area_size = ARRAY_SIZE(rk3368_area_data), },
528 { .base = 0x50, .phy = &rk3368_win23_data,
529 .type = DRM_PLANE_TYPE_CURSOR,
530 .area = rk3368_area_data,
531 .area_size = ARRAY_SIZE(rk3368_area_data), },
534 static const struct vop_data rk3399_vop_big = {
535 .version = VOP_VERSION(3, 5),
536 .csc_table = &rk3399_csc_table,
537 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
538 .max_input = {4096, 8192},
539 .max_output = {4096, 2160},
540 .intr = &rk3366_vop_intr,
541 .ctrl = &rk3288_ctrl_data,
542 .win = rk3399_vop_win_data,
543 .win_size = ARRAY_SIZE(rk3399_vop_win_data),
546 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
547 { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
548 .type = DRM_PLANE_TYPE_PRIMARY },
550 { .base = 0x00, .phy = &rk3368_win23_data,
551 .type = DRM_PLANE_TYPE_CURSOR,
552 .area = rk3368_area_data,
553 .area_size = ARRAY_SIZE(rk3368_area_data), },
558 static const struct vop_data rk3399_vop_lit = {
559 .version = VOP_VERSION(3, 6),
560 .csc_table = &rk3399_csc_table,
561 .max_input = {4096, 8192},
562 .max_output = {2560, 1600},
563 .intr = &rk3366_vop_intr,
564 .ctrl = &rk3288_ctrl_data,
565 .win = rk3399_vop_lit_win_data,
566 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
569 static const struct vop_win_data rk322x_vop_win_data[] = {
570 { .base = 0x00, .phy = &rk3288_win01_data,
571 .type = DRM_PLANE_TYPE_PRIMARY },
572 { .base = 0x40, .phy = &rk3288_win01_data,
573 .type = DRM_PLANE_TYPE_CURSOR },
576 static const struct vop_data rk322x_vop = {
577 .version = VOP_VERSION(3, 7),
578 .feature = VOP_FEATURE_OUTPUT_10BIT,
579 .max_input = {4096, 8192},
580 .max_output = {4096, 2160},
581 .intr = &rk3366_vop_intr,
582 .ctrl = &rk3288_ctrl_data,
583 .win = rk322x_vop_win_data,
584 .win_size = ARRAY_SIZE(rk322x_vop_win_data),
587 static const struct vop_ctrl rk3328_ctrl_data = {
588 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
589 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
590 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
591 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
592 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
593 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
594 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
595 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
596 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
597 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
598 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
599 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
600 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
601 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
602 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
603 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
604 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
605 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
606 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
607 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
608 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
609 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
610 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24),
611 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25),
612 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26),
613 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
614 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
615 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
616 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
617 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
618 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
619 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
620 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
621 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
622 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
623 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
625 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
626 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
628 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
629 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
630 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
631 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
632 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
634 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
635 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
637 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
639 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
642 static const struct vop_intr rk3328_vop_intr = {
643 .intrs = rk3368_vop_intrs,
644 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
645 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
646 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
647 .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
648 .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
649 .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
652 static const struct vop_win_data rk3328_vop_win_data[] = {
653 { .base = 0xd0, .phy = &rk3288_win01_data,
654 .type = DRM_PLANE_TYPE_PRIMARY },
655 { .base = 0x1d0, .phy = &rk3288_win01_data,
656 .type = DRM_PLANE_TYPE_OVERLAY },
657 { .base = 0x2d0, .phy = &rk3288_win01_data,
658 .type = DRM_PLANE_TYPE_CURSOR },
661 static const struct vop_data rk3328_vop = {
662 .version = VOP_VERSION(3, 8),
663 .feature = VOP_FEATURE_OUTPUT_10BIT,
664 .max_input = {4096, 8192},
665 .max_output = {4096, 2160},
666 .intr = &rk3328_vop_intr,
667 .ctrl = &rk3328_ctrl_data,
668 .win = rk3328_vop_win_data,
669 .win_size = ARRAY_SIZE(rk3328_vop_win_data),
672 static const struct vop_scl_regs rk3066_win_scl = {
673 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
674 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
675 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
676 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
679 static const struct vop_win_phy rk3036_win0_data = {
680 .scl = &rk3066_win_scl,
681 .data_formats = formats_win_full,
682 .nformats = ARRAY_SIZE(formats_win_full),
683 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
684 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
685 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
686 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
687 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
688 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
689 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
690 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
691 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
692 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
693 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
694 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
697 static const struct vop_win_phy rk3036_win1_data = {
698 .data_formats = formats_win_lite,
699 .nformats = ARRAY_SIZE(formats_win_lite),
700 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
701 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
702 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
703 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
704 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
705 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
706 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
707 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
708 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
709 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
712 static const struct vop_win_data rk3036_vop_win_data[] = {
713 { .base = 0x00, .phy = &rk3036_win0_data,
714 .type = DRM_PLANE_TYPE_PRIMARY },
715 { .base = 0x00, .phy = &rk3036_win1_data,
716 .type = DRM_PLANE_TYPE_CURSOR },
719 static const int rk3036_vop_intrs[] = {
726 static const struct vop_intr rk3036_intr = {
727 .intrs = rk3036_vop_intrs,
728 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
729 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
730 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
731 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
732 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
735 static const struct vop_ctrl rk3036_ctrl_data = {
736 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
737 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
738 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
739 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
740 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
741 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
742 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
743 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
744 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
745 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
746 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
749 static const struct vop_data rk3036_vop = {
750 .version = VOP_VERSION(2, 2),
751 .max_input = {1920, 1080},
752 .max_output = {1920, 1080},
753 .ctrl = &rk3036_ctrl_data,
754 .intr = &rk3036_intr,
755 .win = rk3036_vop_win_data,
756 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
759 static const int rk3366_vop_lit_intrs[] = {
771 static const struct vop_scl_regs rk3366_lit_win_scl = {
772 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
773 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
774 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
775 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
778 static const struct vop_win_phy rk3366_lit_win0_data = {
779 .scl = &rk3366_lit_win_scl,
780 .data_formats = formats_win_full,
781 .nformats = ARRAY_SIZE(formats_win_full),
783 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
784 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
785 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
786 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
787 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
788 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
789 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
790 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
791 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
792 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
794 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
795 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
796 .key_color = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0xffffff, 0),
797 .key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 24),
800 static const struct vop_win_phy rk3366_lit_win1_data = {
801 .data_formats = formats_win_lite,
802 .nformats = ARRAY_SIZE(formats_win_lite),
804 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
805 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
806 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
807 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
808 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
809 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
810 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
812 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
813 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
814 .key_color = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
815 .key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
818 static const struct vop_win_data rk3366_vop_lit_win_data[] = {
819 { .base = 0x00, .phy = &rk3366_lit_win0_data,
820 .type = DRM_PLANE_TYPE_PRIMARY },
821 { .base = 0x00, .phy = &rk3366_lit_win1_data,
822 .type = DRM_PLANE_TYPE_CURSOR },
825 static const struct vop_intr rk3366_lit_intr = {
826 .intrs = rk3366_vop_lit_intrs,
827 .nintrs = ARRAY_SIZE(rk3366_vop_lit_intrs),
828 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
829 .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
830 .status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
831 .enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
832 .clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
835 static const struct vop_ctrl rk3366_lit_ctrl_data = {
836 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
837 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
838 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
839 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
840 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
841 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
842 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
843 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
844 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
845 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
846 .dsp_layer_sel = VOP_REG(RK3366_LIT_SYS_CTRL0, 0x1, 1),
847 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
848 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
849 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
850 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
851 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
852 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
853 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
854 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
855 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
856 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
857 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
858 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
859 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
860 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
861 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
862 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
863 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
864 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
865 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
866 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
867 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
868 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
869 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
870 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
871 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
872 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
875 static const struct vop_data rk3366_vop_lit = {
876 .max_input = {1920, 8192},
877 .max_output = {1920, 1080},
878 .ctrl = &rk3366_lit_ctrl_data,
879 .intr = &rk3366_lit_intr,
880 .win = rk3366_vop_lit_win_data,
881 .win_size = ARRAY_SIZE(rk3366_vop_lit_win_data),
884 static const struct of_device_id vop_driver_dt_match[] = {
885 { .compatible = "rockchip,rk3036-vop",
886 .data = &rk3036_vop },
887 { .compatible = "rockchip,rk3288-vop",
888 .data = &rk3288_vop },
889 { .compatible = "rockchip,rk3368-vop",
890 .data = &rk3368_vop },
891 { .compatible = "rockchip,rk3366-vop",
892 .data = &rk3366_vop },
893 { .compatible = "rockchip,rk3366-vop-lit",
894 .data = &rk3366_vop_lit },
895 { .compatible = "rockchip,rk3399-vop-big",
896 .data = &rk3399_vop_big },
897 { .compatible = "rockchip,rk3399-vop-lit",
898 .data = &rk3399_vop_lit },
899 { .compatible = "rockchip,rk322x-vop",
900 .data = &rk322x_vop },
901 { .compatible = "rockchip,rk3328-vop",
902 .data = &rk3328_vop },
905 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
907 static int vop_probe(struct platform_device *pdev)
909 struct device *dev = &pdev->dev;
912 dev_err(dev, "can't find vop devices\n");
916 return component_add(dev, &vop_component_ops);
919 static int vop_remove(struct platform_device *pdev)
921 component_del(&pdev->dev, &vop_component_ops);
926 struct platform_driver vop_platform_driver = {
928 .remove = vop_remove,
930 .name = "rockchip-vop",
931 .owner = THIS_MODULE,
932 .of_match_table = of_match_ptr(vop_driver_dt_match),
936 module_platform_driver(vop_platform_driver);
938 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
939 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
940 MODULE_LICENSE("GPL v2");